abstractaccelerator/fpga/ram/Makefile

26 lines
536 B
Makefile
Raw Normal View History

2022-02-08 11:00:40 +08:00
TARGET=ram
OBJS+=ram.v
all: ${TARGET}.bit
$(TARGET).json: $(OBJS)
yosys -p "read_verilog $(OBJS); synth_ecp5 -top ${TARGET} -json $@"
$(TARGET).config: $(TARGET).json
nextpnr-ecp5 --25k --package CABGA381 --speed 6 --json $< --textcfg $@ --lpf $(TARGET).lpf --freq 65
$(TARGET).bit: $(TARGET).config
ecppack --svf ${TARGET}.svf $< $@
${TARGET}.svf : ${TARGET}.bit
prog: ${TARGET}.svf
# openFPGALoader -c digilent_hs2 $(TARGET).bit
./dapprog ${TARGET}.svf
clean:
rm -f *.svf *.bit *.config *.ys *.json
.PHONY: prog clean