abstractaccelerator/fpga/xc7z010/Makefile

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2025-04-19 13:26:08 +08:00
export RV_ROOT = ${PWD}/../..
GCC_PREFIX = /opt/riscv/bin/riscv32-unknown-elf
GDB_PREFIX = /opt/riscv/bin/riscv32-unknown-elf-gdb
TEST_CFLAGS = -g -O3 -funroll-all-loops
ABI = -mabi=ilp32 -march=rv32imc
DEMODIR = ${PWD}
BUILD_DIR = ${DEMODIR}/build
RV_SOC = ${RV_ROOT}/soc
TEST = jtag
all: clean verilator
impl:
cd build && vivado -mode batch -notrace -quiet -source ../vivado.tcl
prog:
cd build && vivado -mode batch -notrace -quiet -source ../vivado-prog.tcl
clean:
rm -rf build obj_dir
openocd:
openocd -f swerv.cfg
gdb:
$(GDB_PREFIX) -x gdbinit ./build/jtag.bin
help:
@echo Possible targets: verilator help clean all verilator-build program.hex
.PHONY: help clean verilator