abstractaccelerator/Cores-SweRV/demo/fpga/Readmd.md

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2022-02-20 12:11:18 +08:00
# jtag simulation
## start openocd
`openocd -d -f swerv.cfg`
## start gdb
`/opt/riscv/bin/riscv32-unknown-elf-gdb -ex "target extended-remote :3333"`
## quick start
At demo/jtag/
1. `make all`
2. `make openocd`
3. `make gdb`