35 lines
894 B
INI
35 lines
894 B
INI
|
# "JTAG adapter" for simulation, exposed to OpenOCD through a TCP socket
|
||
|
|
# speaking the remote_bitbang protocol. The adapter is implemented as
|
||
|
|
# SystemVerilog DPI module.
|
||
|
|
|
||
|
|
adapter driver remote_bitbang
|
||
|
|
remote_bitbang host localhost
|
||
|
|
remote_bitbang port 44853
|
||
|
|
|
||
|
|
# Target configuration for the riscv chip
|
||
|
|
|
||
|
|
set _CHIPNAME riscv
|
||
|
|
set _TARGETNAME $_CHIPNAME.cpu
|
||
|
|
|
||
|
|
jtag newtap $_CHIPNAME tap -irlen 5 -expected-id 0x01
|
||
|
|
set _TARGETNAME $_CHIPNAME.tap
|
||
|
|
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
|
||
|
|
|
||
|
|
# Configure work area in on-chip SRAM
|
||
|
|
# $_TARGETNAME configure -work-area-phys 0x1000e000 -work-area-size 1000 -work-area-backup 0
|
||
|
|
|
||
|
|
riscv expose_csrs 1988
|
||
|
|
|
||
|
|
# Be verbose about GDB errors
|
||
|
|
gdb_report_data_abort enable
|
||
|
|
gdb_report_register_access_error enable
|
||
|
|
|
||
|
|
# Increase timeouts in simulation
|
||
|
|
riscv set_command_timeout_sec 1200
|
||
|
|
|
||
|
|
# Conclude OpenOCD configuration
|
||
|
|
init
|
||
|
|
|
||
|
|
# Halt the target
|
||
|
|
halt
|