67 lines
1.8 KiB
Tcl
67 lines
1.8 KiB
Tcl
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# Project configuration -------------------------------------------------------
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create_project -force vivado
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set_property SOURCE_MGMT_MODE None [current_project]
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set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1]
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set_property PART xc7z010-2-clg400 [current_project]
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# Files inclusion
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add_file /home/colin/develop/abstractaccelerator/fpga/xc7z010/TOP.v
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add_file /home/colin/develop/abstractaccelerator/fpga/xc7z010/led.v
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add_file /home/colin/develop/abstractaccelerator/fpga/xc7z010/design_1/design_1.bd
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# Constraints inclusion
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add_file -fileset constrs_1 /home/colin/develop/abstractaccelerator/fpga/xc7z010/timing.xdc
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set_property TARGET_CONSTRS_FILE /home/colin/develop/abstractaccelerator/fpga/xc7z010/timing.xdc [current_fileset -constrset]
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add_file -fileset constrs_1 /home/colin/develop/abstractaccelerator/fpga/xc7z010/pin.xdc
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# Top-level specification
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set_property TOP TOP [current_fileset]
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# Verilog Includes
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set_property INCLUDE_DIRS { /home/colin/develop/abstractaccelerator/fpga/xc7z010 } [current_fileset]
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# Verilog Parameters / VHDL Generics
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set_property GENERIC { FREQ=125000000 SECS=1 } -objects [get_filesets sources_1]
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close_project
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# Design flow -----------------------------------------------------------------
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open_project vivado
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# Synthesis
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# PRESYNTH
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# set_property DESIGN_MODE GateLvl [current_fileset]
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reset_run synth_1
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launch_runs synth_1
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wait_on_run synth_1
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#report_property [get_runs synth_1]
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if { [get_property STATUS [get_runs synth_1]] ne "synth_design Complete!" } { exit 1 }
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# Place and Route
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reset_run impl_1
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launch_runs impl_1
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wait_on_run impl_1
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#report_property [get_runs impl_1]
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if { [get_property STATUS [get_runs impl_1]] ne "route_design Complete!" } { exit 1 }
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# Bitstream generation
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open_run impl_1
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write_bitstream -force vivado
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write_debug_probes -force -quiet vivado.ltx
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close_project
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