19 lines
338 B
Python
19 lines
338 B
Python
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from pyfpga.vivado import Vivado
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prj = Vivado(odir=f'./build')
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prj.set_part('xc7z010-2-clg400')
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prj.add_param('FREQ', '125000000')
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prj.add_cons('timing.xdc')
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prj.add_cons('pin.xdc')
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prj.add_param('SECS', '1')
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prj.add_include('./')
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prj.add_vlog('*.v')
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prj.add_vlog('./design_1/design_1.bd')
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prj.set_top('TOP')
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# prj.make()
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prj.prog()
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