410 lines
18 KiB
Systemverilog
410 lines
18 KiB
Systemverilog
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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// $Id$
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//
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// Function: Top wrapper file with swerv/mem instantiated inside
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// Comments:
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//
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//********************************************************************************
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`include "build.h"
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//`include "def.sv"
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module swerv_wrapper
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import swerv_types::*;
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(
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input logic clk,
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input logic rst_l,
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input logic [31:1] rst_vec,
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input logic nmi_int,
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input logic [31:1] nmi_vec,
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input logic [31:1] jtag_id,
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output logic [63:0] trace_rv_i_insn_ip,
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output logic [63:0] trace_rv_i_address_ip,
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output logic [2:0] trace_rv_i_valid_ip,
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output logic [2:0] trace_rv_i_exception_ip,
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output logic [4:0] trace_rv_i_ecause_ip,
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output logic [2:0] trace_rv_i_interrupt_ip,
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output logic [31:0] trace_rv_i_tval_ip,
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// Bus signals
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`ifdef RV_BUILD_AXI4
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//-------------------------- LSU AXI signals--------------------------
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// AXI Write Channels
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output logic lsu_axi_awvalid,
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input logic lsu_axi_awready,
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output logic [`RV_LSU_BUS_TAG-1:0] lsu_axi_awid,
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output logic [31:0] lsu_axi_awaddr,
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output logic [3:0] lsu_axi_awregion,
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output logic [7:0] lsu_axi_awlen,
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output logic [2:0] lsu_axi_awsize,
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output logic [1:0] lsu_axi_awburst,
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output logic lsu_axi_awlock,
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output logic [3:0] lsu_axi_awcache,
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output logic [2:0] lsu_axi_awprot,
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output logic [3:0] lsu_axi_awqos,
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output logic lsu_axi_wvalid,
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input logic lsu_axi_wready,
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output logic [63:0] lsu_axi_wdata,
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output logic [7:0] lsu_axi_wstrb,
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output logic lsu_axi_wlast,
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input logic lsu_axi_bvalid,
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output logic lsu_axi_bready,
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input logic [1:0] lsu_axi_bresp,
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input logic [`RV_LSU_BUS_TAG-1:0] lsu_axi_bid,
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// AXI Read Channels
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output logic lsu_axi_arvalid,
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input logic lsu_axi_arready,
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output logic [`RV_LSU_BUS_TAG-1:0] lsu_axi_arid,
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output logic [31:0] lsu_axi_araddr,
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output logic [3:0] lsu_axi_arregion,
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output logic [7:0] lsu_axi_arlen,
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output logic [2:0] lsu_axi_arsize,
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output logic [1:0] lsu_axi_arburst,
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output logic lsu_axi_arlock,
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output logic [3:0] lsu_axi_arcache,
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output logic [2:0] lsu_axi_arprot,
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output logic [3:0] lsu_axi_arqos,
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input logic lsu_axi_rvalid,
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output logic lsu_axi_rready,
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input logic [`RV_LSU_BUS_TAG-1:0] lsu_axi_rid,
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input logic [63:0] lsu_axi_rdata,
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input logic [1:0] lsu_axi_rresp,
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input logic lsu_axi_rlast,
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//-------------------------- IFU AXI signals--------------------------
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// AXI Write Channels
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output logic ifu_axi_awvalid,
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input logic ifu_axi_awready,
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output logic [`RV_IFU_BUS_TAG-1:0] ifu_axi_awid,
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output logic [31:0] ifu_axi_awaddr,
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output logic [3:0] ifu_axi_awregion,
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output logic [7:0] ifu_axi_awlen,
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output logic [2:0] ifu_axi_awsize,
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output logic [1:0] ifu_axi_awburst,
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output logic ifu_axi_awlock,
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output logic [3:0] ifu_axi_awcache,
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output logic [2:0] ifu_axi_awprot,
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output logic [3:0] ifu_axi_awqos,
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output logic ifu_axi_wvalid,
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input logic ifu_axi_wready,
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output logic [63:0] ifu_axi_wdata,
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output logic [7:0] ifu_axi_wstrb,
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output logic ifu_axi_wlast,
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input logic ifu_axi_bvalid,
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output logic ifu_axi_bready,
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input logic [1:0] ifu_axi_bresp,
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input logic [`RV_IFU_BUS_TAG-1:0] ifu_axi_bid,
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// AXI Read Channels
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output logic ifu_axi_arvalid,
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input logic ifu_axi_arready,
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output logic [`RV_IFU_BUS_TAG-1:0] ifu_axi_arid,
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output logic [31:0] ifu_axi_araddr,
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output logic [3:0] ifu_axi_arregion,
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output logic [7:0] ifu_axi_arlen,
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output logic [2:0] ifu_axi_arsize,
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output logic [1:0] ifu_axi_arburst,
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output logic ifu_axi_arlock,
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output logic [3:0] ifu_axi_arcache,
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output logic [2:0] ifu_axi_arprot,
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output logic [3:0] ifu_axi_arqos,
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input logic ifu_axi_rvalid,
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output logic ifu_axi_rready,
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input logic [`RV_IFU_BUS_TAG-1:0] ifu_axi_rid,
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input logic [63:0] ifu_axi_rdata,
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input logic [1:0] ifu_axi_rresp,
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input logic ifu_axi_rlast,
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//-------------------------- SB AXI signals--------------------------
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// AXI Write Channels
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output logic sb_axi_awvalid,
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input logic sb_axi_awready,
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output logic [`RV_SB_BUS_TAG-1:0] sb_axi_awid,
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output logic [31:0] sb_axi_awaddr,
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output logic [3:0] sb_axi_awregion,
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output logic [7:0] sb_axi_awlen,
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output logic [2:0] sb_axi_awsize,
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output logic [1:0] sb_axi_awburst,
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output logic sb_axi_awlock,
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output logic [3:0] sb_axi_awcache,
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output logic [2:0] sb_axi_awprot,
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output logic [3:0] sb_axi_awqos,
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output logic sb_axi_wvalid,
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input logic sb_axi_wready,
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output logic [63:0] sb_axi_wdata,
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output logic [7:0] sb_axi_wstrb,
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output logic sb_axi_wlast,
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input logic sb_axi_bvalid,
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output logic sb_axi_bready,
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input logic [1:0] sb_axi_bresp,
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input logic [`RV_SB_BUS_TAG-1:0] sb_axi_bid,
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// AXI Read Channels
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output logic sb_axi_arvalid,
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input logic sb_axi_arready,
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output logic [`RV_SB_BUS_TAG-1:0] sb_axi_arid,
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output logic [31:0] sb_axi_araddr,
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output logic [3:0] sb_axi_arregion,
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output logic [7:0] sb_axi_arlen,
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output logic [2:0] sb_axi_arsize,
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output logic [1:0] sb_axi_arburst,
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output logic sb_axi_arlock,
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output logic [3:0] sb_axi_arcache,
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output logic [2:0] sb_axi_arprot,
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output logic [3:0] sb_axi_arqos,
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input logic sb_axi_rvalid,
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output logic sb_axi_rready,
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input logic [`RV_SB_BUS_TAG-1:0] sb_axi_rid,
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input logic [63:0] sb_axi_rdata,
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input logic [1:0] sb_axi_rresp,
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input logic sb_axi_rlast,
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//-------------------------- DMA AXI signals--------------------------
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// AXI Write Channels
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input logic dma_axi_awvalid,
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output logic dma_axi_awready,
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input logic [`RV_DMA_BUS_TAG-1:0] dma_axi_awid,
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input logic [31:0] dma_axi_awaddr,
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input logic [2:0] dma_axi_awsize,
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input logic [2:0] dma_axi_awprot,
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input logic [7:0] dma_axi_awlen,
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input logic [1:0] dma_axi_awburst,
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input logic dma_axi_wvalid,
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output logic dma_axi_wready,
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input logic [63:0] dma_axi_wdata,
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input logic [7:0] dma_axi_wstrb,
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input logic dma_axi_wlast,
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output logic dma_axi_bvalid,
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input logic dma_axi_bready,
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output logic [1:0] dma_axi_bresp,
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output logic [`RV_DMA_BUS_TAG-1:0] dma_axi_bid,
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// AXI Read Channels
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input logic dma_axi_arvalid,
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output logic dma_axi_arready,
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input logic [`RV_DMA_BUS_TAG-1:0] dma_axi_arid,
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input logic [31:0] dma_axi_araddr,
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input logic [2:0] dma_axi_arsize,
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input logic [2:0] dma_axi_arprot,
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input logic [7:0] dma_axi_arlen,
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input logic [1:0] dma_axi_arburst,
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output logic dma_axi_rvalid,
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input logic dma_axi_rready,
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output logic [`RV_DMA_BUS_TAG-1:0] dma_axi_rid,
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output logic [63:0] dma_axi_rdata,
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output logic [1:0] dma_axi_rresp,
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output logic dma_axi_rlast,
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`endif
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`ifdef RV_BUILD_AHB_LITE
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//// AHB LITE BUS
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output logic [31:0] haddr,
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output logic [2:0] hburst,
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output logic hmastlock,
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output logic [3:0] hprot,
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output logic [2:0] hsize,
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output logic [1:0] htrans,
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output logic hwrite,
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input logic [63:0] hrdata,
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input logic hready,
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input logic hresp,
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// LSU AHB Master
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output logic [31:0] lsu_haddr,
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output logic [2:0] lsu_hburst,
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output logic lsu_hmastlock,
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output logic [3:0] lsu_hprot,
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output logic [2:0] lsu_hsize,
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output logic [1:0] lsu_htrans,
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output logic lsu_hwrite,
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output logic [63:0] lsu_hwdata,
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input logic [63:0] lsu_hrdata,
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input logic lsu_hready,
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input logic lsu_hresp,
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// Debug Syster Bus AHB
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output logic [31:0] sb_haddr,
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output logic [2:0] sb_hburst,
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output logic sb_hmastlock,
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output logic [3:0] sb_hprot,
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output logic [2:0] sb_hsize,
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output logic [1:0] sb_htrans,
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output logic sb_hwrite,
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output logic [63:0] sb_hwdata,
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input logic [63:0] sb_hrdata,
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input logic sb_hready,
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input logic sb_hresp,
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// DMA Slave
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input logic [31:0] dma_haddr,
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input logic [2:0] dma_hburst,
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input logic dma_hmastlock,
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input logic [3:0] dma_hprot,
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input logic [2:0] dma_hsize,
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input logic [1:0] dma_htrans,
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input logic dma_hwrite,
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input logic [63:0] dma_hwdata,
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input logic dma_hsel,
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input logic dma_hreadyin,
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output logic [63:0] dma_hrdata,
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output logic dma_hreadyout,
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output logic dma_hresp,
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`endif
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// clk ratio signals
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input logic lsu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
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input logic ifu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
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input logic dbg_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
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input logic dma_bus_clk_en, // Clock ratio b/w cpu core clk & AHB slave interface
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// input logic ext_int,
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input logic timer_int,
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input logic [`RV_PIC_TOTAL_INT:1] extintsrc_req,
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output logic [1:0] dec_tlu_perfcnt0, // toggles when perf counter 0 has an event inc
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output logic [1:0] dec_tlu_perfcnt1,
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output logic [1:0] dec_tlu_perfcnt2,
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output logic [1:0] dec_tlu_perfcnt3,
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// ports added by the soc team
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input logic jtag_tck, // JTAG clk
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input logic jtag_tms, // JTAG TMS
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input logic jtag_tdi, // JTAG tdi
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input logic jtag_trst_n, // JTAG Reset
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output logic jtag_tdo, // JTAG TDO
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// external MPC halt/run interface
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input logic mpc_debug_halt_req, // Async halt request
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input logic mpc_debug_run_req, // Async run request
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input logic mpc_reset_run_req, // Run/halt after reset
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output logic mpc_debug_halt_ack, // Halt ack
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output logic mpc_debug_run_ack, // Run ack
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output logic debug_brkpt_status, // debug breakpoint
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input logic i_cpu_halt_req, // Async halt req to CPU
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output logic o_cpu_halt_ack, // core response to halt
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output logic o_cpu_halt_status, // 1'b1 indicates core is halted
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output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
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input logic i_cpu_run_req, // Async restart req to CPU
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output logic o_cpu_run_ack, // Core response to run req
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input logic scan_mode, // To enable scan mode
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||
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input logic mbist_mode // to enable mbist
|
||
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|
);
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||
|
|
|
||
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|
`include "global.h"
|
||
|
|
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||
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// DCCM ports
|
||
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|
logic dccm_wren;
|
||
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|
logic dccm_rden;
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||
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|
logic [DCCM_BITS-1:0] dccm_wr_addr;
|
||
|
|
logic [DCCM_BITS-1:0] dccm_rd_addr_lo;
|
||
|
|
logic [DCCM_BITS-1:0] dccm_rd_addr_hi;
|
||
|
|
logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data;
|
||
|
|
|
||
|
|
logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo;
|
||
|
|
logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi;
|
||
|
|
|
||
|
|
logic lsu_freeze_dc3;
|
||
|
|
|
||
|
|
// PIC ports
|
||
|
|
|
||
|
|
// Icache & Itag ports
|
||
|
|
logic [31:3] ic_rw_addr;
|
||
|
|
logic [3:0] ic_wr_en ; // Which way to write
|
||
|
|
logic ic_rd_en ;
|
||
|
|
|
||
|
|
|
||
|
|
logic [3:0] ic_tag_valid; // Valid from the I$ tag valid outside (in flops).
|
||
|
|
|
||
|
|
logic [3:0] ic_rd_hit; // ic_rd_hit[3:0]
|
||
|
|
logic ic_tag_perr; // Ic tag parity error
|
||
|
|
|
||
|
|
logic [15:2] ic_debug_addr; // Read/Write addresss to the Icache.
|
||
|
|
logic ic_debug_rd_en; // Icache debug rd
|
||
|
|
logic ic_debug_wr_en; // Icache debug wr
|
||
|
|
logic ic_debug_tag_array; // Debug tag array
|
||
|
|
logic [3:0] ic_debug_way; // Debug way. Rd or Wr.
|
||
|
|
|
||
|
|
`ifdef RV_ICACHE_ECC
|
||
|
|
logic [24:0] ictag_debug_rd_data;// Debug icache tag.
|
||
|
|
logic [83:0] ic_wr_data; // ic_wr_data[135:0]
|
||
|
|
logic [167:0] ic_rd_data; // ic_rd_data[135:0]
|
||
|
|
logic [41:0] ic_debug_wr_data; // Debug wr cache.
|
||
|
|
`else
|
||
|
|
logic [20:0] ictag_debug_rd_data;// Debug icache tag.
|
||
|
|
logic [67:0] ic_wr_data; // ic_wr_data[135:0]
|
||
|
|
logic [135:0] ic_rd_data; // ic_rd_data[135:0]
|
||
|
|
logic [33:0] ic_debug_wr_data; // Debug wr cache.
|
||
|
|
`endif
|
||
|
|
|
||
|
|
logic [127:0] ic_premux_data;
|
||
|
|
logic ic_sel_premux_data;
|
||
|
|
|
||
|
|
`ifdef RV_ICCM_ENABLE
|
||
|
|
// ICCM ports
|
||
|
|
logic [`RV_ICCM_BITS-1:2] iccm_rw_addr;
|
||
|
|
logic iccm_wren;
|
||
|
|
logic iccm_rden;
|
||
|
|
logic [2:0] iccm_wr_size;
|
||
|
|
logic [77:0] iccm_wr_data;
|
||
|
|
logic [155:0] iccm_rd_data;
|
||
|
|
`endif
|
||
|
|
|
||
|
|
logic core_rst_l; // Core reset including rst_l and dbg_rst_l
|
||
|
|
logic jtag_tdoEn;
|
||
|
|
|
||
|
|
logic dccm_clk_override;
|
||
|
|
logic icm_clk_override;
|
||
|
|
logic dec_tlu_core_ecc_disable;
|
||
|
|
|
||
|
|
// Instantiate the swerv core
|
||
|
|
swerv swerv (
|
||
|
|
.*
|
||
|
|
);
|
||
|
|
|
||
|
|
// Instantiate the mem
|
||
|
|
mem mem (
|
||
|
|
.rst_l(core_rst_l),
|
||
|
|
.*
|
||
|
|
);
|
||
|
|
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
|