2022-02-22 14:44:45 +08:00
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# "JTAG adapter" for simulation, exposed to OpenOCD through a TCP socket
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# speaking the remote_bitbang protocol. The adapter is implemented as
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# SystemVerilog DPI module.
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2022-02-24 11:18:07 +08:00
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# reset_config srst_only # donot support TRST, use five tms=1
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# adapter_nsrst_assert_width 100
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2022-02-22 14:44:45 +08:00
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adapter driver remote_bitbang
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remote_bitbang host localhost
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remote_bitbang port 44853
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# Target configuration for the riscv chip
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set _CHIPNAME riscv
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set _TARGETNAME $_CHIPNAME.tap
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2022-02-24 11:18:07 +08:00
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jtag newtap $_CHIPNAME tap -irlen 5 -expected-id 0x10000B6F
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# {4'h1, 16'h0, 12'b1011_011_0111_1};
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2022-02-22 14:44:45 +08:00
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target create $_TARGETNAME riscv -chain-position $_TARGETNAME
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# Configure work area in on-chip SRAM
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# $_TARGETNAME configure -work-area-phys 0x1000e000 -work-area-size 1000 -work-area-backup 0
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riscv expose_csrs 1988
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# Be verbose about GDB errors
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gdb_report_data_abort enable
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gdb_report_register_access_error enable
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# Increase timeouts in simulation
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riscv set_command_timeout_sec 1200
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# Conclude OpenOCD configuration
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init
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# Halt the target
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halt
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