abstractaccelerator/fpga/ram/top.sv

50 lines
1.1 KiB
Systemverilog
Raw Normal View History

module top(
input clk,
output reg led_o
);
parameter WIDTH=8;
parameter DEPTH=16;
parameter SIZE=(1<<DEPTH);
reg [DEPTH-1:0] read_addr;
reg [DEPTH-1:0] write_addr;
wire [DEPTH-1:0] read_addr_next = read_addr + 1'b1;
wire [DEPTH-1:0] write_addr_next = write_addr + 1'b1;
wire [WIDTH-1:0] read_data;
reg [WIDTH-1:0] write_data;
bram #(
.WIDTH(WIDTH),
.DEPTH(DEPTH),
.SIZE(SIZE)
) bram_i (
.clk(clk),
.re(1'b1),
.we(1'b1),
.addr_rd(read_addr),
.addr_wr(write_addr),
.data_rd(read_data),
.data_wr(write_data)
);
always @(posedge clk) begin
led_o <= read_data[0];
write_data <= {read_data[6:0],read_data[7]};
read_addr <= read_addr_next;
write_addr <= write_addr_next;
end
initial begin
$display(" Model running...\n");
read_addr = 1;
write_addr = 0;
write_data = 0;
end
endmodule