abstractaccelerator/Cores-SweRV/testbench/link.ld

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OUTPUT_ARCH( "riscv" )
ENTRY(_start)
SECTIONS
{
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. = 0;
.text : { *(.text*) }
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_end = .;
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. = 0x10000;
.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000; }
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.bss : { *(.bss) }
. = 0xd0580000;
.data.io : { *(.data.io) }
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}