abstractaccelerator/fpga/ram/sim_main.cpp

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#include <verilated.h>
#include <memory>
#include "Vtop.h"
#include "verilated_vcd_c.h"
double sc_time_stamp() { return 0; }
int main(int argc, char** argv, char** env) {
Verilated::mkdir("logs");
const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
contextp->debug(0);
contextp->randReset(2);
contextp->traceEverOn(true);
contextp->commandArgs(argc, argv);
const std::unique_ptr<Vtop> top{new Vtop{contextp.get(), "TOP"}};
top->clk = 0;
Verilated::traceEverOn(true);
VerilatedVcdC* tfp = new VerilatedVcdC;
top->trace(tfp, 99); // Trace 99 levels of hierarchy
tfp->open("logs/vlt_dump.vcd");
uint64_t steps = 10000;
while (!contextp->gotFinish() && steps) {
contextp->timeInc(1); // 1 timeprecision period passes...
top->clk = !top->clk;
top->eval();
steps--;
tfp->dump(contextp->time());
}
tfp->close();
top->final();
return 0;
}