50 lines
1.1 KiB
Systemverilog
50 lines
1.1 KiB
Systemverilog
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module top(
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input clk,
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output reg led_o
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);
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parameter WIDTH=8;
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parameter DEPTH=16;
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parameter SIZE=(1<<DEPTH);
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reg [DEPTH-1:0] read_addr;
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reg [DEPTH-1:0] write_addr;
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wire [DEPTH-1:0] read_addr_next = read_addr + 1'b1;
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wire [DEPTH-1:0] write_addr_next = write_addr + 1'b1;
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wire [WIDTH-1:0] read_data;
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reg [WIDTH-1:0] write_data;
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bram #(
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.WIDTH(WIDTH),
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.DEPTH(DEPTH),
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.SIZE(SIZE)
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) bram_i (
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.clk(clk),
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.re(1'b1),
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.we(1'b1),
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.addr_rd(read_addr),
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.addr_wr(write_addr),
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.data_rd(read_data),
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.data_wr(write_data)
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);
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always @(posedge clk) begin
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led_o <= read_data[0];
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write_data <= {read_data[6:0],read_data[7]};
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read_addr <= read_addr_next;
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write_addr <= write_addr_next;
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end
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initial begin
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$display(" Model running...\n");
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read_addr = 1;
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write_addr = 0;
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write_data = 0;
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end
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endmodule
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