abstractaccelerator/opene906/demo/sim/riscv.cfg

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# "JTAG adapter" for simulation, exposed to OpenOCD through a TCP socket
# speaking the remote_bitbang protocol. The adapter is implemented as
# SystemVerilog DPI module.
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# reset_config srst_only # donot support TRST, use five tms=1
# adapter_nsrst_assert_width 100
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adapter driver remote_bitbang
remote_bitbang host localhost
remote_bitbang port 44853
# Target configuration for the riscv chip
set _CHIPNAME riscv
set _TARGETNAME $_CHIPNAME.tap
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jtag newtap $_CHIPNAME tap -irlen 5 -expected-id 0x10000B6F
# {4'h1, 16'h0, 12'b1011_011_0111_1};
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target create $_TARGETNAME riscv -chain-position $_TARGETNAME
# Configure work area in on-chip SRAM
# $_TARGETNAME configure -work-area-phys 0x1000e000 -work-area-size 1000 -work-area-backup 0
riscv expose_csrs 1988
# Be verbose about GDB errors
gdb_report_data_abort enable
gdb_report_register_access_error enable
# Increase timeouts in simulation
riscv set_command_timeout_sec 1200
# Conclude OpenOCD configuration
init
# Halt the target
halt