abstractaccelerator/opene906/demo/sim/test_soc_sim.cpp

// SPDX-License-Identifier: Apache-2.0
// Copyright 2019 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#include <stdlib.h>

#include <iostream>
#include <string>
#include <utility>

#include "Vsoc_sim.h"
#include "verilated.h"
#include "verilated_vcd_c.h"

vluint64_t main_time = 0;
const int isOpenDump = 0;

double sc_time_stamp() { return main_time; }

int main(int argc, char** argv) {
  std::cout << "\nVerilatorTB: Start of sim\n" << std::endl;

  Verilated::commandArgs(argc, argv);
  Vsoc_sim* soc = new Vsoc_sim;
  VerilatedVcdC* tfp = new VerilatedVcdC;

  if (isOpenDump) {
    Verilated::traceEverOn(true);
    soc->trace(tfp, 99);
    tfp->open("vlt_dump.vcd");
  }

  while (!Verilated::gotFinish()) {
    main_time += 5;
    soc->clk = !soc->clk;
    soc->eval();

    if (isOpenDump) {
      tfp->dump(main_time);
    }
  }

  if (isOpenDump) {
    tfp->close();
  }
  soc->final();

  std::cout << "\nVerilatorTB: End of sim" << std::endl;
  exit(EXIT_SUCCESS);
}