228 lines
6.9 KiB
Systemverilog
228 lines
6.9 KiB
Systemverilog
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2020 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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module soc_sim (
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input bit core_clk
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);
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logic rst_l;
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logic dbg_rst_l;
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wire jtag_tdo;
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wire jtag_tck;
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wire jtag_tms;
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wire jtag_tdi;
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wire jtag_trst_n;
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bit [31:0] cycleCnt;
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logic mailbox_data_val;
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int commit_count;
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logic wb_valid [1:0 ];
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logic [ 4:0] wb_dest [1:0 ];
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logic [31:0] wb_data [1:0 ];
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wire [63:0] WriteData;
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string abi_reg [ 32]; // ABI register names
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assign WriteData = rvsoc.lsu_hwdata;
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assign mailbox_data_val = WriteData[7:0] > 8'h5 && WriteData[7:0] < 8'h7f;
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parameter MAILBOX_ADDR = 32'hD0580000;
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logic write;
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logic [31:0] laddr;
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wire mailbox_write = write && laddr == MAILBOX_ADDR;
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always @(posedge core_clk or negedge rst_l) begin
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if (~rst_l) begin
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laddr <= 32'b0;
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write <= 1'b0;
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end else begin
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if (rvsoc.lsu_hready) begin
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laddr <= rvsoc.lsu_haddr;
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write <= rvsoc.lsu_hwrite & |rvsoc.lsu_htrans;
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end
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end
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end
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parameter MAX_CYCLES = 10_000_000_0;
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integer fd, tp, el;
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always @(posedge core_clk) begin
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cycleCnt <= cycleCnt + 1;
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if (cycleCnt == MAX_CYCLES) begin
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$display("Hit max cycle count (%0d) .. stopping", cycleCnt);
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$finish;
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end
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if (mailbox_data_val & mailbox_write) begin
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$fwrite(fd, "%c", WriteData[7:0]);
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$write("%c", WriteData[7:0]);
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end
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if (mailbox_write && WriteData[7:0] == 8'hff) begin
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$display("\nFinished : minstret = %0d, mcycle = %0d",
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rvsoc.rvtop.swerv.dec.tlu.minstretl[31:0],
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rvsoc.rvtop.swerv.dec.tlu.mcyclel[31:0]);
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$display(
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"See \"exec.log\" for execution trace with register updates..\n");
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$display("TEST_PASSED");
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$finish;
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end else if (mailbox_write && WriteData[7:0] == 8'h1) begin
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$display("TEST_FAILED");
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$finish;
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end
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end
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// trace monitor
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always @(posedge core_clk) begin
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wb_valid[1:0] <= '{
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rvsoc.rvtop.swerv.dec.dec_i1_wen_wb,
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rvsoc.rvtop.swerv.dec.dec_i0_wen_wb
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};
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wb_dest[1:0] <= '{
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rvsoc.rvtop.swerv.dec.dec_i1_waddr_wb,
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rvsoc.rvtop.swerv.dec.dec_i0_waddr_wb
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};
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wb_data[1:0] <= '{
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rvsoc.rvtop.swerv.dec.dec_i1_wdata_wb,
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rvsoc.rvtop.swerv.dec.dec_i0_wdata_wb
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};
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if (rvsoc.trace_rv_i_valid_ip !== 0) begin
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$fwrite(tp, "%b,%h,%h,%0h,%0h,3,%b,%h,%h,%b\n", rvsoc.trace_rv_i_valid_ip,
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rvsoc.trace_rv_i_address_ip[63:32],
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rvsoc.trace_rv_i_address_ip[31:0],
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rvsoc.trace_rv_i_insn_ip[63:32], rvsoc.trace_rv_i_insn_ip[31:0],
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rvsoc.trace_rv_i_exception_ip, rvsoc.trace_rv_i_ecause_ip,
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rvsoc.trace_rv_i_tval_ip, rvsoc.trace_rv_i_interrupt_ip);
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// Basic trace - no exception register updates
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// #1 0 ee000000 b0201073 c 0b02 00000000
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for (int i = 0; i < 2; i++)
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if (rvsoc.trace_rv_i_valid_ip[i] == 1) begin
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commit_count++;
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$fwrite(el, "%10d : %8s %0d %h %h%13s ; %s\n", cycleCnt, $sformatf(
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"#%0d", commit_count), 0,
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rvsoc.trace_rv_i_address_ip[31+i*32-:32],
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rvsoc.trace_rv_i_insn_ip[31+i*32-:32],
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(wb_dest[i] != 0 && wb_valid[i]) ? $sformatf(
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"%s=%h", abi_reg[wb_dest[i]], wb_data[i]) : " ",
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dasm(
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rvsoc.trace_rv_i_insn_ip[31+i*32-:32],
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rvsoc.trace_rv_i_address_ip[31+i*32-:32],
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wb_dest[i] & {5{wb_valid[i]}},
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wb_data[i]
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));
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end
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end
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if (rvsoc.rvtop.swerv.dec.dec_nonblock_load_wen) begin
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$fwrite(el, "%10d : %10d%22s=%h ; nbL\n", cycleCnt, 0,
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abi_reg[rvsoc.rvtop.swerv.dec.dec_nonblock_load_waddr],
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rvsoc.rvtop.swerv.dec.lsu_nonblock_load_data);
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soc_sim.gpr[0][rvsoc.rvtop.swerv.dec.dec_nonblock_load_waddr] = rvsoc.rvtop.swerv.dec.lsu_nonblock_load_data;
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end
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end
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initial begin
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abi_reg[0] = "zero";
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abi_reg[1] = "ra";
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abi_reg[2] = "sp";
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abi_reg[3] = "gp";
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abi_reg[4] = "tp";
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abi_reg[5] = "t0";
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abi_reg[6] = "t1";
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abi_reg[7] = "t2";
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abi_reg[8] = "s0";
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abi_reg[9] = "s1";
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abi_reg[10] = "a0";
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abi_reg[11] = "a1";
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abi_reg[12] = "a2";
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abi_reg[13] = "a3";
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abi_reg[14] = "a4";
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abi_reg[15] = "a5";
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abi_reg[16] = "a6";
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abi_reg[17] = "a7";
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abi_reg[18] = "s2";
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abi_reg[19] = "s3";
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abi_reg[20] = "s4";
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abi_reg[21] = "s5";
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abi_reg[22] = "s6";
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abi_reg[23] = "s7";
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abi_reg[24] = "s8";
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abi_reg[25] = "s9";
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abi_reg[26] = "s10";
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abi_reg[27] = "s11";
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abi_reg[28] = "t3";
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abi_reg[29] = "t4";
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abi_reg[30] = "t5";
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abi_reg[31] = "t6";
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tp = $fopen("trace_port.csv", "w");
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el = $fopen("exec.log", "w");
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$fwrite(
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el,
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"// Cycle : #inst hart pc opcode reg=value ; mnemonic\n");
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$fwrite(
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el,
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"//---------------------------------------------------------------\n");
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fd = $fopen("console.log", "w");
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commit_count = 0;
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end
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assign rst_l = cycleCnt > 5;
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assign dbg_rst_l = cycleCnt > 2;
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soc_top rvsoc (
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.clk(core_clk),
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.rst(rst_l),
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.dbg_rst(dbg_rst_l),
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.jtag_tdo(jtag_tdo),
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.jtag_tck(jtag_tck),
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.jtag_tms(jtag_tms),
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.jtag_tdi(jtag_tdi),
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.jtag_trst_n(jtag_trst_n)
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);
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jtagdpi jtagdpi (
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.clk_i (core_clk),
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.rst_ni(rst_l),
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.jtag_tck(jtag_tck),
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.jtag_tms(jtag_tms),
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.jtag_tdi(jtag_tdi),
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.jtag_tdo(jtag_tdo),
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.jtag_trst_n(jtag_trst_n),
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.jtag_srst_n()
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);
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`define DRAM(bank) \
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rvsoc.rvtop.mem.Gen_dccm_enable.dccm.mem_bank[bank].dccm_bank.ram_core
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`define ICCM_PATH `RV_TOP.mem.iccm
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`define IRAM0(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_lo0.ram_core
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`define IRAM1(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_lo1.ram_core
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`define IRAM2(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_hi0.ram_core
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`define IRAM3(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_hi1.ram_core
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/* verilator lint_off WIDTH */
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/* verilator lint_off CASEINCOMPLETE */
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`include "dasm.svi"
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/* verilator lint_on CASEINCOMPLETE */
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/* verilator lint_on WIDTH */
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endmodule
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