37 lines
1.4 KiB
Markdown
37 lines
1.4 KiB
Markdown
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# SweRV RISC-V Core<sup>TM</sup> 1.1 from Western Digital
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## Release Notes
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1. SWERV core RISCV compatibility improvements
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* Illegal instructions no longer increment minstret
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* Debug single-step command no longer executes multiple instructions
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* For instructions, MTVAL register holds the address that actually
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triggered an access fault
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* DICAD1 debug CSR ECC read size enhancements
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1. SWERV core performance enhancements
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* Improved instruction fetch unit external memory access performance
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* Instruction fetcher no longer stalls due to DMA ICCM requests
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* Improved performance of streaming stores
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* Improved performance of divide instruction
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* Improved I/O Timing
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* Non-idempotent Ld/St changed to non-posted in MFDC
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* DMA QoS Configurable in MFDC
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1. SWERV core miscellaneous changes
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* Non-word access to PIC memory generates access-error
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* Improved streaming performance with unified read/write buffer
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* Non-idempotent load enhancements
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* Debug, single-step, and trigger enhancements
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* DMA, IFU, and LSU interaction enhancements
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* Bus error handling improvements
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* DMA h-ready addition
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* DMA slave error response enhancements
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1. Added memory protection regions
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* Now able to define up to eight instruction fetch windows and up to eight
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data load/store windows. See the programmer reference manual for more
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details.
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