abstractaccelerator/Cores-SweRV/soc/soc_top.sv

// SPDX-License-Identifier: Apache-2.0
// Copyright 2020 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//

module soc_top (
    input  clk,
    input  dbg_rst,
    input  rst,
    output jtag_tdo,
    input  jtag_tck,
    input  jtag_tms,
    input  jtag_tdi,
    input  jtag_trst_n
);

  logic                       nmi_int;

  logic [               31:0] reset_vector;
  logic [               31:0] nmi_vector;
  logic [               31:1] jtag_id;

  logic [               31:0] ic_haddr;
  logic [                2:0] ic_hburst;
  logic                       ic_hmastlock;
  logic [                3:0] ic_hprot;
  logic [                2:0] ic_hsize;
  logic [                1:0] ic_htrans;
  logic                       ic_hwrite;
  logic [               63:0] ic_hrdata;
  logic                       ic_hready;
  logic                       ic_hresp;

  logic [               31:0] lsu_haddr;
  logic [                2:0] lsu_hburst;
  logic                       lsu_hmastlock;
  logic [                3:0] lsu_hprot;
  logic [                2:0] lsu_hsize;
  logic [                1:0] lsu_htrans;
  logic                       lsu_hwrite;
  logic [               63:0] lsu_hrdata;
  logic [               63:0] lsu_hwdata;
  logic                       lsu_hready;
  logic                       lsu_hresp;

  logic [               31:0] sb_haddr;
  logic [                2:0] sb_hburst;
  logic                       sb_hmastlock;
  logic [                3:0] sb_hprot;
  logic [                2:0] sb_hsize;
  logic [                1:0] sb_htrans;
  logic                       sb_hwrite;

  logic [               63:0] sb_hrdata;
  logic [               63:0] sb_hwdata;
  logic                       sb_hready;
  logic                       sb_hresp;

  logic [               63:0] trace_rv_i_insn_ip;
  logic [               63:0] trace_rv_i_address_ip;
  logic [                2:0] trace_rv_i_valid_ip;
  logic [                2:0] trace_rv_i_exception_ip;
  logic [                4:0] trace_rv_i_ecause_ip;
  logic [                2:0] trace_rv_i_interrupt_ip;
  logic [               31:0] trace_rv_i_tval_ip;

  logic                       o_debug_mode_status;
  logic [                1:0] dec_tlu_perfcnt0;
  logic [                1:0] dec_tlu_perfcnt1;
  logic [                1:0] dec_tlu_perfcnt2;
  logic [                1:0] dec_tlu_perfcnt3;

  logic                       o_cpu_halt_ack;
  logic                       o_cpu_halt_status;
  logic                       o_cpu_run_ack;

  logic                       mailbox_write;
  logic [               63:0] dma_hrdata;
  logic [               63:0] dma_hwdata;
  logic                       dma_hready;
  logic                       dma_hresp;

  logic                       mpc_debug_halt_req;
  logic                       mpc_debug_run_req;
  logic                       mpc_reset_run_req;
  logic                       mpc_debug_halt_ack;
  logic                       mpc_debug_run_ack;
  logic                       debug_brkpt_status;

  wire                        dma_hready_out;


  //-------------------------- LSU AXI signals--------------------------
  // AXI Write Channels
  wire                        lsu_axi_awvalid;
  wire                        lsu_axi_awready;
  wire  [`RV_LSU_BUS_TAG-1:0] lsu_axi_awid;
  wire  [               31:0] lsu_axi_awaddr;
  wire  [                3:0] lsu_axi_awregion;
  wire  [                7:0] lsu_axi_awlen;
  wire  [                2:0] lsu_axi_awsize;
  wire  [                1:0] lsu_axi_awburst;
  wire                        lsu_axi_awlock;
  wire  [                3:0] lsu_axi_awcache;
  wire  [                2:0] lsu_axi_awprot;
  wire  [                3:0] lsu_axi_awqos;

  wire                        lsu_axi_wvalid;
  wire                        lsu_axi_wready;
  wire  [               63:0] lsu_axi_wdata;
  wire  [                7:0] lsu_axi_wstrb;
  wire                        lsu_axi_wlast;

  wire                        lsu_axi_bvalid;
  wire                        lsu_axi_bready;
  wire  [                1:0] lsu_axi_bresp;
  wire  [`RV_LSU_BUS_TAG-1:0] lsu_axi_bid;

  // AXI Read Channels
  wire                        lsu_axi_arvalid;
  wire                        lsu_axi_arready;
  wire  [`RV_LSU_BUS_TAG-1:0] lsu_axi_arid;
  wire  [               31:0] lsu_axi_araddr;
  wire  [                3:0] lsu_axi_arregion;
  wire  [                7:0] lsu_axi_arlen;
  wire  [                2:0] lsu_axi_arsize;
  wire  [                1:0] lsu_axi_arburst;
  wire                        lsu_axi_arlock;
  wire  [                3:0] lsu_axi_arcache;
  wire  [                2:0] lsu_axi_arprot;
  wire  [                3:0] lsu_axi_arqos;

  wire                        lsu_axi_rvalid;
  wire                        lsu_axi_rready;
  wire  [`RV_LSU_BUS_TAG-1:0] lsu_axi_rid;
  wire  [               63:0] lsu_axi_rdata;
  wire  [                1:0] lsu_axi_rresp;
  wire                        lsu_axi_rlast;

  //-------------------------- IFU AXI signals--------------------------
  // AXI Write Channels
  wire                        ifu_axi_awvalid;
  wire                        ifu_axi_awready;
  wire  [`RV_IFU_BUS_TAG-1:0] ifu_axi_awid;
  wire  [               31:0] ifu_axi_awaddr;
  wire  [                3:0] ifu_axi_awregion;
  wire  [                7:0] ifu_axi_awlen;
  wire  [                2:0] ifu_axi_awsize;
  wire  [                1:0] ifu_axi_awburst;
  wire                        ifu_axi_awlock;
  wire  [                3:0] ifu_axi_awcache;
  wire  [                2:0] ifu_axi_awprot;
  wire  [                3:0] ifu_axi_awqos;

  wire                        ifu_axi_wvalid;
  wire                        ifu_axi_wready;
  wire  [               63:0] ifu_axi_wdata;
  wire  [                7:0] ifu_axi_wstrb;
  wire                        ifu_axi_wlast;

  wire                        ifu_axi_bvalid;
  wire                        ifu_axi_bready;
  wire  [                1:0] ifu_axi_bresp;
  wire  [`RV_IFU_BUS_TAG-1:0] ifu_axi_bid;

  // AXI Read Channels
  wire                        ifu_axi_arvalid;
  wire                        ifu_axi_arready;
  wire  [`RV_IFU_BUS_TAG-1:0] ifu_axi_arid;
  wire  [               31:0] ifu_axi_araddr;
  wire  [                3:0] ifu_axi_arregion;
  wire  [                7:0] ifu_axi_arlen;
  wire  [                2:0] ifu_axi_arsize;
  wire  [                1:0] ifu_axi_arburst;
  wire                        ifu_axi_arlock;
  wire  [                3:0] ifu_axi_arcache;
  wire  [                2:0] ifu_axi_arprot;
  wire  [                3:0] ifu_axi_arqos;

  wire                        ifu_axi_rvalid;
  wire                        ifu_axi_rready;
  wire  [`RV_IFU_BUS_TAG-1:0] ifu_axi_rid;
  wire  [               63:0] ifu_axi_rdata;
  wire  [                1:0] ifu_axi_rresp;
  wire                        ifu_axi_rlast;

  //-------------------------- SB AXI signals--------------------------
  // AXI Write Channels
  wire                        sb_axi_awvalid;
  wire                        sb_axi_awready;
  wire  [ `RV_SB_BUS_TAG-1:0] sb_axi_awid;
  wire  [               31:0] sb_axi_awaddr;
  wire  [                3:0] sb_axi_awregion;
  wire  [                7:0] sb_axi_awlen;
  wire  [                2:0] sb_axi_awsize;
  wire  [                1:0] sb_axi_awburst;
  wire                        sb_axi_awlock;
  wire  [                3:0] sb_axi_awcache;
  wire  [                2:0] sb_axi_awprot;
  wire  [                3:0] sb_axi_awqos;

  wire                        sb_axi_wvalid;
  wire                        sb_axi_wready;
  wire  [               63:0] sb_axi_wdata;
  wire  [                7:0] sb_axi_wstrb;
  wire                        sb_axi_wlast;

  wire                        sb_axi_bvalid;
  wire                        sb_axi_bready;
  wire  [                1:0] sb_axi_bresp;
  wire  [ `RV_SB_BUS_TAG-1:0] sb_axi_bid;

  // AXI Read Channels
  wire                        sb_axi_arvalid;
  wire                        sb_axi_arready;
  wire  [ `RV_SB_BUS_TAG-1:0] sb_axi_arid;
  wire  [               31:0] sb_axi_araddr;
  wire  [                3:0] sb_axi_arregion;
  wire  [                7:0] sb_axi_arlen;
  wire  [                2:0] sb_axi_arsize;
  wire  [                1:0] sb_axi_arburst;
  wire                        sb_axi_arlock;
  wire  [                3:0] sb_axi_arcache;
  wire  [                2:0] sb_axi_arprot;
  wire  [                3:0] sb_axi_arqos;

  wire                        sb_axi_rvalid;
  wire                        sb_axi_rready;
  wire  [ `RV_SB_BUS_TAG-1:0] sb_axi_rid;
  wire  [               63:0] sb_axi_rdata;
  wire  [                1:0] sb_axi_rresp;
  wire                        sb_axi_rlast;

  //-------------------------- DMA AXI signals--------------------------
  // AXI Write Channels
  wire                        dma_axi_awvalid;
  wire                        dma_axi_awready;
  wire  [`RV_DMA_BUS_TAG-1:0] dma_axi_awid;
  wire  [               31:0] dma_axi_awaddr;
  wire  [                2:0] dma_axi_awsize;
  wire  [                2:0] dma_axi_awprot;
  wire  [                7:0] dma_axi_awlen;
  wire  [                1:0] dma_axi_awburst;


  wire                        dma_axi_wvalid;
  wire                        dma_axi_wready;
  wire  [               63:0] dma_axi_wdata;
  wire  [                7:0] dma_axi_wstrb;
  wire                        dma_axi_wlast;

  wire                        dma_axi_bvalid;
  wire                        dma_axi_bready;
  wire  [                1:0] dma_axi_bresp;
  wire  [`RV_DMA_BUS_TAG-1:0] dma_axi_bid;

  // AXI Read Channels
  wire                        dma_axi_arvalid;
  wire                        dma_axi_arready;
  wire  [`RV_DMA_BUS_TAG-1:0] dma_axi_arid;
  wire  [               31:0] dma_axi_araddr;
  wire  [                2:0] dma_axi_arsize;
  wire  [                2:0] dma_axi_arprot;
  wire  [                7:0] dma_axi_arlen;
  wire  [                1:0] dma_axi_arburst;

  wire                        dma_axi_rvalid;
  wire                        dma_axi_rready;
  wire  [`RV_DMA_BUS_TAG-1:0] dma_axi_rid;
  wire  [               63:0] dma_axi_rdata;
  wire  [                1:0] dma_axi_rresp;
  wire                        dma_axi_rlast;

  wire                        lmem_axi_arvalid;
  wire                        lmem_axi_arready;

  wire                        lmem_axi_rvalid;
  wire  [`RV_LSU_BUS_TAG-1:0] lmem_axi_rid;
  wire  [                1:0] lmem_axi_rresp;
  wire  [               63:0] lmem_axi_rdata;
  wire                        lmem_axi_rlast;
  wire                        lmem_axi_rready;

  wire                        lmem_axi_awvalid;
  wire                        lmem_axi_awready;

  wire                        lmem_axi_wvalid;
  wire                        lmem_axi_wready;

  wire  [                1:0] lmem_axi_bresp;
  wire                        lmem_axi_bvalid;
  wire  [`RV_LSU_BUS_TAG-1:0] lmem_axi_bid;
  wire                        lmem_axi_bready;


  initial begin
    jtag_id[31:28] = 4'b1;
    jtag_id[27:12] = '0;
    jtag_id[11:1] = 11'h45;
    reset_vector = 32'h0;
    nmi_vector = 32'hee000000;
    nmi_int = 0;

    $readmemh("program.hex", lmem.mem);
    $readmemh("program.hex", imem.mem);

  end

  swerv_wrapper rvtop (
      .rst_l    (rst),
      .dbg_rst_l(dbg_rst),
      .clk      (clk),
      .rst_vec  (reset_vector[31:1]),
      .nmi_int  (nmi_int),
      .nmi_vec  (nmi_vector[31:1]),
      .jtag_id  (jtag_id[31:1]),

      //-------------------------- LSU AXI signals--------------------------
      // AXI Write Channels
      .lsu_axi_awvalid (lsu_axi_awvalid),
      .lsu_axi_awready (lsu_axi_awready),
      .lsu_axi_awid    (lsu_axi_awid),
      .lsu_axi_awaddr  (lsu_axi_awaddr),
      .lsu_axi_awregion(lsu_axi_awregion),
      .lsu_axi_awlen   (lsu_axi_awlen),
      .lsu_axi_awsize  (lsu_axi_awsize),
      .lsu_axi_awburst (lsu_axi_awburst),
      .lsu_axi_awlock  (lsu_axi_awlock),
      .lsu_axi_awcache (lsu_axi_awcache),
      .lsu_axi_awprot  (lsu_axi_awprot),
      .lsu_axi_awqos   (lsu_axi_awqos),

      .lsu_axi_wvalid(lsu_axi_wvalid),
      .lsu_axi_wready(lsu_axi_wready),
      .lsu_axi_wdata (lsu_axi_wdata),
      .lsu_axi_wstrb (lsu_axi_wstrb),
      .lsu_axi_wlast (lsu_axi_wlast),

      .lsu_axi_bvalid(lsu_axi_bvalid),
      .lsu_axi_bready(lsu_axi_bready),
      .lsu_axi_bresp (lsu_axi_bresp),
      .lsu_axi_bid   (lsu_axi_bid),


      .lsu_axi_arvalid (lsu_axi_arvalid),
      .lsu_axi_arready (lsu_axi_arready),
      .lsu_axi_arid    (lsu_axi_arid),
      .lsu_axi_araddr  (lsu_axi_araddr),
      .lsu_axi_arregion(lsu_axi_arregion),
      .lsu_axi_arlen   (lsu_axi_arlen),
      .lsu_axi_arsize  (lsu_axi_arsize),
      .lsu_axi_arburst (lsu_axi_arburst),
      .lsu_axi_arlock  (lsu_axi_arlock),
      .lsu_axi_arcache (lsu_axi_arcache),
      .lsu_axi_arprot  (lsu_axi_arprot),
      .lsu_axi_arqos   (lsu_axi_arqos),

      .lsu_axi_rvalid(lsu_axi_rvalid),
      .lsu_axi_rready(lsu_axi_rready),
      .lsu_axi_rid   (lsu_axi_rid),
      .lsu_axi_rdata (lsu_axi_rdata),
      .lsu_axi_rresp (lsu_axi_rresp),
      .lsu_axi_rlast (lsu_axi_rlast),

      //-------------------------- IFU AXI signals--------------------------
      // AXI Write Channels
      .ifu_axi_awvalid (ifu_axi_awvalid),
      .ifu_axi_awready (ifu_axi_awready),
      .ifu_axi_awid    (ifu_axi_awid),
      .ifu_axi_awaddr  (ifu_axi_awaddr),
      .ifu_axi_awregion(ifu_axi_awregion),
      .ifu_axi_awlen   (ifu_axi_awlen),
      .ifu_axi_awsize  (ifu_axi_awsize),
      .ifu_axi_awburst (ifu_axi_awburst),
      .ifu_axi_awlock  (ifu_axi_awlock),
      .ifu_axi_awcache (ifu_axi_awcache),
      .ifu_axi_awprot  (ifu_axi_awprot),
      .ifu_axi_awqos   (ifu_axi_awqos),

      .ifu_axi_wvalid(ifu_axi_wvalid),
      .ifu_axi_wready(ifu_axi_wready),
      .ifu_axi_wdata (ifu_axi_wdata),
      .ifu_axi_wstrb (ifu_axi_wstrb),
      .ifu_axi_wlast (ifu_axi_wlast),

      .ifu_axi_bvalid(ifu_axi_bvalid),
      .ifu_axi_bready(ifu_axi_bready),
      .ifu_axi_bresp (ifu_axi_bresp),
      .ifu_axi_bid   (ifu_axi_bid),

      .ifu_axi_arvalid (ifu_axi_arvalid),
      .ifu_axi_arready (ifu_axi_arready),
      .ifu_axi_arid    (ifu_axi_arid),
      .ifu_axi_araddr  (ifu_axi_araddr),
      .ifu_axi_arregion(ifu_axi_arregion),
      .ifu_axi_arlen   (ifu_axi_arlen),
      .ifu_axi_arsize  (ifu_axi_arsize),
      .ifu_axi_arburst (ifu_axi_arburst),
      .ifu_axi_arlock  (ifu_axi_arlock),
      .ifu_axi_arcache (ifu_axi_arcache),
      .ifu_axi_arprot  (ifu_axi_arprot),
      .ifu_axi_arqos   (ifu_axi_arqos),

      .ifu_axi_rvalid(ifu_axi_rvalid),
      .ifu_axi_rready(ifu_axi_rready),
      .ifu_axi_rid   (ifu_axi_rid),
      .ifu_axi_rdata (ifu_axi_rdata),
      .ifu_axi_rresp (ifu_axi_rresp),
      .ifu_axi_rlast (ifu_axi_rlast),

      //-------------------------- SB AXI signals--------------------------
      // AXI Write Channels
      .sb_axi_awvalid (sb_axi_awvalid),
      .sb_axi_awready (sb_axi_awready),
      .sb_axi_awid    (sb_axi_awid),
      .sb_axi_awaddr  (sb_axi_awaddr),
      .sb_axi_awregion(sb_axi_awregion),
      .sb_axi_awlen   (sb_axi_awlen),
      .sb_axi_awsize  (sb_axi_awsize),
      .sb_axi_awburst (sb_axi_awburst),
      .sb_axi_awlock  (sb_axi_awlock),
      .sb_axi_awcache (sb_axi_awcache),
      .sb_axi_awprot  (sb_axi_awprot),
      .sb_axi_awqos   (sb_axi_awqos),

      .sb_axi_wvalid(sb_axi_wvalid),
      .sb_axi_wready(sb_axi_wready),
      .sb_axi_wdata (sb_axi_wdata),
      .sb_axi_wstrb (sb_axi_wstrb),
      .sb_axi_wlast (sb_axi_wlast),

      .sb_axi_bvalid(sb_axi_bvalid),
      .sb_axi_bready(sb_axi_bready),
      .sb_axi_bresp (sb_axi_bresp),
      .sb_axi_bid   (sb_axi_bid),


      .sb_axi_arvalid (sb_axi_arvalid),
      .sb_axi_arready (sb_axi_arready),
      .sb_axi_arid    (sb_axi_arid),
      .sb_axi_araddr  (sb_axi_araddr),
      .sb_axi_arregion(sb_axi_arregion),
      .sb_axi_arlen   (sb_axi_arlen),
      .sb_axi_arsize  (sb_axi_arsize),
      .sb_axi_arburst (sb_axi_arburst),
      .sb_axi_arlock  (sb_axi_arlock),
      .sb_axi_arcache (sb_axi_arcache),
      .sb_axi_arprot  (sb_axi_arprot),
      .sb_axi_arqos   (sb_axi_arqos),

      .sb_axi_rvalid(sb_axi_rvalid),
      .sb_axi_rready(sb_axi_rready),
      .sb_axi_rid   (sb_axi_rid),
      .sb_axi_rdata (sb_axi_rdata),
      .sb_axi_rresp (sb_axi_rresp),
      .sb_axi_rlast (sb_axi_rlast),

      //-------------------------- DMA AXI signals--------------------------
      // AXI Write Channels
      .dma_axi_awvalid(dma_axi_awvalid),
      .dma_axi_awready(dma_axi_awready),
      .dma_axi_awid           ('0),               // ids are not used on DMA since it always responses in order
      .dma_axi_awaddr(lsu_axi_awaddr),
      .dma_axi_awsize(lsu_axi_awsize),
      .dma_axi_awprot('0),
      .dma_axi_awlen('0),
      .dma_axi_awburst('0),


      .dma_axi_wvalid(dma_axi_wvalid),
      .dma_axi_wready(dma_axi_wready),
      .dma_axi_wdata (lsu_axi_wdata),
      .dma_axi_wstrb (lsu_axi_wstrb),
      .dma_axi_wlast (1'b1),

      .dma_axi_bvalid(dma_axi_bvalid),
      .dma_axi_bready(dma_axi_bready),
      .dma_axi_bresp (dma_axi_bresp),
      .dma_axi_bid   (),


      .dma_axi_arvalid(dma_axi_arvalid),
      .dma_axi_arready(dma_axi_arready),
      .dma_axi_arid   ('0),
      .dma_axi_araddr (lsu_axi_araddr),
      .dma_axi_arsize (lsu_axi_arsize),
      .dma_axi_arprot ('0),
      .dma_axi_arlen  ('0),
      .dma_axi_arburst('0),

      .dma_axi_rvalid(dma_axi_rvalid),
      .dma_axi_rready(dma_axi_rready),
      .dma_axi_rid   (),
      .dma_axi_rdata (dma_axi_rdata),
      .dma_axi_rresp (dma_axi_rresp),
      .dma_axi_rlast (dma_axi_rlast),


      .timer_int    (1'b0),
      .extintsrc_req('0),

      .lsu_bus_clk_en(1'b1),
      .ifu_bus_clk_en(1'b1),
      .dbg_bus_clk_en(1'b1),
      .dma_bus_clk_en(1'b1),

      .trace_rv_i_insn_ip     (trace_rv_i_insn_ip),
      .trace_rv_i_address_ip  (trace_rv_i_address_ip),
      .trace_rv_i_valid_ip    (trace_rv_i_valid_ip),
      .trace_rv_i_exception_ip(trace_rv_i_exception_ip),
      .trace_rv_i_ecause_ip   (trace_rv_i_ecause_ip),
      .trace_rv_i_interrupt_ip(trace_rv_i_interrupt_ip),
      .trace_rv_i_tval_ip     (trace_rv_i_tval_ip),

      .jtag_tck   (jtag_tck),
      .jtag_tms   (jtag_tms),
      .jtag_tdi   (jtag_tdi),
      .jtag_trst_n(jtag_trst_n),
      .jtag_tdo   (jtag_tdo),

      .mpc_debug_halt_ack(mpc_debug_halt_ack),
      .mpc_debug_halt_req(1'b0),
      .mpc_debug_run_ack (mpc_debug_run_ack),
      .mpc_debug_run_req (1'b1),
      .mpc_reset_run_req (1'b1),
      .debug_brkpt_status(debug_brkpt_status),

      .i_cpu_halt_req     (1'b0),
      .o_cpu_halt_ack     (o_cpu_halt_ack),
      .o_cpu_halt_status  (o_cpu_halt_status),
      .i_cpu_run_req      (1'b0),
      .o_debug_mode_status(o_debug_mode_status),
      .o_cpu_run_ack      (o_cpu_run_ack),

      .dec_tlu_perfcnt0(dec_tlu_perfcnt0),
      .dec_tlu_perfcnt1(dec_tlu_perfcnt1),
      .dec_tlu_perfcnt2(dec_tlu_perfcnt2),
      .dec_tlu_perfcnt3(dec_tlu_perfcnt3),

      .scan_mode (1'b0),
      .mbist_mode(1'b0)

  );

  axi_slv #(
      .TAGW(`RV_IFU_BUS_TAG)
  ) imem (
      .aclk(clk),
      .rst_l(rst),
      .arvalid(ifu_axi_arvalid),
      .arready(ifu_axi_arready),
      .araddr(ifu_axi_araddr),
      .arid(ifu_axi_arid),
      .arlen(ifu_axi_arlen),
      .arburst(ifu_axi_arburst),
      .arsize(ifu_axi_arsize),

      .rvalid(ifu_axi_rvalid),
      .rready(ifu_axi_rready),
      .rdata(ifu_axi_rdata),
      .rresp(ifu_axi_rresp),
      .rid(ifu_axi_rid),
      .rlast(ifu_axi_rlast),

      .awvalid(1'b0),
      .awready(),
      .awaddr('0),
      .awid('0),
      .awlen('0),
      .awburst('0),
      .awsize('0),

      .wdata ('0),
      .wstrb ('0),
      .wvalid(1'b0),
      .wready(),

      .bvalid(),
      .bready(1'b0),
      .bresp(),
      .bid()
  );

  defparam lmem.TAGW = `RV_LSU_BUS_TAG;

  //axi_slv #(.TAGW(`RV_LSU_BUS_TAG)) lmem(
  axi_slv lmem (
      .aclk(clk),
      .rst_l(rst),
      .arvalid(lmem_axi_arvalid),
      .arready(lmem_axi_arready),
      .araddr(lsu_axi_araddr),
      .arid(lsu_axi_arid),
      .arlen(lsu_axi_arlen),
      .arburst(lsu_axi_arburst),
      .arsize(lsu_axi_arsize),

      .rvalid(lmem_axi_rvalid),
      .rready(lmem_axi_rready),
      .rdata(lmem_axi_rdata),
      .rresp(lmem_axi_rresp),
      .rid(lmem_axi_rid),
      .rlast(lmem_axi_rlast),

      .awvalid(lmem_axi_awvalid),
      .awready(lmem_axi_awready),
      .awaddr(lsu_axi_awaddr),
      .awid(lsu_axi_awid),
      .awlen(lsu_axi_awlen),
      .awburst(lsu_axi_awburst),
      .awsize(lsu_axi_awsize),

      .wdata (lsu_axi_wdata),
      .wstrb (lsu_axi_wstrb),
      .wvalid(lmem_axi_wvalid),
      .wready(lmem_axi_wready),

      .bvalid(lmem_axi_bvalid),
      .bready(lmem_axi_bready),
      .bresp(lmem_axi_bresp),
      .bid(lmem_axi_bid)
  );

  axi_lsu_dma_bridge #(`RV_LSU_BUS_TAG, `RV_LSU_BUS_TAG) bridge (
      .clk(clk),
      .reset_l(rst),

      .m_arvalid(lsu_axi_arvalid),
      .m_arid(lsu_axi_arid),
      .m_araddr(lsu_axi_araddr),
      .m_arready(lsu_axi_arready),

      .m_rvalid(lsu_axi_rvalid),
      .m_rready(lsu_axi_rready),
      .m_rdata(lsu_axi_rdata),
      .m_rid(lsu_axi_rid),
      .m_rresp(lsu_axi_rresp),
      .m_rlast(lsu_axi_rlast),

      .m_awvalid(lsu_axi_awvalid),
      .m_awid(lsu_axi_awid),
      .m_awaddr(lsu_axi_awaddr),
      .m_awready(lsu_axi_awready),

      .m_wvalid(lsu_axi_wvalid),
      .m_wready(lsu_axi_wready),

      .m_bresp(lsu_axi_bresp),
      .m_bvalid(lsu_axi_bvalid),
      .m_bid(lsu_axi_bid),
      .m_bready(lsu_axi_bready),

      .s0_arvalid(lmem_axi_arvalid),
      .s0_arready(lmem_axi_arready),

      .s0_rvalid(lmem_axi_rvalid),
      .s0_rid(lmem_axi_rid),
      .s0_rresp(lmem_axi_rresp),
      .s0_rdata(lmem_axi_rdata),
      .s0_rlast(lmem_axi_rlast),
      .s0_rready(lmem_axi_rready),

      .s0_awvalid(lmem_axi_awvalid),
      .s0_awready(lmem_axi_awready),

      .s0_wvalid(lmem_axi_wvalid),
      .s0_wready(lmem_axi_wready),
      .s0_bresp(lmem_axi_bresp),
      .s0_bvalid(lmem_axi_bvalid),
      .s0_bid(lmem_axi_bid),
      .s0_bready(lmem_axi_bready),


      .s1_arvalid(dma_axi_arvalid),
      .s1_arready(dma_axi_arready),

      .s1_rvalid(dma_axi_rvalid),
      .s1_rresp (dma_axi_rresp),
      .s1_rdata (dma_axi_rdata),
      .s1_rlast (dma_axi_rlast),
      .s1_rready(dma_axi_rready),

      .s1_awvalid(dma_axi_awvalid),
      .s1_awready(dma_axi_awready),

      .s1_wvalid(dma_axi_wvalid),
      .s1_wready(dma_axi_wready),

      .s1_bresp (dma_axi_bresp),
      .s1_bvalid(dma_axi_bvalid),
      .s1_bready(dma_axi_bready)

  );


endmodule