98 lines
2.6 KiB
Plaintext
98 lines
2.6 KiB
Plaintext
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CAPI=2:
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name : chipsalliance.org:cores:SweRV_EL2:1.3
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filesets:
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rtl:
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files:
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- design/include/el2_def.sv
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- design/lib/el2_lib.sv
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- design/lib/beh_lib.sv
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- design/el2_mem.sv
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- design/el2_pic_ctrl.sv
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- design/el2_dma_ctrl.sv
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- design/ifu/el2_ifu_aln_ctl.sv
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- design/ifu/el2_ifu_compress_ctl.sv
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- design/ifu/el2_ifu_ifc_ctl.sv
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- design/ifu/el2_ifu_bp_ctl.sv
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- design/ifu/el2_ifu_ic_mem.sv
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- design/ifu/el2_ifu_mem_ctl.sv
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- design/ifu/el2_ifu_iccm_mem.sv
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- design/ifu/el2_ifu.sv
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- design/dec/el2_dec_decode_ctl.sv
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- design/dec/el2_dec_gpr_ctl.sv
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- design/dec/el2_dec_ib_ctl.sv
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- design/dec/el2_dec_tlu_ctl.sv
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- design/dec/el2_dec_trigger.sv
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- design/dec/el2_dec.sv
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- design/exu/el2_exu_alu_ctl.sv
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- design/exu/el2_exu_mul_ctl.sv
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- design/exu/el2_exu_div_ctl.sv
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- design/exu/el2_exu.sv
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- design/lsu/el2_lsu.sv
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- design/lsu/el2_lsu_bus_buffer.sv
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- design/lsu/el2_lsu_clkdomain.sv
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- design/lsu/el2_lsu_addrcheck.sv
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- design/lsu/el2_lsu_lsc_ctl.sv
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- design/lsu/el2_lsu_stbuf.sv
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- design/lsu/el2_lsu_bus_intf.sv
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- design/lsu/el2_lsu_ecc.sv
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- design/lsu/el2_lsu_dccm_mem.sv
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- design/lsu/el2_lsu_dccm_ctl.sv
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- design/lsu/el2_lsu_trigger.sv
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- design/dbg/el2_dbg.sv
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- design/dmi/dmi_wrapper.v
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- design/dmi/dmi_jtag_to_core_sync.v
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- design/dmi/rvjtag_tap.v
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- design/lib/mem_lib.sv
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- design/el2_swerv.sv
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- design/el2_swerv_wrapper.sv
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file_type : systemVerilogSource
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vivado_tcl: {files: [tools/vivado.tcl : {file_type : tclSource}]}
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targets:
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default:
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filesets :
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- rtl
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- "tool_vivado ? (vivado_tcl)"
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lint:
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default_tool: verilator
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filesets : [rtl]
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generate : [swerv_default_config]
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tools:
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verilator :
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mode : lint-only
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toplevel : el2_swerv_wrapper
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synth:
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default_tool : vivado
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filesets : [rtl, vivado_tcl]
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generate : [swerv_default_config]
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parameters : [RV_FPGA_OPTIMIZE]
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tools:
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vivado:
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part : xc7a100tcsg324-1
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pnr : none
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toplevel : el2_swerv_wrapper
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generate:
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swerv_default_config:
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generator: swerv_el2_config
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position : first
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parameters:
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args : [-unset=assert_on]
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generators:
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swerv_el2_config:
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interpreter: python3
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command: configs/swerv_config_gen.py
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description : Create a SweRV EL2 configuration. Note! Only supports the default config
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parameters:
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RV_FPGA_OPTIMIZE:
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datatype : bool
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default : true
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description : Minimize clock gating to map better to FPGAs
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paramtype : vlogdefine
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