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Reverted change related to enum assign as it broke some Verilog tools.

This commit is contained in:
Joseph Rahmeh 2020-05-27 14:50:39 -07:00
parent 5a004dd2b6
commit 0555dd8763
1 changed files with 4 additions and 4 deletions
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8
design/ifu/ifu_ifc_ctl.sv
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@ -185,11 +185,11 @@ module ifu_ifc_ctl
//11 0-10- 01 //11 0-10- 01
//11 0-00- 11 //11 0-00- 11
assign next_state[1] = state_t'((~state[1] & state[0] & ~reset_delayed & miss_f2 & ~goto_idle) | assign next_state[1] = (~state[1] & state[0] & ~reset_delayed & miss_f2 & ~goto_idle) |
(state[1] & ~reset_delayed & ~mb_empty_mod & ~goto_idle)); (state[1] & ~reset_delayed & ~mb_empty_mod & ~goto_idle);
assign next_state[0] = state_t'((~goto_idle & leave_idle) | (state[0] & ~goto_idle) | assign next_state[0] = (~goto_idle & leave_idle) | (state[0] & ~goto_idle) |
(reset_delayed)); (reset_delayed);
assign flush_fb = exu_flush_final; assign flush_fb = exu_flush_final;