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opene906/E906_RTL_FACTORY/gen_rtl/biu/rtl/pa_ahbl_if.v Normal file
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_ahbl_if(
ahbl_bmu_dbus_acc_err,
ahbl_bmu_dbus_data,
ahbl_bmu_dbus_grnt,
ahbl_bmu_dbus_trans_cmplt,
ahbl_bmu_ibus_acc_err,
ahbl_bmu_ibus_data,
ahbl_bmu_ibus_grnt,
ahbl_bmu_ibus_trans_cmplt,
ahbl_clk_en,
ahbl_dbginfo,
ahbl_gated_clk,
ahbl_pad_haddr,
ahbl_pad_hburst,
ahbl_pad_hlock,
ahbl_pad_hprot,
ahbl_pad_hsize,
ahbl_pad_htrans,
ahbl_pad_hwdata,
ahbl_pad_hwrite,
ahbl_sysio_idle,
bmu_ahbl_dbus_acc_deny,
bmu_ahbl_dbus_addr,
bmu_ahbl_dbus_burst,
bmu_ahbl_dbus_lock,
bmu_ahbl_dbus_lrsc,
bmu_ahbl_dbus_prot,
bmu_ahbl_dbus_req,
bmu_ahbl_dbus_req_dp,
bmu_ahbl_dbus_seq,
bmu_ahbl_dbus_size,
bmu_ahbl_dbus_wdata,
bmu_ahbl_dbus_write,
bmu_ahbl_ibus_acc_deny,
bmu_ahbl_ibus_addr,
bmu_ahbl_ibus_burst,
bmu_ahbl_ibus_prot,
bmu_ahbl_ibus_req,
bmu_ahbl_ibus_req_dp,
bmu_ahbl_ibus_seq,
bmu_ahbl_ibus_size,
cpurst_b,
lsu_biu_amo_pmp_deny,
lsu_biu_async_expt_ack,
lsu_xx_flush,
pad_ahbl_hrdata,
pad_ahbl_hready,
pad_ahbl_hresp,
rtu_yy_xx_async_flush,
sysio_xx_halt_req
);
// &Ports; @24
input ahbl_gated_clk;
input bmu_ahbl_dbus_acc_deny;
input [31:0] bmu_ahbl_dbus_addr;
input [2 :0] bmu_ahbl_dbus_burst;
input bmu_ahbl_dbus_lock;
input bmu_ahbl_dbus_lrsc;
input [3 :0] bmu_ahbl_dbus_prot;
input bmu_ahbl_dbus_req;
input bmu_ahbl_dbus_req_dp;
input bmu_ahbl_dbus_seq;
input [1 :0] bmu_ahbl_dbus_size;
input [31:0] bmu_ahbl_dbus_wdata;
input bmu_ahbl_dbus_write;
input bmu_ahbl_ibus_acc_deny;
input [31:0] bmu_ahbl_ibus_addr;
input [2 :0] bmu_ahbl_ibus_burst;
input [3 :0] bmu_ahbl_ibus_prot;
input bmu_ahbl_ibus_req;
input bmu_ahbl_ibus_req_dp;
input bmu_ahbl_ibus_seq;
input [1 :0] bmu_ahbl_ibus_size;
input cpurst_b;
input lsu_biu_amo_pmp_deny;
input lsu_biu_async_expt_ack;
input lsu_xx_flush;
input [31:0] pad_ahbl_hrdata;
input pad_ahbl_hready;
input pad_ahbl_hresp;
input rtu_yy_xx_async_flush;
input sysio_xx_halt_req;
output ahbl_bmu_dbus_acc_err;
output [31:0] ahbl_bmu_dbus_data;
output ahbl_bmu_dbus_grnt;
output ahbl_bmu_dbus_trans_cmplt;
output ahbl_bmu_ibus_acc_err;
output [31:0] ahbl_bmu_ibus_data;
output ahbl_bmu_ibus_grnt;
output ahbl_bmu_ibus_trans_cmplt;
output ahbl_clk_en;
output [10:0] ahbl_dbginfo;
output [31:0] ahbl_pad_haddr;
output [2 :0] ahbl_pad_hburst;
output ahbl_pad_hlock;
output [3 :0] ahbl_pad_hprot;
output [2 :0] ahbl_pad_hsize;
output [1 :0] ahbl_pad_htrans;
output [31:0] ahbl_pad_hwdata;
output ahbl_pad_hwrite;
output ahbl_sysio_idle;
// &Regs; @25
reg [2 :0] ahblif_cur_state;
reg [2 :0] ahblif_nxt_state;
reg [2 :0] burst_cnt;
reg ibus_not_grant;
reg [1 :0] lock_cur_state;
reg [1 :0] lock_next_state;
reg [1 :0] req_mask;
reg [1 :0] req_sel;
// &Wires; @26
wire acc_err;
wire ahbl_bmu_dbus_acc_err;
wire [31:0] ahbl_bmu_dbus_data;
wire ahbl_bmu_dbus_grnt;
wire ahbl_bmu_dbus_trans_cmplt;
wire ahbl_bmu_ibus_acc_err;
wire [31:0] ahbl_bmu_ibus_data;
wire ahbl_bmu_ibus_grnt;
wire ahbl_bmu_ibus_trans_cmplt;
wire ahbl_clk_en;
wire [10:0] ahbl_dbginfo;
wire ahbl_gated_clk;
wire [31:0] ahbl_pad_haddr;
wire [2 :0] ahbl_pad_hburst;
wire ahbl_pad_hlock;
wire [3 :0] ahbl_pad_hprot;
wire [2 :0] ahbl_pad_hsize;
wire [1 :0] ahbl_pad_htrans;
wire [31:0] ahbl_pad_hwdata;
wire ahbl_pad_hwrite;
wire ahbl_sysio_idle;
wire ahblif_req_idle;
wire ahblif_req_idle_dp;
wire [31:0] bmu_ahbl_dbus_addr;
wire [2 :0] bmu_ahbl_dbus_burst;
wire bmu_ahbl_dbus_lock;
wire bmu_ahbl_dbus_lrsc;
wire [3 :0] bmu_ahbl_dbus_prot;
wire bmu_ahbl_dbus_req;
wire bmu_ahbl_dbus_req_dp;
wire bmu_ahbl_dbus_seq;
wire [1 :0] bmu_ahbl_dbus_size;
wire [31:0] bmu_ahbl_dbus_wdata;
wire bmu_ahbl_dbus_write;
wire [31:0] bmu_ahbl_ibus_addr;
wire [2 :0] bmu_ahbl_ibus_burst;
wire [3 :0] bmu_ahbl_ibus_prot;
wire bmu_ahbl_ibus_req;
wire bmu_ahbl_ibus_req_dp;
wire bmu_ahbl_ibus_seq;
wire [1 :0] bmu_ahbl_ibus_size;
wire burst_clr;
wire burst_req;
wire [31:0] bus_rdata;
wire bus_ready;
wire bus_resp;
wire [31:0] cpu_addr;
wire [2 :0] cpu_burst;
wire cpu_burst_vld;
wire cpu_lock;
wire [3 :0] cpu_prot;
wire cpu_req;
wire cpu_req_gate;
wire cpu_seq;
wire [1 :0] cpu_size;
wire [31:0] cpu_wdata;
wire cpu_write;
wire cpurst_b;
wire dbus_req;
wire dbus_sel;
wire dbus_sel_raw;
wire ibus_req;
wire ibus_sel;
wire ibus_sel_raw;
wire inc2;
wire [2 :0] init_cnt_inc;
wire lock_clr;
wire lock_cur_idle;
wire lock_req_vld;
wire lsu_biu_amo_pmp_deny;
wire lsu_biu_async_expt_ack;
wire lsu_xx_flush;
wire [31:0] pad_ahbl_hrdata;
wire pad_ahbl_hready;
wire pad_ahbl_hresp;
wire req_grnt;
wire req_last;
wire [1 :0] req_mask_raw;
wire req_mask_vld;
wire [1 :0] req_sel_dp;
wire [1 :0] req_valid;
wire [1 :0] req_valid_dp;
wire rtu_yy_xx_async_flush;
wire sysio_xx_halt_req;
wire trans_cmplt;
parameter DATA_WIDTH = 32;
//==============================================================================
//
// AHB LITE master interface FSM
//
//==============================================================================
//1. control one transfer: SINGLE
//2. generate control signals for AHB LITE control signals: HTRANS, HCTRL
//===================================================================
// parameter description
//IDLE : wait for the cpu request; when cpu has request and hready,
// control information is put on the AHB LITE in this state.
//WFD : wait for the data from the AHB LITE; if back-to-back
// transfer occur, the fsm will stay in the state.
//ERROR : wait for the second phase of the two signal error response.
//ERROR1: generate the error vld signal to cpu.
//===================================================================
parameter IDLE = 3'b000,
WFG = 3'b010,
WFD = 3'b001,
ERROR1 = 3'b110,
ERROR2 = 3'b111;
//==========================================================
// FSM main body
//==========================================================
always@(posedge ahbl_gated_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ahblif_cur_state[2:0] <= IDLE;
else
ahblif_cur_state[2:0] <= ahblif_nxt_state[2:0];
end
// &CombBeg; @64
always @( bus_ready
or cpu_req
or sysio_xx_halt_req
or bus_resp
or ahblif_cur_state[2:0]
or cpu_lock)
begin
case(ahblif_cur_state[2:0])
IDLE:
begin
if(cpu_req & !sysio_xx_halt_req) begin
if(bus_ready)
ahblif_nxt_state[2:0] = WFD;
else //no ready
ahblif_nxt_state[2:0] = WFG;
end
else //no request
ahblif_nxt_state[2:0] = IDLE;
end
WFG:
begin
if(bus_ready)
ahblif_nxt_state[2:0] = WFD;
else //no ready
ahblif_nxt_state[2:0] = WFG;
end
WFD: // in this state[2:0] AHBL wait for the data.
begin
if(bus_resp) //resp is ERROR
ahblif_nxt_state[2:0] = ERROR1;
else if(!bus_ready) //resp == OK, hready == 0
ahblif_nxt_state[2:0] = WFD;
else //resp == OK, hready == 1
begin
if(cpu_req & !cpu_lock)
ahblif_nxt_state[2:0] = WFD;
else
ahblif_nxt_state[2:0] = IDLE;
end
end
ERROR1: // error occurs
begin
if(bus_resp) // resp is ERROR
begin
if(!bus_ready) // ready == 0
ahblif_nxt_state[2:0] = ERROR1;
else
ahblif_nxt_state[2:0] = ERROR2; // bus resp is ERROR, hready == 1
end
else
ahblif_nxt_state[2:0] = ERROR2; // bus resp is ERROR, hready == 1
end
ERROR2: // error occurs
ahblif_nxt_state[2:0] = IDLE;
default:
ahblif_nxt_state[2:0] = IDLE;
endcase
// &CombEnd; @115
end
assign ahblif_req_idle_dp = (ahblif_cur_state[2:0] == IDLE) |
(ahblif_cur_state[2:0] == WFD);
assign ahblif_req_idle = (ahblif_cur_state[2:0] == IDLE) & !sysio_xx_halt_req |
(ahblif_cur_state[2:0] == WFD) & bus_ready;
//===========================================================
// BUS LOCK
//===========================================================
parameter LOCK_IDLE = 2'b00;
parameter LOCK_WFS = 2'b01;
parameter LOCK_WFC = 2'b10;
always@(posedge ahbl_gated_clk or negedge cpurst_b)
begin
if(!cpurst_b)
lock_cur_state[1:0] <= LOCK_IDLE;
else if (lsu_biu_amo_pmp_deny)
lock_cur_state[1:0] <= LOCK_IDLE;
else
lock_cur_state[1:0] <= lock_next_state[1:0];
end
assign lock_req_vld = cpu_req & cpu_lock & ahblif_req_idle & !cpu_write & !lsu_biu_amo_pmp_deny & !sysio_xx_halt_req;
// &CombBeg; @142
always @( req_grnt
or req_last
or cpu_req
or lsu_biu_async_expt_ack
or lock_req_vld
or cpu_burst_vld
or acc_err
or lsu_xx_flush
or lock_cur_state[1:0]
or rtu_yy_xx_async_flush)
begin
case(lock_cur_state[1:0])
LOCK_IDLE: begin
if (lock_req_vld)
lock_next_state[1:0] = (req_grnt & !cpu_burst_vld) ? LOCK_WFC : LOCK_WFS;
else
lock_next_state[1:0] = LOCK_IDLE;
end
LOCK_WFS: begin
if (acc_err)
lock_next_state[1:0] = LOCK_IDLE;
else if (req_grnt & req_last)
lock_next_state[1:0] = LOCK_WFC;
else
lock_next_state[1:0] = LOCK_WFS;
end
LOCK_WFC: begin
if (cpu_req & req_grnt | lsu_xx_flush | acc_err | rtu_yy_xx_async_flush | lsu_biu_async_expt_ack)
lock_next_state[1:0] = LOCK_IDLE;
else
lock_next_state[1:0] = LOCK_WFC;
end
default: lock_next_state[1:0] = LOCK_IDLE;
endcase
// &CombEnd; @166
end
assign lock_cur_idle = lock_cur_state[1:0] == LOCK_IDLE;
assign lock_clr = (lock_cur_state[1:0] == LOCK_WFC) & (cpu_req & req_grnt | acc_err | lsu_biu_async_expt_ack) |
(lock_cur_state[1:0] == LOCK_WFS) & acc_err |
!lock_cur_idle & (lsu_xx_flush |
lsu_biu_amo_pmp_deny);
assign cpu_burst_vld = cpu_burst[2:0] != 3'b000;
assign burst_req = cpu_req & cpu_burst_vld & ahblif_req_idle;
assign burst_clr = burst_req & cpu_seq & req_last | acc_err | rtu_yy_xx_async_flush & (req_mask[1:0] == 2'b10);
assign req_mask_raw[1:0] = rtu_yy_xx_async_flush & (req_valid[1:0] == 2'b01)
? 2'b0
: ~req_valid[1:0];
always@(posedge ahbl_gated_clk or negedge cpurst_b)
begin
if(!cpurst_b)
req_mask[1:0] <= 2'b0;
else if (lock_clr & !burst_req | burst_clr)
req_mask[1:0] <= 2'b0;
else if (lock_req_vld & lock_cur_idle | burst_req)
req_mask[1:0] <= req_mask_raw[1:0];
end
assign req_mask_vld = req_mask[1:0] != 2'b00;
always@(posedge ahbl_gated_clk or negedge cpurst_b)
begin
if(!cpurst_b)
burst_cnt[2:0] <= 3'b0;
else if (burst_req & !cpu_seq)
burst_cnt[2:0] <= init_cnt_inc[2:0];
else if (burst_req & burst_cnt[2:0] != 3'b0)
burst_cnt[2:0] <= burst_cnt[2:0] - 3'b001;
end
assign inc2 = cpu_burst[2:0] == 3'b001;
assign init_cnt_inc[2:0] = inc2 ? 3'b000 : 3'b110;
//assign init_cnt[2:0] = inc2 ? 3'b001 : 3'b111;
assign req_last = req_mask_vld & burst_cnt[2:0] == 3'b000;
//===========================================================
// FSM output signal
//===========================================================
// &Force("input","bmu_ahbl_dbus_acc_deny"); @212
// &Force("input","bmu_ahbl_ibus_acc_deny"); @213
always@(posedge ahbl_gated_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ibus_not_grant <= 1'b0;
else if (ibus_req & !req_grnt)
ibus_not_grant <= 1'b1;
else if (req_grnt)
ibus_not_grant <= 1'b0;
end
assign dbus_req = bmu_ahbl_dbus_req & !req_mask[0] & !ibus_not_grant;
assign ibus_req = bmu_ahbl_ibus_req & !req_mask[1] & !dbus_sel_raw;
assign cpu_req = ibus_req | dbus_req;
assign req_valid[1:0] = {ibus_req,dbus_req};
assign dbus_sel_raw = bmu_ahbl_dbus_req_dp & !req_mask[0] & !ibus_not_grant;
assign ibus_sel_raw = bmu_ahbl_ibus_req_dp & !req_mask[1] & !dbus_sel_raw;
assign req_valid_dp[1:0] = {ibus_sel_raw, dbus_sel_raw};
always@(posedge ahbl_gated_clk or negedge cpurst_b)
begin
if(!cpurst_b)
req_sel[1:0] <= 2'b0;
else if (ahblif_req_idle & cpu_req)
req_sel[1:0] <= req_valid[1:0];
end
assign req_sel_dp[1:0] = ahblif_req_idle_dp ? req_valid_dp[1:0] : req_sel[1:0];
assign dbus_sel = req_sel_dp[0];
assign ibus_sel = req_sel_dp[1];
//assign cpu_acc_deny = dbus_sel & bmu_ahbl_dbus_acc_deny
// | ibus_sel & bmu_ahbl_ibus_acc_deny
assign cpu_addr[31:0] = {32{dbus_sel}} & bmu_ahbl_dbus_addr[31:0]
| {32{ibus_sel}} & bmu_ahbl_ibus_addr[31:0];
assign cpu_prot[3:0] = {4{dbus_sel}} & bmu_ahbl_dbus_prot[3:0]
| {4{ibus_sel}} & bmu_ahbl_ibus_prot[3:0];
assign cpu_size[1:0] = {2{dbus_sel}} & bmu_ahbl_dbus_size[1:0]
| {2{ibus_sel}} & bmu_ahbl_ibus_size[1:0];
assign cpu_seq = dbus_sel & bmu_ahbl_dbus_seq
| ibus_sel & bmu_ahbl_ibus_seq;
assign cpu_burst[2:0] = {3{dbus_sel}} & bmu_ahbl_dbus_burst[2:0]
| {3{ibus_sel}} & bmu_ahbl_ibus_burst[2:0];
assign cpu_write = dbus_sel & bmu_ahbl_dbus_write;
assign cpu_wdata[DATA_WIDTH-1:0] = bmu_ahbl_dbus_wdata[DATA_WIDTH-1:0];
assign cpu_lock = dbus_sel & bmu_ahbl_dbus_lock & !bmu_ahbl_dbus_lrsc;
//assign cpu_lrsc = dbus_sel & bmu_ahbl_dbus_lrsc;
//assign cpu_amo = cpu_lock & !cpu_lrsc;
//==========================================================
// interface to AHBL
//==========================================================
//output
// &Force("output","ahbl_pad_htrans"); @279
assign ahbl_pad_htrans[1] = cpu_req & ((ahblif_cur_state[2:0]==IDLE) & !sysio_xx_halt_req |
(ahblif_cur_state[2:0]==WFD) & !cpu_lock) |
(ahblif_cur_state[2:0]==WFG);
assign ahbl_pad_htrans[0] = req_mask_vld & cpu_burst_vld & (ahblif_cur_state[2:0]==WFD);
assign ahbl_pad_haddr[31:0] = cpu_addr[31:0];
assign ahbl_pad_hwrite = cpu_write;
assign ahbl_pad_hsize[2:0] = {1'b0, cpu_size[1:0]};
assign ahbl_pad_hprot[3:0] = cpu_prot[3:0];
assign ahbl_pad_hburst[2:0] = cpu_burst[2:0];
assign ahbl_pad_hlock = ahbl_pad_htrans[1] & cpu_lock | !lock_cur_idle;
assign ahbl_pad_hwdata[DATA_WIDTH-1:0] = cpu_wdata[DATA_WIDTH-1:0];
//input
assign bus_ready = pad_ahbl_hready;
assign bus_resp = pad_ahbl_hresp;
assign bus_rdata[DATA_WIDTH-1:0] = pad_ahbl_hrdata[DATA_WIDTH-1:0];
//==============================================================================
// interface with CPU
//==============================================================================
// cpu grant singal
assign req_grnt = ((ahblif_cur_state[2:0]==IDLE && !sysio_xx_halt_req)
|| ahblif_cur_state[2:0]==WFG
|| (ahblif_cur_state[2:0]==WFD) && !cpu_lock)
&& bus_ready && !bus_resp;
// trans complete singal
assign trans_cmplt = (ahblif_cur_state[2:0]==WFD) && bus_ready && !bus_resp
|| (ahblif_cur_state[2:0]==ERROR2); //error vld
// access error valid singal
assign acc_err = (ahblif_cur_state[2:0]==ERROR2);
//==========================================================
// to BMU
//==========================================================
assign ahbl_bmu_ibus_grnt = req_sel_dp[1] & req_grnt;
assign ahbl_bmu_ibus_trans_cmplt = req_sel[1] & trans_cmplt;
assign ahbl_bmu_ibus_acc_err = req_sel[1] & acc_err;
assign ahbl_bmu_ibus_data[DATA_WIDTH-1:0] = bus_rdata[DATA_WIDTH-1:0];
assign ahbl_bmu_dbus_grnt = req_sel_dp[0] & req_grnt;
assign ahbl_bmu_dbus_trans_cmplt = req_sel[0] & trans_cmplt;
assign ahbl_bmu_dbus_acc_err = req_sel[0] & acc_err;
assign ahbl_bmu_dbus_data[DATA_WIDTH-1:0] = bus_rdata[DATA_WIDTH-1:0];
//==========================================================
// BIU CLK EN
//==========================================================
assign cpu_req_gate = bmu_ahbl_dbus_req_dp |
bmu_ahbl_ibus_req_dp;
assign ahbl_clk_en = !(ahblif_cur_state[2:0]==IDLE) | cpu_req_gate |
!(lock_cur_state[1:0]==LOCK_IDLE) |
rtu_yy_xx_async_flush;
assign ahbl_sysio_idle = (ahblif_cur_state[2:0]==IDLE);
assign ahbl_dbginfo[10:0] = {burst_cnt[2:0],1'b0,req_mask[1:0],lock_cur_state[1:0],ahblif_cur_state[2:0]};
// &Force("nonport", "dbus_ibus_cmpt"); @386
// &Force("nonport", "ibus_req_reg"); @387
// &ModuleEnd; @390
endmodule

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opene906/E906_RTL_FACTORY/gen_rtl/biu/rtl/pa_ahbl_if_fo.v Normal file
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_ahbl_if_fo(
ahbl_bmu_dbus_acc_err,
ahbl_bmu_dbus_data,
ahbl_bmu_dbus_grnt,
ahbl_bmu_dbus_trans_cmplt,
ahbl_bmu_ibus_acc_err,
ahbl_bmu_ibus_data,
ahbl_bmu_ibus_grnt,
ahbl_bmu_ibus_trans_cmplt,
ahbl_clk_en,
ahbl_dbginfo,
ahbl_gated_clk,
ahbl_pad_haddr,
ahbl_pad_hburst,
ahbl_pad_hlock,
ahbl_pad_hprot,
ahbl_pad_hsize,
ahbl_pad_htrans,
ahbl_pad_hwdata,
ahbl_pad_hwrite,
ahbl_sysio_idle,
bmu_ahbl_dbus_acc_deny,
bmu_ahbl_dbus_addr,
bmu_ahbl_dbus_burst,
bmu_ahbl_dbus_lock,
bmu_ahbl_dbus_lrsc,
bmu_ahbl_dbus_prot,
bmu_ahbl_dbus_req,
bmu_ahbl_dbus_req_dp,
bmu_ahbl_dbus_seq,
bmu_ahbl_dbus_size,
bmu_ahbl_dbus_wdata,
bmu_ahbl_dbus_write,
bmu_ahbl_ibus_acc_deny,
bmu_ahbl_ibus_addr,
bmu_ahbl_ibus_burst,
bmu_ahbl_ibus_prot,
bmu_ahbl_ibus_req,
bmu_ahbl_ibus_req_dp,
bmu_ahbl_ibus_seq,
bmu_ahbl_ibus_size,
clk_en,
cpurst_b,
lsu_biu_amo_pmp_deny,
lsu_biu_async_expt_ack,
lsu_xx_flush,
lsu_xx_warm_up,
pad_ahbl_hrdata,
pad_ahbl_hready,
pad_ahbl_hresp,
sysio_xx_halt_req
);
// &Ports; @24
input ahbl_gated_clk;
input bmu_ahbl_dbus_acc_deny;
input [31:0] bmu_ahbl_dbus_addr;
input [2 :0] bmu_ahbl_dbus_burst;
input bmu_ahbl_dbus_lock;
input bmu_ahbl_dbus_lrsc;
input [3 :0] bmu_ahbl_dbus_prot;
input bmu_ahbl_dbus_req;
input bmu_ahbl_dbus_req_dp;
input bmu_ahbl_dbus_seq;
input [1 :0] bmu_ahbl_dbus_size;
input [31:0] bmu_ahbl_dbus_wdata;
input bmu_ahbl_dbus_write;
input bmu_ahbl_ibus_acc_deny;
input [31:0] bmu_ahbl_ibus_addr;
input [2 :0] bmu_ahbl_ibus_burst;
input [3 :0] bmu_ahbl_ibus_prot;
input bmu_ahbl_ibus_req;
input bmu_ahbl_ibus_req_dp;
input bmu_ahbl_ibus_seq;
input [1 :0] bmu_ahbl_ibus_size;
input clk_en;
input cpurst_b;
input lsu_biu_amo_pmp_deny;
input lsu_biu_async_expt_ack;
input lsu_xx_flush;
input lsu_xx_warm_up;
input [31:0] pad_ahbl_hrdata;
input pad_ahbl_hready;
input pad_ahbl_hresp;
input sysio_xx_halt_req;
output ahbl_bmu_dbus_acc_err;
output [31:0] ahbl_bmu_dbus_data;
output ahbl_bmu_dbus_grnt;
output ahbl_bmu_dbus_trans_cmplt;
output ahbl_bmu_ibus_acc_err;
output [31:0] ahbl_bmu_ibus_data;
output ahbl_bmu_ibus_grnt;
output ahbl_bmu_ibus_trans_cmplt;
output ahbl_clk_en;
output [10:0] ahbl_dbginfo;
output [31:0] ahbl_pad_haddr;
output [2 :0] ahbl_pad_hburst;
output ahbl_pad_hlock;
output [3 :0] ahbl_pad_hprot;
output [2 :0] ahbl_pad_hsize;
output [1 :0] ahbl_pad_htrans;
output [31:0] ahbl_pad_hwdata;
output ahbl_pad_hwrite;
output ahbl_sysio_idle;
// &Regs; @25
reg [2 :0] ahblif_cur_state;
reg [2 :0] ahblif_nxt_state;
reg [1 :0] lock_cur_state;
reg [1 :0] lock_next_state;
reg [31:0] req_buf_addr;
reg req_buf_lock;
reg req_buf_pmp_deny;
reg [3 :0] req_buf_prot;
reg [1 :0] req_buf_size;
reg req_buf_vld;
reg [31:0] req_buf_wdata;
reg req_buf_write;
reg [1 :0] req_mask;
reg [1 :0] req_sel;
// &Wires; @26
wire acc_err;
wire ahbl_bmu_dbus_acc_err;
wire [31:0] ahbl_bmu_dbus_data;
wire ahbl_bmu_dbus_grnt;
wire ahbl_bmu_dbus_trans_cmplt;
wire ahbl_bmu_ibus_acc_err;
wire [31:0] ahbl_bmu_ibus_data;
wire ahbl_bmu_ibus_grnt;
wire ahbl_bmu_ibus_trans_cmplt;
wire ahbl_clk_en;
wire [10:0] ahbl_dbginfo;
wire ahbl_gated_clk;
wire [31:0] ahbl_pad_haddr;
wire [2 :0] ahbl_pad_hburst;
wire ahbl_pad_hlock;
wire [3 :0] ahbl_pad_hprot;
wire [2 :0] ahbl_pad_hsize;
wire [1 :0] ahbl_pad_htrans;
wire [31:0] ahbl_pad_hwdata;
wire ahbl_pad_hwrite;
wire ahbl_sysio_idle;
wire ahblif_req_idle;
wire bmu_ahbl_dbus_acc_deny;
wire [31:0] bmu_ahbl_dbus_addr;
wire bmu_ahbl_dbus_lock;
wire bmu_ahbl_dbus_lrsc;
wire [3 :0] bmu_ahbl_dbus_prot;
wire bmu_ahbl_dbus_req;
wire bmu_ahbl_dbus_req_dp;
wire [1 :0] bmu_ahbl_dbus_size;
wire [31:0] bmu_ahbl_dbus_wdata;
wire bmu_ahbl_dbus_write;
wire bmu_ahbl_ibus_acc_deny;
wire [31:0] bmu_ahbl_ibus_addr;
wire [3 :0] bmu_ahbl_ibus_prot;
wire bmu_ahbl_ibus_req;
wire bmu_ahbl_ibus_req_dp;
wire [1 :0] bmu_ahbl_ibus_size;
wire [31:0] bus_rdata;
wire bus_ready;
wire bus_resp;
wire clk_en;
wire cpu_acc_deny;
wire [31:0] cpu_addr;
wire cpu_grant;
wire cpu_lock;
wire [3 :0] cpu_prot;
wire cpu_req;
wire cpu_req_gate;
wire [1 :0] cpu_size;
wire [31:0] cpu_wdata;
wire cpu_write;
wire cpurst_b;
wire dbus_req;
wire dbus_sel;
wire ibus_req;
wire ibus_sel;
wire lock_clr;
wire lock_cur_idle;
wire lock_req_vld;
wire lsu_biu_async_expt_ack;
wire lsu_xx_flush;
wire lsu_xx_warm_up;
wire [31:0] pad_ahbl_hrdata;
wire pad_ahbl_hready;
wire pad_ahbl_hresp;
wire req_buf_create_en;
wire req_buf_lock_clr;
wire req_buf_pop_en;
wire req_buf_wdata_create_en;
wire req_data_ready;
wire [1 :0] req_valid;
wire req_vld;
wire sysio_xx_halt_req;
wire trans_cmplt;
parameter DATA_WIDTH = 32;
//==============================================================================
//
// AHB LITE master interface FSM
//
//==============================================================================
//1. control one transfer: SINGLE
//2. generate control signals for AHB LITE control signals: HTRANS, HCTRL
//===================================================================
// parameter description
//IDLE : wait for the cpu request; when cpu has request and hready,
// control information is put on the AHB LITE in this state.
//WFD : wait for the data from the AHB LITE; if back-to-back
// transfer occur, the fsm will stay in the state.
//ERROR : wait for the second phase of the two signal error response.
//ERROR1: generate the error vld signal to cpu.
//===================================================================
parameter IDLE = 3'b000,
WFG = 3'b010,
WFD = 3'b001,
ERROR1 = 3'b110,
ERROR2 = 3'b111;
//==========================================================
// FSM main body
//==========================================================
always@(posedge ahbl_gated_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ahblif_cur_state[2:0] <= IDLE;
else if (clk_en)
ahblif_cur_state[2:0] <= ahblif_nxt_state[2:0];
end
// &CombBeg; @64
always @( req_buf_pmp_deny
or bus_ready
or req_buf_vld
or bus_resp
or ahblif_cur_state[2:0])
begin
case(ahblif_cur_state[2:0])
IDLE: begin
if (req_buf_vld)
ahblif_nxt_state[2:0] = (bus_ready | req_buf_pmp_deny) ? WFD : WFG;
else
ahblif_nxt_state[2:0] = IDLE;
end
WFG: begin
if (bus_ready)
ahblif_nxt_state[2:0] = WFD;
else
ahblif_nxt_state[2:0] = WFG;
end
WFD: begin
if (bus_resp)
ahblif_nxt_state[2:0] = ERROR1;
else if (!bus_ready & !req_buf_pmp_deny)
ahblif_nxt_state[2:0] = WFD;
else
ahblif_nxt_state[2:0] = IDLE;
end
ERROR1: begin
if (bus_ready | !bus_resp)
ahblif_nxt_state[2:0] = ERROR2;
else
ahblif_nxt_state[2:0] = ERROR1;
end
ERROR2:
ahblif_nxt_state[2:0] = IDLE;
default: ahblif_nxt_state[2:0] = IDLE;
endcase
// &CombEnd; @96
end
assign ahblif_req_idle = (ahblif_cur_state[2:0] == IDLE) |
(ahblif_cur_state[2:0] == WFD) & bus_ready;
assign req_data_ready = (ahblif_cur_state[2:0] == WFD) & bus_ready;
//===========================================================
// BUS LOCK
//===========================================================
// &Force("input","lsu_biu_amo_pmp_deny"); @106
parameter LOCK_IDLE = 2'b00;
parameter LOCK_WFS = 2'b01;
parameter LOCK_WFC = 2'b10;
always@(posedge ahbl_gated_clk or negedge cpurst_b)
begin
if(!cpurst_b)
lock_cur_state[1:0] <= LOCK_IDLE;
else if (req_buf_vld & req_buf_pmp_deny)
lock_cur_state[1:0] <= LOCK_IDLE;
else if (clk_en)
lock_cur_state[1:0] <= lock_next_state[1:0];
end
assign lock_req_vld = cpu_req & cpu_lock & !cpu_write &
cpu_grant;
// &CombBeg; @124
always @( acc_err
or cpu_grant
or cpu_req
or lsu_biu_async_expt_ack
or lock_req_vld
or lock_cur_state[1:0])
begin
case(lock_cur_state[1:0])
LOCK_IDLE: begin
if (lock_req_vld)
lock_next_state[1:0] = LOCK_WFC;
else
lock_next_state[1:0] = LOCK_IDLE;
end
// LOCK_WFS: begin
// if (acc_err)
// lock_next_state[1:0] = LOCK_IDLE;
// else if (trans_cmplt)
// lock_next_state[1:0] = LOCK_WFC;
// else
// lock_next_state[1:0] = LOCK_WFS;
// end
LOCK_WFC: begin
if (acc_err | cpu_req & cpu_grant | lsu_biu_async_expt_ack)
lock_next_state[1:0] = LOCK_IDLE;
else
lock_next_state[1:0] = LOCK_WFC;
end
default: lock_next_state[1:0] = LOCK_IDLE;
endcase
// &CombEnd; @148
end
assign lock_cur_idle = lock_cur_state[1:0] == LOCK_IDLE;
assign lock_clr = (lock_cur_state[1:0] == LOCK_WFC) & (cpu_grant & cpu_req | acc_err | lsu_biu_async_expt_ack) |
!lock_cur_idle & lsu_xx_flush |
req_buf_vld & req_buf_pmp_deny;
always@(posedge ahbl_gated_clk or negedge cpurst_b)
begin
if(!cpurst_b)
req_mask[1:0] <= 2'b0;
else if (lock_req_vld & lock_cur_idle)
req_mask[1:0] <= ~req_valid[1:0];
else if (lock_clr)
req_mask[1:0] <= 2'b0;
end
//===========================================================
// FSM output signal
//===========================================================
// &Force("input", "bmu_ahbl_dbus_burst"); &Force("bus", "bmu_ahbl_dbus_burst",2,0); @168
// &Force("input", "bmu_ahbl_ibus_burst"); &Force("bus", "bmu_ahbl_ibus_burst",2,0); @169
// &Force("input", "bmu_ahbl_dbus_seq"); @170
// &Force("input", "bmu_ahbl_ibus_seq"); @171
assign dbus_req = bmu_ahbl_dbus_req & !req_mask[0];
assign ibus_req = bmu_ahbl_ibus_req & !req_mask[1] & !dbus_sel;
assign cpu_req = ibus_req | dbus_req;
assign dbus_sel = bmu_ahbl_dbus_req_dp & !req_mask[0];
assign ibus_sel = bmu_ahbl_ibus_req_dp & !req_mask[1] & !dbus_sel;
assign req_valid[1:0] = {ibus_req, dbus_req};
assign cpu_acc_deny = dbus_sel & bmu_ahbl_dbus_acc_deny
| ibus_sel & bmu_ahbl_ibus_acc_deny;
assign cpu_addr[31:0] = {32{dbus_sel}} & bmu_ahbl_dbus_addr[31:0]
| {32{ibus_sel}} & bmu_ahbl_ibus_addr[31:0];
assign cpu_prot[3:0] = {4{dbus_sel}} & bmu_ahbl_dbus_prot[3:0]
| {4{ibus_sel}} & bmu_ahbl_ibus_prot[3:0];
assign cpu_size[1:0] = {2{dbus_sel}} & bmu_ahbl_dbus_size[1:0]
| {2{ibus_sel}} & bmu_ahbl_ibus_size[1:0];
assign cpu_write = dbus_sel & bmu_ahbl_dbus_write;
assign cpu_wdata[DATA_WIDTH-1:0] = bmu_ahbl_dbus_wdata[DATA_WIDTH-1:0];
assign cpu_lock = dbus_sel & bmu_ahbl_dbus_lock & !bmu_ahbl_dbus_lrsc;
//assign cpu_amo = cpu_lock & !bmu_ahbl_dbus_lrsc;
assign req_buf_create_en = cpu_req & cpu_grant;
//assign req_buf_pop_en = req_buf_vld & ahblif_req_idle & clk_en;
assign req_buf_pop_en = clk_en & (req_buf_vld & req_data_ready | (ahblif_cur_state[2:0] == ERROR2));
always@(posedge ahbl_gated_clk or negedge cpurst_b)
begin
if (!cpurst_b)
req_buf_vld <= 1'b0;
else if (req_buf_create_en)
req_buf_vld <= 1'b1;
else if (req_buf_pop_en)
req_buf_vld <= 1'b0;
end
always@(posedge ahbl_gated_clk)
begin
if (lsu_xx_warm_up)begin
req_sel[1:0] <= 2'b0;
req_buf_pmp_deny <= 1'b0;
req_buf_addr[31:0] <= 32'b0;
req_buf_prot[3:0] <= 4'b0;
req_buf_size[1:0] <= 2'b0;
req_buf_write <= 1'b0;
end
else if (req_buf_create_en) begin
req_sel[1:0] <= req_valid[1:0];
req_buf_pmp_deny <= cpu_acc_deny;
req_buf_addr[31:0] <= cpu_addr[31:0];
req_buf_prot[3:0] <= cpu_prot[3:0];
req_buf_size[1:0] <= cpu_size[1:0];
req_buf_write <= cpu_write;
end
end
//assign req_buf_lock_clr = req_buf_pop_en & (bus_ready | req_buf_pmp_deny) |
// ahblif_req_idle[2:0]==WFG & bus_ready & clk_en;
assign req_buf_lock_clr = req_buf_pop_en & (bus_ready | req_buf_pmp_deny);
always@(posedge ahbl_gated_clk or negedge cpurst_b)
begin
if (!cpurst_b)
req_buf_lock <= 1'b0;
else if (req_buf_create_en)
req_buf_lock <= cpu_lock;
else if (req_buf_lock_clr & lock_cur_idle)
req_buf_lock <= 1'b0;
end
assign req_buf_wdata_create_en = req_buf_vld & bus_ready & clk_en;
always@(posedge ahbl_gated_clk)
begin
if (lsu_xx_warm_up)
req_buf_wdata[DATA_WIDTH-1:0]<= {DATA_WIDTH{1'b0}};
else if (req_buf_wdata_create_en)
req_buf_wdata[DATA_WIDTH-1:0]<= cpu_wdata[DATA_WIDTH-1:0];
end
assign req_vld = req_buf_vld & !req_buf_pmp_deny;
//==========================================================
// interface to AHBL
//==========================================================
assign ahbl_pad_htrans[1] = req_vld & (ahblif_cur_state[2:0]==IDLE) |
(ahblif_cur_state[2:0]==WFG);
assign ahbl_pad_htrans[0] = 1'b0;
assign ahbl_pad_haddr[31:0] = req_buf_addr[31:0];
assign ahbl_pad_hwrite = req_buf_write;
assign ahbl_pad_hsize[2:0] = {1'b0, req_buf_size[1:0]};
assign ahbl_pad_hprot[3:0] = req_buf_prot[3:0];
assign ahbl_pad_hburst[2:0] = 3'b000;
assign ahbl_pad_hlock = req_buf_lock;
assign ahbl_pad_hwdata[DATA_WIDTH-1:0] = req_buf_wdata[DATA_WIDTH-1:0];
//input
assign bus_ready = pad_ahbl_hready;
assign bus_resp = pad_ahbl_hresp;
assign bus_rdata[DATA_WIDTH-1:0] = pad_ahbl_hrdata[DATA_WIDTH-1:0];
//==============================================================================
// interface with CPU
//==============================================================================
assign cpu_grant = !req_buf_vld & ahblif_req_idle & clk_en & !sysio_xx_halt_req;
// trans complete singal
assign trans_cmplt = clk_en &
((ahblif_cur_state[2:0]==WFD) & (bus_ready & !bus_resp | req_buf_vld & req_buf_pmp_deny)
| (ahblif_cur_state[2:0]==ERROR2)); //error vld
// access error valid singal
assign acc_err = (ahblif_cur_state[2:0]==ERROR2) & clk_en;
//==========================================================
// to BMU
//==========================================================
assign ahbl_bmu_ibus_grnt = ibus_sel & cpu_grant;
assign ahbl_bmu_ibus_trans_cmplt = req_sel[1] & trans_cmplt;
assign ahbl_bmu_ibus_acc_err = req_sel[1] & acc_err;
assign ahbl_bmu_ibus_data[DATA_WIDTH-1:0] = bus_rdata[DATA_WIDTH-1:0];
assign ahbl_bmu_dbus_grnt = dbus_sel & cpu_grant;
assign ahbl_bmu_dbus_trans_cmplt = req_sel[0] & trans_cmplt;
assign ahbl_bmu_dbus_acc_err = req_sel[0] & acc_err;
assign ahbl_bmu_dbus_data[DATA_WIDTH-1:0] = bus_rdata[DATA_WIDTH-1:0];
//==========================================================
// BIU CLK EN
//==========================================================
assign cpu_req_gate = bmu_ahbl_dbus_req_dp |
bmu_ahbl_ibus_req_dp;
assign ahbl_clk_en = !(ahblif_cur_state[2:0]==IDLE) | cpu_req_gate | req_buf_vld | !lock_cur_idle | lsu_xx_warm_up;
assign ahbl_sysio_idle = (ahblif_cur_state[2:0]==IDLE) & !req_buf_vld | lsu_xx_warm_up;
assign ahbl_dbginfo[10:0] = {4'b0,req_mask[1:0],lock_cur_state[1:0],ahblif_cur_state[2:0]};
// &Force("nonport", "req_grnt_reg"); @376
// &Force("output", "ahbl_bmu_ibus_grnt"); @377
// &Force("output", "ahbl_bmu_dbus_grnt"); @378
// // &Force("nonport", "dbus_ibus_hold"); @379
// &Force("nonport", "ibus_req_reg"); @380
// &ModuleEnd; @384
endmodule

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opene906/E906_RTL_FACTORY/gen_rtl/biu/rtl/pa_dahbl_top.v Normal file
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_dahbl_top(
bmu_dahbl_dbus_acc_deny,
bmu_dahbl_dbus_addr,
bmu_dahbl_dbus_burst,
bmu_dahbl_dbus_lock,
bmu_dahbl_dbus_lrsc,
bmu_dahbl_dbus_prot,
bmu_dahbl_dbus_req,
bmu_dahbl_dbus_req_dp,
bmu_dahbl_dbus_seq,
bmu_dahbl_dbus_size,
bmu_dahbl_dbus_wdata,
bmu_dahbl_dbus_write,
bmu_dahbl_ibus_acc_deny,
bmu_dahbl_ibus_addr,
bmu_dahbl_ibus_burst,
bmu_dahbl_ibus_prot,
bmu_dahbl_ibus_req,
bmu_dahbl_ibus_req_dp,
bmu_dahbl_ibus_seq,
bmu_dahbl_ibus_size,
cp0_biu_icg_en,
cpurst_b,
dahbl_bmu_dbus_acc_err,
dahbl_bmu_dbus_data,
dahbl_bmu_dbus_grnt,
dahbl_bmu_dbus_trans_cmplt,
dahbl_bmu_ibus_acc_err,
dahbl_bmu_ibus_data,
dahbl_bmu_ibus_grnt,
dahbl_bmu_ibus_trans_cmplt,
dahbl_dtu_debug_info,
dahbl_pad_haddr,
dahbl_pad_hburst,
dahbl_pad_hlock,
dahbl_pad_hprot,
dahbl_pad_hsize,
dahbl_pad_htrans,
dahbl_pad_hwdata,
dahbl_pad_hwrite,
dahbl_sysio_idle,
forever_cpuclk,
lsu_biu_amo_pmp_deny,
lsu_biu_async_expt_ack,
lsu_xx_flush,
lsu_xx_warm_up,
pad_dahbl_hrdata,
pad_dahbl_hready,
pad_dahbl_hresp,
pad_yy_icg_scan_en,
rtu_yy_xx_async_flush,
sysio_xx_halt_req
);
// &Ports; @23
input bmu_dahbl_dbus_acc_deny;
input [31:0] bmu_dahbl_dbus_addr;
input [2 :0] bmu_dahbl_dbus_burst;
input bmu_dahbl_dbus_lock;
input bmu_dahbl_dbus_lrsc;
input [3 :0] bmu_dahbl_dbus_prot;
input bmu_dahbl_dbus_req;
input bmu_dahbl_dbus_req_dp;
input bmu_dahbl_dbus_seq;
input [1 :0] bmu_dahbl_dbus_size;
input [31:0] bmu_dahbl_dbus_wdata;
input bmu_dahbl_dbus_write;
input bmu_dahbl_ibus_acc_deny;
input [31:0] bmu_dahbl_ibus_addr;
input [2 :0] bmu_dahbl_ibus_burst;
input [3 :0] bmu_dahbl_ibus_prot;
input bmu_dahbl_ibus_req;
input bmu_dahbl_ibus_req_dp;
input bmu_dahbl_ibus_seq;
input [1 :0] bmu_dahbl_ibus_size;
input cp0_biu_icg_en;
input cpurst_b;
input forever_cpuclk;
input lsu_biu_amo_pmp_deny;
input lsu_biu_async_expt_ack;
input lsu_xx_flush;
input lsu_xx_warm_up;
input [31:0] pad_dahbl_hrdata;
input pad_dahbl_hready;
input pad_dahbl_hresp;
input pad_yy_icg_scan_en;
input rtu_yy_xx_async_flush;
input sysio_xx_halt_req;
output dahbl_bmu_dbus_acc_err;
output [31:0] dahbl_bmu_dbus_data;
output dahbl_bmu_dbus_grnt;
output dahbl_bmu_dbus_trans_cmplt;
output dahbl_bmu_ibus_acc_err;
output [31:0] dahbl_bmu_ibus_data;
output dahbl_bmu_ibus_grnt;
output dahbl_bmu_ibus_trans_cmplt;
output [10:0] dahbl_dtu_debug_info;
output [31:0] dahbl_pad_haddr;
output [2 :0] dahbl_pad_hburst;
output dahbl_pad_hlock;
output [3 :0] dahbl_pad_hprot;
output [2 :0] dahbl_pad_hsize;
output [1 :0] dahbl_pad_htrans;
output [31:0] dahbl_pad_hwdata;
output dahbl_pad_hwrite;
output dahbl_sysio_idle;
// &Regs; @24
// &Wires; @25
wire bmu_dahbl_dbus_acc_deny;
wire [31:0] bmu_dahbl_dbus_addr;
wire [2 :0] bmu_dahbl_dbus_burst;
wire bmu_dahbl_dbus_lock;
wire bmu_dahbl_dbus_lrsc;
wire [3 :0] bmu_dahbl_dbus_prot;
wire bmu_dahbl_dbus_req;
wire bmu_dahbl_dbus_req_dp;
wire bmu_dahbl_dbus_seq;
wire [1 :0] bmu_dahbl_dbus_size;
wire [31:0] bmu_dahbl_dbus_wdata;
wire bmu_dahbl_dbus_write;
wire bmu_dahbl_ibus_acc_deny;
wire [31:0] bmu_dahbl_ibus_addr;
wire [2 :0] bmu_dahbl_ibus_burst;
wire [3 :0] bmu_dahbl_ibus_prot;
wire bmu_dahbl_ibus_req;
wire bmu_dahbl_ibus_req_dp;
wire bmu_dahbl_ibus_seq;
wire [1 :0] bmu_dahbl_ibus_size;
wire cp0_biu_icg_en;
wire cpurst_b;
wire dahbl_bmu_dbus_acc_err;
wire [31:0] dahbl_bmu_dbus_data;
wire dahbl_bmu_dbus_grnt;
wire dahbl_bmu_dbus_trans_cmplt;
wire dahbl_bmu_ibus_acc_err;
wire [31:0] dahbl_bmu_ibus_data;
wire dahbl_bmu_ibus_grnt;
wire dahbl_bmu_ibus_trans_cmplt;
wire dahbl_clk_en;
wire [10:0] dahbl_dbginfo;
wire [10:0] dahbl_dtu_debug_info;
wire dahbl_gated_clk;
wire [31:0] dahbl_pad_haddr;
wire [2 :0] dahbl_pad_hburst;
wire dahbl_pad_hlock;
wire [3 :0] dahbl_pad_hprot;
wire [2 :0] dahbl_pad_hsize;
wire [1 :0] dahbl_pad_htrans;
wire [31:0] dahbl_pad_hwdata;
wire dahbl_pad_hwrite;
wire dahbl_sysio_idle;
wire forever_cpuclk;
wire lsu_biu_amo_pmp_deny;
wire lsu_biu_async_expt_ack;
wire lsu_xx_flush;
wire [31:0] pad_dahbl_hrdata;
wire pad_dahbl_hready;
wire pad_dahbl_hresp;
wire pad_yy_icg_scan_en;
wire rtu_yy_xx_async_flush;
wire sysio_xx_halt_req;
//==========================================================
// Instance Gated Cell for Most Common Use
//==========================================================
// &Instance("gated_clk_cell", "x_pa_dahbl_cpuclk_cell"); @30
gated_clk_cell x_pa_dahbl_cpuclk_cell (
.clk_in (forever_cpuclk ),
.clk_out (dahbl_gated_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (dahbl_clk_en ),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @31
// .global_en (1'b1 ), @32
// .local_en (dahbl_clk_en ), @33
// .module_en (cp0_biu_icg_en), @34
// .external_en(1'b0 ), @35
// .clk_out (dahbl_gated_clk)); @36
// &ConnRule(s/ahbl/dahbl/); @38
// &Instance("pa_ahbl_if_fo", "x_pa_ahbl_if"); @40
// &Connect(.clk_en (dlite_clk_en_f)); @41
// &Force("input","lsu_xx_warm_up"); @43
// &Instance("pa_ahbl_if", "x_pa_ahbl_if"); @44
pa_ahbl_if x_pa_ahbl_if (
.ahbl_bmu_dbus_acc_err (dahbl_bmu_dbus_acc_err ),
.ahbl_bmu_dbus_data (dahbl_bmu_dbus_data ),
.ahbl_bmu_dbus_grnt (dahbl_bmu_dbus_grnt ),
.ahbl_bmu_dbus_trans_cmplt (dahbl_bmu_dbus_trans_cmplt),
.ahbl_bmu_ibus_acc_err (dahbl_bmu_ibus_acc_err ),
.ahbl_bmu_ibus_data (dahbl_bmu_ibus_data ),
.ahbl_bmu_ibus_grnt (dahbl_bmu_ibus_grnt ),
.ahbl_bmu_ibus_trans_cmplt (dahbl_bmu_ibus_trans_cmplt),
.ahbl_clk_en (dahbl_clk_en ),
.ahbl_dbginfo (dahbl_dbginfo ),
.ahbl_gated_clk (dahbl_gated_clk ),
.ahbl_pad_haddr (dahbl_pad_haddr ),
.ahbl_pad_hburst (dahbl_pad_hburst ),
.ahbl_pad_hlock (dahbl_pad_hlock ),
.ahbl_pad_hprot (dahbl_pad_hprot ),
.ahbl_pad_hsize (dahbl_pad_hsize ),
.ahbl_pad_htrans (dahbl_pad_htrans ),
.ahbl_pad_hwdata (dahbl_pad_hwdata ),
.ahbl_pad_hwrite (dahbl_pad_hwrite ),
.ahbl_sysio_idle (dahbl_sysio_idle ),
.bmu_ahbl_dbus_acc_deny (bmu_dahbl_dbus_acc_deny ),
.bmu_ahbl_dbus_addr (bmu_dahbl_dbus_addr ),
.bmu_ahbl_dbus_burst (bmu_dahbl_dbus_burst ),
.bmu_ahbl_dbus_lock (bmu_dahbl_dbus_lock ),
.bmu_ahbl_dbus_lrsc (bmu_dahbl_dbus_lrsc ),
.bmu_ahbl_dbus_prot (bmu_dahbl_dbus_prot ),
.bmu_ahbl_dbus_req (bmu_dahbl_dbus_req ),
.bmu_ahbl_dbus_req_dp (bmu_dahbl_dbus_req_dp ),
.bmu_ahbl_dbus_seq (bmu_dahbl_dbus_seq ),
.bmu_ahbl_dbus_size (bmu_dahbl_dbus_size ),
.bmu_ahbl_dbus_wdata (bmu_dahbl_dbus_wdata ),
.bmu_ahbl_dbus_write (bmu_dahbl_dbus_write ),
.bmu_ahbl_ibus_acc_deny (bmu_dahbl_ibus_acc_deny ),
.bmu_ahbl_ibus_addr (bmu_dahbl_ibus_addr ),
.bmu_ahbl_ibus_burst (bmu_dahbl_ibus_burst ),
.bmu_ahbl_ibus_prot (bmu_dahbl_ibus_prot ),
.bmu_ahbl_ibus_req (bmu_dahbl_ibus_req ),
.bmu_ahbl_ibus_req_dp (bmu_dahbl_ibus_req_dp ),
.bmu_ahbl_ibus_seq (bmu_dahbl_ibus_seq ),
.bmu_ahbl_ibus_size (bmu_dahbl_ibus_size ),
.cpurst_b (cpurst_b ),
.lsu_biu_amo_pmp_deny (lsu_biu_amo_pmp_deny ),
.lsu_biu_async_expt_ack (lsu_biu_async_expt_ack ),
.lsu_xx_flush (lsu_xx_flush ),
.pad_ahbl_hrdata (pad_dahbl_hrdata ),
.pad_ahbl_hready (pad_dahbl_hready ),
.pad_ahbl_hresp (pad_dahbl_hresp ),
.rtu_yy_xx_async_flush (rtu_yy_xx_async_flush ),
.sysio_xx_halt_req (sysio_xx_halt_req )
);
assign dahbl_dtu_debug_info[10:0] = dahbl_dbginfo[10:0];
// &ModuleEnd; @48
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_iahbl_top(
bmu_iahbl_dbus_acc_deny,
bmu_iahbl_dbus_addr,
bmu_iahbl_dbus_burst,
bmu_iahbl_dbus_lock,
bmu_iahbl_dbus_lrsc,
bmu_iahbl_dbus_prot,
bmu_iahbl_dbus_req,
bmu_iahbl_dbus_req_dp,
bmu_iahbl_dbus_seq,
bmu_iahbl_dbus_size,
bmu_iahbl_dbus_wdata,
bmu_iahbl_dbus_write,
bmu_iahbl_ibus_acc_deny,
bmu_iahbl_ibus_addr,
bmu_iahbl_ibus_burst,
bmu_iahbl_ibus_prot,
bmu_iahbl_ibus_req,
bmu_iahbl_ibus_req_dp,
bmu_iahbl_ibus_seq,
bmu_iahbl_ibus_size,
cp0_biu_icg_en,
cpurst_b,
forever_cpuclk,
iahbl_bmu_dbus_acc_err,
iahbl_bmu_dbus_data,
iahbl_bmu_dbus_grnt,
iahbl_bmu_dbus_trans_cmplt,
iahbl_bmu_ibus_acc_err,
iahbl_bmu_ibus_data,
iahbl_bmu_ibus_grnt,
iahbl_bmu_ibus_trans_cmplt,
iahbl_dtu_debug_info,
iahbl_pad_haddr,
iahbl_pad_hburst,
iahbl_pad_hlock,
iahbl_pad_hprot,
iahbl_pad_hsize,
iahbl_pad_htrans,
iahbl_pad_hwdata,
iahbl_pad_hwrite,
iahbl_sysio_idle,
lsu_biu_amo_pmp_deny,
lsu_biu_async_expt_ack,
lsu_xx_flush,
lsu_xx_warm_up,
pad_iahbl_hrdata,
pad_iahbl_hready,
pad_iahbl_hresp,
pad_yy_icg_scan_en,
rtu_yy_xx_async_flush,
sysio_xx_halt_req
);
// &Ports; @23
input bmu_iahbl_dbus_acc_deny;
input [31:0] bmu_iahbl_dbus_addr;
input [2 :0] bmu_iahbl_dbus_burst;
input bmu_iahbl_dbus_lock;
input bmu_iahbl_dbus_lrsc;
input [3 :0] bmu_iahbl_dbus_prot;
input bmu_iahbl_dbus_req;
input bmu_iahbl_dbus_req_dp;
input bmu_iahbl_dbus_seq;
input [1 :0] bmu_iahbl_dbus_size;
input [31:0] bmu_iahbl_dbus_wdata;
input bmu_iahbl_dbus_write;
input bmu_iahbl_ibus_acc_deny;
input [31:0] bmu_iahbl_ibus_addr;
input [2 :0] bmu_iahbl_ibus_burst;
input [3 :0] bmu_iahbl_ibus_prot;
input bmu_iahbl_ibus_req;
input bmu_iahbl_ibus_req_dp;
input bmu_iahbl_ibus_seq;
input [1 :0] bmu_iahbl_ibus_size;
input cp0_biu_icg_en;
input cpurst_b;
input forever_cpuclk;
input lsu_biu_amo_pmp_deny;
input lsu_biu_async_expt_ack;
input lsu_xx_flush;
input lsu_xx_warm_up;
input [31:0] pad_iahbl_hrdata;
input pad_iahbl_hready;
input pad_iahbl_hresp;
input pad_yy_icg_scan_en;
input rtu_yy_xx_async_flush;
input sysio_xx_halt_req;
output iahbl_bmu_dbus_acc_err;
output [31:0] iahbl_bmu_dbus_data;
output iahbl_bmu_dbus_grnt;
output iahbl_bmu_dbus_trans_cmplt;
output iahbl_bmu_ibus_acc_err;
output [31:0] iahbl_bmu_ibus_data;
output iahbl_bmu_ibus_grnt;
output iahbl_bmu_ibus_trans_cmplt;
output [10:0] iahbl_dtu_debug_info;
output [31:0] iahbl_pad_haddr;
output [2 :0] iahbl_pad_hburst;
output iahbl_pad_hlock;
output [3 :0] iahbl_pad_hprot;
output [2 :0] iahbl_pad_hsize;
output [1 :0] iahbl_pad_htrans;
output [31:0] iahbl_pad_hwdata;
output iahbl_pad_hwrite;
output iahbl_sysio_idle;
// &Regs; @24
// &Wires; @25
wire bmu_iahbl_dbus_acc_deny;
wire [31:0] bmu_iahbl_dbus_addr;
wire [2 :0] bmu_iahbl_dbus_burst;
wire bmu_iahbl_dbus_lock;
wire bmu_iahbl_dbus_lrsc;
wire [3 :0] bmu_iahbl_dbus_prot;
wire bmu_iahbl_dbus_req;
wire bmu_iahbl_dbus_req_dp;
wire bmu_iahbl_dbus_seq;
wire [1 :0] bmu_iahbl_dbus_size;
wire [31:0] bmu_iahbl_dbus_wdata;
wire bmu_iahbl_dbus_write;
wire bmu_iahbl_ibus_acc_deny;
wire [31:0] bmu_iahbl_ibus_addr;
wire [2 :0] bmu_iahbl_ibus_burst;
wire [3 :0] bmu_iahbl_ibus_prot;
wire bmu_iahbl_ibus_req;
wire bmu_iahbl_ibus_req_dp;
wire bmu_iahbl_ibus_seq;
wire [1 :0] bmu_iahbl_ibus_size;
wire cp0_biu_icg_en;
wire cpurst_b;
wire forever_cpuclk;
wire iahbl_bmu_dbus_acc_err;
wire [31:0] iahbl_bmu_dbus_data;
wire iahbl_bmu_dbus_grnt;
wire iahbl_bmu_dbus_trans_cmplt;
wire iahbl_bmu_ibus_acc_err;
wire [31:0] iahbl_bmu_ibus_data;
wire iahbl_bmu_ibus_grnt;
wire iahbl_bmu_ibus_trans_cmplt;
wire iahbl_clk_en;
wire [10:0] iahbl_dbginfo;
wire [10:0] iahbl_dtu_debug_info;
wire iahbl_gated_clk;
wire [31:0] iahbl_pad_haddr;
wire [2 :0] iahbl_pad_hburst;
wire iahbl_pad_hlock;
wire [3 :0] iahbl_pad_hprot;
wire [2 :0] iahbl_pad_hsize;
wire [1 :0] iahbl_pad_htrans;
wire [31:0] iahbl_pad_hwdata;
wire iahbl_pad_hwrite;
wire iahbl_sysio_idle;
wire lsu_biu_amo_pmp_deny;
wire lsu_biu_async_expt_ack;
wire lsu_xx_flush;
wire [31:0] pad_iahbl_hrdata;
wire pad_iahbl_hready;
wire pad_iahbl_hresp;
wire pad_yy_icg_scan_en;
wire rtu_yy_xx_async_flush;
wire sysio_xx_halt_req;
//==========================================================
// Instance Gated Cell for Most Common Use
//==========================================================
// &Instance("gated_clk_cell", "x_pa_iahbl_cpuclk_cell"); @30
gated_clk_cell x_pa_iahbl_cpuclk_cell (
.clk_in (forever_cpuclk ),
.clk_out (iahbl_gated_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (iahbl_clk_en ),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @31
// .global_en (1'b1 ), @32
// .local_en (iahbl_clk_en ), @33
// .module_en (cp0_biu_icg_en ), @34
// .external_en(1'b0 ), @35
// .clk_out (iahbl_gated_clk)); @36
// &ConnRule(s/ahbl/iahbl/); @38
// &Instance("pa_ahbl_if_fo", "x_pa_ahbl_if"); @40
// &Connect(.clk_en (ilite_clk_en_f)); @41
// &Force("input","lsu_xx_warm_up"); @43
// &Instance("pa_ahbl_if", "x_pa_ahbl_if"); @44
pa_ahbl_if x_pa_ahbl_if (
.ahbl_bmu_dbus_acc_err (iahbl_bmu_dbus_acc_err ),
.ahbl_bmu_dbus_data (iahbl_bmu_dbus_data ),
.ahbl_bmu_dbus_grnt (iahbl_bmu_dbus_grnt ),
.ahbl_bmu_dbus_trans_cmplt (iahbl_bmu_dbus_trans_cmplt),
.ahbl_bmu_ibus_acc_err (iahbl_bmu_ibus_acc_err ),
.ahbl_bmu_ibus_data (iahbl_bmu_ibus_data ),
.ahbl_bmu_ibus_grnt (iahbl_bmu_ibus_grnt ),
.ahbl_bmu_ibus_trans_cmplt (iahbl_bmu_ibus_trans_cmplt),
.ahbl_clk_en (iahbl_clk_en ),
.ahbl_dbginfo (iahbl_dbginfo ),
.ahbl_gated_clk (iahbl_gated_clk ),
.ahbl_pad_haddr (iahbl_pad_haddr ),
.ahbl_pad_hburst (iahbl_pad_hburst ),
.ahbl_pad_hlock (iahbl_pad_hlock ),
.ahbl_pad_hprot (iahbl_pad_hprot ),
.ahbl_pad_hsize (iahbl_pad_hsize ),
.ahbl_pad_htrans (iahbl_pad_htrans ),
.ahbl_pad_hwdata (iahbl_pad_hwdata ),
.ahbl_pad_hwrite (iahbl_pad_hwrite ),
.ahbl_sysio_idle (iahbl_sysio_idle ),
.bmu_ahbl_dbus_acc_deny (bmu_iahbl_dbus_acc_deny ),
.bmu_ahbl_dbus_addr (bmu_iahbl_dbus_addr ),
.bmu_ahbl_dbus_burst (bmu_iahbl_dbus_burst ),
.bmu_ahbl_dbus_lock (bmu_iahbl_dbus_lock ),
.bmu_ahbl_dbus_lrsc (bmu_iahbl_dbus_lrsc ),
.bmu_ahbl_dbus_prot (bmu_iahbl_dbus_prot ),
.bmu_ahbl_dbus_req (bmu_iahbl_dbus_req ),
.bmu_ahbl_dbus_req_dp (bmu_iahbl_dbus_req_dp ),
.bmu_ahbl_dbus_seq (bmu_iahbl_dbus_seq ),
.bmu_ahbl_dbus_size (bmu_iahbl_dbus_size ),
.bmu_ahbl_dbus_wdata (bmu_iahbl_dbus_wdata ),
.bmu_ahbl_dbus_write (bmu_iahbl_dbus_write ),
.bmu_ahbl_ibus_acc_deny (bmu_iahbl_ibus_acc_deny ),
.bmu_ahbl_ibus_addr (bmu_iahbl_ibus_addr ),
.bmu_ahbl_ibus_burst (bmu_iahbl_ibus_burst ),
.bmu_ahbl_ibus_prot (bmu_iahbl_ibus_prot ),
.bmu_ahbl_ibus_req (bmu_iahbl_ibus_req ),
.bmu_ahbl_ibus_req_dp (bmu_iahbl_ibus_req_dp ),
.bmu_ahbl_ibus_seq (bmu_iahbl_ibus_seq ),
.bmu_ahbl_ibus_size (bmu_iahbl_ibus_size ),
.cpurst_b (cpurst_b ),
.lsu_biu_amo_pmp_deny (lsu_biu_amo_pmp_deny ),
.lsu_biu_async_expt_ack (lsu_biu_async_expt_ack ),
.lsu_xx_flush (lsu_xx_flush ),
.pad_ahbl_hrdata (pad_iahbl_hrdata ),
.pad_ahbl_hready (pad_iahbl_hready ),
.pad_ahbl_hresp (pad_iahbl_hresp ),
.rtu_yy_xx_async_flush (rtu_yy_xx_async_flush ),
.sysio_xx_halt_req (sysio_xx_halt_req )
);
assign iahbl_dtu_debug_info[10:0] = iahbl_dbginfo[10:0];
// &ModuleEnd; @47
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_sahbl_top(
bmu_sahbl_dbus_acc_deny,
bmu_sahbl_dbus_addr,
bmu_sahbl_dbus_burst,
bmu_sahbl_dbus_lock,
bmu_sahbl_dbus_lrsc,
bmu_sahbl_dbus_prot,
bmu_sahbl_dbus_req,
bmu_sahbl_dbus_req_dp,
bmu_sahbl_dbus_seq,
bmu_sahbl_dbus_size,
bmu_sahbl_dbus_wdata,
bmu_sahbl_dbus_write,
bmu_sahbl_ibus_acc_deny,
bmu_sahbl_ibus_addr,
bmu_sahbl_ibus_burst,
bmu_sahbl_ibus_prot,
bmu_sahbl_ibus_req,
bmu_sahbl_ibus_req_dp,
bmu_sahbl_ibus_seq,
bmu_sahbl_ibus_size,
clk_en_f,
cp0_biu_icg_en,
cpurst_b,
forever_cpuclk,
lsu_biu_amo_pmp_deny,
lsu_biu_async_expt_ack,
lsu_xx_flush,
lsu_xx_warm_up,
pad_sahbl_hrdata,
pad_sahbl_hready,
pad_sahbl_hresp,
pad_yy_icg_scan_en,
sahbl_bmu_dbus_acc_err,
sahbl_bmu_dbus_data,
sahbl_bmu_dbus_grnt,
sahbl_bmu_dbus_trans_cmplt,
sahbl_bmu_ibus_acc_err,
sahbl_bmu_ibus_data,
sahbl_bmu_ibus_grnt,
sahbl_bmu_ibus_trans_cmplt,
sahbl_dtu_debug_info,
sahbl_pad_haddr,
sahbl_pad_hburst,
sahbl_pad_hlock,
sahbl_pad_hprot,
sahbl_pad_hsize,
sahbl_pad_htrans,
sahbl_pad_hwdata,
sahbl_pad_hwrite,
sahbl_sysio_idle,
sysio_xx_halt_req
);
// &Ports; @23
input bmu_sahbl_dbus_acc_deny;
input [31:0] bmu_sahbl_dbus_addr;
input [2 :0] bmu_sahbl_dbus_burst;
input bmu_sahbl_dbus_lock;
input bmu_sahbl_dbus_lrsc;
input [3 :0] bmu_sahbl_dbus_prot;
input bmu_sahbl_dbus_req;
input bmu_sahbl_dbus_req_dp;
input bmu_sahbl_dbus_seq;
input [1 :0] bmu_sahbl_dbus_size;
input [31:0] bmu_sahbl_dbus_wdata;
input bmu_sahbl_dbus_write;
input bmu_sahbl_ibus_acc_deny;
input [31:0] bmu_sahbl_ibus_addr;
input [2 :0] bmu_sahbl_ibus_burst;
input [3 :0] bmu_sahbl_ibus_prot;
input bmu_sahbl_ibus_req;
input bmu_sahbl_ibus_req_dp;
input bmu_sahbl_ibus_seq;
input [1 :0] bmu_sahbl_ibus_size;
input clk_en_f;
input cp0_biu_icg_en;
input cpurst_b;
input forever_cpuclk;
input lsu_biu_amo_pmp_deny;
input lsu_biu_async_expt_ack;
input lsu_xx_flush;
input lsu_xx_warm_up;
input [31:0] pad_sahbl_hrdata;
input pad_sahbl_hready;
input pad_sahbl_hresp;
input pad_yy_icg_scan_en;
input sysio_xx_halt_req;
output sahbl_bmu_dbus_acc_err;
output [31:0] sahbl_bmu_dbus_data;
output sahbl_bmu_dbus_grnt;
output sahbl_bmu_dbus_trans_cmplt;
output sahbl_bmu_ibus_acc_err;
output [31:0] sahbl_bmu_ibus_data;
output sahbl_bmu_ibus_grnt;
output sahbl_bmu_ibus_trans_cmplt;
output [10:0] sahbl_dtu_debug_info;
output [31:0] sahbl_pad_haddr;
output [2 :0] sahbl_pad_hburst;
output sahbl_pad_hlock;
output [3 :0] sahbl_pad_hprot;
output [2 :0] sahbl_pad_hsize;
output [1 :0] sahbl_pad_htrans;
output [31:0] sahbl_pad_hwdata;
output sahbl_pad_hwrite;
output sahbl_sysio_idle;
// &Regs; @24
// &Wires; @25
wire bmu_sahbl_dbus_acc_deny;
wire [31:0] bmu_sahbl_dbus_addr;
wire [2 :0] bmu_sahbl_dbus_burst;
wire bmu_sahbl_dbus_lock;
wire bmu_sahbl_dbus_lrsc;
wire [3 :0] bmu_sahbl_dbus_prot;
wire bmu_sahbl_dbus_req;
wire bmu_sahbl_dbus_req_dp;
wire bmu_sahbl_dbus_seq;
wire [1 :0] bmu_sahbl_dbus_size;
wire [31:0] bmu_sahbl_dbus_wdata;
wire bmu_sahbl_dbus_write;
wire bmu_sahbl_ibus_acc_deny;
wire [31:0] bmu_sahbl_ibus_addr;
wire [2 :0] bmu_sahbl_ibus_burst;
wire [3 :0] bmu_sahbl_ibus_prot;
wire bmu_sahbl_ibus_req;
wire bmu_sahbl_ibus_req_dp;
wire bmu_sahbl_ibus_seq;
wire [1 :0] bmu_sahbl_ibus_size;
wire clk_en_f;
wire cp0_biu_icg_en;
wire cpurst_b;
wire forever_cpuclk;
wire lsu_biu_amo_pmp_deny;
wire lsu_biu_async_expt_ack;
wire lsu_xx_flush;
wire lsu_xx_warm_up;
wire [31:0] pad_sahbl_hrdata;
wire pad_sahbl_hready;
wire pad_sahbl_hresp;
wire pad_yy_icg_scan_en;
wire sahbl_bmu_dbus_acc_err;
wire [31:0] sahbl_bmu_dbus_data;
wire sahbl_bmu_dbus_grnt;
wire sahbl_bmu_dbus_trans_cmplt;
wire sahbl_bmu_ibus_acc_err;
wire [31:0] sahbl_bmu_ibus_data;
wire sahbl_bmu_ibus_grnt;
wire sahbl_bmu_ibus_trans_cmplt;
wire sahbl_clk_en;
wire [10:0] sahbl_dbginfo;
wire [10:0] sahbl_dtu_debug_info;
wire sahbl_gated_clk;
wire [31:0] sahbl_pad_haddr;
wire [2 :0] sahbl_pad_hburst;
wire sahbl_pad_hlock;
wire [3 :0] sahbl_pad_hprot;
wire [2 :0] sahbl_pad_hsize;
wire [1 :0] sahbl_pad_htrans;
wire [31:0] sahbl_pad_hwdata;
wire sahbl_pad_hwrite;
wire sahbl_sysio_idle;
wire sysio_xx_halt_req;
//==========================================================
// Instance Gated Cell for Most Common Use
//==========================================================
// &Instance("gated_clk_cell", "x_pa_sahbl_cpuclk_cell"); @30
gated_clk_cell x_pa_sahbl_cpuclk_cell (
.clk_in (forever_cpuclk ),
.clk_out (sahbl_gated_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (sahbl_clk_en ),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @31
// .global_en (1'b1 ), @32
// .local_en (sahbl_clk_en ), @33
// .module_en (cp0_biu_icg_en ), @34
// .external_en(1'b0 ), @35
// .clk_out (sahbl_gated_clk)); @36
// &ConnRule(s/ahbl/sahbl/); @38
// &Instance("pa_ahbl_if_fo", "x_pa_ahbl_if"); @40
pa_ahbl_if_fo x_pa_ahbl_if (
.ahbl_bmu_dbus_acc_err (sahbl_bmu_dbus_acc_err ),
.ahbl_bmu_dbus_data (sahbl_bmu_dbus_data ),
.ahbl_bmu_dbus_grnt (sahbl_bmu_dbus_grnt ),
.ahbl_bmu_dbus_trans_cmplt (sahbl_bmu_dbus_trans_cmplt),
.ahbl_bmu_ibus_acc_err (sahbl_bmu_ibus_acc_err ),
.ahbl_bmu_ibus_data (sahbl_bmu_ibus_data ),
.ahbl_bmu_ibus_grnt (sahbl_bmu_ibus_grnt ),
.ahbl_bmu_ibus_trans_cmplt (sahbl_bmu_ibus_trans_cmplt),
.ahbl_clk_en (sahbl_clk_en ),
.ahbl_dbginfo (sahbl_dbginfo ),
.ahbl_gated_clk (sahbl_gated_clk ),
.ahbl_pad_haddr (sahbl_pad_haddr ),
.ahbl_pad_hburst (sahbl_pad_hburst ),
.ahbl_pad_hlock (sahbl_pad_hlock ),
.ahbl_pad_hprot (sahbl_pad_hprot ),
.ahbl_pad_hsize (sahbl_pad_hsize ),
.ahbl_pad_htrans (sahbl_pad_htrans ),
.ahbl_pad_hwdata (sahbl_pad_hwdata ),
.ahbl_pad_hwrite (sahbl_pad_hwrite ),
.ahbl_sysio_idle (sahbl_sysio_idle ),
.bmu_ahbl_dbus_acc_deny (bmu_sahbl_dbus_acc_deny ),
.bmu_ahbl_dbus_addr (bmu_sahbl_dbus_addr ),
.bmu_ahbl_dbus_burst (bmu_sahbl_dbus_burst ),
.bmu_ahbl_dbus_lock (bmu_sahbl_dbus_lock ),
.bmu_ahbl_dbus_lrsc (bmu_sahbl_dbus_lrsc ),
.bmu_ahbl_dbus_prot (bmu_sahbl_dbus_prot ),
.bmu_ahbl_dbus_req (bmu_sahbl_dbus_req ),
.bmu_ahbl_dbus_req_dp (bmu_sahbl_dbus_req_dp ),
.bmu_ahbl_dbus_seq (bmu_sahbl_dbus_seq ),
.bmu_ahbl_dbus_size (bmu_sahbl_dbus_size ),
.bmu_ahbl_dbus_wdata (bmu_sahbl_dbus_wdata ),
.bmu_ahbl_dbus_write (bmu_sahbl_dbus_write ),
.bmu_ahbl_ibus_acc_deny (bmu_sahbl_ibus_acc_deny ),
.bmu_ahbl_ibus_addr (bmu_sahbl_ibus_addr ),
.bmu_ahbl_ibus_burst (bmu_sahbl_ibus_burst ),
.bmu_ahbl_ibus_prot (bmu_sahbl_ibus_prot ),
.bmu_ahbl_ibus_req (bmu_sahbl_ibus_req ),
.bmu_ahbl_ibus_req_dp (bmu_sahbl_ibus_req_dp ),
.bmu_ahbl_ibus_seq (bmu_sahbl_ibus_seq ),
.bmu_ahbl_ibus_size (bmu_sahbl_ibus_size ),
.clk_en (clk_en_f ),
.cpurst_b (cpurst_b ),
.lsu_biu_amo_pmp_deny (lsu_biu_amo_pmp_deny ),
.lsu_biu_async_expt_ack (lsu_biu_async_expt_ack ),
.lsu_xx_flush (lsu_xx_flush ),
.lsu_xx_warm_up (lsu_xx_warm_up ),
.pad_ahbl_hrdata (pad_sahbl_hrdata ),
.pad_ahbl_hready (pad_sahbl_hready ),
.pad_ahbl_hresp (pad_sahbl_hresp ),
.sysio_xx_halt_req (sysio_xx_halt_req )
);
// &Connect(.clk_en(clk_en_f)); @41
assign sahbl_dtu_debug_info[10:0] = sahbl_dbginfo[10:0];
// &Force("input", "lsu_xx_warm_up"); @46
// &Instance("pa_ahbl_if", "x_pa_ahbl_if"); @47
// &Force("nonport","sahbl_dbginfo"); @48
// &ModuleEnd; @51
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_bmu_bus_if(
bmu_clk,
bmu_dahbl_xx_acc_deny,
bmu_dahbl_xx_addr,
bmu_dahbl_xx_burst,
bmu_dahbl_xx_prot,
bmu_dahbl_xx_req,
bmu_dahbl_xx_req_dp,
bmu_dahbl_xx_seq,
bmu_dahbl_xx_size,
bmu_dahbl_xx_wdata,
bmu_dahbl_xx_write,
bmu_iahbl_xx_acc_deny,
bmu_iahbl_xx_addr,
bmu_iahbl_xx_burst,
bmu_iahbl_xx_prot,
bmu_iahbl_xx_req,
bmu_iahbl_xx_req_dp,
bmu_iahbl_xx_seq,
bmu_iahbl_xx_size,
bmu_iahbl_xx_wdata,
bmu_iahbl_xx_write,
bmu_sahbl_xx_acc_deny,
bmu_sahbl_xx_addr,
bmu_sahbl_xx_burst,
bmu_sahbl_xx_prot,
bmu_sahbl_xx_req,
bmu_sahbl_xx_req_dp,
bmu_sahbl_xx_seq,
bmu_sahbl_xx_size,
bmu_sahbl_xx_wdata,
bmu_sahbl_xx_write,
bmu_tcipif_xx_acc_deny,
bmu_tcipif_xx_addr,
bmu_tcipif_xx_req,
bmu_tcipif_xx_req_dp,
bmu_tcipif_xx_size,
bmu_tcipif_xx_supv_mode,
bmu_tcipif_xx_wdata,
bmu_tcipif_xx_write,
bmu_tt_acc_err,
bmu_tt_clk_en,
bmu_tt_grant,
bmu_tt_rdata,
bmu_tt_trans_cmplt,
cpurst_b,
dahbl_bmu_xx_acc_err,
dahbl_bmu_xx_data,
dahbl_bmu_xx_grnt,
dahbl_bmu_xx_trans_cmplt,
iahbl_bmu_xx_acc_err,
iahbl_bmu_xx_data,
iahbl_bmu_xx_grnt,
iahbl_bmu_xx_trans_cmplt,
pad_bmu_dahbl_base,
pad_bmu_dahbl_mask,
pad_bmu_iahbl_base,
pad_bmu_iahbl_mask,
pad_cpu_tcip_base,
sahbl_bmu_xx_acc_err,
sahbl_bmu_xx_data,
sahbl_bmu_xx_grnt,
sahbl_bmu_xx_trans_cmplt,
tcipif_bmu_xx_acc_err,
tcipif_bmu_xx_data,
tcipif_bmu_xx_grnt,
tcipif_bmu_xx_trans_cmplt,
tt_bmu_acc_deny,
tt_bmu_addr,
tt_bmu_burst,
tt_bmu_data_req,
tt_bmu_prot,
tt_bmu_req,
tt_bmu_seq,
tt_bmu_size,
tt_bmu_wdata,
tt_bmu_write,
xx_dbginfo
);
// &Ports; @25
input bmu_clk;
input cpurst_b;
input dahbl_bmu_xx_acc_err;
input [31:0] dahbl_bmu_xx_data;
input dahbl_bmu_xx_grnt;
input dahbl_bmu_xx_trans_cmplt;
input iahbl_bmu_xx_acc_err;
input [31:0] iahbl_bmu_xx_data;
input iahbl_bmu_xx_grnt;
input iahbl_bmu_xx_trans_cmplt;
input [11:0] pad_bmu_dahbl_base;
input [11:0] pad_bmu_dahbl_mask;
input [11:0] pad_bmu_iahbl_base;
input [11:0] pad_bmu_iahbl_mask;
input [31:0] pad_cpu_tcip_base;
input sahbl_bmu_xx_acc_err;
input [31:0] sahbl_bmu_xx_data;
input sahbl_bmu_xx_grnt;
input sahbl_bmu_xx_trans_cmplt;
input tcipif_bmu_xx_acc_err;
input [31:0] tcipif_bmu_xx_data;
input tcipif_bmu_xx_grnt;
input tcipif_bmu_xx_trans_cmplt;
input tt_bmu_acc_deny;
input [31:0] tt_bmu_addr;
input [2 :0] tt_bmu_burst;
input tt_bmu_data_req;
input [3 :0] tt_bmu_prot;
input tt_bmu_req;
input tt_bmu_seq;
input [1 :0] tt_bmu_size;
input [31:0] tt_bmu_wdata;
input tt_bmu_write;
output bmu_dahbl_xx_acc_deny;
output [31:0] bmu_dahbl_xx_addr;
output [2 :0] bmu_dahbl_xx_burst;
output [3 :0] bmu_dahbl_xx_prot;
output bmu_dahbl_xx_req;
output bmu_dahbl_xx_req_dp;
output bmu_dahbl_xx_seq;
output [1 :0] bmu_dahbl_xx_size;
output [31:0] bmu_dahbl_xx_wdata;
output bmu_dahbl_xx_write;
output bmu_iahbl_xx_acc_deny;
output [31:0] bmu_iahbl_xx_addr;
output [2 :0] bmu_iahbl_xx_burst;
output [3 :0] bmu_iahbl_xx_prot;
output bmu_iahbl_xx_req;
output bmu_iahbl_xx_req_dp;
output bmu_iahbl_xx_seq;
output [1 :0] bmu_iahbl_xx_size;
output [31:0] bmu_iahbl_xx_wdata;
output bmu_iahbl_xx_write;
output bmu_sahbl_xx_acc_deny;
output [31:0] bmu_sahbl_xx_addr;
output [2 :0] bmu_sahbl_xx_burst;
output [3 :0] bmu_sahbl_xx_prot;
output bmu_sahbl_xx_req;
output bmu_sahbl_xx_req_dp;
output bmu_sahbl_xx_seq;
output [1 :0] bmu_sahbl_xx_size;
output [31:0] bmu_sahbl_xx_wdata;
output bmu_sahbl_xx_write;
output bmu_tcipif_xx_acc_deny;
output [31:0] bmu_tcipif_xx_addr;
output bmu_tcipif_xx_req;
output bmu_tcipif_xx_req_dp;
output [1 :0] bmu_tcipif_xx_size;
output bmu_tcipif_xx_supv_mode;
output [31:0] bmu_tcipif_xx_wdata;
output bmu_tcipif_xx_write;
output bmu_tt_acc_err;
output bmu_tt_clk_en;
output bmu_tt_grant;
output [31:0] bmu_tt_rdata;
output bmu_tt_trans_cmplt;
output [1 :0] xx_dbginfo;
// &Regs; @26
reg [1 :0] bmu_cur_state;
reg [1 :0] bmu_next_state;
reg [3 :0] bus_sel_f;
// &Wires; @27
wire bmu_clk;
wire bmu_dahbl_xx_acc_deny;
wire [31:0] bmu_dahbl_xx_addr;
wire [2 :0] bmu_dahbl_xx_burst;
wire [3 :0] bmu_dahbl_xx_prot;
wire bmu_dahbl_xx_req;
wire bmu_dahbl_xx_req_dp;
wire bmu_dahbl_xx_seq;
wire [1 :0] bmu_dahbl_xx_size;
wire [31:0] bmu_dahbl_xx_wdata;
wire bmu_dahbl_xx_write;
wire bmu_iahbl_xx_acc_deny;
wire [31:0] bmu_iahbl_xx_addr;
wire [2 :0] bmu_iahbl_xx_burst;
wire [3 :0] bmu_iahbl_xx_prot;
wire bmu_iahbl_xx_req;
wire bmu_iahbl_xx_req_dp;
wire bmu_iahbl_xx_seq;
wire [1 :0] bmu_iahbl_xx_size;
wire [31:0] bmu_iahbl_xx_wdata;
wire bmu_iahbl_xx_write;
wire bmu_sahbl_xx_acc_deny;
wire [31:0] bmu_sahbl_xx_addr;
wire [2 :0] bmu_sahbl_xx_burst;
wire [3 :0] bmu_sahbl_xx_prot;
wire bmu_sahbl_xx_req;
wire bmu_sahbl_xx_req_dp;
wire bmu_sahbl_xx_seq;
wire [1 :0] bmu_sahbl_xx_size;
wire [31:0] bmu_sahbl_xx_wdata;
wire bmu_sahbl_xx_write;
wire bmu_tcipif_xx_acc_deny;
wire [31:0] bmu_tcipif_xx_addr;
wire bmu_tcipif_xx_req;
wire bmu_tcipif_xx_req_dp;
wire [1 :0] bmu_tcipif_xx_size;
wire bmu_tcipif_xx_supv_mode;
wire [31:0] bmu_tcipif_xx_wdata;
wire bmu_tcipif_xx_write;
wire bmu_tt_acc_err;
wire bmu_tt_clk_en;
wire bmu_tt_grant;
wire [31:0] bmu_tt_rdata;
wire bmu_tt_trans_cmplt;
wire bus_acc_err;
wire bus_cmplt;
wire bus_grant;
wire [3 :0] bus_sel;
wire bus_sel_same;
wire cpurst_b;
wire dahbl_bmu_xx_acc_err;
wire [31:0] dahbl_bmu_xx_data;
wire dahbl_bmu_xx_grnt;
wire dahbl_bmu_xx_trans_cmplt;
wire dahbl_hit;
wire dahbl_sel_pred;
wire iahbl_bmu_xx_acc_err;
wire [31:0] iahbl_bmu_xx_data;
wire iahbl_bmu_xx_grnt;
wire iahbl_bmu_xx_trans_cmplt;
wire iahbl_hit;
wire iahbl_sel_pred;
wire new_req_en;
wire [11:0] pad_bmu_dahbl_base;
wire [11:0] pad_bmu_dahbl_mask;
wire [11:0] pad_bmu_iahbl_base;
wire [11:0] pad_bmu_iahbl_mask;
wire [31:0] pad_cpu_tcip_base;
wire req_en;
wire sahbl_bmu_xx_acc_err;
wire [31:0] sahbl_bmu_xx_data;
wire sahbl_bmu_xx_grnt;
wire sahbl_bmu_xx_trans_cmplt;
wire sahbl_hit;
wire sahbl_sel_pred;
wire tcip_sel_pred;
wire [15:0] tcipif_addr_low;
wire tcipif_bmu_xx_acc_err;
wire [31:0] tcipif_bmu_xx_data;
wire tcipif_bmu_xx_grnt;
wire tcipif_bmu_xx_trans_cmplt;
wire tcipif_hit;
wire tt_bmu_acc_deny;
wire [31:0] tt_bmu_addr;
wire [2 :0] tt_bmu_burst;
wire tt_bmu_data_req;
wire [3 :0] tt_bmu_prot;
wire tt_bmu_req;
wire tt_bmu_seq;
wire [1 :0] tt_bmu_size;
wire [31:0] tt_bmu_wdata;
wire tt_bmu_write;
wire [1 :0] xx_dbginfo;
//==========================================================
// compare base address with ahbl base addr
//==========================================================
assign iahbl_hit = ((tt_bmu_addr[31:20] & pad_bmu_iahbl_mask[11:0]) == pad_bmu_iahbl_base[11:0])
& ~tcipif_hit & ~dahbl_hit;
assign dahbl_hit = ((tt_bmu_addr[31:20] & pad_bmu_dahbl_mask[11:0]) == pad_bmu_dahbl_base[11:0])
& ~tcipif_hit;
// &Force("input", "pad_cpu_tcip_base"); @47
// &Force("bus","pad_cpu_tcip_base",31,0); @48
// &Force("bus","tt_bmu_addr",31,0); @49
assign tcipif_hit = (tt_bmu_addr[31:28] == pad_cpu_tcip_base[31:28]);
assign sahbl_hit = ~dahbl_hit & ~iahbl_hit & ~tcipif_hit;
assign bus_sel[3:0] = {sahbl_hit,tcipif_hit,iahbl_hit,dahbl_hit};
//==========================================================
// FSM
//==========================================================
parameter REQ = 2'b00;
parameter WFG = 2'b01;
parameter WFD = 2'b10;
always @(posedge bmu_clk or negedge cpurst_b)
begin
if(!cpurst_b)
bmu_cur_state[1:0] <= REQ;
else
bmu_cur_state[1:0] <= bmu_next_state[1:0];
end
// &CombBeg; @73
always @( bus_grant
or bus_cmplt
or bus_acc_err
or bmu_cur_state[1:0]
or bus_sel_same
or tt_bmu_req)
begin
case(bmu_cur_state[1:0])
REQ: begin
if (tt_bmu_req)
bmu_next_state[1:0] = bus_grant ? WFD : WFG;
else
bmu_next_state[1:0] = REQ;
end
WFG:begin
if (bus_grant)
bmu_next_state[1:0] = WFD;
else
bmu_next_state[1:0] = WFG;
end
WFD: begin
if (bus_cmplt)begin
if (tt_bmu_req & bus_sel_same & !bus_acc_err)
bmu_next_state[1:0] = bus_grant ? WFD : WFG;
else
bmu_next_state[1:0] = REQ;
end
else
bmu_next_state[1:0] = WFD;
end
default: bmu_next_state[1:0] = REQ;
endcase
// &CombEnd; @99
end
assign req_en = (bmu_cur_state[1:0] == REQ) |
(bmu_cur_state[1:0] == WFG) |
(bmu_cur_state[1:0] == WFD) & bus_sel_same;
assign new_req_en = (bmu_cur_state[1:0] == REQ);
always @(posedge bmu_clk or negedge cpurst_b)
begin
if(!cpurst_b)
bus_sel_f[3:0] <= 4'b0;
else if (tt_bmu_req & new_req_en)
bus_sel_f[3:0] <= bus_sel[3:0];
end
assign bus_sel_same = (bus_sel_f[3:0] == bus_sel[3:0]);
assign sahbl_sel_pred = bus_sel_f[3];
assign dahbl_sel_pred = bus_sel_f[0];
assign iahbl_sel_pred = bus_sel_f[1];
assign tcip_sel_pred = bus_sel_f[2];
//==========================================================
// interface
//==========================================================
//input
assign bus_grant = iahbl_hit & iahbl_bmu_xx_grnt |
dahbl_hit & dahbl_bmu_xx_grnt |
tcipif_hit & tcipif_bmu_xx_grnt |
sahbl_hit & sahbl_bmu_xx_grnt;
assign bus_cmplt = iahbl_bmu_xx_trans_cmplt |
dahbl_bmu_xx_trans_cmplt |
tcipif_bmu_xx_trans_cmplt |
sahbl_bmu_xx_trans_cmplt;
assign bus_acc_err = iahbl_bmu_xx_acc_err |
dahbl_bmu_xx_acc_err |
tcipif_bmu_xx_acc_err|
sahbl_bmu_xx_acc_err;
assign bmu_tt_grant = bus_grant & req_en;
assign bmu_tt_trans_cmplt = bus_cmplt;
assign bmu_tt_acc_err = bus_acc_err;
assign bmu_tt_rdata[31:0] = ({32{bus_sel_f[0]}} & dahbl_bmu_xx_data[31:0]) |
({32{bus_sel_f[1]}} & iahbl_bmu_xx_data[31:0]) |
({32{bus_sel_f[2]}} & tcipif_bmu_xx_data[31:0]) |
({32{bus_sel_f[3]}} & sahbl_bmu_xx_data[31:0]);
//--------------------------------------
//output
//--------------------------------------
//interface to ILITE
assign bmu_iahbl_xx_req = tt_bmu_req & iahbl_hit & req_en & iahbl_sel_pred;
assign bmu_iahbl_xx_req_dp = tt_bmu_data_req & iahbl_sel_pred;
assign bmu_iahbl_xx_acc_deny = tt_bmu_acc_deny;
assign bmu_iahbl_xx_size[1:0] = tt_bmu_size[1:0];
assign bmu_iahbl_xx_addr[31:0] = tt_bmu_addr[31:0];
assign bmu_iahbl_xx_prot[3:0] = tt_bmu_prot[3:0];
assign bmu_iahbl_xx_write = tt_bmu_write;
assign bmu_iahbl_xx_wdata[31:0] = tt_bmu_wdata[31:0];
assign bmu_iahbl_xx_seq = tt_bmu_seq;
assign bmu_iahbl_xx_burst[2:0] = tt_bmu_burst[2:0];
//interface to DL
assign bmu_dahbl_xx_req = tt_bmu_req & dahbl_hit & req_en & dahbl_sel_pred;
assign bmu_dahbl_xx_req_dp = tt_bmu_data_req & dahbl_sel_pred;
assign bmu_dahbl_xx_acc_deny = tt_bmu_acc_deny;
assign bmu_dahbl_xx_size[1:0] = tt_bmu_size[1:0];
assign bmu_dahbl_xx_addr[31:0] = tt_bmu_addr[31:0];
assign bmu_dahbl_xx_prot[3:0] = tt_bmu_prot[3:0];
assign bmu_dahbl_xx_write = tt_bmu_write;
assign bmu_dahbl_xx_wdata[31:0] = tt_bmu_wdata[31:0];
assign bmu_dahbl_xx_seq = tt_bmu_seq;
assign bmu_dahbl_xx_burst[2:0] = tt_bmu_burst[2:0];
//tcipif
assign bmu_tcipif_xx_req = tt_bmu_req & req_en & tcipif_hit & tcip_sel_pred;
assign bmu_tcipif_xx_req_dp = tt_bmu_data_req & tcip_sel_pred;
assign bmu_tcipif_xx_acc_deny = tt_bmu_acc_deny;
assign bmu_tcipif_xx_write = tt_bmu_write;
assign bmu_tcipif_xx_size[1:0] = tt_bmu_size[1:0];
assign bmu_tcipif_xx_supv_mode = tt_bmu_prot[1];
assign bmu_tcipif_xx_wdata[31:0] = tt_bmu_wdata[31:0];
assign bmu_tcipif_xx_addr[31:0] = {tt_bmu_addr[31:16], tcipif_addr_low[15:0]};
assign tcipif_addr_low[15:0] = {16{tcipif_hit}} & tt_bmu_addr[15:0];
//sahbl
assign bmu_sahbl_xx_req = tt_bmu_req & sahbl_hit & req_en & sahbl_sel_pred;
assign bmu_sahbl_xx_req_dp = tt_bmu_data_req & sahbl_sel_pred;
assign bmu_sahbl_xx_acc_deny = tt_bmu_acc_deny;
assign bmu_sahbl_xx_size[1:0] = tt_bmu_size[1:0];
assign bmu_sahbl_xx_addr[31:0] = tt_bmu_addr[31:0];
assign bmu_sahbl_xx_prot[3:0] = tt_bmu_prot[3:0];
assign bmu_sahbl_xx_write = tt_bmu_write;
assign bmu_sahbl_xx_wdata[31:0] = tt_bmu_wdata[31:0];
assign bmu_sahbl_xx_seq = tt_bmu_seq;
assign bmu_sahbl_xx_burst[2:0] = tt_bmu_burst[2:0];
assign bmu_tt_clk_en = tt_bmu_data_req | ~(bmu_cur_state[1:0] == REQ);
assign xx_dbginfo[1:0] = bmu_cur_state[1:0];
// &ModuleEnd; @227
endmodule

486
opene906/E906_RTL_FACTORY/gen_rtl/bmu/rtl/pa_bmu_dbus_if.v Normal file
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@ -0,0 +1,486 @@
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_bmu_dbus_if(
bmu_clk,
bmu_dahbl_dbus_acc_deny,
bmu_dahbl_dbus_addr,
bmu_dahbl_dbus_burst,
bmu_dahbl_dbus_lock,
bmu_dahbl_dbus_lrsc,
bmu_dahbl_dbus_prot,
bmu_dahbl_dbus_req,
bmu_dahbl_dbus_req_dp,
bmu_dahbl_dbus_seq,
bmu_dahbl_dbus_size,
bmu_dahbl_dbus_wdata,
bmu_dahbl_dbus_write,
bmu_iahbl_dbus_acc_deny,
bmu_iahbl_dbus_addr,
bmu_iahbl_dbus_burst,
bmu_iahbl_dbus_lock,
bmu_iahbl_dbus_lrsc,
bmu_iahbl_dbus_prot,
bmu_iahbl_dbus_req,
bmu_iahbl_dbus_req_dp,
bmu_iahbl_dbus_seq,
bmu_iahbl_dbus_size,
bmu_iahbl_dbus_wdata,
bmu_iahbl_dbus_write,
bmu_lsu_acc_err,
bmu_lsu_clk_en,
bmu_lsu_grant,
bmu_lsu_rdata,
bmu_lsu_trans_cmplt,
bmu_sahbl_dbus_acc_deny,
bmu_sahbl_dbus_addr,
bmu_sahbl_dbus_burst,
bmu_sahbl_dbus_lock,
bmu_sahbl_dbus_lrsc,
bmu_sahbl_dbus_prot,
bmu_sahbl_dbus_req,
bmu_sahbl_dbus_req_dp,
bmu_sahbl_dbus_seq,
bmu_sahbl_dbus_size,
bmu_sahbl_dbus_wdata,
bmu_sahbl_dbus_write,
bmu_tcipif_dbus_acc_deny,
bmu_tcipif_dbus_addr,
bmu_tcipif_dbus_req,
bmu_tcipif_dbus_req_dp,
bmu_tcipif_dbus_size,
bmu_tcipif_dbus_supv_mode,
bmu_tcipif_dbus_wdata,
bmu_tcipif_dbus_write,
cpurst_b,
dahbl_bmu_dbus_acc_err,
dahbl_bmu_dbus_data,
dahbl_bmu_dbus_grnt,
dahbl_bmu_dbus_trans_cmplt,
dbus_dbginfo,
iahbl_bmu_dbus_acc_err,
iahbl_bmu_dbus_data,
iahbl_bmu_dbus_grnt,
iahbl_bmu_dbus_trans_cmplt,
lsu_bmu_acc_deny,
lsu_bmu_addr,
lsu_bmu_burst,
lsu_bmu_lock,
lsu_bmu_lrsc,
lsu_bmu_prot,
lsu_bmu_req,
lsu_bmu_req_dp,
lsu_bmu_seq,
lsu_bmu_size,
lsu_bmu_wdata,
lsu_bmu_write,
pad_bmu_dahbl_base,
pad_bmu_dahbl_mask,
pad_bmu_iahbl_base,
pad_bmu_iahbl_mask,
pad_cpu_tcip_base,
rtu_yy_xx_async_flush,
sahbl_bmu_dbus_acc_err,
sahbl_bmu_dbus_data,
sahbl_bmu_dbus_grnt,
sahbl_bmu_dbus_trans_cmplt,
tcipif_bmu_dbus_acc_err,
tcipif_bmu_dbus_data,
tcipif_bmu_dbus_grnt,
tcipif_bmu_dbus_trans_cmplt
);
// &Ports; @22
input bmu_clk;
input cpurst_b;
input dahbl_bmu_dbus_acc_err;
input [31:0] dahbl_bmu_dbus_data;
input dahbl_bmu_dbus_grnt;
input dahbl_bmu_dbus_trans_cmplt;
input iahbl_bmu_dbus_acc_err;
input [31:0] iahbl_bmu_dbus_data;
input iahbl_bmu_dbus_grnt;
input iahbl_bmu_dbus_trans_cmplt;
input lsu_bmu_acc_deny;
input [31:0] lsu_bmu_addr;
input [2 :0] lsu_bmu_burst;
input lsu_bmu_lock;
input lsu_bmu_lrsc;
input [3 :0] lsu_bmu_prot;
input lsu_bmu_req;
input lsu_bmu_req_dp;
input lsu_bmu_seq;
input [1 :0] lsu_bmu_size;
input [31:0] lsu_bmu_wdata;
input lsu_bmu_write;
input [11:0] pad_bmu_dahbl_base;
input [11:0] pad_bmu_dahbl_mask;
input [11:0] pad_bmu_iahbl_base;
input [11:0] pad_bmu_iahbl_mask;
input [31:0] pad_cpu_tcip_base;
input rtu_yy_xx_async_flush;
input sahbl_bmu_dbus_acc_err;
input [31:0] sahbl_bmu_dbus_data;
input sahbl_bmu_dbus_grnt;
input sahbl_bmu_dbus_trans_cmplt;
input tcipif_bmu_dbus_acc_err;
input [31:0] tcipif_bmu_dbus_data;
input tcipif_bmu_dbus_grnt;
input tcipif_bmu_dbus_trans_cmplt;
output bmu_dahbl_dbus_acc_deny;
output [31:0] bmu_dahbl_dbus_addr;
output [2 :0] bmu_dahbl_dbus_burst;
output bmu_dahbl_dbus_lock;
output bmu_dahbl_dbus_lrsc;
output [3 :0] bmu_dahbl_dbus_prot;
output bmu_dahbl_dbus_req;
output bmu_dahbl_dbus_req_dp;
output bmu_dahbl_dbus_seq;
output [1 :0] bmu_dahbl_dbus_size;
output [31:0] bmu_dahbl_dbus_wdata;
output bmu_dahbl_dbus_write;
output bmu_iahbl_dbus_acc_deny;
output [31:0] bmu_iahbl_dbus_addr;
output [2 :0] bmu_iahbl_dbus_burst;
output bmu_iahbl_dbus_lock;
output bmu_iahbl_dbus_lrsc;
output [3 :0] bmu_iahbl_dbus_prot;
output bmu_iahbl_dbus_req;
output bmu_iahbl_dbus_req_dp;
output bmu_iahbl_dbus_seq;
output [1 :0] bmu_iahbl_dbus_size;
output [31:0] bmu_iahbl_dbus_wdata;
output bmu_iahbl_dbus_write;
output bmu_lsu_acc_err;
output bmu_lsu_clk_en;
output bmu_lsu_grant;
output [31:0] bmu_lsu_rdata;
output bmu_lsu_trans_cmplt;
output bmu_sahbl_dbus_acc_deny;
output [31:0] bmu_sahbl_dbus_addr;
output [2 :0] bmu_sahbl_dbus_burst;
output bmu_sahbl_dbus_lock;
output bmu_sahbl_dbus_lrsc;
output [3 :0] bmu_sahbl_dbus_prot;
output bmu_sahbl_dbus_req;
output bmu_sahbl_dbus_req_dp;
output bmu_sahbl_dbus_seq;
output [1 :0] bmu_sahbl_dbus_size;
output [31:0] bmu_sahbl_dbus_wdata;
output bmu_sahbl_dbus_write;
output bmu_tcipif_dbus_acc_deny;
output [31:0] bmu_tcipif_dbus_addr;
output bmu_tcipif_dbus_req;
output bmu_tcipif_dbus_req_dp;
output [1 :0] bmu_tcipif_dbus_size;
output bmu_tcipif_dbus_supv_mode;
output [31:0] bmu_tcipif_dbus_wdata;
output bmu_tcipif_dbus_write;
output [1 :0] dbus_dbginfo;
// &Regs; @23
reg [1 :0] bmu_cur_state;
reg [1 :0] bmu_next_state;
reg [3 :0] bus_sel_f;
// &Wires; @24
wire bmu_clk;
wire bmu_dahbl_dbus_acc_deny;
wire [31:0] bmu_dahbl_dbus_addr;
wire [2 :0] bmu_dahbl_dbus_burst;
wire bmu_dahbl_dbus_lock;
wire bmu_dahbl_dbus_lrsc;
wire [3 :0] bmu_dahbl_dbus_prot;
wire bmu_dahbl_dbus_req;
wire bmu_dahbl_dbus_req_dp;
wire bmu_dahbl_dbus_seq;
wire [1 :0] bmu_dahbl_dbus_size;
wire [31:0] bmu_dahbl_dbus_wdata;
wire bmu_dahbl_dbus_write;
wire bmu_iahbl_dbus_acc_deny;
wire [31:0] bmu_iahbl_dbus_addr;
wire [2 :0] bmu_iahbl_dbus_burst;
wire bmu_iahbl_dbus_lock;
wire bmu_iahbl_dbus_lrsc;
wire [3 :0] bmu_iahbl_dbus_prot;
wire bmu_iahbl_dbus_req;
wire bmu_iahbl_dbus_req_dp;
wire bmu_iahbl_dbus_seq;
wire [1 :0] bmu_iahbl_dbus_size;
wire [31:0] bmu_iahbl_dbus_wdata;
wire bmu_iahbl_dbus_write;
wire bmu_lsu_acc_err;
wire bmu_lsu_clk_en;
wire bmu_lsu_grant;
wire [31:0] bmu_lsu_rdata;
wire bmu_lsu_trans_cmplt;
wire bmu_req_vld;
wire bmu_sahbl_dbus_acc_deny;
wire [31:0] bmu_sahbl_dbus_addr;
wire [2 :0] bmu_sahbl_dbus_burst;
wire bmu_sahbl_dbus_lock;
wire bmu_sahbl_dbus_lrsc;
wire [3 :0] bmu_sahbl_dbus_prot;
wire bmu_sahbl_dbus_req;
wire bmu_sahbl_dbus_req_dp;
wire bmu_sahbl_dbus_seq;
wire [1 :0] bmu_sahbl_dbus_size;
wire [31:0] bmu_sahbl_dbus_wdata;
wire bmu_sahbl_dbus_write;
wire bmu_tcipif_dbus_acc_deny;
wire [31:0] bmu_tcipif_dbus_addr;
wire bmu_tcipif_dbus_req;
wire bmu_tcipif_dbus_req_dp;
wire [1 :0] bmu_tcipif_dbus_size;
wire bmu_tcipif_dbus_supv_mode;
wire [31:0] bmu_tcipif_dbus_wdata;
wire bmu_tcipif_dbus_write;
wire [3 :0] bus_sel;
wire bus_sel_same;
wire cpurst_b;
wire dahbl_bmu_dbus_acc_err;
wire [31:0] dahbl_bmu_dbus_data;
wire dahbl_bmu_dbus_grnt;
wire dahbl_bmu_dbus_trans_cmplt;
wire dahbl_hit;
wire dahbl_sel_pred;
wire dbus_acc_err;
wire dbus_cmplt;
wire [1 :0] dbus_dbginfo;
wire dbus_grant;
wire iahbl_bmu_dbus_acc_err;
wire [31:0] iahbl_bmu_dbus_data;
wire iahbl_bmu_dbus_grnt;
wire iahbl_bmu_dbus_trans_cmplt;
wire iahbl_hit;
wire iahbl_sel_pred;
wire lsu_bmu_acc_deny;
wire [31:0] lsu_bmu_addr;
wire [2 :0] lsu_bmu_burst;
wire lsu_bmu_lock;
wire lsu_bmu_lrsc;
wire [3 :0] lsu_bmu_prot;
wire lsu_bmu_req;
wire lsu_bmu_req_dp;
wire lsu_bmu_seq;
wire [1 :0] lsu_bmu_size;
wire [31:0] lsu_bmu_wdata;
wire lsu_bmu_write;
wire new_req_en;
wire [11:0] pad_bmu_dahbl_base;
wire [11:0] pad_bmu_dahbl_mask;
wire [11:0] pad_bmu_iahbl_base;
wire [11:0] pad_bmu_iahbl_mask;
wire [31:0] pad_cpu_tcip_base;
wire req_en;
wire rtu_yy_xx_async_flush;
wire sahbl_bmu_dbus_acc_err;
wire [31:0] sahbl_bmu_dbus_data;
wire sahbl_bmu_dbus_grnt;
wire sahbl_bmu_dbus_trans_cmplt;
wire sahbl_hit;
wire sahbl_sel_pred;
wire tcip_sel_pred;
wire [15:0] tcipif_addr_low;
wire tcipif_bmu_dbus_acc_err;
wire [31:0] tcipif_bmu_dbus_data;
wire tcipif_bmu_dbus_grnt;
wire tcipif_bmu_dbus_trans_cmplt;
wire tcipif_hit;
//==========================================================
// request direction checking
//==========================================================
assign iahbl_hit = ((lsu_bmu_addr[31:20] & pad_bmu_iahbl_mask[11:0]) == pad_bmu_iahbl_base[11:0])
& ~tcipif_hit & ~dahbl_hit;
assign dahbl_hit = ((lsu_bmu_addr[31:20] & pad_bmu_dahbl_mask[11:0]) == pad_bmu_dahbl_base[11:0])
& ~tcipif_hit;
// &Force("input", "pad_cpu_tcip_base"); @44
// &Force("bus","pad_cpu_tcip_base",31,0); @45
assign tcipif_hit = (lsu_bmu_addr[31:28] == pad_cpu_tcip_base[31:28]);
assign sahbl_hit = ~dahbl_hit & ~iahbl_hit & ~tcipif_hit;
assign bus_sel[3:0] = {sahbl_hit,tcipif_hit,iahbl_hit,dahbl_hit};
//==========================================================
// FSM
//==========================================================
parameter REQ = 2'b00;
parameter WFG = 2'b11;
parameter WFD = 2'b01;
always @(posedge bmu_clk or negedge cpurst_b)
begin
if(!cpurst_b)
bmu_cur_state[1:0] <= REQ;
else if (rtu_yy_xx_async_flush)
bmu_cur_state[1:0] <= REQ;
else
bmu_cur_state[1:0] <= bmu_next_state[1:0];
end
assign bmu_req_vld = lsu_bmu_req;
// &CombBeg; @74
always @( dbus_grant
or dbus_cmplt
or dbus_acc_err
or bmu_cur_state[1:0]
or bus_sel_same
or bmu_req_vld)
begin
case(bmu_cur_state[1:0])
REQ: begin
if (bmu_req_vld)
bmu_next_state[1:0] = dbus_grant ? WFD : WFG;
else
bmu_next_state[1:0] = REQ;
end
WFG:begin
if (dbus_grant)
bmu_next_state[1:0] = WFD;
else
bmu_next_state[1:0] = WFG;
end
WFD: begin
if (dbus_cmplt)begin
if (bmu_req_vld & bus_sel_same & !dbus_acc_err)
bmu_next_state[1:0] = dbus_grant ? WFD : WFG;
else
bmu_next_state[1:0] = REQ;
end
else
bmu_next_state[1:0] = WFD;
end
default: bmu_next_state[1:0] = REQ;
endcase
// &CombEnd; @100
end
assign req_en = (bmu_cur_state[1:0] == REQ) |
(bmu_cur_state[1:0] == WFG) |
(bmu_cur_state[1:0] == WFD) & bus_sel_same;
assign new_req_en = (bmu_cur_state[1:0] == REQ);
always @(posedge bmu_clk or negedge cpurst_b)
begin
if(!cpurst_b)
bus_sel_f[3:0] <= 4'b0;
else if (bmu_req_vld & new_req_en)
bus_sel_f[3:0] <= bus_sel[3:0];
end
assign bus_sel_same = (bus_sel_f[3:0] == bus_sel[3:0]);
assign sahbl_sel_pred = bus_sel_f[3];
assign dahbl_sel_pred = bus_sel_f[0];
assign iahbl_sel_pred = bus_sel_f[1];
assign tcip_sel_pred = bus_sel_f[2];
//==========================================================
// interface
//==========================================================
//input
assign dbus_grant = dahbl_hit & dahbl_bmu_dbus_grnt |
iahbl_hit & iahbl_bmu_dbus_grnt |
tcipif_hit & tcipif_bmu_dbus_grnt |
sahbl_hit & sahbl_bmu_dbus_grnt;
assign dbus_cmplt = dahbl_bmu_dbus_trans_cmplt |
iahbl_bmu_dbus_trans_cmplt |
tcipif_bmu_dbus_trans_cmplt |
sahbl_bmu_dbus_trans_cmplt;
assign dbus_acc_err = dahbl_bmu_dbus_acc_err |
iahbl_bmu_dbus_acc_err |
tcipif_bmu_dbus_acc_err |
sahbl_bmu_dbus_acc_err;
assign bmu_lsu_grant = dbus_grant & req_en;
assign bmu_lsu_trans_cmplt = dbus_cmplt;
assign bmu_lsu_acc_err = dbus_acc_err;
assign bmu_lsu_rdata[31:0] = ({32{bus_sel_f[0]}} & dahbl_bmu_dbus_data[31:0]) |
({32{bus_sel_f[1]}} & iahbl_bmu_dbus_data[31:0]) |
({32{bus_sel_f[2]}} & tcipif_bmu_dbus_data[31:0]) |
({32{bus_sel_f[3]}} & sahbl_bmu_dbus_data[31:0]);
//--------------------------------------
//output
//--------------------------------------
//iahbl
assign bmu_iahbl_dbus_req = lsu_bmu_req & req_en & iahbl_hit & iahbl_sel_pred;
assign bmu_iahbl_dbus_req_dp = lsu_bmu_req_dp & iahbl_sel_pred;
assign bmu_iahbl_dbus_addr[31:0] = lsu_bmu_addr[31:0];
assign bmu_iahbl_dbus_acc_deny = lsu_bmu_acc_deny;
assign bmu_iahbl_dbus_write = lsu_bmu_write;
assign bmu_iahbl_dbus_size[1:0] = lsu_bmu_size[1:0];
assign bmu_iahbl_dbus_prot[3:0] = lsu_bmu_prot[3:0];
assign bmu_iahbl_dbus_wdata[31:0] = lsu_bmu_wdata[31:0];
assign bmu_iahbl_dbus_lock = lsu_bmu_lock;
assign bmu_iahbl_dbus_lrsc = lsu_bmu_lrsc;
assign bmu_iahbl_dbus_seq = lsu_bmu_seq;
assign bmu_iahbl_dbus_burst[2:0] = lsu_bmu_burst[2:0];
//dahbl
assign bmu_dahbl_dbus_req = lsu_bmu_req & req_en & dahbl_hit & dahbl_sel_pred;
assign bmu_dahbl_dbus_req_dp = lsu_bmu_req_dp & dahbl_sel_pred;
assign bmu_dahbl_dbus_addr[31:0] = lsu_bmu_addr[31:0];
assign bmu_dahbl_dbus_acc_deny = lsu_bmu_acc_deny;
assign bmu_dahbl_dbus_write = lsu_bmu_write;
assign bmu_dahbl_dbus_size[1:0] = lsu_bmu_size[1:0];
assign bmu_dahbl_dbus_prot[3:0] = lsu_bmu_prot[3:0];
assign bmu_dahbl_dbus_wdata[31:0] = lsu_bmu_wdata[31:0];
assign bmu_dahbl_dbus_lock = lsu_bmu_lock;
assign bmu_dahbl_dbus_lrsc = lsu_bmu_lrsc;
assign bmu_dahbl_dbus_seq = lsu_bmu_seq;
assign bmu_dahbl_dbus_burst[2:0] = lsu_bmu_burst[2:0];
//tcipif
assign bmu_tcipif_dbus_req = lsu_bmu_req & req_en & tcipif_hit & tcip_sel_pred;
assign bmu_tcipif_dbus_req_dp = lsu_bmu_req_dp & tcip_sel_pred;
assign bmu_tcipif_dbus_acc_deny = lsu_bmu_acc_deny;
assign bmu_tcipif_dbus_write = lsu_bmu_write;
assign bmu_tcipif_dbus_size[1:0] = lsu_bmu_size[1:0];
assign bmu_tcipif_dbus_supv_mode = lsu_bmu_prot[1];
assign bmu_tcipif_dbus_wdata[31:0] = lsu_bmu_wdata[31:0];
assign bmu_tcipif_dbus_addr[31:0] = {lsu_bmu_addr[31:16], tcipif_addr_low[15:0]};
assign tcipif_addr_low[15:0] = {16{tcipif_hit}} & lsu_bmu_addr[15:0];
//sahbl
assign bmu_sahbl_dbus_req = lsu_bmu_req & req_en & sahbl_hit & sahbl_sel_pred;
assign bmu_sahbl_dbus_req_dp = lsu_bmu_req_dp & sahbl_sel_pred;
assign bmu_sahbl_dbus_addr[31:0] = lsu_bmu_addr[31:0];
assign bmu_sahbl_dbus_acc_deny = lsu_bmu_acc_deny;
assign bmu_sahbl_dbus_write = lsu_bmu_write;
assign bmu_sahbl_dbus_size[1:0] = lsu_bmu_size[1:0];
assign bmu_sahbl_dbus_prot[3:0] = lsu_bmu_prot[3:0];
assign bmu_sahbl_dbus_wdata[31:0] = lsu_bmu_wdata[31:0];
assign bmu_sahbl_dbus_lock = lsu_bmu_lock;
assign bmu_sahbl_dbus_lrsc = lsu_bmu_lrsc;
assign bmu_sahbl_dbus_seq = lsu_bmu_seq;
assign bmu_sahbl_dbus_burst[2:0] = lsu_bmu_burst[2:0];
assign bmu_lsu_clk_en = lsu_bmu_req_dp |
~(bmu_cur_state[1:0] == REQ);
assign dbus_dbginfo[1:0] = bmu_cur_state[1:0];
// &ModuleEnd; @237
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_bmu_top(
bmu_dahbl_dbus_acc_deny,
bmu_dahbl_dbus_addr,
bmu_dahbl_dbus_burst,
bmu_dahbl_dbus_lock,
bmu_dahbl_dbus_lrsc,
bmu_dahbl_dbus_prot,
bmu_dahbl_dbus_req,
bmu_dahbl_dbus_req_dp,
bmu_dahbl_dbus_seq,
bmu_dahbl_dbus_size,
bmu_dahbl_dbus_wdata,
bmu_dahbl_dbus_write,
bmu_dahbl_ibus_acc_deny,
bmu_dahbl_ibus_addr,
bmu_dahbl_ibus_burst,
bmu_dahbl_ibus_prot,
bmu_dahbl_ibus_req,
bmu_dahbl_ibus_req_dp,
bmu_dahbl_ibus_seq,
bmu_dahbl_ibus_size,
bmu_dtu_debug_info,
bmu_iahbl_dbus_acc_deny,
bmu_iahbl_dbus_addr,
bmu_iahbl_dbus_burst,
bmu_iahbl_dbus_lock,
bmu_iahbl_dbus_lrsc,
bmu_iahbl_dbus_prot,
bmu_iahbl_dbus_req,
bmu_iahbl_dbus_req_dp,
bmu_iahbl_dbus_seq,
bmu_iahbl_dbus_size,
bmu_iahbl_dbus_wdata,
bmu_iahbl_dbus_write,
bmu_iahbl_ibus_acc_deny,
bmu_iahbl_ibus_addr,
bmu_iahbl_ibus_burst,
bmu_iahbl_ibus_prot,
bmu_iahbl_ibus_req,
bmu_iahbl_ibus_req_dp,
bmu_iahbl_ibus_seq,
bmu_iahbl_ibus_size,
bmu_ifu_acc_err,
bmu_ifu_grant,
bmu_ifu_rdata,
bmu_ifu_trans_cmplt,
bmu_lsu_acc_err,
bmu_lsu_grant,
bmu_lsu_rdata,
bmu_lsu_trans_cmplt,
bmu_sahbl_dbus_acc_deny,
bmu_sahbl_dbus_addr,
bmu_sahbl_dbus_burst,
bmu_sahbl_dbus_lock,
bmu_sahbl_dbus_lrsc,
bmu_sahbl_dbus_prot,
bmu_sahbl_dbus_req,
bmu_sahbl_dbus_req_dp,
bmu_sahbl_dbus_seq,
bmu_sahbl_dbus_size,
bmu_sahbl_dbus_wdata,
bmu_sahbl_dbus_write,
bmu_sahbl_ibus_acc_deny,
bmu_sahbl_ibus_addr,
bmu_sahbl_ibus_burst,
bmu_sahbl_ibus_prot,
bmu_sahbl_ibus_req,
bmu_sahbl_ibus_req_dp,
bmu_sahbl_ibus_seq,
bmu_sahbl_ibus_size,
bmu_tcipif_dbus_acc_deny,
bmu_tcipif_dbus_addr,
bmu_tcipif_dbus_req,
bmu_tcipif_dbus_req_dp,
bmu_tcipif_dbus_size,
bmu_tcipif_dbus_supv_mode,
bmu_tcipif_dbus_wdata,
bmu_tcipif_dbus_write,
bmu_tcipif_ibus_acc_deny,
bmu_tcipif_ibus_addr,
bmu_tcipif_ibus_req,
bmu_tcipif_ibus_req_dp,
bmu_tcipif_ibus_size,
bmu_tcipif_ibus_supv_mode,
bmu_tcipif_ibus_wdata,
bmu_tcipif_ibus_write,
cp0_biu_icg_en,
cpurst_b,
dahbl_bmu_dbus_acc_err,
dahbl_bmu_dbus_data,
dahbl_bmu_dbus_grnt,
dahbl_bmu_dbus_trans_cmplt,
dahbl_bmu_ibus_acc_err,
dahbl_bmu_ibus_data,
dahbl_bmu_ibus_grnt,
dahbl_bmu_ibus_trans_cmplt,
forever_cpuclk,
iahbl_bmu_dbus_acc_err,
iahbl_bmu_dbus_data,
iahbl_bmu_dbus_grnt,
iahbl_bmu_dbus_trans_cmplt,
iahbl_bmu_ibus_acc_err,
iahbl_bmu_ibus_data,
iahbl_bmu_ibus_grnt,
iahbl_bmu_ibus_trans_cmplt,
ifu_bmu_acc_deny,
ifu_bmu_addr,
ifu_bmu_burst,
ifu_bmu_data_req,
ifu_bmu_prot,
ifu_bmu_req,
ifu_bmu_seq,
ifu_bmu_size,
lsu_bmu_acc_deny,
lsu_bmu_addr,
lsu_bmu_burst,
lsu_bmu_lock,
lsu_bmu_lrsc,
lsu_bmu_prot,
lsu_bmu_req,
lsu_bmu_req_dp,
lsu_bmu_seq,
lsu_bmu_size,
lsu_bmu_wdata,
lsu_bmu_write,
pad_bmu_dahbl_base,
pad_bmu_dahbl_mask,
pad_bmu_iahbl_base,
pad_bmu_iahbl_mask,
pad_cpu_tcip_base,
pad_yy_icg_scan_en,
rtu_yy_xx_async_flush,
sahbl_bmu_dbus_acc_err,
sahbl_bmu_dbus_data,
sahbl_bmu_dbus_grnt,
sahbl_bmu_dbus_trans_cmplt,
sahbl_bmu_ibus_acc_err,
sahbl_bmu_ibus_data,
sahbl_bmu_ibus_grnt,
sahbl_bmu_ibus_trans_cmplt,
tcipif_bmu_dbus_acc_err,
tcipif_bmu_dbus_data,
tcipif_bmu_dbus_grnt,
tcipif_bmu_dbus_trans_cmplt,
tcipif_bmu_ibus_acc_err,
tcipif_bmu_ibus_data,
tcipif_bmu_ibus_grnt,
tcipif_bmu_ibus_trans_cmplt
);
// &Ports; @23
input cp0_biu_icg_en;
input cpurst_b;
input dahbl_bmu_dbus_acc_err;
input [31:0] dahbl_bmu_dbus_data;
input dahbl_bmu_dbus_grnt;
input dahbl_bmu_dbus_trans_cmplt;
input dahbl_bmu_ibus_acc_err;
input [31:0] dahbl_bmu_ibus_data;
input dahbl_bmu_ibus_grnt;
input dahbl_bmu_ibus_trans_cmplt;
input forever_cpuclk;
input iahbl_bmu_dbus_acc_err;
input [31:0] iahbl_bmu_dbus_data;
input iahbl_bmu_dbus_grnt;
input iahbl_bmu_dbus_trans_cmplt;
input iahbl_bmu_ibus_acc_err;
input [31:0] iahbl_bmu_ibus_data;
input iahbl_bmu_ibus_grnt;
input iahbl_bmu_ibus_trans_cmplt;
input ifu_bmu_acc_deny;
input [31:0] ifu_bmu_addr;
input [2 :0] ifu_bmu_burst;
input ifu_bmu_data_req;
input [3 :0] ifu_bmu_prot;
input ifu_bmu_req;
input ifu_bmu_seq;
input [1 :0] ifu_bmu_size;
input lsu_bmu_acc_deny;
input [31:0] lsu_bmu_addr;
input [2 :0] lsu_bmu_burst;
input lsu_bmu_lock;
input lsu_bmu_lrsc;
input [3 :0] lsu_bmu_prot;
input lsu_bmu_req;
input lsu_bmu_req_dp;
input lsu_bmu_seq;
input [1 :0] lsu_bmu_size;
input [31:0] lsu_bmu_wdata;
input lsu_bmu_write;
input [11:0] pad_bmu_dahbl_base;
input [11:0] pad_bmu_dahbl_mask;
input [11:0] pad_bmu_iahbl_base;
input [11:0] pad_bmu_iahbl_mask;
input [31:0] pad_cpu_tcip_base;
input pad_yy_icg_scan_en;
input rtu_yy_xx_async_flush;
input sahbl_bmu_dbus_acc_err;
input [31:0] sahbl_bmu_dbus_data;
input sahbl_bmu_dbus_grnt;
input sahbl_bmu_dbus_trans_cmplt;
input sahbl_bmu_ibus_acc_err;
input [31:0] sahbl_bmu_ibus_data;
input sahbl_bmu_ibus_grnt;
input sahbl_bmu_ibus_trans_cmplt;
input tcipif_bmu_dbus_acc_err;
input [31:0] tcipif_bmu_dbus_data;
input tcipif_bmu_dbus_grnt;
input tcipif_bmu_dbus_trans_cmplt;
input tcipif_bmu_ibus_acc_err;
input [31:0] tcipif_bmu_ibus_data;
input tcipif_bmu_ibus_grnt;
input tcipif_bmu_ibus_trans_cmplt;
output bmu_dahbl_dbus_acc_deny;
output [31:0] bmu_dahbl_dbus_addr;
output [2 :0] bmu_dahbl_dbus_burst;
output bmu_dahbl_dbus_lock;
output bmu_dahbl_dbus_lrsc;
output [3 :0] bmu_dahbl_dbus_prot;
output bmu_dahbl_dbus_req;
output bmu_dahbl_dbus_req_dp;
output bmu_dahbl_dbus_seq;
output [1 :0] bmu_dahbl_dbus_size;
output [31:0] bmu_dahbl_dbus_wdata;
output bmu_dahbl_dbus_write;
output bmu_dahbl_ibus_acc_deny;
output [31:0] bmu_dahbl_ibus_addr;
output [2 :0] bmu_dahbl_ibus_burst;
output [3 :0] bmu_dahbl_ibus_prot;
output bmu_dahbl_ibus_req;
output bmu_dahbl_ibus_req_dp;
output bmu_dahbl_ibus_seq;
output [1 :0] bmu_dahbl_ibus_size;
output [3 :0] bmu_dtu_debug_info;
output bmu_iahbl_dbus_acc_deny;
output [31:0] bmu_iahbl_dbus_addr;
output [2 :0] bmu_iahbl_dbus_burst;
output bmu_iahbl_dbus_lock;
output bmu_iahbl_dbus_lrsc;
output [3 :0] bmu_iahbl_dbus_prot;
output bmu_iahbl_dbus_req;
output bmu_iahbl_dbus_req_dp;
output bmu_iahbl_dbus_seq;
output [1 :0] bmu_iahbl_dbus_size;
output [31:0] bmu_iahbl_dbus_wdata;
output bmu_iahbl_dbus_write;
output bmu_iahbl_ibus_acc_deny;
output [31:0] bmu_iahbl_ibus_addr;
output [2 :0] bmu_iahbl_ibus_burst;
output [3 :0] bmu_iahbl_ibus_prot;
output bmu_iahbl_ibus_req;
output bmu_iahbl_ibus_req_dp;
output bmu_iahbl_ibus_seq;
output [1 :0] bmu_iahbl_ibus_size;
output bmu_ifu_acc_err;
output bmu_ifu_grant;
output [31:0] bmu_ifu_rdata;
output bmu_ifu_trans_cmplt;
output bmu_lsu_acc_err;
output bmu_lsu_grant;
output [31:0] bmu_lsu_rdata;
output bmu_lsu_trans_cmplt;
output bmu_sahbl_dbus_acc_deny;
output [31:0] bmu_sahbl_dbus_addr;
output [2 :0] bmu_sahbl_dbus_burst;
output bmu_sahbl_dbus_lock;
output bmu_sahbl_dbus_lrsc;
output [3 :0] bmu_sahbl_dbus_prot;
output bmu_sahbl_dbus_req;
output bmu_sahbl_dbus_req_dp;
output bmu_sahbl_dbus_seq;
output [1 :0] bmu_sahbl_dbus_size;
output [31:0] bmu_sahbl_dbus_wdata;
output bmu_sahbl_dbus_write;
output bmu_sahbl_ibus_acc_deny;
output [31:0] bmu_sahbl_ibus_addr;
output [2 :0] bmu_sahbl_ibus_burst;
output [3 :0] bmu_sahbl_ibus_prot;
output bmu_sahbl_ibus_req;
output bmu_sahbl_ibus_req_dp;
output bmu_sahbl_ibus_seq;
output [1 :0] bmu_sahbl_ibus_size;
output bmu_tcipif_dbus_acc_deny;
output [31:0] bmu_tcipif_dbus_addr;
output bmu_tcipif_dbus_req;
output bmu_tcipif_dbus_req_dp;
output [1 :0] bmu_tcipif_dbus_size;
output bmu_tcipif_dbus_supv_mode;
output [31:0] bmu_tcipif_dbus_wdata;
output bmu_tcipif_dbus_write;
output bmu_tcipif_ibus_acc_deny;
output [31:0] bmu_tcipif_ibus_addr;
output bmu_tcipif_ibus_req;
output bmu_tcipif_ibus_req_dp;
output [1 :0] bmu_tcipif_ibus_size;
output bmu_tcipif_ibus_supv_mode;
output [31:0] bmu_tcipif_ibus_wdata;
output bmu_tcipif_ibus_write;
// &Regs; @24
// &Wires; @25
wire bmu_clk;
wire bmu_clk_en;
wire bmu_dahbl_dbus_acc_deny;
wire [31:0] bmu_dahbl_dbus_addr;
wire [2 :0] bmu_dahbl_dbus_burst;
wire bmu_dahbl_dbus_lock;
wire bmu_dahbl_dbus_lrsc;
wire [3 :0] bmu_dahbl_dbus_prot;
wire bmu_dahbl_dbus_req;
wire bmu_dahbl_dbus_req_dp;
wire bmu_dahbl_dbus_seq;
wire [1 :0] bmu_dahbl_dbus_size;
wire [31:0] bmu_dahbl_dbus_wdata;
wire bmu_dahbl_dbus_write;
wire bmu_dahbl_ibus_acc_deny;
wire [31:0] bmu_dahbl_ibus_addr;
wire [2 :0] bmu_dahbl_ibus_burst;
wire [3 :0] bmu_dahbl_ibus_prot;
wire bmu_dahbl_ibus_req;
wire bmu_dahbl_ibus_req_dp;
wire bmu_dahbl_ibus_seq;
wire [1 :0] bmu_dahbl_ibus_size;
wire [31:0] bmu_dahbl_ibus_wdata;
wire bmu_dahbl_ibus_write;
wire [3 :0] bmu_dtu_debug_info;
wire bmu_iahbl_dbus_acc_deny;
wire [31:0] bmu_iahbl_dbus_addr;
wire [2 :0] bmu_iahbl_dbus_burst;
wire bmu_iahbl_dbus_lock;
wire bmu_iahbl_dbus_lrsc;
wire [3 :0] bmu_iahbl_dbus_prot;
wire bmu_iahbl_dbus_req;
wire bmu_iahbl_dbus_req_dp;
wire bmu_iahbl_dbus_seq;
wire [1 :0] bmu_iahbl_dbus_size;
wire [31:0] bmu_iahbl_dbus_wdata;
wire bmu_iahbl_dbus_write;
wire bmu_iahbl_ibus_acc_deny;
wire [31:0] bmu_iahbl_ibus_addr;
wire [2 :0] bmu_iahbl_ibus_burst;
wire [3 :0] bmu_iahbl_ibus_prot;
wire bmu_iahbl_ibus_req;
wire bmu_iahbl_ibus_req_dp;
wire bmu_iahbl_ibus_seq;
wire [1 :0] bmu_iahbl_ibus_size;
wire [31:0] bmu_iahbl_ibus_wdata;
wire bmu_iahbl_ibus_write;
wire bmu_ifu_acc_err;
wire bmu_ifu_clk_en;
wire bmu_ifu_grant;
wire [31:0] bmu_ifu_rdata;
wire bmu_ifu_trans_cmplt;
wire bmu_lsu_acc_err;
wire bmu_lsu_clk_en;
wire bmu_lsu_grant;
wire [31:0] bmu_lsu_rdata;
wire bmu_lsu_trans_cmplt;
wire bmu_sahbl_dbus_acc_deny;
wire [31:0] bmu_sahbl_dbus_addr;
wire [2 :0] bmu_sahbl_dbus_burst;
wire bmu_sahbl_dbus_lock;
wire bmu_sahbl_dbus_lrsc;
wire [3 :0] bmu_sahbl_dbus_prot;
wire bmu_sahbl_dbus_req;
wire bmu_sahbl_dbus_req_dp;
wire bmu_sahbl_dbus_seq;
wire [1 :0] bmu_sahbl_dbus_size;
wire [31:0] bmu_sahbl_dbus_wdata;
wire bmu_sahbl_dbus_write;
wire bmu_sahbl_ibus_acc_deny;
wire [31:0] bmu_sahbl_ibus_addr;
wire [2 :0] bmu_sahbl_ibus_burst;
wire [3 :0] bmu_sahbl_ibus_prot;
wire bmu_sahbl_ibus_req;
wire bmu_sahbl_ibus_req_dp;
wire bmu_sahbl_ibus_seq;
wire [1 :0] bmu_sahbl_ibus_size;
wire [31:0] bmu_sahbl_ibus_wdata;
wire bmu_sahbl_ibus_write;
wire bmu_tcipif_dbus_acc_deny;
wire [31:0] bmu_tcipif_dbus_addr;
wire bmu_tcipif_dbus_req;
wire bmu_tcipif_dbus_req_dp;
wire [1 :0] bmu_tcipif_dbus_size;
wire bmu_tcipif_dbus_supv_mode;
wire [31:0] bmu_tcipif_dbus_wdata;
wire bmu_tcipif_dbus_write;
wire bmu_tcipif_ibus_acc_deny;
wire [31:0] bmu_tcipif_ibus_addr;
wire bmu_tcipif_ibus_req;
wire bmu_tcipif_ibus_req_dp;
wire [1 :0] bmu_tcipif_ibus_size;
wire bmu_tcipif_ibus_supv_mode;
wire [31:0] bmu_tcipif_ibus_wdata;
wire bmu_tcipif_ibus_write;
wire cp0_biu_icg_en;
wire cpurst_b;
wire dahbl_bmu_dbus_acc_err;
wire [31:0] dahbl_bmu_dbus_data;
wire dahbl_bmu_dbus_grnt;
wire dahbl_bmu_dbus_trans_cmplt;
wire dahbl_bmu_ibus_acc_err;
wire [31:0] dahbl_bmu_ibus_data;
wire dahbl_bmu_ibus_grnt;
wire dahbl_bmu_ibus_trans_cmplt;
wire [1 :0] dbus_dbginfo;
wire forever_cpuclk;
wire iahbl_bmu_dbus_acc_err;
wire [31:0] iahbl_bmu_dbus_data;
wire iahbl_bmu_dbus_grnt;
wire iahbl_bmu_dbus_trans_cmplt;
wire iahbl_bmu_ibus_acc_err;
wire [31:0] iahbl_bmu_ibus_data;
wire iahbl_bmu_ibus_grnt;
wire iahbl_bmu_ibus_trans_cmplt;
wire [1 :0] ibus_dbginfo;
wire ifu_bmu_acc_deny;
wire [31:0] ifu_bmu_addr;
wire [2 :0] ifu_bmu_burst;
wire ifu_bmu_data_req;
wire [3 :0] ifu_bmu_prot;
wire ifu_bmu_req;
wire ifu_bmu_seq;
wire [1 :0] ifu_bmu_size;
wire [31:0] ifu_bmu_wdata;
wire ifu_bmu_write;
wire lsu_bmu_acc_deny;
wire [31:0] lsu_bmu_addr;
wire [2 :0] lsu_bmu_burst;
wire lsu_bmu_lock;
wire lsu_bmu_lrsc;
wire [3 :0] lsu_bmu_prot;
wire lsu_bmu_req;
wire lsu_bmu_req_dp;
wire lsu_bmu_seq;
wire [1 :0] lsu_bmu_size;
wire [31:0] lsu_bmu_wdata;
wire lsu_bmu_write;
wire [11:0] pad_bmu_dahbl_base;
wire [11:0] pad_bmu_dahbl_mask;
wire [11:0] pad_bmu_iahbl_base;
wire [11:0] pad_bmu_iahbl_mask;
wire [31:0] pad_cpu_tcip_base;
wire pad_yy_icg_scan_en;
wire rtu_yy_xx_async_flush;
wire sahbl_bmu_dbus_acc_err;
wire [31:0] sahbl_bmu_dbus_data;
wire sahbl_bmu_dbus_grnt;
wire sahbl_bmu_dbus_trans_cmplt;
wire sahbl_bmu_ibus_acc_err;
wire [31:0] sahbl_bmu_ibus_data;
wire sahbl_bmu_ibus_grnt;
wire sahbl_bmu_ibus_trans_cmplt;
wire tcipif_bmu_dbus_acc_err;
wire [31:0] tcipif_bmu_dbus_data;
wire tcipif_bmu_dbus_grnt;
wire tcipif_bmu_dbus_trans_cmplt;
wire tcipif_bmu_ibus_acc_err;
wire [31:0] tcipif_bmu_ibus_data;
wire tcipif_bmu_ibus_grnt;
wire tcipif_bmu_ibus_trans_cmplt;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign ifu_bmu_write = 1'b0;
assign ifu_bmu_wdata[31:0] = 32'b0;
// &Force("nonport", "bmu_dahbl_ibus_write") @33
// &Force("nonport", "bmu_dahbl_ibus_wdata") @34
// &Force("nonport", "bmu_iahbl_ibus_write") @35
// &Force("nonport", "bmu_iahbl_ibus_wdata") @36
// &Force("nonport", "bmu_sahbl_ibus_write") @37
// &Force("nonport", "bmu_sahbl_ibus_wdata") @38
//assign bmu_clk_en = bmu_lsu_clk_en | bmu_had_clk_en | bmu_ifu_clk_en;
assign bmu_clk_en = bmu_lsu_clk_en | bmu_ifu_clk_en;
// &Instance("gated_clk_cell", "x_pa_lsu_bmu_gated_clk"); @43
gated_clk_cell x_pa_lsu_bmu_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (bmu_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (bmu_clk_en ),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @44
// .external_en (1'b0), @45
// .global_en (1'b1), @46
// .module_en (cp0_biu_icg_en), @47
// .local_en (bmu_clk_en), @48
// .clk_out (bmu_clk)); @49
// &ConnRule(s/xx/ibus/); @51
// &ConnRule(s/tt/ifu/); @52
// &Instance("pa_bmu_bus_if","x_pa_bmu_ibus_if"); @53
pa_bmu_bus_if x_pa_bmu_ibus_if (
.bmu_clk (bmu_clk ),
.bmu_dahbl_xx_acc_deny (bmu_dahbl_ibus_acc_deny ),
.bmu_dahbl_xx_addr (bmu_dahbl_ibus_addr ),
.bmu_dahbl_xx_burst (bmu_dahbl_ibus_burst ),
.bmu_dahbl_xx_prot (bmu_dahbl_ibus_prot ),
.bmu_dahbl_xx_req (bmu_dahbl_ibus_req ),
.bmu_dahbl_xx_req_dp (bmu_dahbl_ibus_req_dp ),
.bmu_dahbl_xx_seq (bmu_dahbl_ibus_seq ),
.bmu_dahbl_xx_size (bmu_dahbl_ibus_size ),
.bmu_dahbl_xx_wdata (bmu_dahbl_ibus_wdata ),
.bmu_dahbl_xx_write (bmu_dahbl_ibus_write ),
.bmu_iahbl_xx_acc_deny (bmu_iahbl_ibus_acc_deny ),
.bmu_iahbl_xx_addr (bmu_iahbl_ibus_addr ),
.bmu_iahbl_xx_burst (bmu_iahbl_ibus_burst ),
.bmu_iahbl_xx_prot (bmu_iahbl_ibus_prot ),
.bmu_iahbl_xx_req (bmu_iahbl_ibus_req ),
.bmu_iahbl_xx_req_dp (bmu_iahbl_ibus_req_dp ),
.bmu_iahbl_xx_seq (bmu_iahbl_ibus_seq ),
.bmu_iahbl_xx_size (bmu_iahbl_ibus_size ),
.bmu_iahbl_xx_wdata (bmu_iahbl_ibus_wdata ),
.bmu_iahbl_xx_write (bmu_iahbl_ibus_write ),
.bmu_sahbl_xx_acc_deny (bmu_sahbl_ibus_acc_deny ),
.bmu_sahbl_xx_addr (bmu_sahbl_ibus_addr ),
.bmu_sahbl_xx_burst (bmu_sahbl_ibus_burst ),
.bmu_sahbl_xx_prot (bmu_sahbl_ibus_prot ),
.bmu_sahbl_xx_req (bmu_sahbl_ibus_req ),
.bmu_sahbl_xx_req_dp (bmu_sahbl_ibus_req_dp ),
.bmu_sahbl_xx_seq (bmu_sahbl_ibus_seq ),
.bmu_sahbl_xx_size (bmu_sahbl_ibus_size ),
.bmu_sahbl_xx_wdata (bmu_sahbl_ibus_wdata ),
.bmu_sahbl_xx_write (bmu_sahbl_ibus_write ),
.bmu_tcipif_xx_acc_deny (bmu_tcipif_ibus_acc_deny ),
.bmu_tcipif_xx_addr (bmu_tcipif_ibus_addr ),
.bmu_tcipif_xx_req (bmu_tcipif_ibus_req ),
.bmu_tcipif_xx_req_dp (bmu_tcipif_ibus_req_dp ),
.bmu_tcipif_xx_size (bmu_tcipif_ibus_size ),
.bmu_tcipif_xx_supv_mode (bmu_tcipif_ibus_supv_mode ),
.bmu_tcipif_xx_wdata (bmu_tcipif_ibus_wdata ),
.bmu_tcipif_xx_write (bmu_tcipif_ibus_write ),
.bmu_tt_acc_err (bmu_ifu_acc_err ),
.bmu_tt_clk_en (bmu_ifu_clk_en ),
.bmu_tt_grant (bmu_ifu_grant ),
.bmu_tt_rdata (bmu_ifu_rdata ),
.bmu_tt_trans_cmplt (bmu_ifu_trans_cmplt ),
.cpurst_b (cpurst_b ),
.dahbl_bmu_xx_acc_err (dahbl_bmu_ibus_acc_err ),
.dahbl_bmu_xx_data (dahbl_bmu_ibus_data ),
.dahbl_bmu_xx_grnt (dahbl_bmu_ibus_grnt ),
.dahbl_bmu_xx_trans_cmplt (dahbl_bmu_ibus_trans_cmplt ),
.iahbl_bmu_xx_acc_err (iahbl_bmu_ibus_acc_err ),
.iahbl_bmu_xx_data (iahbl_bmu_ibus_data ),
.iahbl_bmu_xx_grnt (iahbl_bmu_ibus_grnt ),
.iahbl_bmu_xx_trans_cmplt (iahbl_bmu_ibus_trans_cmplt ),
.pad_bmu_dahbl_base (pad_bmu_dahbl_base ),
.pad_bmu_dahbl_mask (pad_bmu_dahbl_mask ),
.pad_bmu_iahbl_base (pad_bmu_iahbl_base ),
.pad_bmu_iahbl_mask (pad_bmu_iahbl_mask ),
.pad_cpu_tcip_base (pad_cpu_tcip_base ),
.sahbl_bmu_xx_acc_err (sahbl_bmu_ibus_acc_err ),
.sahbl_bmu_xx_data (sahbl_bmu_ibus_data ),
.sahbl_bmu_xx_grnt (sahbl_bmu_ibus_grnt ),
.sahbl_bmu_xx_trans_cmplt (sahbl_bmu_ibus_trans_cmplt ),
.tcipif_bmu_xx_acc_err (tcipif_bmu_ibus_acc_err ),
.tcipif_bmu_xx_data (tcipif_bmu_ibus_data ),
.tcipif_bmu_xx_grnt (tcipif_bmu_ibus_grnt ),
.tcipif_bmu_xx_trans_cmplt (tcipif_bmu_ibus_trans_cmplt),
.tt_bmu_acc_deny (ifu_bmu_acc_deny ),
.tt_bmu_addr (ifu_bmu_addr ),
.tt_bmu_burst (ifu_bmu_burst ),
.tt_bmu_data_req (ifu_bmu_data_req ),
.tt_bmu_prot (ifu_bmu_prot ),
.tt_bmu_req (ifu_bmu_req ),
.tt_bmu_seq (ifu_bmu_seq ),
.tt_bmu_size (ifu_bmu_size ),
.tt_bmu_wdata (ifu_bmu_wdata ),
.tt_bmu_write (ifu_bmu_write ),
.xx_dbginfo (ibus_dbginfo )
);
// &Instance("pa_bmu_dbus_if","x_pa_bmu_dbus_if"); @55
pa_bmu_dbus_if x_pa_bmu_dbus_if (
.bmu_clk (bmu_clk ),
.bmu_dahbl_dbus_acc_deny (bmu_dahbl_dbus_acc_deny ),
.bmu_dahbl_dbus_addr (bmu_dahbl_dbus_addr ),
.bmu_dahbl_dbus_burst (bmu_dahbl_dbus_burst ),
.bmu_dahbl_dbus_lock (bmu_dahbl_dbus_lock ),
.bmu_dahbl_dbus_lrsc (bmu_dahbl_dbus_lrsc ),
.bmu_dahbl_dbus_prot (bmu_dahbl_dbus_prot ),
.bmu_dahbl_dbus_req (bmu_dahbl_dbus_req ),
.bmu_dahbl_dbus_req_dp (bmu_dahbl_dbus_req_dp ),
.bmu_dahbl_dbus_seq (bmu_dahbl_dbus_seq ),
.bmu_dahbl_dbus_size (bmu_dahbl_dbus_size ),
.bmu_dahbl_dbus_wdata (bmu_dahbl_dbus_wdata ),
.bmu_dahbl_dbus_write (bmu_dahbl_dbus_write ),
.bmu_iahbl_dbus_acc_deny (bmu_iahbl_dbus_acc_deny ),
.bmu_iahbl_dbus_addr (bmu_iahbl_dbus_addr ),
.bmu_iahbl_dbus_burst (bmu_iahbl_dbus_burst ),
.bmu_iahbl_dbus_lock (bmu_iahbl_dbus_lock ),
.bmu_iahbl_dbus_lrsc (bmu_iahbl_dbus_lrsc ),
.bmu_iahbl_dbus_prot (bmu_iahbl_dbus_prot ),
.bmu_iahbl_dbus_req (bmu_iahbl_dbus_req ),
.bmu_iahbl_dbus_req_dp (bmu_iahbl_dbus_req_dp ),
.bmu_iahbl_dbus_seq (bmu_iahbl_dbus_seq ),
.bmu_iahbl_dbus_size (bmu_iahbl_dbus_size ),
.bmu_iahbl_dbus_wdata (bmu_iahbl_dbus_wdata ),
.bmu_iahbl_dbus_write (bmu_iahbl_dbus_write ),
.bmu_lsu_acc_err (bmu_lsu_acc_err ),
.bmu_lsu_clk_en (bmu_lsu_clk_en ),
.bmu_lsu_grant (bmu_lsu_grant ),
.bmu_lsu_rdata (bmu_lsu_rdata ),
.bmu_lsu_trans_cmplt (bmu_lsu_trans_cmplt ),
.bmu_sahbl_dbus_acc_deny (bmu_sahbl_dbus_acc_deny ),
.bmu_sahbl_dbus_addr (bmu_sahbl_dbus_addr ),
.bmu_sahbl_dbus_burst (bmu_sahbl_dbus_burst ),
.bmu_sahbl_dbus_lock (bmu_sahbl_dbus_lock ),
.bmu_sahbl_dbus_lrsc (bmu_sahbl_dbus_lrsc ),
.bmu_sahbl_dbus_prot (bmu_sahbl_dbus_prot ),
.bmu_sahbl_dbus_req (bmu_sahbl_dbus_req ),
.bmu_sahbl_dbus_req_dp (bmu_sahbl_dbus_req_dp ),
.bmu_sahbl_dbus_seq (bmu_sahbl_dbus_seq ),
.bmu_sahbl_dbus_size (bmu_sahbl_dbus_size ),
.bmu_sahbl_dbus_wdata (bmu_sahbl_dbus_wdata ),
.bmu_sahbl_dbus_write (bmu_sahbl_dbus_write ),
.bmu_tcipif_dbus_acc_deny (bmu_tcipif_dbus_acc_deny ),
.bmu_tcipif_dbus_addr (bmu_tcipif_dbus_addr ),
.bmu_tcipif_dbus_req (bmu_tcipif_dbus_req ),
.bmu_tcipif_dbus_req_dp (bmu_tcipif_dbus_req_dp ),
.bmu_tcipif_dbus_size (bmu_tcipif_dbus_size ),
.bmu_tcipif_dbus_supv_mode (bmu_tcipif_dbus_supv_mode ),
.bmu_tcipif_dbus_wdata (bmu_tcipif_dbus_wdata ),
.bmu_tcipif_dbus_write (bmu_tcipif_dbus_write ),
.cpurst_b (cpurst_b ),
.dahbl_bmu_dbus_acc_err (dahbl_bmu_dbus_acc_err ),
.dahbl_bmu_dbus_data (dahbl_bmu_dbus_data ),
.dahbl_bmu_dbus_grnt (dahbl_bmu_dbus_grnt ),
.dahbl_bmu_dbus_trans_cmplt (dahbl_bmu_dbus_trans_cmplt ),
.dbus_dbginfo (dbus_dbginfo ),
.iahbl_bmu_dbus_acc_err (iahbl_bmu_dbus_acc_err ),
.iahbl_bmu_dbus_data (iahbl_bmu_dbus_data ),
.iahbl_bmu_dbus_grnt (iahbl_bmu_dbus_grnt ),
.iahbl_bmu_dbus_trans_cmplt (iahbl_bmu_dbus_trans_cmplt ),
.lsu_bmu_acc_deny (lsu_bmu_acc_deny ),
.lsu_bmu_addr (lsu_bmu_addr ),
.lsu_bmu_burst (lsu_bmu_burst ),
.lsu_bmu_lock (lsu_bmu_lock ),
.lsu_bmu_lrsc (lsu_bmu_lrsc ),
.lsu_bmu_prot (lsu_bmu_prot ),
.lsu_bmu_req (lsu_bmu_req ),
.lsu_bmu_req_dp (lsu_bmu_req_dp ),
.lsu_bmu_seq (lsu_bmu_seq ),
.lsu_bmu_size (lsu_bmu_size ),
.lsu_bmu_wdata (lsu_bmu_wdata ),
.lsu_bmu_write (lsu_bmu_write ),
.pad_bmu_dahbl_base (pad_bmu_dahbl_base ),
.pad_bmu_dahbl_mask (pad_bmu_dahbl_mask ),
.pad_bmu_iahbl_base (pad_bmu_iahbl_base ),
.pad_bmu_iahbl_mask (pad_bmu_iahbl_mask ),
.pad_cpu_tcip_base (pad_cpu_tcip_base ),
.rtu_yy_xx_async_flush (rtu_yy_xx_async_flush ),
.sahbl_bmu_dbus_acc_err (sahbl_bmu_dbus_acc_err ),
.sahbl_bmu_dbus_data (sahbl_bmu_dbus_data ),
.sahbl_bmu_dbus_grnt (sahbl_bmu_dbus_grnt ),
.sahbl_bmu_dbus_trans_cmplt (sahbl_bmu_dbus_trans_cmplt ),
.tcipif_bmu_dbus_acc_err (tcipif_bmu_dbus_acc_err ),
.tcipif_bmu_dbus_data (tcipif_bmu_dbus_data ),
.tcipif_bmu_dbus_grnt (tcipif_bmu_dbus_grnt ),
.tcipif_bmu_dbus_trans_cmplt (tcipif_bmu_dbus_trans_cmplt)
);
// //&ConnRule(s/xx/had/); @57
// //&ConnRule(s/tt/had/); @58
//&Instance("pa_bmu_bus_if","x_pa_bmu_had_if");
//assign had_bmu_acc_deny = 1'b0;
//assign had_bmu_data_req = had_bmu_req;
assign bmu_dtu_debug_info[3:0] = {ibus_dbginfo[1:0],dbus_dbginfo[1:0]};
// &ModuleEnd; @64
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @28
module pa_clic_arb(
arb_ctrl_int_hv,
arb_ctrl_int_id,
arb_ctrl_int_il,
arb_ctrl_int_mode,
arb_ctrl_int_req_raw,
ctrl_xx_int_lv_or_mask,
kid_arb_int_all_vec,
kid_arb_int_hv,
kid_arb_int_req
);
// &Ports; @29
input [2 :0] ctrl_xx_int_lv_or_mask;
input [575:0] kid_arb_int_all_vec;
input [143:0] kid_arb_int_hv;
input [143:0] kid_arb_int_req;
output arb_ctrl_int_hv;
output [11 :0] arb_ctrl_int_id;
output [7 :0] arb_ctrl_int_il;
output arb_ctrl_int_mode;
output arb_ctrl_int_req_raw;
// &Regs; @30
// &Wires; @31
wire arb_ctrl_int_hv;
wire [11 :0] arb_ctrl_int_id;
wire [7 :0] arb_ctrl_int_il;
wire arb_ctrl_int_mode;
wire arb_ctrl_int_req_raw;
wire [3 :0] arb_final_int_all;
wire arb_final_int_hv;
wire [11 :0] arb_final_int_id;
wire [2 :0] arb_final_int_lv;
wire arb_final_int_mode;
wire arb_final_int_req;
wire [2 :0] ctrl_xx_int_lv_or_mask;
wire [143:0] kid_arb_int_req;
parameter CLICINTNUM = `CLIC_INTNUM;
parameter CLICINTCTLBITS = `CLIC_INTCTLBITS;
parameter ID_WIDTH = 12;
// &Force("input", "kid_arb_int_all_vec"); @37
// &Force("bus", "kid_arb_int_all_vec", (CLICINTCTLBITS+1)*(CLICINTNUM)-1, 0); @38
// &Force("input", "kid_arb_int_hv"); &Force("bus", "kid_arb_int_hv", CLICINTNUM-1, 0); @39
// &Force("input", "kid_arb_int_req"); &Force("bus", "kid_arb_int_req", CLICINTNUM-1, 0); @40
//==========================================================
// Arbiter
//==========================================================
//csky vperl_off
wire [ID_WIDTH*CLICINTNUM-1:0] id_vec;
genvar i;
generate
for (i = 0; i < CLICINTNUM; i = i+1)
begin: GEN_ID
assign id_vec[ID_WIDTH*i+:ID_WIDTH] = $unsigned(i) & {ID_WIDTH{1'b1}};
end
endgenerate
pa_clic_arb_kernel #(.PRIO_WIDTH(CLICINTCTLBITS+1), .INT_NUM(CLICINTNUM)) x_pa_clic_arb_kernel (
.id_in_vec (id_vec),
.hv_in_vec (kid_arb_int_hv),
.prio_in_vec (kid_arb_int_all_vec),
.req_in_vec (kid_arb_int_req),
.id_out (arb_final_int_id),
.hv_out (arb_final_int_hv),
.prio_out (arb_final_int_all),
.req_out (arb_final_int_req)
);
//csky vperl_on
// &Force("nonport", "arb_final_int_id"); @69
// &Force("nonport", "arb_final_int_hv"); @70
// &Force("nonport", "arb_final_int_all"); @71
// &Force("nonport", "arb_final_int_req"); @72
assign arb_final_int_mode = arb_final_int_all[CLICINTCTLBITS];
assign arb_final_int_lv[CLICINTCTLBITS-1:0] = arb_final_int_all[CLICINTCTLBITS-1:0]
| ctrl_xx_int_lv_or_mask[CLICINTCTLBITS-1:0]
& {CLICINTCTLBITS{arb_final_int_req}};
//==========================================================
// Output Signal
//==========================================================
assign arb_ctrl_int_hv = arb_final_int_hv;
assign arb_ctrl_int_id[ID_WIDTH-1:0] = arb_final_int_id[ID_WIDTH-1:0];
assign arb_ctrl_int_mode = arb_final_int_mode;
assign arb_ctrl_int_il[7:0] = {arb_final_int_lv[CLICINTCTLBITS-1:0],
{(8-CLICINTCTLBITS){arb_final_int_req}}};
//==========================================================
// Gate Clk Cell
//==========================================================
assign arb_ctrl_int_req_raw = |kid_arb_int_req[CLICINTNUM-1:0];
// &ModuleEnd; @94
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_clic_arb_32to1_kernel(
// input
prio_in_vec,
// output
prio_out_mid,
sel_out_onehot
);
parameter PRIO_WIDTH = 6;
parameter INT_NUM = 32;
localparam PRIO_EXP_NUM = 1 <<< PRIO_WIDTH;
input [PRIO_EXP_NUM*INT_NUM-1:0] prio_in_vec;
output [PRIO_EXP_NUM-1:0] prio_out_mid;
output [INT_NUM-1:0] sel_out_onehot;
wire [PRIO_EXP_NUM*INT_NUM-1:0] prio_in_vec;
wire [PRIO_EXP_NUM-1:0] prio_out_mid;
wire [INT_NUM-1:0] sel_out_onehot;
wire [PRIO_EXP_NUM-1:0] prio_in_2d[INT_NUM-1:0];
wire [INT_NUM-1:0] prio_in_2d_rev[PRIO_EXP_NUM-1:0];
genvar i;
genvar j;
genvar k;
//==========================================================
// Generate 2D prio
//==========================================================
generate
for (k = 0; k < INT_NUM; k = k+1)
begin: EXPEND_PRIO
assign prio_in_2d[k][PRIO_EXP_NUM-1:0] = prio_in_vec[PRIO_EXP_NUM*k+:PRIO_EXP_NUM];
end
endgenerate
//==========================================================
// Reverse 2D signal
//==========================================================
generate
for (i = 0; i < INT_NUM; i = i+1) begin: REVERSEI
for (j = 0; j < PRIO_EXP_NUM; j = j+1) begin: REVERSEJ
assign prio_in_2d_rev[j][i] = prio_in_2d[i][j];
end
end
endgenerate
wire [PRIO_EXP_NUM-1:0] high_prio_onehot;
wire [PRIO_EXP_NUM-1:0] prio_out;
//==========================================================
// Do or to sel
//==========================================================
generate
for (i = 0; i < PRIO_EXP_NUM; i = i+1) begin: OR_SEL
assign prio_out[i] = |prio_in_2d_rev[i][INT_NUM-1:0];
end
endgenerate
assign prio_out_mid[PRIO_EXP_NUM-1:0] = prio_out[PRIO_EXP_NUM-1:0];
pa_clic_ff1_onehot #(PRIO_EXP_NUM) x_pa_clic_high_prio(
.data_in (prio_out),
.ff1_out_onehot (high_prio_onehot)
);
wire [PRIO_EXP_NUM-1:0] prio_after_mask_2d[INT_NUM-1:0];
wire [INT_NUM-1:0] int_hit_prio;
generate
for (k = 0; k < INT_NUM; k = k+1)
begin: PRIO_MASK
assign prio_after_mask_2d[k][PRIO_EXP_NUM-1:0] = prio_in_2d[k][PRIO_EXP_NUM-1:0] & high_prio_onehot[PRIO_EXP_NUM-1:0];
assign int_hit_prio[k] = |prio_after_mask_2d[k][PRIO_EXP_NUM-1:0];
end
endgenerate
wire [INT_NUM-1:0] int_sel_onehot;
pa_clic_ff1_onehot #(INT_NUM) x_pa_clic_num(
.data_in (int_hit_prio),
.ff1_out_onehot (int_sel_onehot)
);
assign sel_out_onehot[INT_NUM-1:0] = int_sel_onehot[INT_NUM-1:0];
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_clic_arb_kernel(
// input
id_in_vec,
hv_in_vec,
prio_in_vec,
req_in_vec,
// output
id_out,
hv_out,
prio_out,
req_out
);
parameter PRIO_WIDTH = 6;
parameter INT_NUM = 64;
parameter NUM_PER_GROUP = 16;
parameter ID_WIDTH = 12;
parameter PRIO_EXP_NUM = 1 <<< PRIO_WIDTH;
parameter GROUP_NUM = (INT_NUM-1) / NUM_PER_GROUP + 1;
parameter ALL_ARB_WIDTH = PRIO_WIDTH*GROUP_NUM*NUM_PER_GROUP;
parameter ALL_EXP_WIDTH = PRIO_EXP_NUM*GROUP_NUM*NUM_PER_GROUP;
parameter ALL_ID_WIDTH = ID_WIDTH*GROUP_NUM*NUM_PER_GROUP;
parameter ALL_INT_WIDTH = GROUP_NUM*NUM_PER_GROUP;
input [ID_WIDTH*INT_NUM-1:0] id_in_vec;
input [INT_NUM-1:0] hv_in_vec;
input [PRIO_WIDTH*INT_NUM-1:0] prio_in_vec;
input [INT_NUM-1:0] req_in_vec;
output [ID_WIDTH-1:0] id_out;
output hv_out;
output [PRIO_WIDTH-1:0] prio_out;
output req_out;
wire [ID_WIDTH*INT_NUM-1:0] id_in_vec;
wire [INT_NUM-1:0] hv_in_vec;
wire [PRIO_WIDTH*INT_NUM-1:0] prio_in_vec;
wire [INT_NUM-1:0] req_in_vec;
wire [ID_WIDTH-1:0] id_out;
wire hv_out;
wire [PRIO_WIDTH-1:0] prio_out;
wire req_out;
//==========================================================
// Expand Priority
//==========================================================
wire [PRIO_EXP_NUM*INT_NUM-1:0] prio_expand_vec;
pa_clic_expand #(PRIO_WIDTH, INT_NUM) x_pa_clic_prio_expand(
.data_in_vec (prio_in_vec),
.expand_out_vec (prio_expand_vec)
);
//==========================================================
// Padding
//==========================================================
wire [ALL_EXP_WIDTH:0] prio_expand_vec_padding;
assign prio_expand_vec_padding[ALL_EXP_WIDTH:0] = {{(ALL_EXP_WIDTH-PRIO_EXP_NUM*INT_NUM+1){1'b0}},
prio_expand_vec[PRIO_EXP_NUM*INT_NUM-1:0]};
wire [ALL_ARB_WIDTH:0] prio_in_vec_padding;
assign prio_in_vec_padding[ALL_ARB_WIDTH:0] = {{(ALL_ARB_WIDTH-PRIO_WIDTH*INT_NUM+1){1'b0}},
prio_in_vec[PRIO_WIDTH*INT_NUM-1:0]};
wire [ALL_ID_WIDTH:0] id_vec_padding;
assign id_vec_padding[ALL_ID_WIDTH:0] = {{(ALL_ID_WIDTH-ID_WIDTH*INT_NUM+1){1'b0}},
id_in_vec[ID_WIDTH*INT_NUM-1:0]};
wire [ALL_INT_WIDTH:0] hv_vec_padding;
assign hv_vec_padding[ALL_INT_WIDTH:0] = {{(ALL_INT_WIDTH-INT_NUM+1){1'b0}}, hv_in_vec[INT_NUM-1:0]};
wire [ALL_INT_WIDTH:0] req_vec_padding;
assign req_vec_padding[ALL_INT_WIDTH:0] = {{(ALL_INT_WIDTH-INT_NUM+1){1'b0}}, req_in_vec[INT_NUM-1:0]};
//==========================================================
// 1st Stage Arbiter & Select
//==========================================================
wire [PRIO_EXP_NUM*GROUP_NUM-1:0] prio_out_mid_1st;
wire [NUM_PER_GROUP*GROUP_NUM-1:0] sel_out_onehot_1st;
wire [PRIO_WIDTH*GROUP_NUM-1:0] sel_out_prio_vec_1st;
wire [ID_WIDTH*GROUP_NUM-1:0] sel_out_id_vec_1st;
wire [GROUP_NUM-1:0] sel_out_hv_vec_1st;
wire [GROUP_NUM-1:0] sel_out_req_vec_1st;
genvar i;
generate
for (i = 0; i < GROUP_NUM; i = i+1)
begin: GROUP_X
//----------------------------------------------------------
// Arbiter
//----------------------------------------------------------
pa_clic_arb_32to1_kernel #(PRIO_WIDTH, NUM_PER_GROUP) x_pa_clic_arb_1st_round(
.prio_in_vec (prio_expand_vec_padding[(PRIO_EXP_NUM*NUM_PER_GROUP)*i+:(PRIO_EXP_NUM*NUM_PER_GROUP)]),
.prio_out_mid (prio_out_mid_1st[PRIO_EXP_NUM*i+:PRIO_EXP_NUM]),
.sel_out_onehot (sel_out_onehot_1st[NUM_PER_GROUP*i+:NUM_PER_GROUP])
);
//----------------------------------------------------------
// Select Priority
//----------------------------------------------------------
pa_clic_sel #(PRIO_WIDTH, NUM_PER_GROUP) x_pa_clic_lv_sel_1st_round(
.data_in (prio_in_vec_padding[(PRIO_WIDTH*NUM_PER_GROUP)*i+:(PRIO_WIDTH*NUM_PER_GROUP)]),
.sel_in_onehot (sel_out_onehot_1st[NUM_PER_GROUP*i+:NUM_PER_GROUP]),
.data_out (sel_out_prio_vec_1st[PRIO_WIDTH*i+:PRIO_WIDTH])
);
//----------------------------------------------------------
// Select ID
//----------------------------------------------------------
pa_clic_sel #(ID_WIDTH, NUM_PER_GROUP) x_pa_clic_id_sel_1st_round(
.data_in (id_vec_padding[(ID_WIDTH*NUM_PER_GROUP)*i+:(ID_WIDTH*NUM_PER_GROUP)]),
.sel_in_onehot (sel_out_onehot_1st[NUM_PER_GROUP*i+:NUM_PER_GROUP]),
.data_out (sel_out_id_vec_1st[ID_WIDTH*i+:ID_WIDTH])
);
//----------------------------------------------------------
// Select hv & req
//----------------------------------------------------------
assign sel_out_hv_vec_1st[i] = |(sel_out_onehot_1st[NUM_PER_GROUP*i+:NUM_PER_GROUP] & hv_vec_padding[NUM_PER_GROUP*i+:NUM_PER_GROUP]);
assign sel_out_req_vec_1st[i] = |(sel_out_onehot_1st[NUM_PER_GROUP*i+:NUM_PER_GROUP] & req_vec_padding[NUM_PER_GROUP*i+:NUM_PER_GROUP]);
end
endgenerate
//==========================================================
// 2nd Stage Arbiter & Select
//==========================================================
//----------------------------------------------------------
// Arbiter
//----------------------------------------------------------
wire [PRIO_EXP_NUM-1:0] prio_out_mid_2nd;
wire [GROUP_NUM-1:0] sel_out_2nd_round;
pa_clic_arb_32to1_kernel #(PRIO_WIDTH, GROUP_NUM) x_pa_clic_arb_2nd_round(
.prio_in_vec (prio_out_mid_1st),
.prio_out_mid (prio_out_mid_2nd), // Not Use.
.sel_out_onehot (sel_out_2nd_round)
);
//----------------------------------------------------------
// Select Priority
//----------------------------------------------------------
pa_clic_sel #(PRIO_WIDTH, GROUP_NUM) x_pa_clic_lv_sel_2nd_round(
.data_in (sel_out_prio_vec_1st),
.sel_in_onehot (sel_out_2nd_round),
.data_out (prio_out)
);
//----------------------------------------------------------
// Select ID
//----------------------------------------------------------
pa_clic_sel #(ID_WIDTH, GROUP_NUM) x_pa_clic_id_sel_2nd_round(
.data_in (sel_out_id_vec_1st),
.sel_in_onehot (sel_out_2nd_round),
.data_out (id_out)
);
//----------------------------------------------------------
// Select hv & req
//----------------------------------------------------------
assign hv_out = |(sel_out_hv_vec_1st[GROUP_NUM-1:0] & sel_out_2nd_round[GROUP_NUM-1:0]);
assign req_out = |(sel_out_req_vec_1st[GROUP_NUM-1:0] & sel_out_2nd_round[GROUP_NUM-1:0]);
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_clic_busif(
busif_ctrl_cliccfg_sel,
busif_ctrl_clicinfo_sel,
busif_ctrl_mintthresh_sel,
busif_kid_clicintattr_sel,
busif_kid_clicintctl_sel,
busif_kid_clicintie_sel,
busif_kid_clicintip_sel,
busif_kid_wdata,
busif_xx_write_vld,
clic_clk,
clic_clk_en,
clic_tcipif_cmplt,
clic_tcipif_rdata,
cpurst_b,
ctrl_busif_cliccfg_val,
ctrl_busif_clicinfo_val,
ctrl_busif_mintthresh_val,
ifu_clic_warm_up,
kid_busif_rdata_vec,
pad_yy_icg_scan_en,
pad_yy_scan_mode,
tcipif_clic_addr,
tcipif_clic_sel,
tcipif_clic_size,
tcipif_clic_wdata,
tcipif_clic_write
);
// &Ports; @24
input clic_clk;
input clic_clk_en;
input cpurst_b;
input [31 :0] ctrl_busif_cliccfg_val;
input [31 :0] ctrl_busif_clicinfo_val;
input [31 :0] ctrl_busif_mintthresh_val;
input ifu_clic_warm_up;
input [4607:0] kid_busif_rdata_vec;
input pad_yy_icg_scan_en;
input pad_yy_scan_mode;
input [15 :0] tcipif_clic_addr;
input tcipif_clic_sel;
input [1 :0] tcipif_clic_size;
input [31 :0] tcipif_clic_wdata;
input tcipif_clic_write;
output busif_ctrl_cliccfg_sel;
output busif_ctrl_clicinfo_sel;
output busif_ctrl_mintthresh_sel;
output [143 :0] busif_kid_clicintattr_sel;
output [143 :0] busif_kid_clicintctl_sel;
output [143 :0] busif_kid_clicintie_sel;
output [143 :0] busif_kid_clicintip_sel;
output [31 :0] busif_kid_wdata;
output busif_xx_write_vld;
output clic_tcipif_cmplt;
output [31 :0] clic_tcipif_rdata;
// &Regs; @25
reg [15 :0] busif_addr;
reg [3 :0] busif_kid_reg_sel;
reg busif_sel;
reg [1 :0] busif_size;
reg [31 :0] busif_wdata;
reg busif_write;
reg [31 :0] clic_tcipif_rdata_test_point;
// &Wires; @26
wire busif_cmplt;
wire busif_ctrl_cliccfg_sel;
wire busif_ctrl_clicinfo_sel;
wire busif_ctrl_mintthresh_sel;
wire [143 :0] busif_kid_sel;
wire [31 :0] busif_kid_wdata;
wire busif_read_vld;
wire busif_sel_updt;
wire busif_xx_write_vld;
wire clic_clk;
wire clic_clk_en;
wire [15 :0] clic_kid_base;
wire clic_tcipif_cmplt;
wire [31 :0] clic_tcipif_rdata;
wire [31 :0] clic_tcipif_rdata_pre;
wire cliccfg_sel;
wire clicinfo_sel;
wire cpurst_b;
wire [31 :0] ctrl_busif_cliccfg_val;
wire [31 :0] ctrl_busif_clicinfo_val;
wire [31 :0] ctrl_busif_mintthresh_val;
wire [31 :0] kid_busif_rdata;
wire mintthresh_sel;
wire pad_yy_icg_scan_en;
wire pad_yy_scan_mode;
wire tcip_clk;
wire tcip_clk_en;
wire [15 :0] tcipif_clic_addr;
wire tcipif_clic_sel;
wire [1 :0] tcipif_clic_size;
wire [31 :0] tcipif_clic_wdata;
wire tcipif_clic_write;
parameter CLICINTNUM = `CLIC_INTNUM;
parameter CLICCFG_BASE = 16'h0000;
parameter CLICINFO_BASE = 16'h0004;
parameter MINTTHRESH_BASE = 16'h0008;
parameter CLICKID_BASE = 16'h1000;
assign clic_kid_base[15:0] = CLICKID_BASE;
// &Force("nonport", "clic_kid_base"); @37
assign busif_sel_updt = busif_sel ^ tcipif_clic_sel;
always @ (posedge tcip_clk or negedge cpurst_b)
begin
if (!cpurst_b) begin
busif_sel <= 1'b0;
end
else if (busif_sel) begin
busif_sel <= 1'b0;
end
else if (busif_sel_updt) begin
busif_sel <= tcipif_clic_sel;
end
end
always @ (posedge tcip_clk or negedge cpurst_b)
begin
if (!cpurst_b) begin
busif_addr[15:0] <= 16'b0;
busif_write <= 1'b0;
busif_size[1:0] <= 2'b0;
busif_wdata[31:0] <= 32'b0;
end
else if (tcipif_clic_sel) begin
busif_addr[15:0] <= tcipif_clic_addr[15:0];
busif_write <= tcipif_clic_write;
busif_size[1:0] <= tcipif_clic_size[1:0];
busif_wdata[31:0] <= tcipif_clic_wdata[31:0];
end
end
assign tcip_clk_en = tcipif_clic_sel
|| busif_sel_updt;
// &Instance("gated_clk_cell", "x_tcip_clk"); @72
gated_clk_cell x_tcip_clk (
.clk_in (clic_clk ),
.clk_out (tcip_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (tcip_clk_en ),
.module_en (1'b0 ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (clic_clk), @73
// .external_en (1'b0), @74
// .global_en (1'b1), @75
// .module_en (1'b0), @76
// .local_en (tcip_clk_en), @77
// .clk_out (tcip_clk)); @78
// &Force("input", "ifu_clic_warm_up"); @87
assign cliccfg_sel = busif_addr[15:0] == CLICCFG_BASE;
assign clicinfo_sel = busif_addr[15:0] == CLICINFO_BASE;
assign mintthresh_sel = busif_addr[15:0] == MINTTHRESH_BASE;
assign busif_ctrl_cliccfg_sel = cliccfg_sel;
assign busif_ctrl_clicinfo_sel = clicinfo_sel;
assign busif_ctrl_mintthresh_sel = mintthresh_sel;
assign busif_cmplt = busif_sel;
assign clic_tcipif_cmplt = busif_cmplt && clic_clk_en;
assign busif_kid_wdata[31:0] = busif_wdata[31:0];
// &CombBeg; @100
always @( busif_addr[1:0]
or busif_size[1:0])
begin
case({busif_addr[1:0], busif_size[1:0]})
4'b00_00: busif_kid_reg_sel[3:0] = 4'b0001; // Byte
4'b01_00: busif_kid_reg_sel[3:0] = 4'b0010;
4'b10_00: busif_kid_reg_sel[3:0] = 4'b0100;
4'b11_00: busif_kid_reg_sel[3:0] = 4'b1000; // Half word
4'b00_01: busif_kid_reg_sel[3:0] = 4'b0011;
4'b10_01: busif_kid_reg_sel[3:0] = 4'b1100;
4'b00_10: busif_kid_reg_sel[3:0] = 4'b1111;
default: busif_kid_reg_sel[3:0] = 4'b0000;
endcase
// &CombEnd; @111
end
// &Force("nonport", "busif_kid_reg_sel"); @112
// &Force("nonport", "busif_kid_sel"); @113
// &Force("output", "busif_kid_clicintip_sel"); @115
// &Force("output", "busif_kid_clicintie_sel"); @116
// &Force("output", "busif_kid_clicintattr_sel"); @117
// &Force("output", "busif_kid_clicintctl_sel"); @118
// &Force("bus", "busif_kid_clicintip_sel", CLICINTNUM-1, 0); @119
// &Force("bus", "busif_kid_clicintie_sel", CLICINTNUM-1, 0); @120
// &Force("bus", "busif_kid_clicintattr_sel", CLICINTNUM-1, 0); @121
// &Force("bus", "busif_kid_clicintctl_sel", CLICINTNUM-1, 0); @122
//csky vperl_off
wire [CLICINTNUM-1:0] busif_kid_clicintip_sel;
wire [CLICINTNUM-1:0] busif_kid_clicintie_sel;
wire [CLICINTNUM-1:0] busif_kid_clicintattr_sel;
wire [CLICINTNUM-1:0] busif_kid_clicintctl_sel;
genvar i;
generate
for (i = 0; i < CLICINTNUM; i = i+1)
begin: BUSIF_KID
assign busif_kid_sel[i] = (busif_addr[15:2] - clic_kid_base[15:2]) == $unsigned(i);
assign busif_kid_clicintip_sel[i] = busif_kid_sel[i] && busif_kid_reg_sel[0];
assign busif_kid_clicintie_sel[i] = busif_kid_sel[i] && busif_kid_reg_sel[1];
assign busif_kid_clicintattr_sel[i] = busif_kid_sel[i] && busif_kid_reg_sel[2];
assign busif_kid_clicintctl_sel[i] = busif_kid_sel[i] && busif_kid_reg_sel[3];
end
endgenerate
//csky vperl_on
assign busif_xx_write_vld = busif_sel && busif_write;
assign busif_read_vld = busif_sel && !busif_write;
//==========================================================
// Read Sel
//==========================================================
// &Force("input", "kid_busif_rdata_vec"); @148
// &Force("bus", "kid_busif_rdata_vec", (CLICINTNUM)*32-1, 0); @149
// &Force("nonport", "kid_busif_rdata"); @150
//csky vperl_off
pa_clic_sel #(32, CLICINTNUM) x_pa_clic_kid_rdata_sel(
.data_in (kid_busif_rdata_vec),
.sel_in_onehot (busif_kid_sel),
.data_out (kid_busif_rdata)
);
//csky vperl_on
assign clic_tcipif_rdata_pre[31:0] = {{32{cliccfg_sel}} & ctrl_busif_cliccfg_val[31:0]
| {32{clicinfo_sel}} & ctrl_busif_clicinfo_val[31:0]
| {32{mintthresh_sel}} & ctrl_busif_mintthresh_val[31:0]
| {32{|busif_kid_sel[CLICINTNUM-1:0]}} & kid_busif_rdata[31:0]}
& {32{busif_read_vld}};
assign clic_tcipif_rdata[31:0] = pad_yy_scan_mode ? clic_tcipif_rdata_test_point[31:0] : clic_tcipif_rdata_pre[31:0];
always @(posedge clic_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
clic_tcipif_rdata_test_point[31:0] <= 32'b0;
end
else begin
clic_tcipif_rdata_test_point[31:0] <= clic_tcipif_rdata_pre[31:0];
end
end
// &ModuleEnd; @175
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_clic_cpuif_2cycle(
clic_clk_en,
clic_cpu_int_hv,
clic_cpu_int_id,
clic_cpu_int_il,
clic_cpu_int_priv,
clic_int_hv,
clic_int_id,
clic_int_il_raw,
clic_int_priv,
cpu_clic_curid,
cpu_clic_int_exit,
cpu_int_exit,
cpurst_b,
ctrl_kid_ack_int,
forever_cpuclk,
pad_yy_icg_scan_en
);
// &Ports; @25
input clic_clk_en;
input clic_int_hv;
input [11 :0] clic_int_id;
input [7 :0] clic_int_il_raw;
input [1 :0] clic_int_priv;
input [11 :0] cpu_clic_curid;
input cpu_clic_int_exit;
input cpurst_b;
input forever_cpuclk;
input pad_yy_icg_scan_en;
output clic_cpu_int_hv;
output [11 :0] clic_cpu_int_id;
output [7 :0] clic_cpu_int_il;
output [1 :0] clic_cpu_int_priv;
output cpu_int_exit;
output [143:0] ctrl_kid_ack_int;
// &Regs; @26
reg clic_int_en;
reg [11 :0] cpuif_curid;
reg cpuif_exit;
// &Wires; @27
wire clic_clk_en;
wire clic_clk_en_f;
wire clic_cpu_int_hv;
wire [11 :0] clic_cpu_int_id;
wire [7 :0] clic_cpu_int_il;
wire [1 :0] clic_cpu_int_priv;
wire clic_int_hv;
wire [11 :0] clic_int_id;
wire [7 :0] clic_int_il;
wire [7 :0] clic_int_il_raw;
wire [1 :0] clic_int_priv;
wire [11 :0] cpu_clic_curid;
wire cpu_clic_int_exit;
wire [11 :0] cpu_curid;
wire cpu_int_exit;
wire cpuif_clk;
wire cpuif_clk_en;
wire cpurst_b;
wire forever_cpuclk;
wire if_clic_en;
wire pad_yy_icg_scan_en;
parameter CLICINTNUM = `CLIC_INTNUM;
parameter CLICINTCTLBITS = `CLIC_INTCTLBITS;
parameter ID_WIDTH = 12;
//==========================================================
// Int Exit
//==========================================================
assign cpu_int_exit = cpuif_exit || cpu_clic_int_exit;
// &Force("output", "cpu_int_exit"); @37
always @ (posedge cpuif_clk or negedge cpurst_b)
begin
if (!cpurst_b)
cpuif_exit <= 1'b0;
else
cpuif_exit <= cpu_clic_int_exit;
end
always @ (posedge cpuif_clk or negedge cpurst_b)
begin
if (!cpurst_b)
cpuif_curid[ID_WIDTH-1:0] <= {ID_WIDTH{1'b0}};
else if (cpu_clic_int_exit)
cpuif_curid[ID_WIDTH-1:0] <= cpu_clic_curid[ID_WIDTH-1:0];
end
assign cpu_curid[ID_WIDTH-1:0] = cpuif_exit ? cpuif_curid[ID_WIDTH-1:0]
: cpu_clic_curid[ID_WIDTH-1:0];
// &Force("output", "ctrl_kid_ack_int"); &Force("bus", "ctrl_kid_ack_int", CLICINTNUM-1, 0); @57
// &Force("nonport", "cpu_curid"); @58
//csky vperl_off
wire [CLICINTNUM-1:0] ctrl_kid_ack_sel;
wire [CLICINTNUM-1:0] ctrl_kid_ack_int;
genvar i;
generate
for (i = 0; i < CLICINTNUM; i = i+1)
begin: KID_ACK
assign ctrl_kid_ack_sel[i] = cpu_curid[ID_WIDTH-1:0] == ($unsigned(i) & {ID_WIDTH{1'b1}});
assign ctrl_kid_ack_int[i] = ctrl_kid_ack_sel[i] && cpu_int_exit;
end
endgenerate
//csky vperl_on
//==========================================================
// Output Interface
//==========================================================
assign clic_int_il[7:0] = {8{if_clic_en}} & clic_int_il_raw[7:0];
// ATTENTION: Only in 2 cycle, clic_clk_en_f = !clic_clk_en.
assign clic_clk_en_f = !clic_clk_en;
assign if_clic_en = clic_clk_en_f || clic_int_en;
always @ (posedge cpuif_clk or negedge cpurst_b)
begin
if (!cpurst_b)
clic_int_en <= 1'b0;
else if (cpu_clic_int_exit)
clic_int_en <= 1'b0;
else
clic_int_en <= |clic_int_il[7:0];
end
assign clic_cpu_int_hv = clic_int_hv;
assign clic_cpu_int_id[ID_WIDTH-1:0] = clic_int_id[ID_WIDTH-1:0];
assign clic_cpu_int_priv[1:0] = clic_int_priv[1:0];
assign clic_cpu_int_il[7:0] = clic_int_il[7:0];
//==========================================================
// ICG
//==========================================================
assign cpuif_clk_en = |clic_int_il_raw[7:0]
|| cpuif_exit
|| clic_int_en;
// &Instance("gated_clk_cell", "x_cpuif_clk"); @103
gated_clk_cell x_cpuif_clk (
.clk_in (forever_cpuclk ),
.clk_out (cpuif_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (cpuif_clk_en ),
.module_en (1'b0 ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @104
// .external_en (1'b0), @105
// .global_en (1'b1), @106
// .module_en (1'b0), @107
// .local_en (cpuif_clk_en), @108
// .clk_out (cpuif_clk)); @109
// &ModuleEnd; @111
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_clic_ctrl(
arb_ctrl_int_hv,
arb_ctrl_int_id,
arb_ctrl_int_il,
arb_ctrl_int_mode,
arb_ctrl_int_req_raw,
busif_ctrl_cliccfg_sel,
busif_ctrl_clicinfo_sel,
busif_ctrl_mintthresh_sel,
busif_kid_wdata,
busif_xx_write_vld,
clic_clk,
clic_clk_en,
clic_cpu_int_hv,
clic_cpu_int_id,
clic_cpu_int_il,
clic_cpu_int_priv,
clicreg_clk,
cpu_clic_curid,
cpu_clic_int_exit,
cpu_clic_mode,
cpurst_b,
ctrl_busif_cliccfg_val,
ctrl_busif_clicinfo_val,
ctrl_busif_mintthresh_val,
ctrl_clicreg_en,
ctrl_kid_ack_int,
ctrl_xx_int_lv_or_mask,
ctrl_xx_mode_or_mask,
forever_cpuclk,
pad_yy_icg_scan_en
);
// &Ports; @23
input arb_ctrl_int_hv;
input [11 :0] arb_ctrl_int_id;
input [7 :0] arb_ctrl_int_il;
input arb_ctrl_int_mode;
input arb_ctrl_int_req_raw;
input busif_ctrl_cliccfg_sel;
input busif_ctrl_clicinfo_sel;
input busif_ctrl_mintthresh_sel;
input [31 :0] busif_kid_wdata;
input busif_xx_write_vld;
input clic_clk;
input clic_clk_en;
input clicreg_clk;
input [11 :0] cpu_clic_curid;
input cpu_clic_int_exit;
input [1 :0] cpu_clic_mode;
input cpurst_b;
input forever_cpuclk;
input pad_yy_icg_scan_en;
output clic_cpu_int_hv;
output [11 :0] clic_cpu_int_id;
output [7 :0] clic_cpu_int_il;
output [1 :0] clic_cpu_int_priv;
output [31 :0] ctrl_busif_cliccfg_val;
output [31 :0] ctrl_busif_clicinfo_val;
output [31 :0] ctrl_busif_mintthresh_val;
output ctrl_clicreg_en;
output [143:0] ctrl_kid_ack_int;
output [2 :0] ctrl_xx_int_lv_or_mask;
output ctrl_xx_mode_or_mask;
// &Regs; @24
reg clic_int_hv;
reg [11 :0] clic_int_id;
reg [7 :0] clic_int_il_raw;
reg [1 :0] clic_int_priv;
reg [3 :0] cliccfg_nlbits;
reg [7 :0] mintthresh_mth;
// &Wires; @25
wire arb_ctrl_int_hv;
wire [11 :0] arb_ctrl_int_id;
wire [7 :0] arb_ctrl_int_il;
wire arb_ctrl_int_mode;
wire arb_ctrl_int_req_raw;
wire busif_ctrl_cliccfg_sel;
wire busif_ctrl_mintthresh_sel;
wire [31 :0] busif_kid_wdata;
wire busif_xx_write_vld;
wire clic_clk;
wire clic_clk_en;
wire clic_cpu_int_hv;
wire [11 :0] clic_cpu_int_id;
wire [7 :0] clic_cpu_int_il;
wire [1 :0] clic_cpu_int_priv;
wire [1 :0] cliccfg_nmbits;
wire cliccfg_nmbits_0;
wire cliccfg_nvbits;
wire [31 :0] cliccfg_reg;
wire [7 :0] cliccfg_updt_val;
wire [3 :0] clicinfo_arch_ver;
wire [3 :0] clicinfo_clicintctlbits;
wire [3 :0] clicinfo_impl_ver;
wire [12 :0] clicinfo_num_int;
wire [31 :0] clicinfo_reg;
wire clicreg_clk;
wire [11 :0] cpu_clic_curid;
wire cpu_clic_int_exit;
wire [1 :0] cpu_clic_mode;
wire cpu_int_exit;
wire cpurst_b;
wire [31 :0] ctrl_busif_cliccfg_val;
wire [31 :0] ctrl_busif_clicinfo_val;
wire [31 :0] ctrl_busif_mintthresh_val;
wire ctrl_cliccfg_updt_vld;
wire ctrl_clicreg_en;
wire ctrl_int_gt_thresh;
wire [143:0] ctrl_kid_ack_int;
wire ctrl_mintthresh_updt_vld;
wire ctrl_mode_vld;
wire [7 :0] ctrl_thresh;
wire ctrl_write_vld;
wire ctrl_xx_mode_or_mask;
wire forever_cpuclk;
wire [7 :0] mintthresh_hth;
wire [31 :0] mintthresh_reg;
wire [7 :0] mintthresh_sth;
wire [31 :0] mintthresh_updt_val;
wire [7 :0] mintthresh_uth;
wire out_clk;
wire out_clk_en;
wire pad_yy_icg_scan_en;
parameter CLICINTNUM = `CLIC_INTNUM;
parameter CLICINTCTLBITS = `CLIC_INTCTLBITS;
parameter ID_WIDTH = 12;
parameter INT_MODE_U = 1'b0;
parameter INT_MODE_M = 1'b1;
parameter CPU_MODE_U = 2'b00;
parameter CPU_MODE_M = 2'b11;
//==========================================================
// Rename Input
//==========================================================
assign cliccfg_updt_val[7:0] = busif_kid_wdata[7:0];
// assign clicinfo_updt_val[31:0] = busif_kid_wdata[31:0];
assign mintthresh_updt_val[31:0] = busif_kid_wdata[31:0];
//==========================================================
// Write Vld
//==========================================================
assign ctrl_mode_vld = cpu_clic_mode[1:0] == CPU_MODE_M;
assign ctrl_write_vld = busif_xx_write_vld && ctrl_mode_vld;
assign ctrl_cliccfg_updt_vld = ctrl_write_vld && busif_ctrl_cliccfg_sel;
// &Force("input", "busif_ctrl_clicinfo_sel"); @50
// assign ctrl_clicinfo_updt_vld = ctrl_write_vld && busif_ctrl_clicinfo_sel;
assign ctrl_mintthresh_updt_vld = ctrl_write_vld && busif_ctrl_mintthresh_sel;
//==========================================================
// CLICCFG
//==========================================================
always @ (posedge clicreg_clk or negedge cpurst_b)
begin
if (!cpurst_b)
cliccfg_nlbits[3:0] <= 4'b0;
else if (ctrl_cliccfg_updt_vld)
cliccfg_nlbits[3:0] <= cliccfg_updt_val[4] ? 4'd8 : cliccfg_updt_val[4:1]; // if nlbits > 8, it will be 8.
else
cliccfg_nlbits[3:0] <= cliccfg_nlbits[3:0];
end
assign cliccfg_nmbits_0 = 1'b0;
assign ctrl_xx_mode_or_mask = !cliccfg_nmbits_0;
// cliccfg_nmbits only can be 0/1 so [1] is not use.
assign cliccfg_nmbits[1:0] = {1'b0, cliccfg_nmbits_0};
assign cliccfg_nvbits = 1'b1;
assign cliccfg_reg[31:0] = {25'b0,
cliccfg_nmbits[1:0],
cliccfg_nlbits[3:0],
cliccfg_nvbits};
//==========================================================
// CLICINFO
//==========================================================
//csky vperl_off
assign clicinfo_clicintctlbits[3:0] = $unsigned(CLICINTCTLBITS) & 4'hf;
assign clicinfo_arch_ver[3:0] = 4'b0;
assign clicinfo_impl_ver[3:0] = 4'b0;
assign clicinfo_num_int[12:0] = $unsigned(CLICINTNUM) & 13'h1fff;
//csky vperl_on
// &Force("nonport", "clicinfo_clicintctlbits"); @101
// &Force("nonport", "clicinfo_arch_ver"); @102
// &Force("nonport", "clicinfo_impl_ver"); @103
// &Force("nonport", "clicinfo_num_int"); @104
assign clicinfo_reg[31:0] = {7'b0,
clicinfo_clicintctlbits[3:0],
clicinfo_arch_ver[3:0],
clicinfo_impl_ver[3:0],
clicinfo_num_int[12:0]};
//==========================================================
// MINTTHRESH
//==========================================================
always @ (posedge clicreg_clk or negedge cpurst_b)
begin
if (!cpurst_b) begin
mintthresh_mth[7:0] <= 8'b0;
// mintthresh_hth[7:0] <= 8'b0;
// mintthresh_sth[7:0] <= 8'b0;
end
else if (ctrl_mintthresh_updt_vld) begin
mintthresh_mth[7:0] <= mintthresh_updt_val[31:24];
// mintthresh_hth[7:0] <= mintthresh_updt_val[23:16];
// mintthresh_sth[7:0] <= mintthresh_updt_val[15:8];
end
else begin
mintthresh_mth[7:0] <= mintthresh_mth[7:0];
// mintthresh_hth[7:0] <= mintthresh_hth[7:0];
// mintthresh_sth[7:0] <= mintthresh_sth[7:0];
end
end
assign mintthresh_uth[7:0] = 8'b0;
assign mintthresh_hth[7:0] = 8'b0;
assign mintthresh_sth[7:0] = 8'b0;
assign mintthresh_reg[31:0] = {mintthresh_mth[7:0],
mintthresh_hth[7:0],
mintthresh_sth[7:0],
mintthresh_uth[7:0]};
//==========================================================
// For Gate Clk Cell
//==========================================================
assign ctrl_clicreg_en = ctrl_mintthresh_updt_vld || ctrl_cliccfg_updt_vld;
//==========================================================
// To busif
//==========================================================
// &Force("output", "ctrl_xx_int_lv_or_mask"); &Force("bus", "ctrl_xx_int_lv_or_mask", CLICINTCTLBITS-1, 0); @165
//csky vperl_off
wire [CLICINTCTLBITS-1:0] ctrl_xx_int_lv_or_mask;
genvar i;
generate
for (i = 0; i < CLICINTCTLBITS; i = i+1)
begin: LEVEL_MASK
assign ctrl_xx_int_lv_or_mask[CLICINTCTLBITS-1-i] = !(($unsigned(i) & {4'hf}) < cliccfg_nlbits[3:0]);
end
endgenerate
//csky vperl_on
//==========================================================
// To busif
//==========================================================
assign ctrl_busif_cliccfg_val[31:0] = cliccfg_reg[31:0] & {32{ctrl_mode_vld}};
assign ctrl_busif_clicinfo_val[31:0] = clicinfo_reg[31:0] & {32{ctrl_mode_vld}};
assign ctrl_busif_mintthresh_val[31:0] = mintthresh_reg[31:0] & {32{ctrl_mode_vld}};
//==========================================================
// Final judge mintthresh
//==========================================================
assign ctrl_thresh[7:0] = arb_ctrl_int_mode == INT_MODE_M ? mintthresh_mth[7:0]
: mintthresh_uth[7:0];
assign ctrl_int_gt_thresh = ctrl_thresh[7:0] < arb_ctrl_int_il[7:0];
always @ (posedge out_clk or negedge cpurst_b)
begin
if (!cpurst_b) begin
clic_int_hv <= 1'b0;
clic_int_id[ID_WIDTH-1:0] <= {ID_WIDTH{1'b0}};
clic_int_priv[1:0] <= 2'b0;
clic_int_il_raw[7:0] <= 8'b0;
end
else if (cpu_int_exit) begin
clic_int_hv <= 1'b0;
clic_int_id[ID_WIDTH-1:0] <= {ID_WIDTH{1'b0}};
clic_int_priv[1:0] <= 2'b0;
clic_int_il_raw[7:0] <= 8'b0;
end
else if (out_clk_en) begin
clic_int_hv <= arb_ctrl_int_hv;
clic_int_id[ID_WIDTH-1:0] <= arb_ctrl_int_id[ID_WIDTH-1:0];
clic_int_priv[1:0] <= {2{arb_ctrl_int_mode}};
clic_int_il_raw[7:0] <= {8{ctrl_int_gt_thresh}} & arb_ctrl_int_il[7:0];
end
end
assign out_clk_en = arb_ctrl_int_req_raw
|| |clic_int_il_raw[7:0];
// &Instance("gated_clk_cell", "x_out_clk"); @217
gated_clk_cell x_out_clk (
.clk_in (clic_clk ),
.clk_out (out_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (out_clk_en ),
.module_en (1'b0 ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (clic_clk), @218
// .external_en (1'b0), @219
// .global_en (1'b1), @220
// .module_en (1'b0), @221
// .local_en (out_clk_en), @222
// .clk_out (out_clk)); @223
// &Instance("pa_clic_cpuif_2cycle"); @226
pa_clic_cpuif_2cycle x_pa_clic_cpuif_2cycle (
.clic_clk_en (clic_clk_en ),
.clic_cpu_int_hv (clic_cpu_int_hv ),
.clic_cpu_int_id (clic_cpu_int_id ),
.clic_cpu_int_il (clic_cpu_int_il ),
.clic_cpu_int_priv (clic_cpu_int_priv ),
.clic_int_hv (clic_int_hv ),
.clic_int_id (clic_int_id ),
.clic_int_il_raw (clic_int_il_raw ),
.clic_int_priv (clic_int_priv ),
.cpu_clic_curid (cpu_clic_curid ),
.cpu_clic_int_exit (cpu_clic_int_exit ),
.cpu_int_exit (cpu_int_exit ),
.cpurst_b (cpurst_b ),
.ctrl_kid_ack_int (ctrl_kid_ack_int ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Instance("pa_clic_cpuif"); @228
// &ModuleEnd; @231
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_clic_expand(
// input
data_in_vec,
// output
expand_out_vec
);
parameter WIDTH = 6;
parameter NUM = 32;
localparam EXP_WIDTH = 1 <<< WIDTH;
input [WIDTH*NUM-1:0] data_in_vec;
output [EXP_WIDTH*NUM-1:0] expand_out_vec;
wire [WIDTH*NUM-1:0] data_in_vec;
wire [EXP_WIDTH*NUM-1:0] expand_out_vec;
genvar i;
generate
for (i = 0; i < NUM; i = i+1)
begin: EXPAND
assign expand_out_vec[EXP_WIDTH*i+:EXP_WIDTH] = {{EXP_WIDTH-1{1'b0}}, 1'b1} << data_in_vec[WIDTH*i+:WIDTH];
end
endgenerate
endmodule

40
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_clic_ff1_onehot(
data_in,
ff1_out_onehot
);
parameter WIDTH = 32;
input [WIDTH-1:0] data_in;
output [WIDTH-1:0] ff1_out_onehot;
wire [WIDTH:0] ff1_tmp;
assign ff1_tmp[WIDTH] = 1'b0;
genvar i;
generate
for (i = 0; i < WIDTH; i = i+1)
begin: FF1_ONEHOT
assign ff1_tmp[i] = data_in[i] || ff1_tmp[i+1];
end
endgenerate
assign ff1_out_onehot[WIDTH-1:0] = ff1_tmp[WIDTH:1] ^ ff1_tmp[WIDTH-1:0];
endmodule

379
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_clic_kid(
busif_kid_clicintattr_sel,
busif_kid_clicintctl_sel,
busif_kid_clicintie_sel,
busif_kid_clicintip_sel,
busif_kid_wdata,
busif_xx_write_vld,
clic_clk,
cpu_clic_mode,
cpurst_b,
ctrl_kid_ack_int,
ctrl_xx_mode_or_mask,
forever_cpuclk,
kid_arb_int_all,
kid_arb_int_hv,
kid_arb_int_req,
kid_busif_rdata,
kid_int_vld,
pad_yy_icg_scan_en
);
// &Ports; @23
input busif_kid_clicintattr_sel;
input busif_kid_clicintctl_sel;
input busif_kid_clicintie_sel;
input busif_kid_clicintip_sel;
input [31:0] busif_kid_wdata;
input busif_xx_write_vld;
input clic_clk;
input [1 :0] cpu_clic_mode;
input cpurst_b;
input ctrl_kid_ack_int;
input ctrl_xx_mode_or_mask;
input forever_cpuclk;
input kid_int_vld;
input pad_yy_icg_scan_en;
output [3 :0] kid_arb_int_all;
output kid_arb_int_hv;
output kid_arb_int_req;
output [31:0] kid_busif_rdata;
// &Regs; @24
reg clicintattr_shv;
reg [1 :0] clicintattr_trig;
reg int_enable;
reg int_pending;
reg int_pending_updt_val;
reg [2 :0] int_prio;
reg int_vld_ff_1;
reg int_vld_ff_2;
// &Wires; @25
wire busif_kid_clicintattr_sel;
wire busif_kid_clicintctl_sel;
wire busif_kid_clicintie_sel;
wire busif_kid_clicintip_sel;
wire [31:0] busif_kid_wdata;
wire busif_xx_write_vld;
wire clic_clk;
wire clic_kid_clk;
wire clic_kid_clk_en;
wire [1 :0] clicintattr_mode;
wire [7 :0] clicintattr_reg;
wire [7 :0] clicintattr_updt_val;
wire clicintattr_updt_vld;
wire [7 :0] clicintctl_reg;
wire [7 :0] clicintctl_updt_val;
wire clicintctl_updt_vld;
wire [7 :0] clicintie_reg;
wire clicintie_updt_vld;
wire [7 :0] clicintip_reg;
wire [1 :0] cpu_clic_mode;
wire cpurst_b;
wire ctrl_kid_ack_int;
wire forever_cpuclk;
wire int_enable_updt_val;
wire int_level;
wire int_neg_pulse;
wire int_neg_pulse_1;
wire int_neg_pulse_2;
wire int_pending_clear;
wire int_pending_set;
wire int_pending_updt_val_raw;
wire int_pending_updt_vld;
wire int_pos_pulse;
wire int_pos_pulse_1;
wire int_pos_pulse_2;
wire int_pulse;
wire int_vld;
wire [3 :0] kid_arb_int_all;
wire kid_arb_int_hv;
wire kid_arb_int_req;
wire [31:0] kid_busif_rdata;
wire kid_ctrl_clicintattr_en;
wire kid_ctrl_clicintctl_en;
wire kid_ctrl_clicintie_en;
wire kid_ctrl_clicintip_en;
wire kid_int_mode;
wire kid_int_vld;
wire kid_mode_vld;
wire kid_sample_clk;
wire kid_sample_clk_en;
wire kid_write_vld;
wire pad_yy_icg_scan_en;
wire sw_clear_pending;
wire sw_set_pending;
parameter CLICINTCTLBITS = `CLIC_INTCTLBITS;
parameter INT_MODE_U = 1'b0;
parameter INT_MODE_M = 1'b1;
parameter CPU_MODE_U = 2'b00;
parameter CPU_MODE_M = 2'b11;
//==========================================================
// Rename Input
//==========================================================
assign int_pending_updt_val_raw = busif_kid_wdata[0];
assign int_enable_updt_val = busif_kid_wdata[8];
assign clicintattr_updt_val[7:0] = busif_kid_wdata[23:16];
assign clicintctl_updt_val[7:0] = busif_kid_wdata[31:24];
assign int_vld = kid_int_vld;
//==========================================================
// kid mode Vld
//==========================================================
// if cpu mode is M, all is vld.
// if cpu mode is U, only U mode int is vld.
assign kid_mode_vld = cpu_clic_mode[1:0] == CPU_MODE_M
|| cpu_clic_mode[1:0] == CPU_MODE_U && kid_int_mode == INT_MODE_U;
//==========================================================
// Write Vld
//==========================================================
assign kid_write_vld = busif_xx_write_vld && kid_mode_vld;
assign sw_set_pending = kid_write_vld && busif_kid_clicintip_sel && int_pending_updt_val_raw;
assign sw_clear_pending = kid_write_vld && busif_kid_clicintip_sel && !int_pending_updt_val_raw;
assign clicintie_updt_vld = kid_write_vld && busif_kid_clicintie_sel;
assign clicintattr_updt_vld = kid_write_vld && busif_kid_clicintattr_sel;
assign clicintctl_updt_vld = kid_write_vld && busif_kid_clicintctl_sel;
//------------------------------------------------
// Interrupt Sample
//------------------------------------------------
assign kid_sample_clk_en = int_vld ^ int_vld_ff_1
|| int_vld_ff_1 ^ int_vld_ff_2;
always@(posedge kid_sample_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
int_vld_ff_1 <= 1'b0;
int_vld_ff_2 <= 1'b0;
end
else begin
int_vld_ff_1 <= int_vld;
int_vld_ff_2 <= int_vld_ff_1;
end
end
assign int_level = int_vld_ff_1;
assign int_pos_pulse_1 = int_vld && !int_vld_ff_1;
assign int_neg_pulse_1 = !int_vld && int_vld_ff_1;
assign int_pos_pulse_2 = int_vld_ff_1 && !int_vld_ff_2;
assign int_neg_pulse_2 = !int_vld_ff_1 && int_vld_ff_2;
assign int_pos_pulse = int_pos_pulse_1 || int_pos_pulse_2;
assign int_neg_pulse = int_neg_pulse_1 || int_neg_pulse_2;
//===========================================================
// interrupt control/status register
//===========================================================
//------------------------------------------------
// security bit
//------------------------------------------------
// assign op_en = 1'b1;
// // &Force("input","ctl_xx_prot_sec"); @130
// // &Force("input","int_sec_updt_val"); @131
//==========================================================
// CLICINTIP
//==========================================================
assign int_pulse = clicintattr_trig[1:0] == 2'b01 && int_pos_pulse
|| clicintattr_trig[1:0] == 2'b11 && int_neg_pulse;
assign int_pending_set = int_pulse || sw_set_pending;
assign int_pending_clear = ctrl_kid_ack_int || sw_clear_pending;
assign int_pending_updt_vld = int_pending_set || int_pending_clear;
// assign kid_ctrl_clicintip_en = !int_pending & int_pending_set ||
// int_pending & int_pending_clear & !int_pending_set;
assign kid_ctrl_clicintip_en = int_pending_set
|| int_pending
|| !clicintattr_trig[0] && (int_pending ^ int_level);
// &CombBeg; @152
always @( int_pending_clear
or int_pending
or int_pending_set)
begin
if (int_pending_set)
int_pending_updt_val = 1'b1;
else if (int_pending_clear)
int_pending_updt_val = 1'b0;
else
int_pending_updt_val = int_pending;
// &CombEnd; @159
end
always@(posedge clic_kid_clk or negedge cpurst_b)
begin
if (!cpurst_b)
int_pending <= 1'b0;
else if (!clicintattr_trig[0])
int_pending <= int_level;
else if (int_pending_updt_vld)
int_pending <= int_pending_updt_val;
else
int_pending <= int_pending;
end
assign clicintip_reg[7:0] = {7'b0, int_pending};
//==========================================================
// CLICINTIE
//==========================================================
// assign int_enable_updt_vld = op_en && clicintie_updt_vld;
assign kid_ctrl_clicintie_en = clicintie_updt_vld;
always@(posedge clic_kid_clk or negedge cpurst_b)
begin
if(!cpurst_b)
int_enable <= 1'b0;
else if (clicintie_updt_vld)
int_enable <= int_enable_updt_val;
else
int_enable <= int_enable;
end
assign clicintie_reg[7:0] = {7'b0, int_enable};
//==========================================================
// CLICINTATTR
//==========================================================
assign kid_ctrl_clicintattr_en = clicintattr_updt_vld;
always @ (posedge clic_kid_clk or negedge cpurst_b)
begin
if (!cpurst_b) begin
clicintattr_trig[1:0] <= 2'b0;
clicintattr_shv <= 1'b0;
end
else if (clicintattr_updt_vld) begin
clicintattr_trig[1:0] <= clicintattr_updt_val[2:1];
clicintattr_shv <= clicintattr_updt_val[0];
end
else begin
clicintattr_trig[1:0] <= clicintattr_trig[1:0];
clicintattr_shv <= clicintattr_shv;
end
end
// &Force("input", "ctrl_xx_mode_or_mask"); @225
assign clicintattr_mode[1:0] = 2'b11;
assign kid_int_mode = 1'b1;
assign clicintattr_reg[7:0] = {clicintattr_mode[1:0],
3'b0,
clicintattr_trig[1:0],
clicintattr_shv};
//==========================================================
// CLICINTCTL
//==========================================================
assign kid_ctrl_clicintctl_en = clicintctl_updt_vld;
always@(posedge clic_kid_clk or negedge cpurst_b)
begin
if(!cpurst_b)
int_prio[CLICINTCTLBITS-1:0] <= {CLICINTCTLBITS{1'b0}};
else if (clicintctl_updt_vld)
int_prio[CLICINTCTLBITS-1:0] <= clicintctl_updt_val[7:8-CLICINTCTLBITS];
else
int_prio[CLICINTCTLBITS-1:0] <= int_prio[CLICINTCTLBITS-1:0];
end
assign clicintctl_reg[7:0] = {int_prio[CLICINTCTLBITS-1:0],
{(8-CLICINTCTLBITS){1'b1}}};
//==========================================================
// Read Data
//==========================================================
assign kid_busif_rdata[31:0] = {({8{busif_kid_clicintctl_sel}} & clicintctl_reg[7:0]),
({8{busif_kid_clicintattr_sel}} & clicintattr_reg[7:0]),
({8{busif_kid_clicintie_sel}} & clicintie_reg[7:0]),
({8{busif_kid_clicintip_sel}} & clicintip_reg[7:0])}
& {32{kid_mode_vld}};
//==========================================================
// OUTPUT
//==========================================================
// TO arbiter
//------------------------------------------------
assign kid_arb_int_req = int_enable & int_pending;
// &Force("output", "kid_arb_int_req"); @272
assign kid_arb_int_hv = clicintattr_shv;
// int_all has three field:
// [CLICINTCTLBITS]: mode
// [CLICINTCTLBITS-1: CLICINTCTLBITS-1-nlbits]: int level
// [CLICINTCTLBITS-2-nlbits]: prio level
assign kid_arb_int_all[CLICINTCTLBITS:0] = {kid_int_mode,
int_prio[CLICINTCTLBITS-1:0]}
& {(CLICINTCTLBITS+1){kid_arb_int_req}};
// assign kid_arb_int_sec = 1'b0;
assign clic_kid_clk_en = kid_ctrl_clicintip_en
|| kid_ctrl_clicintie_en
|| kid_ctrl_clicintattr_en
|| kid_ctrl_clicintctl_en;
// &Instance("gated_clk_cell", "x_clic_kid_clk"); @292
gated_clk_cell x_clic_kid_clk (
.clk_in (clic_clk ),
.clk_out (clic_kid_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (clic_kid_clk_en ),
.module_en (1'b0 ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (clic_clk), @293
// .external_en (1'b0), @294
// .global_en (1'b1), @295
// .module_en (1'b0), @296
// .local_en (clic_kid_clk_en), @297
// .clk_out (clic_kid_clk)); @298
// &Instance("gated_clk_cell", "x_kid_sample_clk"); @300
gated_clk_cell x_kid_sample_clk (
.clk_in (forever_cpuclk ),
.clk_out (kid_sample_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (kid_sample_clk_en ),
.module_en (1'b0 ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @301
// .external_en (1'b0), @302
// .global_en (1'b1), @303
// .module_en (1'b0), @304
// .local_en (kid_sample_clk_en), @305
// .clk_out (kid_sample_clk)); @306
// &ModuleEnd; @308
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_clic_kid_dummy(
kid_arb_int_all,
kid_arb_int_hv,
kid_arb_int_req,
kid_busif_rdata
);
// &Ports; @23
output [3 :0] kid_arb_int_all;
output kid_arb_int_hv;
output kid_arb_int_req;
output [31:0] kid_busif_rdata;
// &Regs; @24
// &Wires; @25
wire [3 :0] kid_arb_int_all;
wire kid_arb_int_hv;
wire kid_arb_int_req;
wire [31:0] kid_busif_rdata;
parameter CLICINTCTLBITS = `CLIC_INTCTLBITS;
assign kid_arb_int_all[CLICINTCTLBITS:0] = {CLICINTCTLBITS+1{1'b0}};
assign kid_arb_int_hv = 1'b0;
assign kid_arb_int_req = 1'b0;
assign kid_busif_rdata[31:0] = 32'b0;
// &ModuleEnd; @34
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_clic_sel(
// input
data_in,
sel_in_onehot,
// output
data_out
);
parameter DATA_WIDTH = 32;
parameter SEL_NUM = 256;
input [DATA_WIDTH*SEL_NUM-1:0] data_in;
input [SEL_NUM-1:0] sel_in_onehot;
output [DATA_WIDTH-1:0] data_out;
wire [DATA_WIDTH-1:0] data_in_2d[SEL_NUM-1:0];
wire [SEL_NUM-1:0] data_in_2d_rev[DATA_WIDTH-1:0];
wire [DATA_WIDTH-1:0] data_out;
//==========================================================
// Generate 2D signal
//==========================================================
genvar i;
genvar j;
generate
for (i = 0; i < SEL_NUM; i = i+1) begin: EXPAND
assign data_in_2d[i][DATA_WIDTH-1:0] = data_in[i*DATA_WIDTH+:DATA_WIDTH] & {DATA_WIDTH{sel_in_onehot[i]}};
end
endgenerate
//==========================================================
// Reverse 2D signal
//==========================================================
generate
for (i = 0; i < SEL_NUM; i = i+1) begin: REVERSEI
for (j = 0; j < DATA_WIDTH; j = j+1) begin: REVERSEJ
assign data_in_2d_rev[j][i] = data_in_2d[i][j];
end
end
endgenerate
//==========================================================
// Do or to sel
//==========================================================
generate
for (i = 0; i < DATA_WIDTH; i = i+1) begin: OR_SEL
assign data_out[i] = |data_in_2d_rev[i][SEL_NUM-1:0];
end
endgenerate
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @27
module pa_clic_top(
clic_cpu_int_hv,
clic_cpu_int_id,
clic_cpu_int_il,
clic_cpu_int_priv,
clic_tcipif_cmplt,
clic_tcipif_rdata,
clint_cpu_me_int,
clint_cpu_ms_int,
clint_cpu_mt_int,
cpu_clic_curid,
cpu_clic_int_exit,
cpu_clic_mode,
cpurst_b,
forever_cpuclk,
ifu_clic_warm_up,
pad_clic_int_vld,
pad_yy_dft_clk_rst_b,
pad_yy_icg_scan_en,
pad_yy_scan_mode,
tcipif_clic_addr,
tcipif_clic_sel,
tcipif_clic_size,
tcipif_clic_wdata,
tcipif_clic_write
);
// &Ports; @28
input clint_cpu_me_int;
input clint_cpu_ms_int;
input clint_cpu_mt_int;
input [11 :0] cpu_clic_curid;
input cpu_clic_int_exit;
input [1 :0] cpu_clic_mode;
input cpurst_b;
input forever_cpuclk;
input ifu_clic_warm_up;
input [127 :0] pad_clic_int_vld;
input pad_yy_dft_clk_rst_b;
input pad_yy_icg_scan_en;
input pad_yy_scan_mode;
input [15 :0] tcipif_clic_addr;
input tcipif_clic_sel;
input [1 :0] tcipif_clic_size;
input [31 :0] tcipif_clic_wdata;
input tcipif_clic_write;
output clic_cpu_int_hv;
output [11 :0] clic_cpu_int_id;
output [7 :0] clic_cpu_int_il;
output [1 :0] clic_cpu_int_priv;
output clic_tcipif_cmplt;
output [31 :0] clic_tcipif_rdata;
// &Regs; @29
reg clic_clk_en_raw;
reg clic_test_point;
// &Wires; @30
wire arb_ctrl_int_hv;
wire [11 :0] arb_ctrl_int_id;
wire [7 :0] arb_ctrl_int_il;
wire arb_ctrl_int_mode;
wire arb_ctrl_int_req_raw;
wire busif_ctrl_cliccfg_sel;
wire busif_ctrl_clicinfo_sel;
wire busif_ctrl_mintthresh_sel;
wire [143 :0] busif_kid_clicintattr_sel;
wire [143 :0] busif_kid_clicintctl_sel;
wire [143 :0] busif_kid_clicintie_sel;
wire [143 :0] busif_kid_clicintip_sel;
wire [31 :0] busif_kid_wdata;
wire busif_xx_write_vld;
wire clic_clk;
wire clic_clk_en;
wire clic_cpu_int_hv;
wire [11 :0] clic_cpu_int_id;
wire [7 :0] clic_cpu_int_il;
wire [1 :0] clic_cpu_int_priv;
wire clic_rst_b;
wire clic_tcipif_cmplt;
wire [31 :0] clic_tcipif_rdata;
wire clicreg_clk;
wire clint_cpu_me_int;
wire clint_cpu_ms_int;
wire clint_cpu_mt_int;
wire [11 :0] cpu_clic_curid;
wire cpu_clic_int_exit;
wire [1 :0] cpu_clic_mode;
wire cpurst_b;
wire [31 :0] ctrl_busif_cliccfg_val;
wire [31 :0] ctrl_busif_clicinfo_val;
wire [31 :0] ctrl_busif_mintthresh_val;
wire ctrl_clicreg_en;
wire [143 :0] ctrl_kid_ack_int;
wire [2 :0] ctrl_xx_int_lv_or_mask;
wire ctrl_xx_mode_or_mask;
wire forever_cpuclk;
wire ifu_clic_warm_up;
wire [575 :0] kid_arb_int_all_vec;
wire [143 :0] kid_arb_int_hv;
wire [143 :0] kid_arb_int_req;
wire [4607:0] kid_busif_rdata_vec;
wire [143 :0] kid_int_vld;
wire [127 :0] pad_clic_int_vld;
wire pad_yy_dft_clk_rst_b;
wire pad_yy_icg_scan_en;
wire pad_yy_scan_mode;
wire [15 :0] tcipif_clic_addr;
wire tcipif_clic_sel;
wire [1 :0] tcipif_clic_size;
wire [31 :0] tcipif_clic_wdata;
wire tcipif_clic_write;
parameter CLICINTNUM = `CLIC_INTNUM;
parameter CLICINTCTLBITS = `CLIC_INTCTLBITS;
// &Instance("pa_clic_arb"); @35
pa_clic_arb x_pa_clic_arb (
.arb_ctrl_int_hv (arb_ctrl_int_hv ),
.arb_ctrl_int_id (arb_ctrl_int_id ),
.arb_ctrl_int_il (arb_ctrl_int_il ),
.arb_ctrl_int_mode (arb_ctrl_int_mode ),
.arb_ctrl_int_req_raw (arb_ctrl_int_req_raw ),
.ctrl_xx_int_lv_or_mask (ctrl_xx_int_lv_or_mask),
.kid_arb_int_all_vec (kid_arb_int_all_vec ),
.kid_arb_int_hv (kid_arb_int_hv ),
.kid_arb_int_req (kid_arb_int_req )
);
// &Instance("pa_clic_busif"); @36
pa_clic_busif x_pa_clic_busif (
.busif_ctrl_cliccfg_sel (busif_ctrl_cliccfg_sel ),
.busif_ctrl_clicinfo_sel (busif_ctrl_clicinfo_sel ),
.busif_ctrl_mintthresh_sel (busif_ctrl_mintthresh_sel),
.busif_kid_clicintattr_sel (busif_kid_clicintattr_sel),
.busif_kid_clicintctl_sel (busif_kid_clicintctl_sel ),
.busif_kid_clicintie_sel (busif_kid_clicintie_sel ),
.busif_kid_clicintip_sel (busif_kid_clicintip_sel ),
.busif_kid_wdata (busif_kid_wdata ),
.busif_xx_write_vld (busif_xx_write_vld ),
.clic_clk (clic_clk ),
.clic_clk_en (clic_clk_en ),
.clic_tcipif_cmplt (clic_tcipif_cmplt ),
.clic_tcipif_rdata (clic_tcipif_rdata ),
.cpurst_b (cpurst_b ),
.ctrl_busif_cliccfg_val (ctrl_busif_cliccfg_val ),
.ctrl_busif_clicinfo_val (ctrl_busif_clicinfo_val ),
.ctrl_busif_mintthresh_val (ctrl_busif_mintthresh_val),
.ifu_clic_warm_up (ifu_clic_warm_up ),
.kid_busif_rdata_vec (kid_busif_rdata_vec ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.pad_yy_scan_mode (pad_yy_scan_mode ),
.tcipif_clic_addr (tcipif_clic_addr ),
.tcipif_clic_sel (tcipif_clic_sel ),
.tcipif_clic_size (tcipif_clic_size ),
.tcipif_clic_wdata (tcipif_clic_wdata ),
.tcipif_clic_write (tcipif_clic_write )
);
// &Instance("pa_clic_ctrl"); @37
pa_clic_ctrl x_pa_clic_ctrl (
.arb_ctrl_int_hv (arb_ctrl_int_hv ),
.arb_ctrl_int_id (arb_ctrl_int_id ),
.arb_ctrl_int_il (arb_ctrl_int_il ),
.arb_ctrl_int_mode (arb_ctrl_int_mode ),
.arb_ctrl_int_req_raw (arb_ctrl_int_req_raw ),
.busif_ctrl_cliccfg_sel (busif_ctrl_cliccfg_sel ),
.busif_ctrl_clicinfo_sel (busif_ctrl_clicinfo_sel ),
.busif_ctrl_mintthresh_sel (busif_ctrl_mintthresh_sel),
.busif_kid_wdata (busif_kid_wdata ),
.busif_xx_write_vld (busif_xx_write_vld ),
.clic_clk (clic_clk ),
.clic_clk_en (clic_clk_en ),
.clic_cpu_int_hv (clic_cpu_int_hv ),
.clic_cpu_int_id (clic_cpu_int_id ),
.clic_cpu_int_il (clic_cpu_int_il ),
.clic_cpu_int_priv (clic_cpu_int_priv ),
.clicreg_clk (clicreg_clk ),
.cpu_clic_curid (cpu_clic_curid ),
.cpu_clic_int_exit (cpu_clic_int_exit ),
.cpu_clic_mode (cpu_clic_mode ),
.cpurst_b (cpurst_b ),
.ctrl_busif_cliccfg_val (ctrl_busif_cliccfg_val ),
.ctrl_busif_clicinfo_val (ctrl_busif_clicinfo_val ),
.ctrl_busif_mintthresh_val (ctrl_busif_mintthresh_val),
.ctrl_clicreg_en (ctrl_clicreg_en ),
.ctrl_kid_ack_int (ctrl_kid_ack_int ),
.ctrl_xx_int_lv_or_mask (ctrl_xx_int_lv_or_mask ),
.ctrl_xx_mode_or_mask (ctrl_xx_mode_or_mask ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
assign kid_int_vld[CLICINTNUM-1:16] = pad_clic_int_vld[CLICINTNUM-17:0];
// &Force("input", "pad_clic_int_vld"); &Force("bus", "pad_clic_int_vld", CLICINTNUM-17, 0); @41
assign kid_int_vld[15:0] = {3'b0, 1'b0, // clic software int
clint_cpu_me_int, 3'b0,
clint_cpu_mt_int, 3'b0,
clint_cpu_ms_int, 3'b0};
// &Force("nonport", "kid_int_vld"); @47
// &Force("nonport", "kid_busif_rdata_bus"); @49
// &Force("nonport", "busif_kid_clicintattr_sel"); @50
// &Force("nonport", "busif_kid_clicintctl_sel"); @51
// &Force("nonport", "busif_kid_clicintie_sel"); @52
// &Force("nonport", "busif_kid_clicintip_sel"); @53
// &Force("nonport", "ctrl_kid_ack_int"); @54
// &Force("nonport", "ctrl_kid_int_exit_gate"); @55
// &Force("nonport", "ctrl_xx_mode_or_mask"); @56
// &Force("nonport", "kid_arb_int_all_vec"); @57
// &Force("nonport", "kid_arb_int_hv"); @58
// &Force("nonport", "kid_arb_int_req"); @59
// &Force("nonport", "kid_busif_rdata_vec"); @60
//csky vperl_off
genvar i;
generate
for (i = 0; i < CLICINTNUM; i = i+1)
begin: INT_KID
case(i)
0, 1, 2,
4, 5, 6,
8, 9, 10,
13, 14, 15:
begin: KID_DUMMY
pa_clic_kid_dummy x_pa_clic_kid(
.kid_arb_int_all (kid_arb_int_all_vec[(CLICINTCTLBITS+1)*i+:(CLICINTCTLBITS+1)]),
.kid_arb_int_hv (kid_arb_int_hv[i]),
.kid_arb_int_req (kid_arb_int_req[i]),
.kid_busif_rdata (kid_busif_rdata_vec[32*i+:32])
);
end
default:
begin: KID_TRUE
pa_clic_kid x_pa_clic_kid(
.busif_kid_clicintattr_sel (busif_kid_clicintattr_sel[i]),
.busif_kid_clicintctl_sel (busif_kid_clicintctl_sel[i]),
.busif_kid_clicintie_sel (busif_kid_clicintie_sel[i]),
.busif_kid_clicintip_sel (busif_kid_clicintip_sel[i]),
.busif_kid_wdata (busif_kid_wdata),
.busif_xx_write_vld (busif_xx_write_vld),
.clic_clk (clic_clk),
.cpu_clic_mode (cpu_clic_mode),
.cpurst_b (cpurst_b),
.ctrl_kid_ack_int (ctrl_kid_ack_int[i]),
.ctrl_xx_mode_or_mask (ctrl_xx_mode_or_mask),
.forever_cpuclk (forever_cpuclk),
.kid_arb_int_all (kid_arb_int_all_vec[(CLICINTCTLBITS+1)*i+:(CLICINTCTLBITS+1)]),
.kid_arb_int_hv (kid_arb_int_hv[i]),
.kid_arb_int_req (kid_arb_int_req[i]),
.kid_busif_rdata (kid_busif_rdata_vec[32*i+:32]),
.kid_int_vld (kid_int_vld[i]),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
end
endcase
end
endgenerate
//csky vperl_on
assign clic_rst_b = pad_yy_scan_mode ? pad_yy_dft_clk_rst_b : cpurst_b;
always @ (posedge forever_cpuclk or negedge clic_rst_b)
begin
if (!clic_rst_b) begin
clic_clk_en_raw <= 1'b0;
end
else begin
clic_clk_en_raw <= !clic_clk_en_raw;
end
end
always @ (posedge forever_cpuclk or negedge cpurst_b)
begin
if (!cpurst_b) begin
clic_test_point <= 1'b0;
end
else begin
clic_test_point <= 1'b1;
end
end
assign clic_clk_en = pad_yy_scan_mode ? clic_test_point : clic_clk_en_raw;
// &Force("nonport", "clic_clk"); @134
BUFGCE clic_clk_buf
(.O (clic_clk),
.I (forever_cpuclk),
.CE (clic_clk_en_raw)
);
// &Instance("gated_clk_cell", "x_clic_clk"); @141
// &Connect(.clk_in (forever_cpuclk), @142
// .external_en (1'b0), @143
// .global_en (1'b1), @144
// .module_en (1'b0), @145
// .local_en (clic_clk_en_raw), @146
// .clk_out (clic_clk), @147
// .pad_yy_icg_scan_en (1'b0)); @148
//==========================================================
// Gate Clk Cell
//==========================================================
// &Instance("gated_clk_cell", "x_clicreg_clk"); @160
gated_clk_cell x_clicreg_clk (
.clk_in (clic_clk ),
.clk_out (clicreg_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (ctrl_clicreg_en ),
.module_en (1'b0 ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (clic_clk), @161
// .external_en (1'b0), @162
// .global_en (1'b1), @163
// .module_en (1'b0), @164
// .local_en (ctrl_clicreg_en), @165
// .clk_out (clicreg_clk)); @166
// &ModuleEnd; @168
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_clint_busif(
busif_regs_msip_sel,
busif_regs_mtimecmp_hi_sel,
busif_regs_mtimecmp_lo_sel,
busif_regs_wdata,
busif_regs_write_vld,
clint_tcipif_cmplt,
clint_tcipif_rdata,
msip_value,
mtime_hi_value,
mtime_lo_value,
mtimecmp_hi_value,
mtimecmp_lo_value,
tcipif_clint_addr,
tcipif_clint_sel,
tcipif_clint_wdata,
tcipif_clint_write
);
// &Ports; @23
input [31:0] msip_value;
input [31:0] mtime_hi_value;
input [31:0] mtime_lo_value;
input [31:0] mtimecmp_hi_value;
input [31:0] mtimecmp_lo_value;
input [15:0] tcipif_clint_addr;
input tcipif_clint_sel;
input [31:0] tcipif_clint_wdata;
input tcipif_clint_write;
output busif_regs_msip_sel;
output busif_regs_mtimecmp_hi_sel;
output busif_regs_mtimecmp_lo_sel;
output [31:0] busif_regs_wdata;
output busif_regs_write_vld;
output clint_tcipif_cmplt;
output [31:0] clint_tcipif_rdata;
// &Regs; @24
// &Wires; @25
wire busif_read_vld;
wire busif_regs_msip_sel;
wire busif_regs_mtimecmp_hi_sel;
wire busif_regs_mtimecmp_lo_sel;
wire [31:0] busif_regs_wdata;
wire busif_regs_write_vld;
wire clint_tcipif_cmplt;
wire [31:0] clint_tcipif_rdata;
wire msip_sel;
wire [31:0] msip_value;
wire mtime_hi_sel;
wire [31:0] mtime_hi_value;
wire mtime_lo_sel;
wire [31:0] mtime_lo_value;
wire mtimecmp_hi_sel;
wire [31:0] mtimecmp_hi_value;
wire mtimecmp_lo_sel;
wire [31:0] mtimecmp_lo_value;
wire [15:0] tcipif_clint_addr;
wire tcipif_clint_sel;
wire [31:0] tcipif_clint_wdata;
wire tcipif_clint_write;
parameter MSIP = 16'h0000;
parameter MTIMECMPLO = 16'h4000;
parameter MTIMECMPHI = 16'h4004;
parameter MTIMELO = 16'hbff8;
parameter MTIMEHI = 16'hbffc;
assign msip_sel = tcipif_clint_addr[15:0] == MSIP;
assign mtimecmp_lo_sel = tcipif_clint_addr[15:0] == MTIMECMPLO;
assign mtimecmp_hi_sel = tcipif_clint_addr[15:0] == MTIMECMPHI;
assign mtime_lo_sel = tcipif_clint_addr[15:0] == MTIMELO;
assign mtime_hi_sel = tcipif_clint_addr[15:0] == MTIMEHI;
assign busif_regs_msip_sel = msip_sel;
assign busif_regs_mtimecmp_lo_sel = mtimecmp_lo_sel;
assign busif_regs_mtimecmp_hi_sel = mtimecmp_hi_sel;
assign clint_tcipif_cmplt = tcipif_clint_sel;
assign busif_regs_write_vld = tcipif_clint_sel && tcipif_clint_write;
assign busif_read_vld = tcipif_clint_sel && !tcipif_clint_write;
assign clint_tcipif_rdata[31:0] = ({32{msip_sel}} & msip_value[31:0]
| {32{mtimecmp_lo_sel}} & mtimecmp_lo_value[31:0]
| {32{mtimecmp_hi_sel}} & mtimecmp_hi_value[31:0]
| {32{mtime_lo_sel}} & mtime_lo_value[31:0]
| {32{mtime_hi_sel}} & mtime_hi_value[31:0])
& {32{busif_read_vld}};
assign busif_regs_wdata[31:0] = tcipif_clint_wdata[31:0];
// &ModuleEnd; @59
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_clint_regs(
busif_regs_msip_sel,
busif_regs_mtimecmp_hi_sel,
busif_regs_mtimecmp_lo_sel,
busif_regs_wdata,
busif_regs_write_vld,
clint_clk,
clint_cpu_me_int,
clint_cpu_ms_int,
clint_cpu_mt_int,
cpu_clint_mode,
cpurst_b,
msip_value,
mtime_hi_value,
mtime_lo_value,
mtimecmp_hi_value,
mtimecmp_lo_value,
sysio_clint_me_int,
sysio_clint_mtime
);
// &Ports; @23
input busif_regs_msip_sel;
input busif_regs_mtimecmp_hi_sel;
input busif_regs_mtimecmp_lo_sel;
input [31:0] busif_regs_wdata;
input busif_regs_write_vld;
input clint_clk;
input [1 :0] cpu_clint_mode;
input cpurst_b;
input sysio_clint_me_int;
input [63:0] sysio_clint_mtime;
output clint_cpu_me_int;
output clint_cpu_ms_int;
output clint_cpu_mt_int;
output [31:0] msip_value;
output [31:0] mtime_hi_value;
output [31:0] mtime_lo_value;
output [31:0] mtimecmp_hi_value;
output [31:0] mtimecmp_lo_value;
// &Regs; @24
reg msip_en;
reg [31:0] mtimecmp_hi;
reg [31:0] mtimecmp_lo;
// &Wires; @25
wire busif_regs_msip_sel;
wire busif_regs_mtimecmp_hi_sel;
wire busif_regs_mtimecmp_lo_sel;
wire [31:0] busif_regs_wdata;
wire busif_regs_write_vld;
wire clint_clk;
wire clint_cpu_me_int;
wire clint_cpu_ms_int;
wire clint_cpu_mt_int;
wire [1 :0] cpu_clint_mode;
wire cpu_is_m_mode;
wire cpurst_b;
wire mregs_write_vld;
wire [31:0] msip_value;
wire [31:0] mtime_hi_value;
wire [31:0] mtime_lo_value;
wire [31:0] mtimecmp_hi_value;
wire [31:0] mtimecmp_lo_value;
wire sysio_clint_me_int;
wire [63:0] sysio_clint_mtime;
parameter CPU_M_MODE = 2'b11;
//==========================================================
// Write Ctrl
//==========================================================
assign cpu_is_m_mode = cpu_clint_mode[1:0] == CPU_M_MODE;
assign mregs_write_vld = busif_regs_write_vld && cpu_is_m_mode;
//==========================================================
// Regs
//==========================================================
//----------------- MSIP ---------------
always @ (posedge clint_clk or negedge cpurst_b)
begin
if (!cpurst_b)
msip_en <= 1'b0;
else if (mregs_write_vld && busif_regs_msip_sel)
msip_en <= busif_regs_wdata[0];
else
msip_en <= msip_en;
end
assign msip_value[31:0] = {31'b0, msip_en};
//------------- MTIMECMP_LO ------------
always @ (posedge clint_clk or negedge cpurst_b)
begin
if (!cpurst_b)
mtimecmp_lo[31:0] <= 32'hffffffff;
else if (mregs_write_vld && busif_regs_mtimecmp_lo_sel)
mtimecmp_lo[31:0] <= busif_regs_wdata[31:0];
else
mtimecmp_lo[31:0] <= mtimecmp_lo[31:0];
end
assign mtimecmp_lo_value[31:0] = mtimecmp_lo[31:0];
//------------- MTIMECMP_HI ------------
always @ (posedge clint_clk or negedge cpurst_b)
begin
if (!cpurst_b)
mtimecmp_hi[31:0] <= 32'hffffffff;
else if (mregs_write_vld && busif_regs_mtimecmp_hi_sel)
mtimecmp_hi[31:0] <= busif_regs_wdata[31:0];
else
mtimecmp_hi[31:0] <= mtimecmp_hi[31:0];
end
assign mtimecmp_hi_value[31:0] = mtimecmp_hi[31:0];
//--------------- MTIME_LOW ------------
assign mtime_lo_value[31:0] = sysio_clint_mtime[31:0];
//--------------- MTIME_HI -------------
assign mtime_hi_value[31:0] = sysio_clint_mtime[63:32];
//==========================================================
// CLINT Output Signal
//==========================================================
assign clint_cpu_ms_int = msip_en;
assign clint_cpu_mt_int = !({mtimecmp_hi[31:0], mtimecmp_lo[31:0]}
> sysio_clint_mtime[63:0]);
assign clint_cpu_me_int = sysio_clint_me_int;
// &ModuleEnd; @93
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_clint_top(
clint_cpu_me_int,
clint_cpu_ms_int,
clint_cpu_mt_int,
clint_tcipif_cmplt,
clint_tcipif_rdata,
cpu_clint_mode,
cpurst_b,
forever_cpuclk,
pad_yy_icg_scan_en,
sysio_clint_me_int,
sysio_clint_mtime,
tcipif_clint_addr,
tcipif_clint_sel,
tcipif_clint_wdata,
tcipif_clint_write
);
// &Ports; @23
input [1 :0] cpu_clint_mode;
input cpurst_b;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input sysio_clint_me_int;
input [63:0] sysio_clint_mtime;
input [15:0] tcipif_clint_addr;
input tcipif_clint_sel;
input [31:0] tcipif_clint_wdata;
input tcipif_clint_write;
output clint_cpu_me_int;
output clint_cpu_ms_int;
output clint_cpu_mt_int;
output clint_tcipif_cmplt;
output [31:0] clint_tcipif_rdata;
// &Regs; @24
// &Wires; @25
wire busif_regs_msip_sel;
wire busif_regs_mtimecmp_hi_sel;
wire busif_regs_mtimecmp_lo_sel;
wire [31:0] busif_regs_wdata;
wire busif_regs_write_vld;
wire clint_clk;
wire clint_clk_en;
wire clint_cpu_me_int;
wire clint_cpu_ms_int;
wire clint_cpu_mt_int;
wire clint_tcipif_cmplt;
wire [31:0] clint_tcipif_rdata;
wire [1 :0] cpu_clint_mode;
wire cpurst_b;
wire forever_cpuclk;
wire [31:0] msip_value;
wire [31:0] mtime_hi_value;
wire [31:0] mtime_lo_value;
wire [31:0] mtimecmp_hi_value;
wire [31:0] mtimecmp_lo_value;
wire pad_yy_icg_scan_en;
wire sysio_clint_me_int;
wire [63:0] sysio_clint_mtime;
wire [15:0] tcipif_clint_addr;
wire tcipif_clint_sel;
wire [31:0] tcipif_clint_wdata;
wire tcipif_clint_write;
// &Instance("pa_clint_regs"); @27
pa_clint_regs x_pa_clint_regs (
.busif_regs_msip_sel (busif_regs_msip_sel ),
.busif_regs_mtimecmp_hi_sel (busif_regs_mtimecmp_hi_sel),
.busif_regs_mtimecmp_lo_sel (busif_regs_mtimecmp_lo_sel),
.busif_regs_wdata (busif_regs_wdata ),
.busif_regs_write_vld (busif_regs_write_vld ),
.clint_clk (clint_clk ),
.clint_cpu_me_int (clint_cpu_me_int ),
.clint_cpu_ms_int (clint_cpu_ms_int ),
.clint_cpu_mt_int (clint_cpu_mt_int ),
.cpu_clint_mode (cpu_clint_mode ),
.cpurst_b (cpurst_b ),
.msip_value (msip_value ),
.mtime_hi_value (mtime_hi_value ),
.mtime_lo_value (mtime_lo_value ),
.mtimecmp_hi_value (mtimecmp_hi_value ),
.mtimecmp_lo_value (mtimecmp_lo_value ),
.sysio_clint_me_int (sysio_clint_me_int ),
.sysio_clint_mtime (sysio_clint_mtime )
);
// &Instance("pa_clint_busif"); @28
pa_clint_busif x_pa_clint_busif (
.busif_regs_msip_sel (busif_regs_msip_sel ),
.busif_regs_mtimecmp_hi_sel (busif_regs_mtimecmp_hi_sel),
.busif_regs_mtimecmp_lo_sel (busif_regs_mtimecmp_lo_sel),
.busif_regs_wdata (busif_regs_wdata ),
.busif_regs_write_vld (busif_regs_write_vld ),
.clint_tcipif_cmplt (clint_tcipif_cmplt ),
.clint_tcipif_rdata (clint_tcipif_rdata ),
.msip_value (msip_value ),
.mtime_hi_value (mtime_hi_value ),
.mtime_lo_value (mtime_lo_value ),
.mtimecmp_hi_value (mtimecmp_hi_value ),
.mtimecmp_lo_value (mtimecmp_lo_value ),
.tcipif_clint_addr (tcipif_clint_addr ),
.tcipif_clint_sel (tcipif_clint_sel ),
.tcipif_clint_wdata (tcipif_clint_wdata ),
.tcipif_clint_write (tcipif_clint_write )
);
assign clint_clk_en = tcipif_clint_sel;
// &Instance("gated_clk_cell", "x_clint_gateclk"); @31
gated_clk_cell x_clint_gateclk (
.clk_in (forever_cpuclk ),
.clk_out (clint_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (clint_clk_en ),
.module_en (1'b0 ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @32
// .external_en(1'b0 ), @33
// .global_en (1'b1 ), @34
// .module_en (1'b0 ), @35
// .local_en (clint_clk_en ), @36
// .clk_out (clint_clk ) @37
// ); @38
// &ModuleEnd; @41
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module gated_clk_cell(
clk_in,
global_en,
module_en,
local_en,
external_en,
pad_yy_icg_scan_en,
clk_out
);
input clk_in;
input global_en;
input module_en;
input local_en;
input external_en;
input pad_yy_icg_scan_en;
output clk_out;
wire clk_en_bf_latch;
wire SE;
assign clk_en_bf_latch = (global_en && (module_en || local_en)) || external_en ;
// SE driven from primary input, held constant
assign SE = pad_yy_icg_scan_en;
// // &Connect( .clk_in (clk_in), @50
// // .SE (SE), @51
// // .external_en (clk_en_bf_latch), @52
// // .clk_out (clk_out) @53
// // ) ; @54
assign clk_out = clk_in;
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_clk_top(
clk_en,
clk_en_f,
forever_cpuclk,
pll_core_cpuclk
);
// &Ports; @24
input clk_en;
input pll_core_cpuclk;
output clk_en_f;
output forever_cpuclk;
// &Regs; @25
reg clk_en_f;
// &Wires; @26
wire clk_en;
wire forever_cpuclk;
wire pll_core_cpuclk;
//assign forever_jtgclk = pad_had_jtg_tclk;
assign forever_cpuclk = pll_core_cpuclk;
// &Force("output","forever_cpuclk"); @30
// &Force("output", "axim_clk_en_f"); @32
always@(posedge forever_cpuclk)
begin
clk_en_f <= clk_en;
end
// &ModuleEnd; @65
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @22
module pa_clkrst_top(
clk_en,
clk_en_f,
cpurst_b,
forever_cpuclk,
pad_cpu_rst_b,
pad_yy_scan_mode,
pad_yy_scan_rst_b,
pll_core_cpuclk,
sync_sys_apb_rst_b,
sys_apb_clk,
sys_apb_rst_b
);
// &Ports; @23
input clk_en;
input pad_cpu_rst_b;
input pad_yy_scan_mode;
input pad_yy_scan_rst_b;
input pll_core_cpuclk;
input sys_apb_clk;
input sys_apb_rst_b;
output clk_en_f;
output cpurst_b;
output forever_cpuclk;
output sync_sys_apb_rst_b;
// &Regs; @24
// &Wires; @25
wire clk_en;
wire clk_en_f;
wire cpurst_b;
wire forever_cpuclk;
wire pad_cpu_rst_b;
wire pad_yy_scan_mode;
wire pad_yy_scan_rst_b;
wire pll_core_cpuclk;
wire sync_sys_apb_rst_b;
wire sys_apb_clk;
wire sys_apb_rst_b;
// &Force("output", "forever_cpuclk"); @27
//----------------------------------------------------------
// clock top
//----------------------------------------------------------
// &Instance("pa_clk_top"); @32
pa_clk_top x_pa_clk_top (
.clk_en (clk_en ),
.clk_en_f (clk_en_f ),
.forever_cpuclk (forever_cpuclk ),
.pll_core_cpuclk (pll_core_cpuclk)
);
//----------------------------------------------------------
// reset top
//----------------------------------------------------------
// &Instance("pa_rst_top"); @37
pa_rst_top x_pa_rst_top (
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.pad_yy_scan_mode (pad_yy_scan_mode ),
.pad_yy_scan_rst_b (pad_yy_scan_rst_b ),
.sync_sys_apb_rst_b (sync_sys_apb_rst_b),
.sys_apb_clk (sys_apb_clk ),
.sys_apb_rst_b (sys_apb_rst_b )
);
// &ModuleEnd; @38
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module BUFGCE(
I,
CE,
O
);
input I;
input CE ;
output O;
reg clk_en_af_latch;
always @(I or CE)
begin
if(!I)
clk_en_af_latch <= CE;
end
reg clk_en ;
always @ (clk_en_af_latch )
begin
clk_en <= clk_en_af_latch;
end
assign O = I && clk_en ;
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_cp0_ext_csr(
cp0_biu_icg_en,
cp0_dtu_icg_en,
cp0_dtu_pcfifo_frz,
cp0_fpu_icg_en,
cp0_hpcp_icg_en,
cp0_idu_icg_en,
cp0_idu_spec_push_en,
cp0_idu_swap_sp_en,
cp0_ifu_bht_en,
cp0_ifu_bht_inv,
cp0_ifu_btb_clr,
cp0_ifu_btb_en,
cp0_ifu_icache_en,
cp0_ifu_icache_inv_addr,
cp0_ifu_icache_inv_req,
cp0_ifu_icache_inv_type,
cp0_ifu_icg_en,
cp0_ifu_ras_en,
cp0_ifu_rst_inv_done,
cp0_iu_icg_en,
cp0_lsu_dcache_en,
cp0_lsu_dcache_wa,
cp0_lsu_dcache_wb,
cp0_lsu_icc_addr,
cp0_lsu_icc_op,
cp0_lsu_icc_req,
cp0_lsu_icc_type,
cp0_lsu_icg_en,
cp0_pmp_icg_en,
cp0_rtu_icg_en,
cp0_rtu_in_expt,
cp0_rtu_wfe_en,
cp0_xx_async_expt_en,
cpurst_b,
ext_inst_ifu_icc_addr,
ext_inst_ifu_icc_req,
ext_inst_ifu_icc_type,
ext_inst_ifu_inv_done,
ext_inst_lsu_icc_addr,
ext_inst_lsu_icc_done,
ext_inst_lsu_icc_op,
ext_inst_lsu_icc_req,
ext_inst_lsu_icc_type,
forever_cpuclk,
ifu_cp0_bht_inv_done,
ifu_cp0_icache_inv_done,
ifu_cp0_rst_inv_req,
inv_sm_clk,
iui_regs_inst_mret,
iui_regs_wdata,
iui_regs_wdata_srst,
lsu_cp0_icc_done,
mexstatus_local_en,
mexstatus_value,
mhcr_local_en,
mhcr_value,
mhint2_local_en,
mhint2_value,
mhint_local_en,
mhint_value,
mraddr_value,
pad_yy_icg_scan_en,
regs_clk,
regs_cpu_in_int,
regs_cpu_in_nmi,
regs_flush_clk,
regs_special_lpmd,
regs_spswap_en,
regs_srst_srst_vld,
regs_srst_srstmd,
rst_top_op_done,
rtu_cp0_bus_error,
rtu_cp0_lockup_clr,
rtu_cp0_lockup_vld,
rtu_cp0_nmi_vld,
rtu_yy_xx_dbgon,
rtu_yy_xx_expt_int,
rtu_yy_xx_expt_vld,
special_dcache_clean,
special_icache_inv,
special_icache_inv_done,
special_regs_clk_en,
special_regs_inv_sm_clk_en,
sysio_cp0_clkratio,
sysio_cp0_rst_addr
);
// &Ports; @24
input cpurst_b;
input [31:0] ext_inst_ifu_icc_addr;
input ext_inst_ifu_icc_req;
input ext_inst_ifu_icc_type;
input [31:0] ext_inst_lsu_icc_addr;
input [1 :0] ext_inst_lsu_icc_op;
input ext_inst_lsu_icc_req;
input [1 :0] ext_inst_lsu_icc_type;
input forever_cpuclk;
input ifu_cp0_bht_inv_done;
input ifu_cp0_icache_inv_done;
input ifu_cp0_rst_inv_req;
input iui_regs_inst_mret;
input [31:0] iui_regs_wdata;
input [1 :0] iui_regs_wdata_srst;
input lsu_cp0_icc_done;
input mexstatus_local_en;
input mhcr_local_en;
input mhint2_local_en;
input mhint_local_en;
input pad_yy_icg_scan_en;
input regs_clk;
input regs_cpu_in_int;
input regs_flush_clk;
input rtu_cp0_bus_error;
input rtu_cp0_lockup_clr;
input rtu_cp0_lockup_vld;
input rtu_cp0_nmi_vld;
input rtu_yy_xx_dbgon;
input rtu_yy_xx_expt_int;
input rtu_yy_xx_expt_vld;
input special_dcache_clean;
input special_icache_inv;
input special_regs_clk_en;
input special_regs_inv_sm_clk_en;
input [2 :0] sysio_cp0_clkratio;
input [31:0] sysio_cp0_rst_addr;
output cp0_biu_icg_en;
output cp0_dtu_icg_en;
output cp0_dtu_pcfifo_frz;
output cp0_fpu_icg_en;
output cp0_hpcp_icg_en;
output cp0_idu_icg_en;
output cp0_idu_spec_push_en;
output cp0_idu_swap_sp_en;
output cp0_ifu_bht_en;
output cp0_ifu_bht_inv;
output cp0_ifu_btb_clr;
output cp0_ifu_btb_en;
output cp0_ifu_icache_en;
output [31:0] cp0_ifu_icache_inv_addr;
output cp0_ifu_icache_inv_req;
output cp0_ifu_icache_inv_type;
output cp0_ifu_icg_en;
output cp0_ifu_ras_en;
output cp0_ifu_rst_inv_done;
output cp0_iu_icg_en;
output cp0_lsu_dcache_en;
output cp0_lsu_dcache_wa;
output cp0_lsu_dcache_wb;
output [31:0] cp0_lsu_icc_addr;
output [1 :0] cp0_lsu_icc_op;
output cp0_lsu_icc_req;
output [1 :0] cp0_lsu_icc_type;
output cp0_lsu_icg_en;
output cp0_pmp_icg_en;
output cp0_rtu_icg_en;
output cp0_rtu_in_expt;
output cp0_rtu_wfe_en;
output cp0_xx_async_expt_en;
output ext_inst_ifu_inv_done;
output ext_inst_lsu_icc_done;
output inv_sm_clk;
output [31:0] mexstatus_value;
output [31:0] mhcr_value;
output [31:0] mhint2_value;
output [31:0] mhint_value;
output [31:0] mraddr_value;
output regs_cpu_in_nmi;
output [1 :0] regs_special_lpmd;
output regs_spswap_en;
output regs_srst_srst_vld;
output [1 :0] regs_srst_srstmd;
output rst_top_op_done;
output special_icache_inv_done;
// &Regs; @25
reg bpe;
reg de;
reg ie;
reg l0btb;
reg mexstatus_bus_err;
reg mexstatus_expt;
reg mexstatus_lockup;
reg [1 :0] mexstatus_lpmd;
reg mexstatus_nmi;
reg [1 :0] mexstatus_rstmd;
reg mexstatus_spswapen;
reg mexstatus_spushen;
reg mexstatus_wfeen;
reg mhint_aee;
reg [8 :0] module_icg_en;
reg pcfifo_freeze;
reg rs;
reg [1 :0] rst_bht_inv;
reg [1 :0] rst_bht_inv_nxt;
reg [1 :0] rst_cache_inv;
reg [1 :0] rst_cache_inv_nxt;
reg [1 :0] rst_dcache_inv;
reg [1 :0] rst_dcache_inv_nxt;
reg [1 :0] rst_icache_inv;
reg [1 :0] rst_icache_inv_nxt;
reg wa;
reg wb;
// &Wires; @26
wire [1 :0] amr;
wire bht_inv_req;
wire bht_rst_inv_req;
wire [2 :0] clk_ratio;
wire cp0_biu_icg_en;
wire cp0_dtu_icg_en;
wire cp0_dtu_pcfifo_frz;
wire cp0_fpu_icg_en;
wire cp0_hpcp_icg_en;
wire cp0_idu_icg_en;
wire cp0_idu_spec_push_en;
wire cp0_idu_swap_sp_en;
wire cp0_ifu_bht_en;
wire cp0_ifu_bht_inv;
wire cp0_ifu_btb_clr;
wire cp0_ifu_btb_en;
wire cp0_ifu_icache_en;
wire [31:0] cp0_ifu_icache_inv_addr;
wire cp0_ifu_icache_inv_req;
wire cp0_ifu_icache_inv_type;
wire cp0_ifu_icg_en;
wire cp0_ifu_ras_en;
wire cp0_ifu_rst_inv_done;
wire cp0_iu_icg_en;
wire cp0_lsu_dcache_en;
wire cp0_lsu_dcache_wa;
wire cp0_lsu_dcache_wb;
wire [31:0] cp0_lsu_icc_addr;
wire [1 :0] cp0_lsu_icc_op;
wire cp0_lsu_icc_req;
wire [1 :0] cp0_lsu_icc_type;
wire cp0_lsu_icg_en;
wire cp0_pmp_icg_en;
wire cp0_rtu_icg_en;
wire cp0_rtu_in_expt;
wire cp0_rtu_wfe_en;
wire cp0_xx_async_expt_en;
wire cpurst_b;
wire [1 :0] dcache_pref_dist;
wire dcache_pref_en;
wire dcache_rst_inv_req;
wire ext_ifu_inv_done;
wire [31:0] ext_inst_ifu_icc_addr;
wire ext_inst_ifu_icc_req;
wire ext_inst_ifu_icc_type;
wire ext_inst_ifu_inv_done;
wire [31:0] ext_inst_lsu_icc_addr;
wire ext_inst_lsu_icc_done;
wire [1 :0] ext_inst_lsu_icc_op;
wire ext_inst_lsu_icc_req;
wire [1 :0] ext_inst_lsu_icc_type;
wire forever_cpuclk;
wire icache_inv_req;
wire icache_rst_inv_req;
wire ifu_cp0_bht_inv_done;
wire ifu_cp0_icache_inv_done;
wire ifu_cp0_rst_inv_req;
wire inst_dcache_op;
wire inst_icache_op;
wire inv_sm_clk;
wire inv_sm_clk_en;
wire iui_regs_inst_mret;
wire [31:0] iui_regs_wdata;
wire [1 :0] iui_regs_wdata_srst;
wire lsu_cp0_icc_done;
wire mexstatus_local_en;
wire [31:0] mexstatus_value;
wire mhcr_local_en;
wire [31:0] mhcr_value;
wire mhint2_local_en;
wire [31:0] mhint2_value;
wire mhint_local_en;
wire [31:0] mhint_value;
wire [31:0] mraddr_value;
wire pad_yy_icg_scan_en;
wire regs_clk;
wire regs_cpu_in_int;
wire regs_cpu_in_nmi;
wire regs_doing_inv;
wire regs_flush_clk;
wire [1 :0] regs_special_lpmd;
wire regs_spswap_en;
wire regs_srst_srst_vld;
wire [1 :0] regs_srst_srstmd;
wire rst_inv_done;
wire rst_top_op_done;
wire [1 :0] rstmd_in;
wire rtu_cp0_bus_error;
wire rtu_cp0_lockup_clr;
wire rtu_cp0_lockup_vld;
wire rtu_cp0_nmi_vld;
wire rtu_yy_xx_dbgon;
wire rtu_yy_xx_expt_int;
wire rtu_yy_xx_expt_vld;
wire special_dcache_clean;
wire special_icache_inv;
wire special_icache_inv_done;
wire special_regs_clk_en;
wire special_regs_inv_sm_clk_en;
wire srst_vld;
wire [2 :0] sysio_cp0_clkratio;
wire [31:0] sysio_cp0_rst_addr;
// &Force("bus", "iui_regs_wdata", 31, 0); @28
//==========================================================
// Define the MHCR register
// Machine Hardwire Control Register
// 32-bit Machine Mode Read/Write
// the definiton for MHSR register is listed as follows
//==========================================================
assign clk_ratio[2:0] = sysio_cp0_clkratio[2:0];
always @ (posedge regs_clk or negedge cpurst_b)
begin
if (!cpurst_b) begin
l0btb <= 1'b0;
bpe <= 1'b0;
rs <= 1'b0;
end
else if (mhcr_local_en) begin
l0btb <= iui_regs_wdata[12];
bpe <= iui_regs_wdata[5];
rs <= iui_regs_wdata[4];
end
else begin
l0btb <= l0btb;
bpe <= bpe;
rs <= rs;
end
end
always @ (posedge regs_clk or negedge cpurst_b)
begin
if (!cpurst_b) begin
wa <= 1'b0;
wb <= 1'b0;
de <= 1'b0;
end
else if (mhcr_local_en) begin
wa <= iui_regs_wdata[3];
wb <= iui_regs_wdata[2];
de <= iui_regs_wdata[1];
end
else begin
wa <= wa;
wb <= wb;
de <= de;
end
end
always @ (posedge regs_clk or negedge cpurst_b)
begin
if (!cpurst_b)
ie <= 1'b0;
else if (mhcr_local_en)
ie <= iui_regs_wdata[0];
else
ie <= ie;
end
assign mhcr_value[31:0] = {13'b0, clk_ratio[2:0], 3'b0, l0btb, // [31:12]
6'b0, bpe, rs, wa, wb, de, ie}; // [11:0]
//==========================================================
// Define the MHINT register
// Machine Register
// 32-bit Machine Mode Read/Write
// the definiton for MHSR register is listed as follows
//==========================================================
always @ (posedge regs_clk or negedge cpurst_b)
begin
if (!cpurst_b) begin
mhint_aee <= 1'b0;
end
else if (mhint_local_en) begin
mhint_aee <= iui_regs_wdata[20];
end
else begin
mhint_aee <= mhint_aee;
end
end
assign dcache_pref_dist[1:0] = 2'b0;
assign amr[1:0] = 2'b0;
assign dcache_pref_en = 1'b0;
assign mhint_value[31:0] = {7'b0,pcfifo_freeze,3'b0, mhint_aee,5'b0,dcache_pref_dist[1:0],8'b0,amr[1:0], dcache_pref_en, 2'b0};
always @(posedge regs_clk or negedge cpurst_b)
begin
if(!cpurst_b)
pcfifo_freeze <= 1'b0;
else if(mhint_local_en)
pcfifo_freeze <= iui_regs_wdata[24];
else
pcfifo_freeze <= pcfifo_freeze;
end
always @(posedge regs_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
module_icg_en[8:0] <= 9'b0;
end
else if(mhint2_local_en) begin
module_icg_en[8:0] <= iui_regs_wdata[22:14];
end
else begin
module_icg_en[8:0] <= module_icg_en[8:0];
end
end
assign mhint2_value[31:0] = {9'b0,
module_icg_en[8:0], 14'b0};
//for ifu control
assign cp0_ifu_icg_en = module_icg_en[0];
assign cp0_idu_icg_en = module_icg_en[1];
assign cp0_iu_icg_en = module_icg_en[2];
assign cp0_hpcp_icg_en = module_icg_en[2];
assign cp0_lsu_icg_en = module_icg_en[3];
assign cp0_pmp_icg_en = module_icg_en[4];
assign cp0_biu_icg_en = module_icg_en[5];
assign cp0_rtu_icg_en = module_icg_en[6];
assign cp0_fpu_icg_en = module_icg_en[7];
assign cp0_dtu_icg_en = module_icg_en[8];
//==========================================================
// Define the MRADDR register
// Machine Register
// 32-bit Machine Mode Read/Write
// the definiton for MRADDR register is listed as follows
//==========================================================
assign mraddr_value[31:0] = sysio_cp0_rst_addr[31:0];
//==========================================================
// Define the MEXSTATUS register
// Machine Register
// 32-bit Machine Mode Read/Write
// the definiton for MEXSTATUS register is listed as follows
//==========================================================
assign rstmd_in[1:0] = &iui_regs_wdata_srst[1:0] ? 2'b0 : iui_regs_wdata_srst[1:0];
// Use individed signal to opt timing.
always @ (posedge regs_clk or negedge cpurst_b)
begin
if (!cpurst_b) begin
mexstatus_rstmd[1:0] <= 2'b0;
mexstatus_lpmd[1:0] <= 2'b0;
mexstatus_wfeen <= 1'b1;
end
else if (mexstatus_local_en) begin
mexstatus_rstmd[1:0] <= rstmd_in[1:0];
mexstatus_lpmd[1:0] <= {1'b0, iui_regs_wdata[2]};
mexstatus_wfeen <= iui_regs_wdata[4];
end
end
assign srst_vld = mexstatus_local_en && |rstmd_in[1:0];
always @ (posedge regs_clk or negedge cpurst_b)
begin
if (!cpurst_b) begin
mexstatus_spushen <= 1'b0;
mexstatus_spswapen <= 1'b0;
end
else if (mexstatus_local_en) begin
mexstatus_spushen <= iui_regs_wdata[16];
mexstatus_spswapen <= iui_regs_wdata[17];
end
end
always @ (posedge regs_flush_clk or negedge cpurst_b)
begin
if (!cpurst_b)
mexstatus_expt <= 1'b0;
else if (mexstatus_local_en && rtu_yy_xx_dbgon)
mexstatus_expt <= iui_regs_wdata[5];
else if (rtu_cp0_lockup_clr)
mexstatus_expt <= 1'b0;
else if (rtu_yy_xx_expt_vld && !rtu_yy_xx_expt_int && !rtu_cp0_nmi_vld)
mexstatus_expt <= 1'b1;
else if (iui_regs_inst_mret && !mexstatus_nmi && !regs_cpu_in_int)
mexstatus_expt <= 1'b0;
end
always @ (posedge regs_flush_clk or negedge cpurst_b)
begin
if (!cpurst_b)
mexstatus_nmi <= 1'b0;
else if (mexstatus_local_en && rtu_yy_xx_dbgon)
mexstatus_nmi <= iui_regs_wdata[7];
else if (rtu_cp0_lockup_clr)
mexstatus_nmi <= 1'b0;
else if (rtu_cp0_nmi_vld)
mexstatus_nmi <= 1'b1;
else if (iui_regs_inst_mret)
mexstatus_nmi <= 1'b0;
end
always @ (posedge regs_flush_clk or negedge cpurst_b)
begin
if (!cpurst_b)
mexstatus_bus_err <= 1'b0;
else if (rtu_yy_xx_expt_vld && !rtu_yy_xx_expt_int)
mexstatus_bus_err <= rtu_cp0_bus_error;
else if (mexstatus_local_en)
mexstatus_bus_err <= iui_regs_wdata[8];
end
always @ (posedge regs_flush_clk or negedge cpurst_b)
begin
if (!cpurst_b)
mexstatus_lockup <= 1'b0;
else if (rtu_cp0_lockup_clr)
mexstatus_lockup <= 1'b0;
else if (rtu_cp0_lockup_vld)
mexstatus_lockup <= 1'b1;
end
assign mexstatus_value[31:0] = {14'b0, mexstatus_spswapen, mexstatus_spushen,
7'b0, mexstatus_bus_err, mexstatus_nmi, mexstatus_lockup, mexstatus_expt,
mexstatus_wfeen, mexstatus_lpmd[1:0], mexstatus_rstmd[1:0]};
// MNMICAUSE, MNMIPC is in trap_csr.
//==========================================================
// CP0 Extension CSR Module
//==========================================================
assign inv_sm_clk_en = regs_doing_inv
|| special_regs_inv_sm_clk_en
|| inst_dcache_op
|| icache_inv_req;
// &Instance("gated_clk_cell", "x_inv_sm_gated_clk"); @307
gated_clk_cell x_inv_sm_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (inv_sm_clk ),
.external_en (1'b0 ),
.global_en (special_regs_clk_en),
.local_en (1'b0 ),
.module_en (inv_sm_clk_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk), @308
// .external_en (1'b0), @309
// .global_en (special_regs_clk_en), @310
// .module_en (inv_sm_clk_en), @311
// .local_en (1'b0), @312
// .clk_out (inv_sm_clk)); @313
// &Force("output", "inv_sm_clk"); @314
parameter RST_IDLE = 2'b00;
parameter RST_WFC = 2'b01;
parameter RST_DONE = 2'b10;
//==========================================================
// FSM of reset cache inv cctl logic
//==========================================================
always @(posedge inv_sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
rst_cache_inv[1:0] <= RST_IDLE;
else
rst_cache_inv[1:0] <= rst_cache_inv_nxt[1:0];
end
// &CombBeg; @330
always @( rst_cache_inv
or rst_inv_done
or ifu_cp0_rst_inv_req)
begin
case(rst_cache_inv)
RST_IDLE:
begin
if(ifu_cp0_rst_inv_req)
rst_cache_inv_nxt[1:0] = RST_WFC;
else
rst_cache_inv_nxt[1:0] = RST_IDLE;
end
RST_WFC:
begin
if(rst_inv_done)
rst_cache_inv_nxt[1:0] = RST_IDLE;
else
rst_cache_inv_nxt[1:0] = RST_WFC;
end
default:
begin
rst_cache_inv_nxt[1:0] = RST_IDLE;
end
endcase
// &CombEnd; @351
end
assign rst_inv_done = rst_icache_inv[1:0] == RST_IDLE &&
rst_dcache_inv[1:0] == RST_IDLE &&
rst_bht_inv[1:0] == RST_IDLE;
assign cp0_ifu_rst_inv_done = rst_cache_inv[1:0] == RST_IDLE && !ifu_cp0_rst_inv_req;
//==========================================================
// ICache Operation
//==========================================================
assign inst_icache_op = ext_inst_ifu_icc_req
|| special_icache_inv;
assign icache_inv_req = (ifu_cp0_rst_inv_req | inst_icache_op) & (rst_bht_inv[1:0] == RST_IDLE);
always @(posedge inv_sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
rst_icache_inv[1:0] <= RST_IDLE;
else
rst_icache_inv[1:0] <= rst_icache_inv_nxt[1:0];
end
// &CombBeg; @374
always @( rst_icache_inv
or ext_ifu_inv_done
or ifu_cp0_icache_inv_done
or icache_inv_req)
begin
case(rst_icache_inv)
RST_IDLE:
begin
if(icache_inv_req)
rst_icache_inv_nxt[1:0] = RST_WFC;
else
rst_icache_inv_nxt[1:0] = RST_IDLE;
end
RST_WFC:
begin
if(ifu_cp0_icache_inv_done)
rst_icache_inv_nxt[1:0] = RST_DONE;
else
rst_icache_inv_nxt[1:0] = RST_WFC;
end
RST_DONE:
if (ext_ifu_inv_done)
rst_icache_inv_nxt[1:0] = RST_IDLE;
else
rst_icache_inv_nxt[1:0] = RST_DONE;
default:
begin
rst_icache_inv_nxt[1:0] = RST_IDLE;
end
endcase
// &CombEnd; @400
end
//assign icache_sm_idle = rst_icache_inv[1:0] == RST_IDLE;
//assign icache_sm_done = rst_icache_inv[1:0] == RST_DONE;
//assign icache_op_done = icache_sm_idle & ~icache_inv_req |
// icache_sm_done;
assign bht_inv_req = (ifu_cp0_rst_inv_req | inst_icache_op) & (rst_icache_inv[1:0] == RST_IDLE);
always @(posedge inv_sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
rst_bht_inv[1:0] <= RST_IDLE;
else
rst_bht_inv[1:0] <= rst_bht_inv_nxt[1:0];
end
// &CombBeg; @417
always @( bht_inv_req
or ext_ifu_inv_done
or ifu_cp0_bht_inv_done
or rst_bht_inv)
begin
case(rst_bht_inv)
RST_IDLE:
begin
if(bht_inv_req)
rst_bht_inv_nxt[1:0] = RST_WFC;
else
rst_bht_inv_nxt[1:0] = RST_IDLE;
end
RST_WFC:
begin
if(ifu_cp0_bht_inv_done)
rst_bht_inv_nxt[1:0] = RST_DONE;
else
rst_bht_inv_nxt[1:0] = RST_WFC;
end
RST_DONE:
if (ext_ifu_inv_done)
rst_bht_inv_nxt[1:0] = RST_IDLE;
else
rst_bht_inv_nxt[1:0] = RST_DONE;
default:
begin
rst_bht_inv_nxt[1:0] = RST_IDLE;
end
endcase
// &CombEnd; @443
end
//assign bht_sm_idle = rst_bht_inv[1:0] == RST_IDLE;
//assign bht_sm_done = rst_bht_inv[1:0] == RST_DONE;
//assign bht_op_done = bht_sm_idle & ~bht_inv_req |
// bht_sm_done;
//==========================================================
// DCache Operation
//==========================================================
assign inst_dcache_op = ext_inst_lsu_icc_req
|| special_dcache_clean;
always @(posedge inv_sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
rst_dcache_inv[1:0] <= RST_IDLE;
else
rst_dcache_inv[1:0] <= rst_dcache_inv_nxt[1:0];
end
// &CombBeg; @462
always @( inst_dcache_op
or rst_dcache_inv
or ifu_cp0_rst_inv_req
or lsu_cp0_icc_done)
begin
case(rst_dcache_inv)
RST_IDLE:
begin
if(ifu_cp0_rst_inv_req)
rst_dcache_inv_nxt[1:0] = RST_WFC;
else if (inst_dcache_op)
rst_dcache_inv_nxt[1:0] = RST_WFC;
else
rst_dcache_inv_nxt[1:0] = RST_IDLE;
end
RST_WFC:
begin
if(lsu_cp0_icc_done)
rst_dcache_inv_nxt[1:0] = RST_DONE;
else
rst_dcache_inv_nxt[1:0] = RST_WFC;
end
RST_DONE:
rst_dcache_inv_nxt[1:0] = RST_IDLE;
default:
begin
rst_dcache_inv_nxt[1:0] = RST_IDLE;
end
endcase
// &CombEnd; @487
end
//assign dcache_sm_idle = rst_dcache_inv[1:0] == RST_IDLE;
//assign dcache_sm_done = rst_dcache_inv[1:0] == RST_DONE;
//assign dcache_op_done = dcache_sm_idle & ~dcache_inv_req |
// dcache_sm_done;
assign regs_doing_inv = ifu_cp0_rst_inv_req
|| !rst_inv_done
|| rst_dcache_inv[1:0] != RST_IDLE
|| rst_icache_inv[1:0] != RST_IDLE
|| rst_bht_inv[1:0] != RST_IDLE
|| rst_cache_inv[1:0] != RST_IDLE;
assign ext_ifu_inv_done = rst_bht_inv[1:0] == RST_DONE
&& rst_icache_inv[1:0] == RST_DONE;
assign ext_inst_ifu_inv_done = ext_ifu_inv_done;
assign special_icache_inv_done = ext_ifu_inv_done;
assign ext_inst_lsu_icc_done = rst_dcache_inv[1:0] == RST_WFC && lsu_cp0_icc_done
|| rst_dcache_inv[1:0] == RST_IDLE && !inst_dcache_op;
assign icache_rst_inv_req = rst_icache_inv[1:0] == RST_WFC;
assign bht_rst_inv_req = rst_bht_inv[1:0] == RST_WFC;
assign dcache_rst_inv_req = rst_dcache_inv[1:0] == RST_WFC;
assign cp0_lsu_icc_req = dcache_rst_inv_req;
assign cp0_lsu_icc_type[1:0] = ext_inst_lsu_icc_req ? ext_inst_lsu_icc_type[1:0]
: 2'b0;
assign cp0_lsu_icc_addr[31:0] = ext_inst_lsu_icc_req ? ext_inst_lsu_icc_addr[31:0]
: 32'b0;
assign cp0_lsu_icc_op[1:0] = ext_inst_lsu_icc_req ? ext_inst_lsu_icc_op[1:0]
: special_dcache_clean ? 2'b10 // Clean Dcache
: 2'b01; // Inv Dcache
assign cp0_ifu_btb_clr = 1'b0;
assign cp0_ifu_btb_en = l0btb;
assign cp0_ifu_bht_inv = bht_rst_inv_req;
assign cp0_ifu_bht_en = bpe;
assign cp0_ifu_ras_en = rs;
// &Force("nonport", "cp0_ifu_btb_clr"); @531
// &Force("nonport", "cp0_ifu_btb_en"); @532
// &Force("nonport", "cp0_ifu_bht_inv"); @537
// &Force("nonport", "cp0_ifu_bht_en"); @538
// &Force("nonport", "cp0_ifu_ras_en"); @543
//==========================================================
// Rename for Output
//==========================================================
// Output to LSU
assign cp0_lsu_dcache_en = de;
assign cp0_lsu_dcache_wb = wb;
assign cp0_lsu_dcache_wa = wa;
assign cp0_ifu_icache_en = ie;
assign cp0_ifu_icache_inv_req = icache_rst_inv_req;
assign cp0_ifu_icache_inv_type = ext_inst_ifu_icc_req ? ext_inst_ifu_icc_type
: 1'b0;
assign cp0_ifu_icache_inv_addr[31:0] = ext_inst_ifu_icc_addr[31:0];
// &Force("nonport", "icache_rst_inv_req"); @572
// AEE means Accurated Expt, So Async Expt is !mhint_aee.
assign cp0_xx_async_expt_en = !mhint_aee;
//==========================================================
// Output for CP0
//==========================================================
assign regs_special_lpmd[1:0] = mexstatus_lpmd[1:0];
assign regs_srst_srstmd[1:0] = mexstatus_rstmd[1:0];
assign regs_srst_srst_vld = srst_vld;
assign regs_spswap_en = mexstatus_spswapen;
assign regs_cpu_in_nmi = mexstatus_nmi;
//==========================================================
// Output for RTU
//==========================================================
assign cp0_rtu_wfe_en = mexstatus_wfeen;
assign cp0_rtu_in_expt = mexstatus_expt;
//==========================================================
// Output for IDU
//==========================================================
assign cp0_idu_spec_push_en = mexstatus_spushen;
assign cp0_idu_swap_sp_en = mexstatus_spswapen;
//output to dbg infor
assign rst_top_op_done = rst_inv_done;
//----------------------------------------------------------
// For DTU
//----------------------------------------------------------
//assign cp0_dtu_icg_en = module_icg_en[8];
assign cp0_dtu_pcfifo_frz = pcfifo_freeze;
// &ModuleEnd; @607
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_cp0_ext_inst(
ext_inst_ifu_icc_addr,
ext_inst_ifu_icc_req,
ext_inst_ifu_icc_type,
ext_inst_ifu_inv_done,
ext_inst_lsu_icc_addr,
ext_inst_lsu_icc_done,
ext_inst_lsu_icc_op,
ext_inst_lsu_icc_req,
ext_inst_lsu_icc_type,
ext_iui_cache_stall,
ext_iui_expt_vld,
iui_ext_inst_cache,
iui_ext_inst_imm,
iui_ext_inst_rs1
);
// &Ports; @24
input ext_inst_ifu_inv_done;
input ext_inst_lsu_icc_done;
input iui_ext_inst_cache;
input [11:0] iui_ext_inst_imm;
input [31:0] iui_ext_inst_rs1;
output [31:0] ext_inst_ifu_icc_addr;
output ext_inst_ifu_icc_req;
output ext_inst_ifu_icc_type;
output [31:0] ext_inst_lsu_icc_addr;
output [1 :0] ext_inst_lsu_icc_op;
output ext_inst_lsu_icc_req;
output [1 :0] ext_inst_lsu_icc_type;
output ext_iui_cache_stall;
output ext_iui_expt_vld;
// &Regs; @25
reg [1 :0] inst_dst;
reg [1 :0] inst_type;
// &Wires; @26
wire cache_inst_illegal;
wire [1 :0] cache_inst_op;
wire cache_inst_rs1;
wire [2 :0] cache_inst_type;
wire [31:0] ext_inst_ifu_icc_addr;
wire ext_inst_ifu_icc_req;
wire ext_inst_ifu_icc_type;
wire ext_inst_ifu_inv_done;
wire [31:0] ext_inst_lsu_icc_addr;
wire ext_inst_lsu_icc_done;
wire [1 :0] ext_inst_lsu_icc_op;
wire ext_inst_lsu_icc_req;
wire [1 :0] ext_inst_lsu_icc_type;
wire ext_iui_cache_stall;
wire ext_iui_expt_vld;
wire iui_ext_inst_cache;
wire [11:0] iui_ext_inst_imm;
wire [31:0] iui_ext_inst_rs1;
parameter CPU_MODE_U = 2'b00;
parameter NOP = 2'b00,
DCHE = 2'b01,
ICHE = 2'b10;
parameter CACHE_ALL = 2'b0,
CACHE_SETWAY = 2'b01,
CACHE_PA = 2'b10;
//==========================================================
// Cache Inst Decode
//==========================================================
assign cache_inst_op[1:0] = iui_ext_inst_imm[1:0];
assign cache_inst_type[2:0] = iui_ext_inst_imm[4:2];
assign cache_inst_rs1 = iui_ext_inst_imm[5];
// &Force("bus", "iui_ext_inst_imm", 11, 0); @44
// &CombBeg; @46
always @( cache_inst_rs1
or cache_inst_type[2:0])
begin
case({cache_inst_rs1, cache_inst_type[2:0]})
4'b0_000: begin
inst_dst[1:0] = DCHE;
inst_type[1:0] = CACHE_ALL;
end
4'b1_000: begin
inst_dst[1:0] = DCHE;
inst_type[1:0] = CACHE_SETWAY;
end
4'b1_001: begin
inst_dst[1:0] = NOP;
inst_type[1:0] = CACHE_ALL;
end
4'b1_010: begin
inst_dst[1:0] = DCHE;
inst_type[1:0] = CACHE_PA;
end
4'b0_100: begin
inst_dst[1:0] = ICHE;
inst_type[1:0] = CACHE_ALL;
end
4'b1_110: begin
inst_dst[1:0] = ICHE;
inst_type[1:0] = CACHE_PA;
end
4'b1_100: begin
inst_dst[1:0] = NOP;
inst_type[1:0] = CACHE_ALL;
end
4'b0_101: begin
inst_dst[1:0] = NOP;
inst_type[1:0] = CACHE_ALL;
end
default: begin
inst_dst[1:0] = NOP;
inst_type[1:0] = CACHE_ALL;
end
endcase
// &CombEnd; @85
end
// assign cache_inst_illegal = cp0_yy_priv_mode[1:0] == CPU_MODE_U;
assign cache_inst_illegal = 1'b0; // Now illegal judge is in ID.
assign ext_iui_expt_vld = cache_inst_illegal;
assign ext_iui_cache_stall = inst_dst[1] && !ext_inst_ifu_inv_done
|| inst_dst[0] && !ext_inst_lsu_icc_done;
//==========================================================
// Dcache inst
//==========================================================
assign ext_inst_lsu_icc_req = iui_ext_inst_cache && inst_dst[0] && !cache_inst_illegal;
assign ext_inst_lsu_icc_type[1:0] = inst_type[1:0];
assign ext_inst_lsu_icc_op[1:0] = {cache_inst_op[0], cache_inst_op[1]};
assign ext_inst_lsu_icc_addr[31:0] = iui_ext_inst_rs1[31:0];
//==========================================================
// Icache inst
//==========================================================
assign ext_inst_ifu_icc_req = iui_ext_inst_cache && inst_dst[1] && !cache_inst_illegal;
assign ext_inst_ifu_icc_type = inst_type[1];
assign ext_inst_ifu_icc_addr[31:0] = iui_ext_inst_rs1[31:0];
// &ModuleEnd; @111
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_cp0_float_csr(
cp0_fpu_xx_dqnan,
cp0_fpu_xx_rm,
cp0_idu_rm,
cpurst_b,
fcsr_local_en,
fcsr_value,
fflags_clk,
fflags_local_en,
fflags_value,
fpu_cp0_fflags_updt,
fpu_cp0_wb_fflags,
fpu_cp0_wb_fflags_updt,
frm_local_en,
frm_value,
fxcr_local_en,
fxcr_value,
iui_regs_wdata,
regs_clk
);
// &Ports; @24
input cpurst_b;
input fcsr_local_en;
input fflags_clk;
input fflags_local_en;
input [4 :0] fpu_cp0_wb_fflags;
input fpu_cp0_wb_fflags_updt;
input frm_local_en;
input fxcr_local_en;
input [31:0] iui_regs_wdata;
input regs_clk;
output cp0_fpu_xx_dqnan;
output [2 :0] cp0_fpu_xx_rm;
output [2 :0] cp0_idu_rm;
output [31:0] fcsr_value;
output [31:0] fflags_value;
output fpu_cp0_fflags_updt;
output [31:0] frm_value;
output [31:0] fxcr_value;
// &Regs; @25
reg [4 :0] fcsr_fflags;
reg [2 :0] fcsr_frm;
reg fxcr_dqnan;
reg fxcr_fe;
// &Wires; @26
wire cp0_fpu_xx_dqnan;
wire [2 :0] cp0_fpu_xx_rm;
wire [2 :0] cp0_idu_rm;
wire cpurst_b;
wire fcsr_local_en;
wire [31:0] fcsr_value;
wire fflags_clk;
wire fflags_local_en;
wire [31:0] fflags_value;
wire [4 :0] fpu_cp0_fflags;
wire fpu_cp0_fflags_updt;
wire [4 :0] fpu_cp0_wb_fflags;
wire fpu_cp0_wb_fflags_updt;
wire frm_local_en;
wire [31:0] frm_value;
wire fxcr_local_en;
wire [31:0] fxcr_value;
wire [31:0] iui_regs_wdata;
wire regs_clk;
// &Force("bus", "iui_regs_wdata", 31, 0); @28
always @ (posedge regs_clk or negedge cpurst_b)
begin
if (!cpurst_b) begin
fcsr_frm[2:0] <= 3'b0;
end
else if (fcsr_local_en) begin
fcsr_frm[2:0] <= iui_regs_wdata[7:5];
end
else if (frm_local_en) begin
fcsr_frm[2:0] <= iui_regs_wdata[2:0];
end
else if (fxcr_local_en) begin
fcsr_frm[2:0] <= iui_regs_wdata[26:24];
end
else begin
fcsr_frm[2:0] <= fcsr_frm[2:0];
end
end
assign frm_value[31:0] = {29'b0, fcsr_frm[2:0]};
always @ (posedge fflags_clk or negedge cpurst_b)
begin
if (!cpurst_b) begin
fcsr_fflags[4:0] <= 5'b0;
end
else if (fcsr_local_en) begin
fcsr_fflags[4:0] <= iui_regs_wdata[4:0];
end
else if (fflags_local_en) begin
fcsr_fflags[4:0] <= iui_regs_wdata[4:0];
end
else if (fxcr_local_en) begin
fcsr_fflags[4:0] <= iui_regs_wdata[4:0];
end
else if (fpu_cp0_fflags_updt) begin
fcsr_fflags[4:0] <= fcsr_fflags[4:0] | fpu_cp0_fflags[4:0];
end
else begin
fcsr_fflags[4:0] <= fcsr_fflags[4:0];
end
end
assign fpu_cp0_fflags_updt = fpu_cp0_wb_fflags_updt;
// &Force("output","fpu_cp0_fflags_updt"); @74
assign fpu_cp0_fflags[4:0] = fpu_cp0_wb_fflags[4:0];
assign fflags_value[31:0] = {27'b0, fcsr_fflags[4:0]};
assign fcsr_value[31:0] = {24'b0, fcsr_frm[2:0], fcsr_fflags[4:0]};
always @ (posedge fflags_clk or negedge cpurst_b)
begin
if (!cpurst_b)
fxcr_fe <= 1'b0;
else if (fxcr_local_en)
fxcr_fe <= iui_regs_wdata[5];
else if (fpu_cp0_fflags_updt)
fxcr_fe <= fxcr_fe || (|fpu_cp0_fflags[4:0]);
else
fxcr_fe <= fxcr_fe;
end
always @ (posedge regs_clk or negedge cpurst_b)
begin
if (!cpurst_b)
fxcr_dqnan <= 1'b0;
else if (fxcr_local_en)
fxcr_dqnan <= iui_regs_wdata[23];
else
fxcr_dqnan <= fxcr_dqnan;
end
assign fxcr_value[31:0] = {5'b0, fcsr_frm[2:0], fxcr_dqnan, 17'b0, fxcr_fe, fcsr_fflags[4:0]};
//==========================================================
// Output Signal
//==========================================================
assign cp0_fpu_xx_rm[2:0] = fcsr_frm[2:0];
assign cp0_fpu_xx_dqnan = fxcr_dqnan;
assign cp0_idu_rm[2:0] = fcsr_frm[2:0];
// &ModuleEnd; @113
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_cp0_info_csr(
cpurst_b,
iui_regs_inst_csr,
marchid_value,
mcpuid_local_en,
mcpuid_value,
mhartid_value,
mimpid_value,
mvendorid_value,
regs_clk
);
// &Ports; @24
input cpurst_b;
input iui_regs_inst_csr;
input mcpuid_local_en;
input regs_clk;
output [31:0] marchid_value;
output [31:0] mcpuid_value;
output [31:0] mhartid_value;
output [31:0] mimpid_value;
output [31:0] mvendorid_value;
// &Regs; @25
reg [31:0] cpuid_value;
reg [1 :0] index;
// &Wires; @26
wire [31:0] cpuid_index0_value;
wire [31:0] cpuid_index1_value;
wire [31:0] cpuid_index2_value;
wire cpurst_b;
wire index_max;
wire [1 :0] index_next_val;
wire iui_regs_inst_csr;
wire [31:0] marchid_value;
wire mcpuid_local_en;
wire [31:0] mcpuid_value;
wire [31:0] mhartid_value;
wire [31:0] mimpid_value;
wire [31:0] mvendorid_value;
wire regs_clk;
//==========================================================
// Machine Information CSR Module
// 1. RISC-V Priviledge 1.11 Information Group
// 2. RISC-V Priviledge 1.11 Basic Counters
// 3. T-Head CPU Information Extension
//==========================================================
//----------------------------------------------------------
// 1. RISC-V Priviledge 1.11 Information Group
//----------------------------------------------------------
//==========================================================
// Define the MVENDORID Register
//==========================================================
// Machine Vendor ID Register
// 32-bit readonly
// Providing the JEDEC ID of T-Head
//==========================================================
assign mvendorid_value[31:0] = 32'h5B7;
//==========================================================
// Define the MARCHID Register
//==========================================================
// Machine Architecture ID Register
// 32-bit readonly
// *Currently not implemented, need to be defined
//==========================================================
assign marchid_value[31:0] = 32'b0;
//==========================================================
// Define the MIMPID Register
//==========================================================
// Machine Implementation ID Register
// 32-bit readonly
// Providing the implementation ID of the version of core
// *Currently not implemented, need to be defined
//==========================================================
assign mimpid_value[31:0] = 32'b0;
//==========================================================
// Define the MHARTID Register
//==========================================================
// Machine Hart ID Register
// 32-bit readonly
// Providing the Hart ID of the current core
// For single core only, fix to 32'b0
//==========================================================
assign mhartid_value[31:0] = 32'b0;
//----------------------------------------------------------
// 2. RISC-V Priviledge 1.11 Basic Counters
//----------------------------------------------------------
// mcycle, minstret now in HPCP.
//----------------------------------------------------------
// 3. T-Head CPU Information Extension
//----------------------------------------------------------
//==========================================================
// Define the cpuid register
//==========================================================
//----------------------------------------------------------
// Index Register
//----------------------------------------------------------
assign index_max = (index[1:0] == 2'd2);
assign index_next_val[1:0] = (index_max) ? 2'd0
: index[1:0] + 2'd1;
always @(posedge regs_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
index[1:0] <= 2'b0;
end
else if (iui_regs_inst_csr && mcpuid_local_en)
begin
index[1:0] <= index_next_val[1:0];
end
else
begin
index[1:0] <= index[1:0];
end
end
//----------------------------------------------------------
// Implement of cpuid register
//----------------------------------------------------------
// &CombBeg; @115
always @( cpuid_index1_value[31:0]
or cpuid_index0_value[31:0]
or index[1:0]
or cpuid_index2_value[31:0])
begin
case(index[1:0])
2'b00 : cpuid_value[31:0] = cpuid_index0_value[31:0];
2'b01 : cpuid_value[31:0] = cpuid_index1_value[31:0];
2'b10 : cpuid_value[31:0] = cpuid_index2_value[31:0];
default : cpuid_value[31:0] = {32{1'bx}};
endcase
// &CombEnd; @122
end
//---------------------------------------------------------
// Index 0
//---------------------------------------------------------
assign cpuid_index0_value[31:28] = 4'b0000;
//------------------------------------------------
// Arch
//------------------------------------------------
assign cpuid_index0_value[27:26] = 2'b10; // CSKY V3 instruction set
//------------------------------------------------
// Family
//------------------------------------------------
assign cpuid_index0_value[25:22] = 4'b0000; // E Series
//------------------------------------------------
// Class
//------------------------------------------------
assign cpuid_index0_value[21:18] = 4'b0100; // E906
//------------------------------------------------
// Model
//------------------------------------------------
assign cpuid_index0_value[17:11] = 7'b0;
assign cpuid_index0_value[9] = 1'b0;
assign cpuid_index0_value[8] = 1'b1;
assign cpuid_index0_value[10] = 1'b0;
//------------------------------------------------
// ISA Revision
//------------------------------------------------
assign cpuid_index0_value[7:3] = 5'b00001;
//------------------------------------------------
// Version
//------------------------------------------------
assign cpuid_index0_value[2:0] = 3'b101; //CPID Rev.5
//---------------------------------------------------------
// Index 1
//---------------------------------------------------------
assign cpuid_index1_value[31:28] = 4'b0001;
//------------------------------------------------
// Revision
//------------------------------------------------
assign cpuid_index1_value[27:24] = `REVISION;
//------------------------------------------------
// Sub Revision
//------------------------------------------------
assign cpuid_index1_value[23:18] = `SUB_VERSION;
//------------------------------------------------
// Patch
//------------------------------------------------
assign cpuid_index1_value[17:12] = `PATCH;
//------------------------------------------------
// PRODUCT ID
//------------------------------------------------
assign cpuid_index1_value[11:0] = `PRODUCT_ID;
//------------------------------------------------
// Index 2
//------------------------------------------------
assign cpuid_index2_value[31:28] = 4'b0010;
//------------------------------------------------
// IBUS
//------------------------------------------------
assign cpuid_index2_value[27:26] = 2'b01;
//------------------------------------------------
// DBUS
//------------------------------------------------
assign cpuid_index2_value[25:24] = 2'b01;
//------------------------------------------------
// SBUS
//------------------------------------------------
assign cpuid_index2_value[23:21] = 3'b001;
//------------------------------------------------
// BTB
//------------------------------------------------
assign cpuid_index2_value[20:19] = 2'b01;
//------------------------------------------------
// BHT
//------------------------------------------------
assign cpuid_index2_value[18:16] = 3'b011;
//------------------------------------------------
// INTC
//------------------------------------------------
assign cpuid_index2_value[15:12] = 4'b1111;
//------------------------------------------------
// DCACHE Todo
//------------------------------------------------
assign cpuid_index2_value[11:9] = 3'b100;
//------------------------------------------------
// ICACHE
//------------------------------------------------
assign cpuid_index2_value[8:6] = 3'b100;
//------------------------------------------------
// PMP zone size
//------------------------------------------------
assign cpuid_index2_value[5:3] = 3'b111; // 4B
//------------------------------------------------
// MGU zone num
//------------------------------------------------
assign cpuid_index2_value[2:0] = 3'b011;
assign mcpuid_value[31:0] = cpuid_value[31:0];
//==========================================================
// Rename for Output
//==========================================================
//assign info_csr_cpuid0_value[31:0] = cpuid_index0_value[31:0];
// &ModuleEnd; @365
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_cp0_iui(
cp0_dtu_addr,
cp0_dtu_rreg,
cp0_dtu_wdata,
cp0_dtu_wreg,
cp0_idu_ex1_stall,
cp0_iu_adder_borrow_in,
cp0_iu_adder_borrow_vld,
cp0_rtu_ex1_chgflw_pc,
cp0_rtu_ex1_chgflw_vld,
cp0_rtu_ex1_cmplt,
cp0_rtu_ex1_cmplt_dp,
cp0_rtu_ex1_dret,
cp0_rtu_ex1_ebreak,
cp0_rtu_ex1_expt_inst,
cp0_rtu_ex1_expt_tval,
cp0_rtu_ex1_expt_vec,
cp0_rtu_ex1_flush,
cp0_rtu_ex1_halt_info,
cp0_rtu_ex1_inst_len,
cp0_rtu_ex1_inst_vld,
cp0_rtu_ex1_ipush_spec_fail,
cp0_rtu_ex1_mret,
cp0_rtu_ex1_split_inst,
cp0_rtu_ex1_tail_fail,
cp0_rtu_wb_data,
cp0_rtu_wb_preg,
cp0_rtu_wb_vld,
cpurst_b,
ext_iui_cache_stall,
ext_iui_expt_vld,
idu_cp0_ex1_cmplt_dp_sel,
idu_cp0_ex1_dst_idx,
idu_cp0_ex1_dst_vld,
idu_cp0_ex1_expt_high,
idu_cp0_ex1_expt_type,
idu_cp0_ex1_expt_vld,
idu_cp0_ex1_func,
idu_cp0_ex1_gateclk_sel,
idu_cp0_ex1_halt_info,
idu_cp0_ex1_inst_len,
idu_cp0_ex1_ipush_spec_fail,
idu_cp0_ex1_opcode,
idu_cp0_ex1_rs1,
idu_cp0_ex1_rs2,
idu_cp0_ex1_sel,
idu_cp0_ex1_split_inst,
idu_cp0_ex1_tail_fail,
ifu_cp0_warm_up,
iu_cp0_ex1_borrow_expt_pc,
iui_csr_wen_f,
iui_ext_inst_cache,
iui_ext_inst_imm,
iui_ext_inst_rs1,
iui_regs_csr_mnxti_vld,
iui_regs_csr_wen,
iui_regs_imm,
iui_regs_inst_csr,
iui_regs_inst_mret,
iui_regs_wdata,
iui_regs_wdata_mie,
iui_regs_wdata_rs1,
iui_regs_wdata_srst,
iui_special_ecall,
iui_special_fence,
iui_special_fencei,
iui_special_int_vld,
iui_special_sync,
iui_special_synci,
iui_special_wfi,
regs_clk,
regs_iui_expt_vld,
regs_iui_mepc,
regs_iui_mie,
regs_iui_mnxti_sel,
regs_iui_mstatus,
regs_iui_pm,
regs_iui_rdata,
rtu_cp0_wk_int,
rtu_yy_xx_dbgon,
special_iui_expt_vld,
special_iui_stall,
srst_iui_stall
);
// &Ports; @24
input cpurst_b;
input ext_iui_cache_stall;
input ext_iui_expt_vld;
input idu_cp0_ex1_cmplt_dp_sel;
input [5 :0] idu_cp0_ex1_dst_idx;
input idu_cp0_ex1_dst_vld;
input idu_cp0_ex1_expt_high;
input idu_cp0_ex1_expt_type;
input idu_cp0_ex1_expt_vld;
input [19:0] idu_cp0_ex1_func;
input idu_cp0_ex1_gateclk_sel;
input [14:0] idu_cp0_ex1_halt_info;
input idu_cp0_ex1_inst_len;
input idu_cp0_ex1_ipush_spec_fail;
input [31:0] idu_cp0_ex1_opcode;
input [31:0] idu_cp0_ex1_rs1;
input [11:0] idu_cp0_ex1_rs2;
input idu_cp0_ex1_sel;
input idu_cp0_ex1_split_inst;
input idu_cp0_ex1_tail_fail;
input ifu_cp0_warm_up;
input [31:0] iu_cp0_ex1_borrow_expt_pc;
input regs_clk;
input regs_iui_expt_vld;
input [31:0] regs_iui_mepc;
input regs_iui_mie;
input regs_iui_mnxti_sel;
input [31:0] regs_iui_mstatus;
input [1 :0] regs_iui_pm;
input [31:0] regs_iui_rdata;
input rtu_cp0_wk_int;
input rtu_yy_xx_dbgon;
input special_iui_expt_vld;
input special_iui_stall;
input srst_iui_stall;
output [11:0] cp0_dtu_addr;
output cp0_dtu_rreg;
output [31:0] cp0_dtu_wdata;
output cp0_dtu_wreg;
output cp0_idu_ex1_stall;
output cp0_iu_adder_borrow_in;
output cp0_iu_adder_borrow_vld;
output [30:0] cp0_rtu_ex1_chgflw_pc;
output cp0_rtu_ex1_chgflw_vld;
output cp0_rtu_ex1_cmplt;
output cp0_rtu_ex1_cmplt_dp;
output cp0_rtu_ex1_dret;
output cp0_rtu_ex1_ebreak;
output cp0_rtu_ex1_expt_inst;
output [31:0] cp0_rtu_ex1_expt_tval;
output [3 :0] cp0_rtu_ex1_expt_vec;
output cp0_rtu_ex1_flush;
output [14:0] cp0_rtu_ex1_halt_info;
output cp0_rtu_ex1_inst_len;
output cp0_rtu_ex1_inst_vld;
output cp0_rtu_ex1_ipush_spec_fail;
output cp0_rtu_ex1_mret;
output cp0_rtu_ex1_split_inst;
output cp0_rtu_ex1_tail_fail;
output [31:0] cp0_rtu_wb_data;
output [5 :0] cp0_rtu_wb_preg;
output cp0_rtu_wb_vld;
output iui_csr_wen_f;
output iui_ext_inst_cache;
output [11:0] iui_ext_inst_imm;
output [31:0] iui_ext_inst_rs1;
output iui_regs_csr_mnxti_vld;
output iui_regs_csr_wen;
output [11:0] iui_regs_imm;
output iui_regs_inst_csr;
output iui_regs_inst_mret;
output [31:0] iui_regs_wdata;
output iui_regs_wdata_mie;
output [31:0] iui_regs_wdata_rs1;
output [1 :0] iui_regs_wdata_srst;
output iui_special_ecall;
output iui_special_fence;
output iui_special_fencei;
output iui_special_int_vld;
output iui_special_sync;
output iui_special_synci;
output iui_special_wfi;
// &Regs; @25
reg iui_csr_wen_f;
reg [31:0] iui_expt_tval;
reg [3 :0] iui_expt_vec;
// &Wires; @26
wire [11:0] cp0_dtu_addr;
wire cp0_dtu_rreg;
wire [31:0] cp0_dtu_wdata;
wire cp0_dtu_wreg;
wire cp0_idu_ex1_stall;
wire cp0_iu_adder_borrow_in;
wire cp0_iu_adder_borrow_vld;
wire [30:0] cp0_rtu_ex1_chgflw_pc;
wire cp0_rtu_ex1_chgflw_vld;
wire cp0_rtu_ex1_cmplt;
wire cp0_rtu_ex1_cmplt_dp;
wire cp0_rtu_ex1_dret;
wire cp0_rtu_ex1_ebreak;
wire cp0_rtu_ex1_expt_inst;
wire [31:0] cp0_rtu_ex1_expt_tval;
wire [3 :0] cp0_rtu_ex1_expt_vec;
wire cp0_rtu_ex1_flush;
wire [14:0] cp0_rtu_ex1_halt_info;
wire cp0_rtu_ex1_inst_len;
wire cp0_rtu_ex1_inst_vld;
wire cp0_rtu_ex1_ipush_spec_fail;
wire cp0_rtu_ex1_mret;
wire cp0_rtu_ex1_split_inst;
wire cp0_rtu_ex1_tail_fail;
wire [31:0] cp0_rtu_wb_data;
wire [5 :0] cp0_rtu_wb_preg;
wire cp0_rtu_wb_vld;
wire cpurst_b;
wire ext_iui_cache_stall;
wire ext_iui_expt_vld;
wire idu_cp0_ex1_cmplt_dp_sel;
wire [5 :0] idu_cp0_ex1_dst_idx;
wire idu_cp0_ex1_dst_vld;
wire idu_cp0_ex1_expt_high;
wire idu_cp0_ex1_expt_type;
wire idu_cp0_ex1_expt_vld;
wire [19:0] idu_cp0_ex1_func;
wire idu_cp0_ex1_gateclk_sel;
wire [14:0] idu_cp0_ex1_halt_info;
wire idu_cp0_ex1_inst_len;
wire idu_cp0_ex1_ipush_spec_fail;
wire [31:0] idu_cp0_ex1_opcode;
wire [31:0] idu_cp0_ex1_rs1;
wire [11:0] idu_cp0_ex1_rs2;
wire idu_cp0_ex1_sel;
wire idu_cp0_ex1_split_inst;
wire idu_cp0_ex1_tail_fail;
wire [31:0] iu_cp0_ex1_borrow_expt_pc;
wire iui_accflt_expt_vld;
wire iui_cancel;
wire [31:0] iui_chgflw_pc;
wire iui_chgflw_vld;
wire iui_csr_expt_vld;
wire [31:0] iui_csr_mstatus;
wire [31:0] iui_csr_rdata;
wire iui_csr_umode_inv;
wire [31:0] iui_csr_wdata;
wire [31:0] iui_csr_wdata_mstatus;
wire iui_csr_wen;
wire iui_csr_wen_vld;
wire iui_csr_write_inv;
wire [31:0] iui_csrrc_rs1;
wire [31:0] iui_csrrc_rs1_mstatus;
wire [31:0] iui_csrrs_rs1;
wire [31:0] iui_csrrs_rs1_mstatus;
wire [31:0] iui_csrrw_rs1;
wire iui_ebreak_expt_vld;
wire iui_expt_vld;
wire iui_ext_inst_cache;
wire [11:0] iui_ext_inst_imm;
wire [31:0] iui_ext_inst_rs1;
wire iui_illegal_expt_vld;
wire iui_inst_cache;
wire iui_inst_cmplt;
wire iui_inst_csr;
wire [2 :0] iui_inst_csr_func;
wire iui_inst_dret;
wire [5 :0] iui_inst_dst_idx;
wire iui_inst_dst_vld;
wire iui_inst_ebrek;
wire iui_inst_ecall;
wire iui_inst_fence;
wire iui_inst_fenci;
wire iui_inst_flush;
wire [5 :0] iui_inst_func;
wire [14:0] iui_inst_halt_info;
wire [11:0] iui_inst_imm;
wire iui_inst_ipush_spec_fail;
wire iui_inst_mret;
wire iui_inst_mret_vld;
wire [31:0] iui_inst_opcode;
wire [31:0] iui_inst_rs1;
wire iui_inst_split_inst;
wire iui_inst_stall;
wire [4 :0] iui_inst_sub_func;
wire iui_inst_sync;
wire iui_inst_synci;
wire iui_inst_tail_fail;
wire iui_inst_vld;
wire iui_inst_wfi;
wire iui_mecall_expt_vld;
wire iui_mret_umode_inv;
wire iui_regs_csr_mnxti_vld;
wire iui_regs_csr_wen;
wire [11:0] iui_regs_imm;
wire iui_regs_inst_csr;
wire iui_regs_inst_mret;
wire [31:0] iui_regs_wdata;
wire iui_regs_wdata_mie;
wire [31:0] iui_regs_wdata_rs1;
wire [1 :0] iui_regs_wdata_srst;
wire iui_special_ebrek;
wire iui_special_ecall;
wire iui_special_fence;
wire iui_special_fencei;
wire iui_special_int_vld;
wire iui_special_sync;
wire iui_special_synci;
wire iui_special_wfi;
wire iui_uecall_expt_vld;
wire iui_wfi_umode_inv;
wire regs_clk;
wire regs_iui_expt_vld;
wire [31:0] regs_iui_mepc;
wire regs_iui_mie;
wire regs_iui_mnxti_sel;
wire [31:0] regs_iui_mstatus;
wire [1 :0] regs_iui_pm;
wire [31:0] regs_iui_rdata;
wire rtu_cp0_wk_int;
wire rtu_yy_xx_dbgon;
wire special_iui_expt_vld;
wire special_iui_stall;
wire srst_iui_stall;
//==========================================================
// CP0 IUI Module
// 1. Prepare CSR and Special Inst Information
// 2. Generate Retire and Exception Signals
//==========================================================
//------------------------------------------------
// 1. Prepare CSR and Special Inst Information
// a. Get the instruction functions
// b. Generate CSR Inst Information
// c. Generate Special Inst Information
//------------------------------------------------
// &Force("bus","idu_cp0_ex1_func",19,0); @40
// a. Get the instruction functions
assign iui_inst_vld = idu_cp0_ex1_gateclk_sel && !idu_cp0_ex1_expt_vld && !iui_cancel;
assign iui_inst_func[5:0] = idu_cp0_ex1_func[10:5];
assign iui_inst_sub_func[4:0] = idu_cp0_ex1_func[4:0];
assign iui_inst_dst_vld = idu_cp0_ex1_gateclk_sel && idu_cp0_ex1_dst_vld;
assign iui_inst_dst_idx[5:0] = idu_cp0_ex1_dst_idx[5:0];
// &Force("bus", "idu_cp0_ex1_dst_idx", 5, 0); @47
assign iui_inst_rs1[31:0] = idu_cp0_ex1_rs1[31:0];
assign iui_inst_imm[11:0] = {12{idu_cp0_ex1_gateclk_sel}} & idu_cp0_ex1_rs2[11:0];
assign iui_inst_opcode[31:0] = {32{idu_cp0_ex1_gateclk_sel}} & idu_cp0_ex1_opcode[31:0];
assign iui_inst_halt_info[`TDT_HINFO_WIDTH-1:0] =
{`TDT_HINFO_WIDTH{idu_cp0_ex1_gateclk_sel}} & idu_cp0_ex1_halt_info[`TDT_HINFO_WIDTH-1:0];
assign iui_inst_ipush_spec_fail = idu_cp0_ex1_ipush_spec_fail;
assign iui_inst_tail_fail = idu_cp0_ex1_tail_fail;
assign iui_inst_split_inst = idu_cp0_ex1_split_inst;
// b. Generate CSR Inst Information
// CSR Write Enable
assign iui_inst_csr = iui_inst_vld && iui_inst_func[0];
assign iui_csr_wen = iui_inst_vld && iui_inst_func[0]
&& !iui_inst_sub_func[3];
// &Force("input","ifu_cp0_warm_up"); @61
always @ (posedge regs_clk or negedge cpurst_b)
begin
if (!cpurst_b)
iui_csr_wen_f <= 1'b0;
else if (iui_regs_csr_wen && iui_inst_stall)
iui_csr_wen_f <= 1'b1;
else
iui_csr_wen_f <= 1'b0;
end
assign iui_csr_wen_vld = iui_regs_csr_wen && !iui_csr_wen_f
&& !iui_csr_expt_vld;
// &Force("output","iui_csr_wen_f"); @75
// &Force("input","regs_clk"); @78
// CSR Func 0:CSRRW, 1: CSRRS, 2: CSRRC
assign iui_inst_csr_func[2:0] = {3{idu_cp0_ex1_func[5]}}
& idu_cp0_ex1_func[2:0];
// CSR write data prepare
assign iui_csr_rdata[31:0] = regs_iui_rdata[31:0];
assign iui_csrrw_rs1[31:0] = iui_inst_rs1[31:0];
assign iui_csrrs_rs1[31:0] = iui_csr_rdata[31:0] | iui_inst_rs1[31:0];
assign iui_csrrc_rs1[31:0] = iui_csr_rdata[31:0] & (~iui_inst_rs1[31:0]);
assign iui_csr_wdata[31:0] = {32{iui_inst_csr_func[0]}} & iui_csrrw_rs1[31:0]
| {32{iui_inst_csr_func[1]}} & iui_csrrs_rs1[31:0]
| {32{iui_inst_csr_func[2]}} & iui_csrrc_rs1[31:0];
assign iui_regs_csr_mnxti_vld = !(iui_inst_rs1[31:0] == 32'b0 && (iui_inst_csr_func[1]
|| iui_inst_csr_func[2]));
assign iui_csr_mstatus[31:0] = regs_iui_mstatus[31:0];
assign iui_csrrs_rs1_mstatus[31:0] = iui_csr_mstatus[31:0] | iui_inst_rs1[31:0];
assign iui_csrrc_rs1_mstatus[31:0] = iui_csr_mstatus[31:0] & (~iui_inst_rs1[31:0]);
assign iui_csr_wdata_mstatus[31:0] = {32{iui_inst_csr_func[0]}} & iui_csrrw_rs1[31:0]
| {32{iui_inst_csr_func[1]}} & iui_csrrs_rs1_mstatus[31:0]
| {32{iui_inst_csr_func[2]}} & iui_csrrc_rs1_mstatus[31:0];
assign iui_regs_wdata_srst[1:0] = {2{|iui_inst_csr_func[1:0]}} & iui_inst_rs1[1:0]; // srst[1:0] is always 2'b0.
assign iui_regs_wdata_mie = iui_inst_csr_func[0] && iui_inst_rs1[3]
|| iui_inst_csr_func[1] && (regs_iui_mie || iui_inst_rs1[3])
|| iui_inst_csr_func[2] && (regs_iui_mie && !iui_inst_rs1[3]);
// mie is mstatus[3].
// c. Generate Special Inst Information
assign iui_inst_fence = iui_inst_vld && iui_inst_func[1]
&& iui_inst_sub_func[0];
assign iui_inst_fenci = iui_inst_vld && iui_inst_func[1]
&& iui_inst_sub_func[1];
assign iui_inst_sync = iui_inst_vld && iui_inst_func[1]
&& iui_inst_sub_func[2];
assign iui_inst_synci = iui_inst_vld && iui_inst_func[1]
&& iui_inst_sub_func[3];
assign iui_inst_ecall = iui_inst_vld && iui_inst_func[2]
&& iui_inst_sub_func[0] && !rtu_yy_xx_dbgon;
assign iui_inst_ebrek = iui_inst_vld && iui_inst_func[2]
&& iui_inst_sub_func[1];
assign iui_inst_mret = iui_inst_vld && iui_inst_func[2]
&& iui_inst_sub_func[2]&& !rtu_yy_xx_dbgon;
assign iui_inst_wfi = iui_inst_vld && iui_inst_func[2]
&& iui_inst_sub_func[3] && !rtu_yy_xx_dbgon;
assign iui_inst_cache = iui_inst_vld && iui_inst_func[2]
&& iui_inst_sub_func[4];
assign iui_inst_dret = iui_inst_vld && iui_inst_sub_func[1]
&& iui_inst_func[4] && rtu_yy_xx_dbgon;
//------------------------------------------------
// 2. Generate Retire and Exception Signals
// a. Inst Complete
// b. Inst Exception
// c. Change Flow
//------------------------------------------------
// a. Inst Complete
// Inst Complete except for WFI stall
// assign iui_inst_cmplt = idu_cp0_ex1_sel && (!special_iui_stall
// || iui_inst_cache && ext_iui_cache_stall);
assign iui_inst_cmplt = idu_cp0_ex1_sel && !iui_inst_stall;
assign iui_inst_stall = iui_inst_cache && ext_iui_cache_stall
|| srst_iui_stall
|| special_iui_stall;
assign iui_inst_flush = iui_inst_cmplt && !(iui_inst_func[0] && iui_inst_sub_func[3]
|| iui_inst_fence || iui_inst_sync)
&& !idu_cp0_ex1_expt_vld
&& !iui_cancel;
// b. Inst Exception
// Invalid operation when write read-only regs
assign iui_csr_write_inv = iui_csr_wen && iui_inst_imm[11:10] == 2'b11;
assign iui_csr_umode_inv = regs_iui_pm[1:0] == 2'b00 && !rtu_yy_xx_dbgon
&& iui_inst_csr && iui_inst_imm[9:8] != 2'b00;
assign iui_mret_umode_inv = regs_iui_pm[1:0] == 2'b00 && iui_inst_mret && !rtu_yy_xx_dbgon;
assign iui_wfi_umode_inv = regs_iui_pm[1:0] == 2'b00 && iui_inst_wfi && !rtu_yy_xx_dbgon;
assign iui_csr_expt_vld = iui_csr_write_inv || iui_csr_umode_inv
|| iui_inst_csr && regs_iui_expt_vld
|| iui_inst_cache && ext_iui_expt_vld;
assign iui_expt_vld = (idu_cp0_ex1_expt_vld
|| iui_csr_expt_vld
|| iui_mret_umode_inv
|| iui_wfi_umode_inv
|| special_iui_expt_vld)
&& idu_cp0_ex1_gateclk_sel;
assign iui_cancel = iui_inst_halt_info[`TDT_HINFO_CANCEL]
&& idu_cp0_ex1_gateclk_sel;
//// Generate iui int vector
//assign iui_int_vld = |regs_iui_int_sel[2:0];
//&CombBeg;
//casez(regs_iui_int_sel[2:0])
// 3'b1?? : iui_int_vec[3:0] = 4'd11;
// 3'b01? : iui_int_vec[3:0] = 4'd7;
// 3'b001 : iui_int_vec[3:0] = 4'd3;
// default : iui_int_vec[3:0] = 3'bx;
//endcase
//&CombEnd;
// Generate iui expt vector
assign iui_accflt_expt_vld = idu_cp0_ex1_expt_vld && idu_cp0_ex1_expt_type;
assign iui_illegal_expt_vld = idu_cp0_ex1_expt_vld && !idu_cp0_ex1_expt_type
|| iui_csr_expt_vld
|| iui_mret_umode_inv
|| iui_wfi_umode_inv;
assign iui_mecall_expt_vld = iui_inst_ecall && regs_iui_pm[1:0] == 2'b11;
assign iui_uecall_expt_vld = iui_inst_ecall && regs_iui_pm[1:0] == 2'b00;
assign iui_ebreak_expt_vld = iui_inst_ebrek;
// &CombBeg; @193
always @( iui_illegal_expt_vld
or iui_uecall_expt_vld
or iui_mecall_expt_vld
or iui_ebreak_expt_vld
or iui_accflt_expt_vld)
begin
if(iui_accflt_expt_vld)
iui_expt_vec[3:0] = 4'd1;
else if(iui_illegal_expt_vld)
iui_expt_vec[3:0] = 4'd2;
else if(iui_mecall_expt_vld)
iui_expt_vec[3:0] = 4'd11;
else if(iui_uecall_expt_vld)
iui_expt_vec[3:0] = 4'd8;
else if(iui_ebreak_expt_vld)
iui_expt_vec[3:0] = 4'd3;
else
iui_expt_vec[3:0] = 4'd0;
// &CombEnd; @206
end
//assign iui_ex1_pc[31:0] = {`PA_WIDTH{idu_cp0_ex1_gateclk_sel}} & iu_cp0_ex1_cur_pc[31:0];
//assign iui_ex1_expt_pc[31:0] = iui_ex1_pc[31:0]
// + {{(`PA_WIDTH-2){1'b0}}, idu_cp0_ex1_expt_high, 1'b0};
assign cp0_iu_adder_borrow_vld = idu_cp0_ex1_gateclk_sel & (iui_accflt_expt_vld | iui_cancel);
assign cp0_iu_adder_borrow_in = idu_cp0_ex1_expt_high;
// &CombBeg; @213
always @( iui_cancel
or iui_inst_opcode[31:0]
or iu_cp0_ex1_borrow_expt_pc[31:0]
or iui_accflt_expt_vld)
begin
if (iui_accflt_expt_vld || iui_cancel)
iui_expt_tval[31:0] = iu_cp0_ex1_borrow_expt_pc[31:0];
else
iui_expt_tval[31:0] = {iui_inst_opcode[31:0]};
// &CombEnd; @218
end
// c. Change Flow
assign iui_inst_mret_vld = iui_inst_mret && !iui_mret_umode_inv;
assign iui_chgflw_vld = iui_inst_mret_vld && !iui_cancel;
assign iui_chgflw_pc[31:0] = regs_iui_mepc[31:0];
//==========================================================
// Rename for Output
//==========================================================
// Output to Regs
assign iui_regs_imm[11:0] = iui_inst_imm[11:0];
// &Force("output","iui_regs_csr_wen"); @232
assign iui_regs_csr_wen = iui_csr_wen && !iui_csr_expt_vld;
assign iui_regs_wdata[31:0] = regs_iui_mnxti_sel ? iui_csr_wdata_mstatus[31:0]
: iui_csr_wdata[31:0];
assign iui_regs_wdata_rs1[31:0] = iui_csrrw_rs1[31:0];
assign iui_regs_inst_csr = iui_inst_csr && !iui_csr_expt_vld;
assign iui_regs_inst_mret = iui_inst_mret_vld;
// &Force("output","iui_regs_inst_csr"); @241
// Output to Regs
assign iui_special_fence = iui_inst_fence;
assign iui_special_fencei = iui_inst_fenci;
assign iui_special_sync = iui_inst_sync;
assign iui_special_synci = iui_inst_synci;
assign iui_special_ecall = iui_inst_ecall;
assign iui_special_ebrek = iui_inst_ebrek;
assign iui_special_wfi = iui_inst_wfi && !iui_wfi_umode_inv;
assign iui_special_int_vld = rtu_cp0_wk_int;
// Output to ext
assign iui_ext_inst_imm[11:0] = iui_inst_imm[11:0];
assign iui_ext_inst_cache = iui_inst_cache;
assign iui_ext_inst_rs1[31:0] = iui_inst_rs1[31:0];
// Output to RTU
assign cp0_rtu_ex1_cmplt = iui_inst_cmplt;
assign cp0_rtu_ex1_cmplt_dp = idu_cp0_ex1_cmplt_dp_sel;
assign cp0_rtu_ex1_flush = iui_inst_flush;
assign cp0_idu_ex1_stall = iui_inst_stall;
assign cp0_rtu_ex1_inst_vld = idu_cp0_ex1_gateclk_sel;
assign cp0_rtu_ex1_expt_inst = iui_expt_vld;
assign cp0_rtu_ex1_expt_vec[3:0] = iui_expt_vec[3:0];
assign cp0_rtu_ex1_chgflw_vld = iui_chgflw_vld;
assign cp0_rtu_ex1_chgflw_pc[30:0] = iui_chgflw_pc[31:1];
assign cp0_rtu_wb_vld = iui_inst_cmplt && iui_inst_dst_vld && !iui_expt_vld & ~iui_cancel;
assign cp0_rtu_wb_preg[5:0] = {iui_inst_dst_idx[5:0]};
assign cp0_rtu_wb_data[31:0] = iui_expt_vld ? idu_cp0_ex1_opcode[31:0]
: regs_iui_rdata[31:0];
//assign cp0_rtu_ex1_inst_bkpt[8:0] = idu_cp0_ex1_inst_bkpt[8:0];
assign cp0_rtu_ex1_mret = iui_inst_mret_vld;
assign cp0_rtu_ex1_dret = iui_inst_dret;
assign cp0_rtu_ex1_ebreak = iui_special_ebrek;
assign cp0_rtu_ex1_ipush_spec_fail = iui_inst_ipush_spec_fail;
assign cp0_rtu_ex1_tail_fail = iui_inst_tail_fail;
assign cp0_rtu_ex1_split_inst = iui_inst_split_inst;
assign cp0_rtu_ex1_expt_tval[31:0] = iui_expt_tval[31:0];
assign cp0_rtu_ex1_inst_len = idu_cp0_ex1_inst_len;
assign cp0_rtu_ex1_halt_info[`TDT_HINFO_WIDTH-1:0] = iui_inst_halt_info[`TDT_HINFO_WIDTH-1:0];
// Output to Sysio
//
//----------------------------------------------------------
// For DTU
//----------------------------------------------------------
assign cp0_dtu_wreg = iui_csr_wen_vld;
assign cp0_dtu_rreg = iui_regs_inst_csr;
assign cp0_dtu_addr[11:0] = iui_inst_imm[11:0];
assign cp0_dtu_wdata[31:0] = iui_csr_wdata[31:0];
// &ModuleEnd; @304
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_cp0_special(
cp0_ifu_in_lpmd,
cp0_ifu_lpmd_req,
cp0_lsu_fence_req,
cp0_lsu_sync_req,
cp0_sysio_ipend_b,
cp0_sysio_lpmd_b,
cp0_yy_clk_en,
cpurst_b,
dtu_cp0_wake_up,
fence_top_cur_state,
forever_cpuclk,
ifu_cp0_lpmd_ack,
inv_sm_clk,
iui_special_ecall,
iui_special_fence,
iui_special_fencei,
iui_special_int_vld,
iui_special_sync,
iui_special_synci,
iui_special_wfi,
lpmd_top_cur_state,
lsu_cp0_fence_ack,
lsu_cp0_icc_done,
lsu_cp0_sync_ack,
pad_yy_icg_scan_en,
regs_special_lpmd,
rtu_yy_xx_dbgon,
rtu_yy_xx_flush,
special_dcache_clean,
special_icache_inv,
special_icache_inv_done,
special_iui_expt_vld,
special_iui_stall,
special_regs_clk_en,
special_regs_inv_sm_clk_en,
srst_in_wait_state,
srst_sm_clk,
srst_special_srst_sm_clk_en
);
// &Ports; @24
input cpurst_b;
input dtu_cp0_wake_up;
input forever_cpuclk;
input ifu_cp0_lpmd_ack;
input inv_sm_clk;
input iui_special_ecall;
input iui_special_fence;
input iui_special_fencei;
input iui_special_int_vld;
input iui_special_sync;
input iui_special_synci;
input iui_special_wfi;
input lsu_cp0_fence_ack;
input lsu_cp0_icc_done;
input lsu_cp0_sync_ack;
input pad_yy_icg_scan_en;
input [1:0] regs_special_lpmd;
input rtu_yy_xx_dbgon;
input rtu_yy_xx_flush;
input special_icache_inv_done;
input srst_in_wait_state;
input srst_special_srst_sm_clk_en;
output cp0_ifu_in_lpmd;
output cp0_ifu_lpmd_req;
output cp0_lsu_fence_req;
output cp0_lsu_sync_req;
output cp0_sysio_ipend_b;
output [1:0] cp0_sysio_lpmd_b;
output cp0_yy_clk_en;
output [2:0] fence_top_cur_state;
output [1:0] lpmd_top_cur_state;
output special_dcache_clean;
output special_icache_inv;
output special_iui_expt_vld;
output special_iui_stall;
output special_regs_clk_en;
output special_regs_inv_sm_clk_en;
output srst_sm_clk;
// &Regs; @25
reg [1:0] cur_state;
reg [1:0] lpmd_b;
reg [1:0] next_state;
reg [2:0] spec_cur_state;
reg [2:0] spec_nxt_state;
// &Wires; @26
wire cp0_ifu_in_lpmd;
wire cp0_ifu_lpmd_req;
wire cp0_lsu_fence_req;
wire cp0_lsu_sync_req;
wire cp0_sysio_ipend_b;
wire [1:0] cp0_sysio_lpmd_b;
wire cp0_yy_clk_en;
wire cpu_in_lpmd;
wire cpu_in_lpmd_core_view;
wire cpurst_b;
wire dtu_cp0_wake_up;
wire fence_lsu_cmplt;
wire [2:0] fence_top_cur_state;
wire forever_cpuclk;
wire ifu_cp0_lpmd_ack;
wire inv_sm_clk;
wire iui_special_ecall;
wire iui_special_fence;
wire iui_special_fencei;
wire iui_special_int_vld;
wire iui_special_sync;
wire iui_special_synci;
wire iui_special_wfi;
wire lpmd_ack;
wire lpmd_clk;
wire lpmd_clk_en;
wire lpmd_in_wait_state;
wire lpmd_sm_clk;
wire lpmd_sm_icg_en;
wire lpmd_stall;
wire lpmd_start;
wire [1:0] lpmd_top_cur_state;
wire lsu_cp0_fence_ack;
wire lsu_cp0_icc_done;
wire lsu_cp0_sync_ack;
wire pad_yy_icg_scan_en;
wire [1:0] regs_special_lpmd;
wire rtu_yy_xx_dbgon;
wire rtu_yy_xx_flush;
wire spcial_fence_sync;
wire spec_inst_vld;
wire special_dcache_clean;
wire special_fence_req;
wire special_icache_inv;
wire special_icache_inv_done;
wire special_iui_expt_vld;
wire special_iui_stall;
wire special_regs_clk_en;
wire special_regs_inv_sm_clk_en;
wire special_sm_stall;
wire srst_in_wait_state;
wire srst_sm_clk;
wire srst_special_srst_sm_clk_en;
wire sync_lsu_cmplt;
//==========================================================
// Special Inst Module
// 1. Instance ICG cell
// 2. Low Power Mode Maintainment
// 3. Other Special Inst Execution
//==========================================================
parameter IDLE = 2'b00;
parameter WFACK = 2'b01;
parameter WFCPLT = 2'b11;
parameter CPLT = 2'b10;
//------------------------------------------------
// 1. Instance ICG cell
//------------------------------------------------
assign lpmd_sm_icg_en = iui_special_wfi || (cur_state[1:0] != IDLE)
|| srst_special_srst_sm_clk_en;
// &Instance("gated_clk_cell", "x_lpmd_sm_gated_clk"); @46
gated_clk_cell x_lpmd_sm_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (lpmd_sm_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (1'b0 ),
.module_en (lpmd_sm_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @47
// .external_en (1'b0), @48
// .global_en (1'b1), @49
// .module_en (lpmd_sm_icg_en), @50
// .local_en (1'b0), @51
// .clk_out (lpmd_sm_clk)); @52
assign srst_sm_clk = lpmd_sm_clk;
assign lpmd_clk_en = dtu_cp0_wake_up || iui_special_int_vld
|| rtu_yy_xx_dbgon || lpmd_start;
// &Instance("gated_clk_cell", "x_lpmd_gated_clk"); @59
gated_clk_cell x_lpmd_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (lpmd_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (1'b0 ),
.module_en (lpmd_clk_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @60
// .external_en (1'b0), @61
// .global_en (1'b1), @62
// .module_en (lpmd_clk_en), @63
// .local_en (1'b0), @64
// .clk_out (lpmd_clk)); @65
//------------------------------------------------
// 2. Low Power Mode Maintainment
//------------------------------------------------
//-----------------------------------------------------
// Request the BIU to enter low power mode and do
// not accept any more transaction from IFU or LSU
//-----------------------------------------------------
//-------------------FSM of lpmd req logic-----------------
// State Description:
// IDLE : no lpmd instruction (wait,stop,doze)
// WFACK : request sysio and wait for sysio ack
// the lpmd request
//-----------------------------------------------------
always @(posedge lpmd_sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
cur_state[1:0] <= IDLE;
else if(rtu_yy_xx_flush)
cur_state[1:0] <= IDLE;
else
cur_state[1:0] <= next_state[1:0];
end
// &CombBeg; @90
always @( cur_state[1:0]
or lpmd_start
or iui_special_wfi
or cpu_in_lpmd)
begin
case(cur_state[1:0])
IDLE : if(iui_special_wfi)
next_state[1:0] = WFACK;
else
next_state[1:0] = IDLE;
WFACK : if(lpmd_start)
next_state[1:0] = WFCPLT;
else
next_state[1:0] = WFACK;
WFCPLT : if(!cpu_in_lpmd)
next_state[1:0] = CPLT;
else
next_state[1:0] = WFCPLT;
CPLT : next_state[1:0] = IDLE;
default : next_state[1:0] = IDLE;
endcase
// &CombEnd; @107
end
assign lpmd_in_wait_state = (cur_state[1:0] == WFACK);
//-------------------control signal by lpmd FSM-------------
assign lpmd_stall = (cur_state[1:0] == IDLE) && iui_special_wfi
|| (cur_state[1:0] == WFACK)
|| (cur_state[1:0] == WFCPLT);
//-----------------------------------------------------
// lpmd request ack
//-----------------------------------------------------
assign lpmd_ack = ifu_cp0_lpmd_ack & lsu_cp0_sync_ack;
assign lpmd_start = lpmd_ack;
//-----------------------------------------------------
// Send lpmd bits to BIU and HAD, when
// cp0 can enter low power mode (get sysio_cp0_no_op)
//-----------------------------------------------------
always @(posedge lpmd_clk or negedge cpurst_b)
begin
if(!cpurst_b)
lpmd_b[1:0] <= 2'b11;
else if((dtu_cp0_wake_up || iui_special_int_vld)&& cpu_in_lpmd
|| rtu_yy_xx_dbgon)
lpmd_b[1:0] <= 2'b11;
else if(lpmd_start && !cpu_in_lpmd)
begin
lpmd_b[1:0] <= regs_special_lpmd[1:0];
end
else
lpmd_b[1:0] <= lpmd_b[1:0];
end
//the cpu condsider both pm bit in cp0(cpu view) and sysio(soc view)
//assign sys_lpmd_b[1:0] = sysio_cp0_sys_view_lpmd_b[1:0];
//assign cpu_in_lpmd_sys_view = !(sys_lpmd_b[1] & sys_lpmd_b[0]);
assign cpu_in_lpmd_core_view = !(lpmd_b[1] & lpmd_b[0]);
assign cpu_in_lpmd = cpu_in_lpmd_core_view;
//------------------------------------------------
// 3. Other Special Inst Execution
//------------------------------------------------
// FENCE, FENCE.I, SYNC, SYNC.I state machine.
assign spec_inst_vld = iui_special_fence
|| iui_special_fencei
|| iui_special_sync
|| iui_special_synci;
parameter SPEC_IDLE = 3'b000,
SPEC_FENC = 3'b001,
SPEC_CDCA = 3'b010,
SPEC_IICA = 3'b011,
SPEC_CMPLT= 3'b100;
always @ (posedge inv_sm_clk or negedge cpurst_b)
begin
if (!cpurst_b)
spec_cur_state[2:0] <= SPEC_IDLE;
else
spec_cur_state[2:0] <= spec_nxt_state[2:0];
end
assign fence_lsu_cmplt = lsu_cp0_fence_ack & iui_special_fence;
assign sync_lsu_cmplt = lsu_cp0_sync_ack & (iui_special_sync | iui_special_synci);
assign spcial_fence_sync = iui_special_fence || iui_special_sync || iui_special_synci;
// &CombBeg; @172
always @( iui_special_fencei
or sync_lsu_cmplt
or spec_cur_state
or spcial_fence_sync
or fence_lsu_cmplt
or lsu_cp0_icc_done
or special_icache_inv_done)
begin
case(spec_cur_state)
SPEC_IDLE:
if (iui_special_fencei)
spec_nxt_state[2:0] = SPEC_CDCA;
else if(spcial_fence_sync)
spec_nxt_state[2:0] = SPEC_FENC;
else
spec_nxt_state[2:0] = SPEC_IDLE;
SPEC_FENC:
if(spcial_fence_sync)
if(sync_lsu_cmplt || fence_lsu_cmplt)
spec_nxt_state[2:0] = SPEC_CMPLT;
else
spec_nxt_state[2:0] = SPEC_FENC;
else
spec_nxt_state[2:0] = SPEC_CMPLT;
SPEC_CDCA:
if (iui_special_fencei)
if (lsu_cp0_icc_done)
spec_nxt_state[2:0] = SPEC_IICA;
else
spec_nxt_state[2:0] = SPEC_CDCA;
else
spec_nxt_state[2:0] = SPEC_CMPLT;
SPEC_IICA:
if (iui_special_fencei)
if (special_icache_inv_done)
spec_nxt_state[2:0] = SPEC_CMPLT;
else
spec_nxt_state[2:0] = SPEC_IICA;
else
spec_nxt_state[2:0] = SPEC_CMPLT;
SPEC_CMPLT:
spec_nxt_state[2:0] = SPEC_IDLE;
default:
spec_nxt_state[2:0] = SPEC_IDLE;
endcase
// &CombEnd; @210
end
assign special_fence_req = spec_cur_state[2:0] == SPEC_FENC;
assign special_dcache_clean = spec_cur_state[2:0] == SPEC_CDCA;
assign special_icache_inv = spec_cur_state[2:0] == SPEC_IICA;
//assign special_fence_done = spec_cur_state[1:0] == SPEC_FENC && lsu_xx_no_op;
//assign special_fencei_done = spec_cur_state[1:0] == SPEC_IICA && special_icache_inv_done;
//assign special_sync_done = spec_cur_state[1:0] == SPEC_FENC && lsu_xx_no_op;
//assign special_synci_done = spec_cur_state[1:0] == SPEC_FENC && lsu_xx_no_op;
// &Force("output","special_dcache_clean"); @220
// &Force("output","special_icache_inv"); @221
assign special_sm_stall = spec_cur_state[2:0] == SPEC_IDLE && spec_inst_vld
|| special_fence_req
|| special_dcache_clean
|| special_icache_inv;
//==========================================================
// Rename for Output
//==========================================================
// Output to IUI
assign special_iui_expt_vld = iui_special_ecall;
assign special_iui_stall = lpmd_stall
|| special_sm_stall;
assign special_regs_clk_en = !cpu_in_lpmd;
assign special_regs_inv_sm_clk_en = spec_cur_state[2:0] != SPEC_IDLE
|| spec_inst_vld;
// Output to IFU
assign cp0_ifu_lpmd_req = lpmd_in_wait_state;
assign cp0_ifu_in_lpmd = cpu_in_lpmd;
// Output to LSU
assign cp0_lsu_fence_req = special_fence_req && (iui_special_fence);
assign cp0_lsu_sync_req = lpmd_in_wait_state || // low power req
srst_in_wait_state || // srst req
special_fence_req && (iui_special_sync || iui_special_synci);
// Output to RTU
//assign cp0_rtu_ex1_inst_ebreak = iui_special_ebrek;
// Output to HAD
//assign cp0_had_lpmd_b[1:0] = lpmd_b[1:0];
// Output to SYSIO
assign cp0_sysio_lpmd_b[1:0] = lpmd_b[1:0];
assign cp0_sysio_ipend_b = !iui_special_int_vld;
// Output to Global Clock Enable
assign cp0_yy_clk_en = !cpu_in_lpmd;
//debug infor
assign lpmd_top_cur_state[1:0] = cur_state[1:0];
assign fence_top_cur_state[2:0] = spec_cur_state[2:0];
// &ModuleEnd; @274
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_cp0_srst(
cp0_ifu_srst_mask,
cp0_ifu_srst_req,
cp0_sysio_srst,
cpurst_b,
ifu_cp0_srst_ack,
lsu_cp0_sync_ack,
regs_srst_srst_vld,
regs_srst_srstmd,
rtu_yy_xx_dbgon,
rtu_yy_xx_flush,
srst_in_wait_state,
srst_iui_stall,
srst_sm_clk,
srst_special_srst_sm_clk_en,
sysio_cp0_clk_en
);
// &Ports; @24
input cpurst_b;
input ifu_cp0_srst_ack;
input lsu_cp0_sync_ack;
input regs_srst_srst_vld;
input [1:0] regs_srst_srstmd;
input rtu_yy_xx_dbgon;
input rtu_yy_xx_flush;
input srst_sm_clk;
input sysio_cp0_clk_en;
output cp0_ifu_srst_mask;
output cp0_ifu_srst_req;
output [1:0] cp0_sysio_srst;
output srst_in_wait_state;
output srst_iui_stall;
output srst_special_srst_sm_clk_en;
// &Regs; @25
reg [1:0] cur_state;
reg [1:0] next_state;
// &Wires; @26
wire cp0_ifu_srst_mask;
wire cp0_ifu_srst_req;
wire [1:0] cp0_sysio_srst;
wire cpurst_b;
wire ifu_cp0_srst_ack;
wire lsu_cp0_sync_ack;
wire regs_srst_srst_vld;
wire [1:0] regs_srst_srstmd;
wire rtu_yy_xx_dbgon;
wire rtu_yy_xx_flush;
wire srst_ack;
wire srst_cmplt;
wire srst_in_wait_state;
wire srst_iui_stall;
wire srst_sm_clk;
wire srst_sm_clk_en;
wire srst_special_srst_sm_clk_en;
wire sysio_cp0_clk_en;
parameter IDLE = 2'b00;
parameter WFACK = 2'b01;
parameter WFCPLT = 2'b10;
parameter WFRST = 2'b11;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign srst_sm_clk_en = regs_srst_srst_vld || (cur_state[1:0] != IDLE);
//-----------------------------------------------------
// Request the BIU to enter low power mode and do
// not accept any more transaction from IFU or LSU
//-----------------------------------------------------
//-------------------FSM of srst req logic-----------------
// State Description:
// IDLE : no srst instruction (wait,stop,doze)
// WFACK : request sysio and wait for sysio ack
// the srst request
//-----------------------------------------------------
always @(posedge srst_sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
cur_state[1:0] <= IDLE;
else if(rtu_yy_xx_flush)
cur_state[1:0] <= IDLE;
else
cur_state[1:0] <= next_state[1:0];
end
// &CombBeg; @60
always @( cur_state[1:0]
or regs_srst_srst_vld
or sysio_cp0_clk_en
or srst_ack)
begin
case(cur_state[1:0])
IDLE : if(regs_srst_srst_vld)
next_state[1:0] = WFACK;
else
next_state[1:0] = IDLE;
WFACK : if(srst_ack)
next_state[1:0] = WFCPLT;
else
next_state[1:0] = WFACK;
WFCPLT : if(sysio_cp0_clk_en)
next_state[1:0] = WFRST;
else
next_state[1:0] = WFCPLT;
WFRST : next_state[1:0] = WFRST;
default: next_state[1:0] = IDLE;
endcase
// &CombEnd; @77
end
assign srst_in_wait_state = (cur_state[1:0] == WFACK);
assign srst_cmplt = (cur_state[1:0] == WFCPLT);
//-------------------control signal by srst FSM-------------
assign srst_iui_stall = (cur_state[1:0] == IDLE) && regs_srst_srst_vld
|| (cur_state[1:0] != IDLE);
assign cp0_ifu_srst_req = srst_in_wait_state;
// assign cp0_cache_srst_req = srst_in_wait_state;
// &Force("output","srst_in_wait_state"); @94
//-----------------------------------------------------
// srst request ack
//-----------------------------------------------------
assign srst_ack = (ifu_cp0_srst_ack && lsu_cp0_sync_ack)
|| rtu_yy_xx_dbgon;
assign cp0_sysio_srst[1:0] = {2{srst_cmplt && sysio_cp0_clk_en}} & regs_srst_srstmd[1:0];
assign cp0_ifu_srst_mask = (cur_state[1:0] == WFCPLT) || (cur_state[1:0] == WFRST);
assign srst_special_srst_sm_clk_en = srst_sm_clk_en;
// &ModuleEnd; @106
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
`define PRODUCT_ID 12'h000
`define RESET_VAL 16'hABCD
`define E906
`ifdef E906
`define REVISION 4'd2
`define SUB_VERSION 6'd2
`define PATCH 6'd2
`endif
`define FPGA
`define NEW_DFT
`define BHT
`ifdef BHT
//`define BHT_2K
//`define BHT_4K
`define BHT_8K
//`define BHT_16K
`endif
`define BTB
`define RAS
`define CLIC_MODE
`define HARDWARE_STACK
`define LS_MISALIGN
`define FPU
`ifdef FPU_DOUBLE
`define FLEN 64
`else
`define FLEN 32
`endif
`ifdef E906
`define IAHB_LITE
`define DAHB_LITE
`endif
`ifdef IAHB_LITE
//`define FLOP_OUT_IBUS
`define IBUS_32
`endif
`ifdef DAHB_LITE
//`define FLOP_OUT_DBUS
`define DBUS_32
`endif
`define SYS_AHB_LITE
`define BIU_32
`define FLOP_OUT_BIU
`define PMP
`ifdef PMP
//`define PMP_REGION_4
`define PMP_REGION_8
//`define PMP_REGION_12
//`define PMP_REGION_16
`endif
`define ICACHE
`define DCACHE
`ifdef ICACHE
`define ICACHE_16K
`endif
`ifdef DCACHE
//`define DCACHE_8K
`define DCACHE_16K
`endif
`define TCIPIF
`define DYNAMIC_SYSMAP
`ifdef CLIC_MODE
// Attention:
// 1. EXT_INT_NUM *MUST* > 0.
// 2. If you don't want to use extensional clic int, use //`define EXT_INT_NUM rather than change EXT_INT_NUM to 0.
// 3. If EXT_INT_NUM > 48, you need define CLIC_2_CYCLES unless the timing is loose.
// 4. Don't change definition of CLIC_INTNUM.
`define CLIC_2_CYCLES
//`define U_MODE_INT
`define CLIC_INTCTLBITS 3
`define EXT_INT_NUM 128
`ifdef EXT_INT_NUM
`define CLIC_INTNUM `EXT_INT_NUM+16
`else
`define CLIC_INTNUM 16
`endif
`endif
`define PMU
`define THEAD_IP
`define TDT_DEBUG
`define TDT_DM_PB_EN
`ifdef TDT_DM_PB_EN
`define TDT_DM_IEBREAK
`define TDT_DM_PB_SIZE 2
`endif
`ifdef TDT_DM_EXT_TRIGGER_EN
//`define TDT_DM_EXTHALTTRI_4
//`define TDT_DM_EXTHALTTRI_3
//`define TDT_DM_EXTHALTTRI_2
`define TDT_DM_EXTHALTTRI_1
//`define TDT_DM_EXTRESUMETRI_4
//`define TDT_DM_EXTRESUMETRI_3
//`define TDT_DM_EXTRESUMETRI_2
`define TDT_DM_EXTRESUMETRI_1
`endif
`define TDT_DM_NEXTDM_BA 32'h00000000
`define TDT_TM_TYPICAL
`define TDT_DEBUG_PCFIFO
`ifdef TDT_DEBUG_PCFIFO
`define TDT_DEBUG_PCFIFO_8_ENTRY
//`define TDT_DEBUG_PCFIFO_16_ENTRY
`endif
`define TDT_DEBUG_INFO
`define TDT_SYSAPB_ASYNC_CLK
`ifdef BHT_2K
`define BHT_IDX_WIDTH 7
`endif
`ifdef BHT_4K
`define BHT_IDX_WIDTH 8
`endif
`ifdef BHT_8K
`define BHT_IDX_WIDTH 9
`endif
`ifdef BHT_16K
`define BHT_IDX_WIDTH 10
`endif
`ifdef E906
`define AHB_LITE
`endif
`ifdef PMP_REGION_2
`define REGION_ENTRY0
`define REGION_ENTRY1
`endif
`ifdef PMP_REGION_4
`define REGION_ENTRY0
`define REGION_ENTRY1
`define REGION_ENTRY2
`define REGION_ENTRY3
`endif
`ifdef PMP_REGION_8
`define REGION_ENTRY0
`define REGION_ENTRY1
`define REGION_ENTRY2
`define REGION_ENTRY3
`define REGION_ENTRY4
`define REGION_ENTRY5
`define REGION_ENTRY6
`define REGION_ENTRY7
`endif
`ifdef PMP_REGION_12
`define REGION_ENTRY0
`define REGION_ENTRY1
`define REGION_ENTRY2
`define REGION_ENTRY3
`define REGION_ENTRY4
`define REGION_ENTRY5
`define REGION_ENTRY6
`define REGION_ENTRY7
`define REGION_ENTRY8
`define REGION_ENTRY9
`define REGION_ENTRY10
`define REGION_ENTRY11
`endif
`ifdef PMP_REGION_16
`define REGION_ENTRY0
`define REGION_ENTRY1
`define REGION_ENTRY2
`define REGION_ENTRY3
`define REGION_ENTRY4
`define REGION_ENTRY5
`define REGION_ENTRY6
`define REGION_ENTRY7
`define REGION_ENTRY8
`define REGION_ENTRY9
`define REGION_ENTRY10
`define REGION_ENTRY11
`define REGION_ENTRY12
`define REGION_ENTRY13
`define REGION_ENTRY14
`define REGION_ENTRY15
`endif
`ifdef ICACHE_2K
`define I_TAG_INDEX_WIDTH 5
`define I_TAG_TAG_WIDTH 22
`endif
`ifdef ICACHE_4K
`define I_TAG_INDEX_WIDTH 6
`define I_TAG_TAG_WIDTH 21
`endif
`ifdef ICACHE_8K
`define I_TAG_INDEX_WIDTH 7
`define I_TAG_TAG_WIDTH 20
`endif
`ifdef ICACHE_16K
`define I_TAG_INDEX_WIDTH 8
`define I_TAG_TAG_WIDTH 19
`endif
`ifdef ICACHE_32K
`define I_TAG_INDEX_WIDTH 9
`define I_TAG_TAG_WIDTH 18
`endif
`ifdef ICACHE_64K
`define I_TAG_INDEX_WIDTH 10
`define I_TAG_TAG_WIDTH 17
`endif
`ifdef DCACHE_2K
`define D_TAG_INDEX_WIDTH 5
`define D_TAG_TAG_WIDTH 22
`define D_DATA_INDEX_WIDTH 7
`endif
`ifdef DCACHE_4K
`define D_TAG_INDEX_WIDTH 6
`define D_TAG_TAG_WIDTH 21
`define D_DATA_INDEX_WIDTH 8
`endif
`ifdef DCACHE_8K
`define D_TAG_INDEX_WIDTH 7
`define D_TAG_TAG_WIDTH 20
`define D_DATA_INDEX_WIDTH 9
`endif
`ifdef DCACHE_16K
`define D_TAG_INDEX_WIDTH 8
`define D_TAG_TAG_WIDTH 19
`define D_DATA_INDEX_WIDTH 10
`endif
`ifdef DCACHE_32K
`define D_TAG_INDEX_WIDTH 9
`define D_TAG_TAG_WIDTH 18
`define D_DATA_INDEX_WIDTH 11
`endif
`ifdef DCACHE_64K
`define D_TAG_INDEX_WIDTH 10
`define D_TAG_TAG_WIDTH 17
`define D_DATA_INDEX_WIDTH 12
`endif
`ifdef IAHBL_ICACHE_2K
`define IC_TAG_TAG_LENGTH 22
`define IC_TAG_LINE_LENGTH 47
`define IC_TAG_INDEX_LENGTH 5
`define IC_DATA_INDEX_LENGTH 8
`endif
`ifdef IAHBL_ICACHE_4K
`define IC_TAG_TAG_LENGTH 21
`define IC_TAG_LINE_LENGTH 45
`define IC_TAG_INDEX_LENGTH 6
`define IC_DATA_INDEX_LENGTH 9
`endif
`ifdef IAHBL_ICACHE_8K
`define IC_TAG_TAG_LENGTH 20
`define IC_TAG_LINE_LENGTH 43
`define IC_TAG_INDEX_LENGTH 7
`define IC_DATA_INDEX_LENGTH 10
`endif
`ifdef IAHBL_ICACHE_16K
`define IC_TAG_TAG_LENGTH 19
`define IC_TAG_LINE_LENGTH 41
`define IC_TAG_INDEX_LENGTH 8
`define IC_DATA_INDEX_LENGTH 11
`endif
`ifdef IAHBL_ICACHE_32K
`define IC_TAG_TAG_LENGTH 18
`define IC_TAG_LINE_LENGTH 39
`define IC_TAG_INDEX_LENGTH 9
`define IC_DATA_INDEX_LENGTH 12
`endif
`ifdef IAHBL_ICACHE_64K
`define IC_TAG_TAG_LENGTH 17
`define IC_TAG_LINE_LENGTH 37
`define IC_TAG_INDEX_LENGTH 10
`define IC_DATA_INDEX_LENGTH 13
`endif
`ifdef TDT_DM_SBA
`ifdef E907
`define TDT_DM_SBA_AXI
`endif
`ifdef E906
`define TDT_DM_SBA_AHB
`endif
`endif
`define PA_WIDTH 32
`define VA_WIDTH 31
`define INDEPENDENT_AXI_SLAVE_ENV
`define INDEPENDENT_AXI_SLAVE_64
`define AXI_SLV_AGENT_NUM 2
`define TDT_DM_CORE_RV32
`define TDT_DM_CORE_NSCRATCH 4'h2
`ifdef TDT_DM_SBA
//`define TDT_DM_SBA_DW_128
`ifdef TDT_DM_SBA_AXI
`define TDT_DM_SBA_DW_64
`endif
`ifdef TDT_DM_SBA_AHB
`define TDT_DM_SBA_DW_32
`endif
`ifdef TDT_DM_SBA_AHB
`define TDT_DM_SBAW `PA_WIDTH
`else
`define TDT_DM_SBAW `PA_WIDTH
`endif
`endif

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @33
module openE906(
biu_pad_haddr,
biu_pad_hburst,
biu_pad_hlock,
biu_pad_hprot,
biu_pad_hsize,
biu_pad_htrans,
biu_pad_hwdata,
biu_pad_hwrite,
clk_en,
cp0_pad_mcause,
cp0_pad_mintstatus,
cp0_pad_mstatus,
cpu_pad_dfs_ack,
cpu_pad_halted,
cpu_pad_lockup,
cpu_pad_soft_rst,
dahbl_pad_haddr,
dahbl_pad_hburst,
dahbl_pad_hlock,
dahbl_pad_hprot,
dahbl_pad_hsize,
dahbl_pad_htrans,
dahbl_pad_hwdata,
dahbl_pad_hwrite,
iahbl_pad_haddr,
iahbl_pad_hburst,
iahbl_pad_hlock,
iahbl_pad_hprot,
iahbl_pad_hsize,
iahbl_pad_htrans,
iahbl_pad_hwdata,
iahbl_pad_hwrite,
pad_biu_hrdata,
pad_biu_hready,
pad_biu_hresp,
pad_bmu_dahbl_base,
pad_bmu_dahbl_mask,
pad_bmu_iahbl_base,
pad_bmu_iahbl_mask,
pad_clic_int_vld,
pad_cpu_dfs_req,
pad_cpu_ext_int_b,
pad_cpu_nmi,
pad_cpu_rst_addr,
pad_cpu_rst_b,
pad_cpu_sys_cnt,
pad_cpu_sysmap_addr0,
pad_cpu_sysmap_addr0_attr,
pad_cpu_sysmap_addr1,
pad_cpu_sysmap_addr1_attr,
pad_cpu_sysmap_addr2,
pad_cpu_sysmap_addr2_attr,
pad_cpu_sysmap_addr3,
pad_cpu_sysmap_addr3_attr,
pad_cpu_sysmap_addr4,
pad_cpu_sysmap_addr4_attr,
pad_cpu_sysmap_addr5,
pad_cpu_sysmap_addr5_attr,
pad_cpu_sysmap_addr6,
pad_cpu_sysmap_addr6_attr,
pad_cpu_sysmap_addr7,
pad_cpu_sysmap_addr7_attr,
pad_cpu_tcip_base,
pad_cpu_wakeup_event,
pad_dahbl_hrdata,
pad_dahbl_hready,
pad_dahbl_hresp,
pad_iahbl_hrdata,
pad_iahbl_hready,
pad_iahbl_hresp,
pad_tdt_dm_core_unavail,
pad_yy_dft_clk_rst_b,
pad_yy_icg_scan_en,
pad_yy_scan_enable,
pad_yy_scan_mode,
pad_yy_scan_rst_b,
pll_core_cpuclk,
rtu_pad_inst_retire,
rtu_pad_inst_split,
rtu_pad_retire_pc,
rtu_pad_wb0_data,
rtu_pad_wb0_preg,
rtu_pad_wb0_vld,
rtu_pad_wb1_data,
rtu_pad_wb1_preg,
rtu_pad_wb1_vld,
rtu_pad_wb2_data,
rtu_pad_wb2_preg,
rtu_pad_wb2_vld,
rtu_pad_wb_freg,
rtu_pad_wb_freg_data,
rtu_pad_wb_freg_vld,
sys_apb_clk,
sys_apb_rst_b,
sysio_pad_lpmd_b,
tdt_dm_pad_hartreset_n,
tdt_dm_pad_ndmreset_n,
tdt_dmi_paddr,
tdt_dmi_penable,
tdt_dmi_prdata,
tdt_dmi_pready,
tdt_dmi_psel,
tdt_dmi_pslverr,
tdt_dmi_pwdata,
tdt_dmi_pwrite
);
// &Ports("compare", "../../../gen_rtl/cpu/rtl/pa_cpu_top_golden_port.v"); @34
input clk_en;
input [31 :0] pad_biu_hrdata;
input pad_biu_hready;
input pad_biu_hresp;
input [11 :0] pad_bmu_dahbl_base;
input [11 :0] pad_bmu_dahbl_mask;
input [11 :0] pad_bmu_iahbl_base;
input [11 :0] pad_bmu_iahbl_mask;
input [127:0] pad_clic_int_vld;
input pad_cpu_dfs_req;
input pad_cpu_ext_int_b;
input pad_cpu_nmi;
input [31 :0] pad_cpu_rst_addr;
input pad_cpu_rst_b;
input [63 :0] pad_cpu_sys_cnt;
input [19 :0] pad_cpu_sysmap_addr0;
input [2 :0] pad_cpu_sysmap_addr0_attr;
input [19 :0] pad_cpu_sysmap_addr1;
input [2 :0] pad_cpu_sysmap_addr1_attr;
input [19 :0] pad_cpu_sysmap_addr2;
input [2 :0] pad_cpu_sysmap_addr2_attr;
input [19 :0] pad_cpu_sysmap_addr3;
input [2 :0] pad_cpu_sysmap_addr3_attr;
input [19 :0] pad_cpu_sysmap_addr4;
input [2 :0] pad_cpu_sysmap_addr4_attr;
input [19 :0] pad_cpu_sysmap_addr5;
input [2 :0] pad_cpu_sysmap_addr5_attr;
input [19 :0] pad_cpu_sysmap_addr6;
input [2 :0] pad_cpu_sysmap_addr6_attr;
input [19 :0] pad_cpu_sysmap_addr7;
input [2 :0] pad_cpu_sysmap_addr7_attr;
input [31 :0] pad_cpu_tcip_base;
input pad_cpu_wakeup_event;
input [31 :0] pad_dahbl_hrdata;
input pad_dahbl_hready;
input pad_dahbl_hresp;
input [31 :0] pad_iahbl_hrdata;
input pad_iahbl_hready;
input pad_iahbl_hresp;
input pad_tdt_dm_core_unavail;
input pad_yy_dft_clk_rst_b;
input pad_yy_icg_scan_en;
input pad_yy_scan_enable;
input pad_yy_scan_mode;
input pad_yy_scan_rst_b;
input pll_core_cpuclk;
input sys_apb_clk;
input sys_apb_rst_b;
input [11 :0] tdt_dmi_paddr;
input tdt_dmi_penable;
input tdt_dmi_psel;
input [31 :0] tdt_dmi_pwdata;
input tdt_dmi_pwrite;
output [31 :0] biu_pad_haddr;
output [2 :0] biu_pad_hburst;
output biu_pad_hlock;
output [3 :0] biu_pad_hprot;
output [2 :0] biu_pad_hsize;
output [1 :0] biu_pad_htrans;
output [31 :0] biu_pad_hwdata;
output biu_pad_hwrite;
output [31 :0] cp0_pad_mcause;
output [31 :0] cp0_pad_mintstatus;
output [31 :0] cp0_pad_mstatus;
output cpu_pad_dfs_ack;
output cpu_pad_halted;
output cpu_pad_lockup;
output [1 :0] cpu_pad_soft_rst;
output [31 :0] dahbl_pad_haddr;
output [2 :0] dahbl_pad_hburst;
output dahbl_pad_hlock;
output [3 :0] dahbl_pad_hprot;
output [2 :0] dahbl_pad_hsize;
output [1 :0] dahbl_pad_htrans;
output [31 :0] dahbl_pad_hwdata;
output dahbl_pad_hwrite;
output [31 :0] iahbl_pad_haddr;
output [2 :0] iahbl_pad_hburst;
output iahbl_pad_hlock;
output [3 :0] iahbl_pad_hprot;
output [2 :0] iahbl_pad_hsize;
output [1 :0] iahbl_pad_htrans;
output [31 :0] iahbl_pad_hwdata;
output iahbl_pad_hwrite;
output rtu_pad_inst_retire;
output rtu_pad_inst_split;
output [31 :0] rtu_pad_retire_pc;
output [31 :0] rtu_pad_wb0_data;
output [5 :0] rtu_pad_wb0_preg;
output rtu_pad_wb0_vld;
output [31 :0] rtu_pad_wb1_data;
output [5 :0] rtu_pad_wb1_preg;
output rtu_pad_wb1_vld;
output [31 :0] rtu_pad_wb2_data;
output [5 :0] rtu_pad_wb2_preg;
output rtu_pad_wb2_vld;
output [4 :0] rtu_pad_wb_freg;
output [31 :0] rtu_pad_wb_freg_data;
output rtu_pad_wb_freg_vld;
output [1 :0] sysio_pad_lpmd_b;
output tdt_dm_pad_hartreset_n;
output tdt_dm_pad_ndmreset_n;
output [31 :0] tdt_dmi_prdata;
output tdt_dmi_pready;
output tdt_dmi_pslverr;
//&Ports;
// &Regs; @36
// &Wires; @37
wire [31 :0] biu_pad_haddr;
wire [2 :0] biu_pad_hburst;
wire biu_pad_hlock;
wire [3 :0] biu_pad_hprot;
wire [2 :0] biu_pad_hsize;
wire [1 :0] biu_pad_htrans;
wire [31 :0] biu_pad_hwdata;
wire biu_pad_hwrite;
wire bmu_tcipif_dbus_acc_deny;
wire [31 :0] bmu_tcipif_dbus_addr;
wire bmu_tcipif_dbus_req;
wire bmu_tcipif_dbus_req_dp;
wire [1 :0] bmu_tcipif_dbus_size;
wire bmu_tcipif_dbus_supv_mode;
wire [31 :0] bmu_tcipif_dbus_wdata;
wire bmu_tcipif_dbus_write;
wire bmu_tcipif_ibus_acc_deny;
wire [31 :0] bmu_tcipif_ibus_addr;
wire bmu_tcipif_ibus_req;
wire bmu_tcipif_ibus_req_dp;
wire [1 :0] bmu_tcipif_ibus_size;
wire bmu_tcipif_ibus_supv_mode;
wire [31 :0] bmu_tcipif_ibus_wdata;
wire bmu_tcipif_ibus_write;
wire clic_cpu_int_hv;
wire [11 :0] clic_cpu_int_id;
wire [7 :0] clic_cpu_int_il;
wire [1 :0] clic_cpu_int_priv;
wire clk_en;
wire clk_en_f;
wire cp0_biu_icg_en;
wire [31 :0] cp0_pad_mcause;
wire [31 :0] cp0_pad_mintstatus;
wire [31 :0] cp0_pad_mstatus;
wire [1 :0] cp0_yy_priv_mode;
wire [11 :0] cpu_clic_curid;
wire cpu_clic_int_exit;
wire cpu_pad_dfs_ack;
wire cpu_pad_halted;
wire cpu_pad_lockup;
wire [1 :0] cpu_pad_soft_rst;
wire cpurst_b;
wire [31 :0] dahbl_pad_haddr;
wire [2 :0] dahbl_pad_hburst;
wire dahbl_pad_hlock;
wire [3 :0] dahbl_pad_hprot;
wire [2 :0] dahbl_pad_hsize;
wire [1 :0] dahbl_pad_htrans;
wire [31 :0] dahbl_pad_hwdata;
wire dahbl_pad_hwrite;
wire dtu_tdt_dm_halted;
wire dtu_tdt_dm_havereset;
wire dtu_tdt_dm_itr_done;
wire dtu_tdt_dm_retire_debug_expt_vld;
wire [31 :0] dtu_tdt_dm_rx_data;
wire dtu_tdt_dm_wr_ready;
wire forever_cpuclk;
wire [31 :0] iahbl_pad_haddr;
wire [2 :0] iahbl_pad_hburst;
wire iahbl_pad_hlock;
wire [3 :0] iahbl_pad_hprot;
wire [2 :0] iahbl_pad_hsize;
wire [1 :0] iahbl_pad_htrans;
wire [31 :0] iahbl_pad_hwdata;
wire iahbl_pad_hwrite;
wire ifu_clic_warm_up;
wire [31 :0] pad_biu_hrdata;
wire pad_biu_hready;
wire pad_biu_hresp;
wire [11 :0] pad_bmu_dahbl_base;
wire [11 :0] pad_bmu_dahbl_mask;
wire [11 :0] pad_bmu_iahbl_base;
wire [11 :0] pad_bmu_iahbl_mask;
wire [127:0] pad_clic_int_vld;
wire pad_cpu_dfs_req;
wire pad_cpu_ext_int_b;
wire pad_cpu_nmi;
wire [31 :0] pad_cpu_rst_addr;
wire pad_cpu_rst_b;
wire [63 :0] pad_cpu_sys_cnt;
wire [19 :0] pad_cpu_sysmap_addr0;
wire [2 :0] pad_cpu_sysmap_addr0_attr;
wire [19 :0] pad_cpu_sysmap_addr1;
wire [2 :0] pad_cpu_sysmap_addr1_attr;
wire [19 :0] pad_cpu_sysmap_addr2;
wire [2 :0] pad_cpu_sysmap_addr2_attr;
wire [19 :0] pad_cpu_sysmap_addr3;
wire [2 :0] pad_cpu_sysmap_addr3_attr;
wire [19 :0] pad_cpu_sysmap_addr4;
wire [2 :0] pad_cpu_sysmap_addr4_attr;
wire [19 :0] pad_cpu_sysmap_addr5;
wire [2 :0] pad_cpu_sysmap_addr5_attr;
wire [19 :0] pad_cpu_sysmap_addr6;
wire [2 :0] pad_cpu_sysmap_addr6_attr;
wire [19 :0] pad_cpu_sysmap_addr7;
wire [2 :0] pad_cpu_sysmap_addr7_attr;
wire [31 :0] pad_cpu_tcip_base;
wire pad_cpu_wakeup_event;
wire [31 :0] pad_dahbl_hrdata;
wire pad_dahbl_hready;
wire pad_dahbl_hresp;
wire [31 :0] pad_iahbl_hrdata;
wire pad_iahbl_hready;
wire pad_iahbl_hresp;
wire pad_tdt_dm_core_unavail;
wire pad_yy_dft_clk_rst_b;
wire pad_yy_icg_scan_en;
wire pad_yy_scan_mode;
wire pad_yy_scan_rst_b;
wire pll_core_cpuclk;
wire rtu_pad_inst_retire;
wire rtu_pad_inst_split;
wire [31 :0] rtu_pad_retire_pc;
wire [31 :0] rtu_pad_wb0_data;
wire [5 :0] rtu_pad_wb0_preg;
wire rtu_pad_wb0_vld;
wire [31 :0] rtu_pad_wb1_data;
wire [5 :0] rtu_pad_wb1_preg;
wire rtu_pad_wb1_vld;
wire [31 :0] rtu_pad_wb2_data;
wire [5 :0] rtu_pad_wb2_preg;
wire rtu_pad_wb2_vld;
wire [4 :0] rtu_pad_wb_freg;
wire [31 :0] rtu_pad_wb_freg_data;
wire rtu_pad_wb_freg_vld;
wire rtu_yy_xx_dbgon;
wire sync_sys_apb_rst_b;
wire sys_apb_clk;
wire sys_apb_rst_b;
wire sysio_clint_me_int;
wire [63 :0] sysio_clint_mtime;
wire [1 :0] sysio_pad_lpmd_b;
wire sysmap_tcipif_cmplt;
wire [31 :0] sysmap_tcipif_rdata;
wire [31 :0] tcip_cp0_clic_base;
wire tcipif_bmu_dbus_acc_err;
wire [31 :0] tcipif_bmu_dbus_data;
wire tcipif_bmu_dbus_grnt;
wire tcipif_bmu_dbus_trans_cmplt;
wire tcipif_bmu_ibus_acc_err;
wire [31 :0] tcipif_bmu_ibus_data;
wire tcipif_bmu_ibus_grnt;
wire tcipif_bmu_ibus_trans_cmplt;
wire [15 :0] tcipif_sysmap_addr;
wire tcipif_sysmap_sel;
wire [31 :0] tcipif_sysmap_wdata;
wire tcipif_sysmap_write;
wire tdt_dm_dtu_ack_havereset;
wire tdt_dm_dtu_async_halt_req;
wire tdt_dm_dtu_halt_on_reset;
wire tdt_dm_dtu_halt_req;
wire [1 :0] tdt_dm_dtu_halt_req_cause;
wire [31 :0] tdt_dm_dtu_itr;
wire tdt_dm_dtu_itr_vld;
wire tdt_dm_dtu_resume_req;
wire [31 :0] tdt_dm_dtu_wdata;
wire [1 :0] tdt_dm_dtu_wr_flg;
wire tdt_dm_dtu_wr_vld;
wire tdt_dm_pad_hartreset_n;
wire tdt_dm_pad_ndmreset_n;
wire [11 :0] tdt_dmi_paddr;
wire tdt_dmi_penable;
wire [31 :0] tdt_dmi_prdata;
wire tdt_dmi_pready;
wire tdt_dmi_psel;
wire tdt_dmi_pslverr;
wire [31 :0] tdt_dmi_pwdata;
wire tdt_dmi_pwrite;
// &Force("input","pad_yy_scan_enable"); @39
//==========================================================
// Instance 906 core top module
//==========================================================
// &Instance("pa_core_top"); @43
pa_core_top x_pa_core_top (
.biu_pad_haddr (biu_pad_haddr ),
.biu_pad_hburst (biu_pad_hburst ),
.biu_pad_hlock (biu_pad_hlock ),
.biu_pad_hprot (biu_pad_hprot ),
.biu_pad_hsize (biu_pad_hsize ),
.biu_pad_htrans (biu_pad_htrans ),
.biu_pad_hwdata (biu_pad_hwdata ),
.biu_pad_hwrite (biu_pad_hwrite ),
.bmu_tcipif_dbus_acc_deny (bmu_tcipif_dbus_acc_deny ),
.bmu_tcipif_dbus_addr (bmu_tcipif_dbus_addr ),
.bmu_tcipif_dbus_req (bmu_tcipif_dbus_req ),
.bmu_tcipif_dbus_req_dp (bmu_tcipif_dbus_req_dp ),
.bmu_tcipif_dbus_size (bmu_tcipif_dbus_size ),
.bmu_tcipif_dbus_supv_mode (bmu_tcipif_dbus_supv_mode ),
.bmu_tcipif_dbus_wdata (bmu_tcipif_dbus_wdata ),
.bmu_tcipif_dbus_write (bmu_tcipif_dbus_write ),
.bmu_tcipif_ibus_acc_deny (bmu_tcipif_ibus_acc_deny ),
.bmu_tcipif_ibus_addr (bmu_tcipif_ibus_addr ),
.bmu_tcipif_ibus_req (bmu_tcipif_ibus_req ),
.bmu_tcipif_ibus_req_dp (bmu_tcipif_ibus_req_dp ),
.bmu_tcipif_ibus_size (bmu_tcipif_ibus_size ),
.bmu_tcipif_ibus_supv_mode (bmu_tcipif_ibus_supv_mode ),
.bmu_tcipif_ibus_wdata (bmu_tcipif_ibus_wdata ),
.bmu_tcipif_ibus_write (bmu_tcipif_ibus_write ),
.clic_cpu_int_hv (clic_cpu_int_hv ),
.clic_cpu_int_id (clic_cpu_int_id ),
.clic_cpu_int_il (clic_cpu_int_il ),
.clic_cpu_int_priv (clic_cpu_int_priv ),
.clk_en_f (clk_en_f ),
.cp0_biu_icg_en (cp0_biu_icg_en ),
.cp0_pad_mcause (cp0_pad_mcause ),
.cp0_pad_mintstatus (cp0_pad_mintstatus ),
.cp0_pad_mstatus (cp0_pad_mstatus ),
.cp0_yy_priv_mode (cp0_yy_priv_mode ),
.cpu_clic_curid (cpu_clic_curid ),
.cpu_clic_int_exit (cpu_clic_int_exit ),
.cpu_pad_dfs_ack (cpu_pad_dfs_ack ),
.cpu_pad_halted (cpu_pad_halted ),
.cpu_pad_lockup (cpu_pad_lockup ),
.cpu_pad_soft_rst (cpu_pad_soft_rst ),
.cpurst_b (cpurst_b ),
.dahbl_pad_haddr (dahbl_pad_haddr ),
.dahbl_pad_hburst (dahbl_pad_hburst ),
.dahbl_pad_hlock (dahbl_pad_hlock ),
.dahbl_pad_hprot (dahbl_pad_hprot ),
.dahbl_pad_hsize (dahbl_pad_hsize ),
.dahbl_pad_htrans (dahbl_pad_htrans ),
.dahbl_pad_hwdata (dahbl_pad_hwdata ),
.dahbl_pad_hwrite (dahbl_pad_hwrite ),
.dtu_tdt_dm_halted (dtu_tdt_dm_halted ),
.dtu_tdt_dm_havereset (dtu_tdt_dm_havereset ),
.dtu_tdt_dm_itr_done (dtu_tdt_dm_itr_done ),
.dtu_tdt_dm_retire_debug_expt_vld (dtu_tdt_dm_retire_debug_expt_vld),
.dtu_tdt_dm_rx_data (dtu_tdt_dm_rx_data ),
.dtu_tdt_dm_wr_ready (dtu_tdt_dm_wr_ready ),
.forever_cpuclk (forever_cpuclk ),
.iahbl_pad_haddr (iahbl_pad_haddr ),
.iahbl_pad_hburst (iahbl_pad_hburst ),
.iahbl_pad_hlock (iahbl_pad_hlock ),
.iahbl_pad_hprot (iahbl_pad_hprot ),
.iahbl_pad_hsize (iahbl_pad_hsize ),
.iahbl_pad_htrans (iahbl_pad_htrans ),
.iahbl_pad_hwdata (iahbl_pad_hwdata ),
.iahbl_pad_hwrite (iahbl_pad_hwrite ),
.ifu_clic_warm_up (ifu_clic_warm_up ),
.pad_biu_hrdata (pad_biu_hrdata ),
.pad_biu_hready (pad_biu_hready ),
.pad_biu_hresp (pad_biu_hresp ),
.pad_bmu_dahbl_base (pad_bmu_dahbl_base ),
.pad_bmu_dahbl_mask (pad_bmu_dahbl_mask ),
.pad_bmu_iahbl_base (pad_bmu_iahbl_base ),
.pad_bmu_iahbl_mask (pad_bmu_iahbl_mask ),
.pad_cpu_dfs_req (pad_cpu_dfs_req ),
.pad_cpu_ext_int_b (pad_cpu_ext_int_b ),
.pad_cpu_nmi (pad_cpu_nmi ),
.pad_cpu_rst_addr (pad_cpu_rst_addr ),
.pad_cpu_sys_cnt (pad_cpu_sys_cnt ),
.pad_cpu_sysmap_addr0 (pad_cpu_sysmap_addr0 ),
.pad_cpu_sysmap_addr0_attr (pad_cpu_sysmap_addr0_attr ),
.pad_cpu_sysmap_addr1 (pad_cpu_sysmap_addr1 ),
.pad_cpu_sysmap_addr1_attr (pad_cpu_sysmap_addr1_attr ),
.pad_cpu_sysmap_addr2 (pad_cpu_sysmap_addr2 ),
.pad_cpu_sysmap_addr2_attr (pad_cpu_sysmap_addr2_attr ),
.pad_cpu_sysmap_addr3 (pad_cpu_sysmap_addr3 ),
.pad_cpu_sysmap_addr3_attr (pad_cpu_sysmap_addr3_attr ),
.pad_cpu_sysmap_addr4 (pad_cpu_sysmap_addr4 ),
.pad_cpu_sysmap_addr4_attr (pad_cpu_sysmap_addr4_attr ),
.pad_cpu_sysmap_addr5 (pad_cpu_sysmap_addr5 ),
.pad_cpu_sysmap_addr5_attr (pad_cpu_sysmap_addr5_attr ),
.pad_cpu_sysmap_addr6 (pad_cpu_sysmap_addr6 ),
.pad_cpu_sysmap_addr6_attr (pad_cpu_sysmap_addr6_attr ),
.pad_cpu_sysmap_addr7 (pad_cpu_sysmap_addr7 ),
.pad_cpu_sysmap_addr7_attr (pad_cpu_sysmap_addr7_attr ),
.pad_cpu_tcip_base (pad_cpu_tcip_base ),
.pad_cpu_wakeup_event (pad_cpu_wakeup_event ),
.pad_dahbl_hrdata (pad_dahbl_hrdata ),
.pad_dahbl_hready (pad_dahbl_hready ),
.pad_dahbl_hresp (pad_dahbl_hresp ),
.pad_iahbl_hrdata (pad_iahbl_hrdata ),
.pad_iahbl_hready (pad_iahbl_hready ),
.pad_iahbl_hresp (pad_iahbl_hresp ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_pad_inst_retire (rtu_pad_inst_retire ),
.rtu_pad_inst_split (rtu_pad_inst_split ),
.rtu_pad_retire_pc (rtu_pad_retire_pc ),
.rtu_pad_wb0_data (rtu_pad_wb0_data ),
.rtu_pad_wb0_preg (rtu_pad_wb0_preg ),
.rtu_pad_wb0_vld (rtu_pad_wb0_vld ),
.rtu_pad_wb1_data (rtu_pad_wb1_data ),
.rtu_pad_wb1_preg (rtu_pad_wb1_preg ),
.rtu_pad_wb1_vld (rtu_pad_wb1_vld ),
.rtu_pad_wb2_data (rtu_pad_wb2_data ),
.rtu_pad_wb2_preg (rtu_pad_wb2_preg ),
.rtu_pad_wb2_vld (rtu_pad_wb2_vld ),
.rtu_pad_wb_freg (rtu_pad_wb_freg ),
.rtu_pad_wb_freg_data (rtu_pad_wb_freg_data ),
.rtu_pad_wb_freg_vld (rtu_pad_wb_freg_vld ),
.rtu_yy_xx_dbgon (rtu_yy_xx_dbgon ),
.sys_apb_clk (sys_apb_clk ),
.sys_apb_rst_b (sync_sys_apb_rst_b ),
.sysio_clint_me_int (sysio_clint_me_int ),
.sysio_clint_mtime (sysio_clint_mtime ),
.sysio_pad_lpmd_b (sysio_pad_lpmd_b ),
.sysmap_tcipif_cmplt (sysmap_tcipif_cmplt ),
.sysmap_tcipif_rdata (sysmap_tcipif_rdata ),
.tcip_cp0_clic_base (tcip_cp0_clic_base ),
.tcipif_bmu_dbus_acc_err (tcipif_bmu_dbus_acc_err ),
.tcipif_bmu_dbus_data (tcipif_bmu_dbus_data ),
.tcipif_bmu_dbus_grnt (tcipif_bmu_dbus_grnt ),
.tcipif_bmu_dbus_trans_cmplt (tcipif_bmu_dbus_trans_cmplt ),
.tcipif_bmu_ibus_acc_err (tcipif_bmu_ibus_acc_err ),
.tcipif_bmu_ibus_data (tcipif_bmu_ibus_data ),
.tcipif_bmu_ibus_grnt (tcipif_bmu_ibus_grnt ),
.tcipif_bmu_ibus_trans_cmplt (tcipif_bmu_ibus_trans_cmplt ),
.tcipif_sysmap_addr (tcipif_sysmap_addr ),
.tcipif_sysmap_sel (tcipif_sysmap_sel ),
.tcipif_sysmap_wdata (tcipif_sysmap_wdata ),
.tcipif_sysmap_write (tcipif_sysmap_write ),
.tdt_dm_dtu_ack_havereset (tdt_dm_dtu_ack_havereset ),
.tdt_dm_dtu_async_halt_req (tdt_dm_dtu_async_halt_req ),
.tdt_dm_dtu_halt_on_reset (tdt_dm_dtu_halt_on_reset ),
.tdt_dm_dtu_halt_req (tdt_dm_dtu_halt_req ),
.tdt_dm_dtu_itr (tdt_dm_dtu_itr ),
.tdt_dm_dtu_itr_vld (tdt_dm_dtu_itr_vld ),
.tdt_dm_dtu_resume_req (tdt_dm_dtu_resume_req ),
.tdt_dm_dtu_wdata (tdt_dm_dtu_wdata ),
.tdt_dm_dtu_wr_flg (tdt_dm_dtu_wr_flg ),
.tdt_dm_dtu_wr_vld (tdt_dm_dtu_wr_vld )
);
// &Connect(.sys_apb_rst_b (sync_sys_apb_rst_b)); @44
//==========================================================
// TDT
//==========================================================
// &Instance("tdt_top"); @50
tdt_top x_tdt_top (
.ciu_rst_b (cpurst_b ),
.dtu_tdt_dm_halted (dtu_tdt_dm_halted ),
.dtu_tdt_dm_havereset (dtu_tdt_dm_havereset ),
.dtu_tdt_dm_itr_done (dtu_tdt_dm_itr_done ),
.dtu_tdt_dm_retire_debug_expt_vld (dtu_tdt_dm_retire_debug_expt_vld),
.dtu_tdt_dm_rx_data (dtu_tdt_dm_rx_data ),
.dtu_tdt_dm_wr_ready (dtu_tdt_dm_wr_ready ),
.forever_cpuclk (forever_cpuclk ),
.pad_tdt_dm_core_unavail (pad_tdt_dm_core_unavail ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.pad_yy_scan_mode (pad_yy_scan_mode ),
.pad_yy_scan_rst_b (pad_yy_scan_rst_b ),
.sys_apb_clk (sys_apb_clk ),
.sys_apb_rst_b (sync_sys_apb_rst_b ),
.sys_bus_clk_en (clk_en_f ),
.tdt_dm_dtu_ack_havereset (tdt_dm_dtu_ack_havereset ),
.tdt_dm_dtu_async_halt_req (tdt_dm_dtu_async_halt_req ),
.tdt_dm_dtu_halt_on_reset (tdt_dm_dtu_halt_on_reset ),
.tdt_dm_dtu_halt_req (tdt_dm_dtu_halt_req ),
.tdt_dm_dtu_halt_req_cause (tdt_dm_dtu_halt_req_cause ),
.tdt_dm_dtu_itr (tdt_dm_dtu_itr ),
.tdt_dm_dtu_itr_vld (tdt_dm_dtu_itr_vld ),
.tdt_dm_dtu_resume_req (tdt_dm_dtu_resume_req ),
.tdt_dm_dtu_wdata (tdt_dm_dtu_wdata ),
.tdt_dm_dtu_wr_flg (tdt_dm_dtu_wr_flg ),
.tdt_dm_dtu_wr_vld (tdt_dm_dtu_wr_vld ),
.tdt_dm_pad_hartreset_n (tdt_dm_pad_hartreset_n ),
.tdt_dm_pad_ndmreset_n (tdt_dm_pad_ndmreset_n ),
.tdt_dmi_paddr (tdt_dmi_paddr ),
.tdt_dmi_penable (tdt_dmi_penable ),
.tdt_dmi_prdata (tdt_dmi_prdata ),
.tdt_dmi_pready (tdt_dmi_pready ),
.tdt_dmi_psel (tdt_dmi_psel ),
.tdt_dmi_pslverr (tdt_dmi_pslverr ),
.tdt_dmi_pwdata (tdt_dmi_pwdata ),
.tdt_dmi_pwrite (tdt_dmi_pwrite )
);
// &Connect(.ciu_rst_b (cpurst_b)); @51
// &Connect(.sys_apb_clk (sys_apb_clk)); @52
// &Connect(.sys_apb_rst_b (sync_sys_apb_rst_b)); @53
// &Connect(.sys_bus_clk_en (axim_clk_en_f)); @55
// &Connect(.sys_bus_clk_en (clk_en_f)); @57
//scan chain
//make sure whether to delete this pin
// &Force("nonport", "tdt_dm_dtu_halt_req_cause"); @61
// &Instance("tdt_top_dummy"); @63
// &Connect(.ciu_rst_b (cpurst_b)); @64
// &Connect(.sys_apb_clk (sys_apb_clk)); @65
// &Connect(.sys_apb_rst_b (sys_apb_rst_b)); @66
// &Connect(.sys_bus_clk_en (1'b0)); @67
// &Force("nonport", "tdt_dm_dtu_halt_req_cause"); @69
//==========================================================
// Instance CLOCK and RST module
//==========================================================
// &Instance("pa_clkrst_top"); @74
pa_clkrst_top x_pa_clkrst_top (
.clk_en (clk_en ),
.clk_en_f (clk_en_f ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.pad_yy_scan_mode (pad_yy_scan_mode ),
.pad_yy_scan_rst_b (pad_yy_scan_rst_b ),
.pll_core_cpuclk (pll_core_cpuclk ),
.sync_sys_apb_rst_b (sync_sys_apb_rst_b),
.sys_apb_clk (sys_apb_clk ),
.sys_apb_rst_b (sys_apb_rst_b )
);
//==========================================================
// Instance TCIPIF module
//==========================================================
// &Instance("pa_tcipif_top"); @80
pa_tcipif_top x_pa_tcipif_top (
.bmu_tcipif_dbus_acc_deny (bmu_tcipif_dbus_acc_deny ),
.bmu_tcipif_dbus_addr (bmu_tcipif_dbus_addr ),
.bmu_tcipif_dbus_req (bmu_tcipif_dbus_req ),
.bmu_tcipif_dbus_req_dp (bmu_tcipif_dbus_req_dp ),
.bmu_tcipif_dbus_size (bmu_tcipif_dbus_size ),
.bmu_tcipif_dbus_supv_mode (bmu_tcipif_dbus_supv_mode ),
.bmu_tcipif_dbus_wdata (bmu_tcipif_dbus_wdata ),
.bmu_tcipif_dbus_write (bmu_tcipif_dbus_write ),
.bmu_tcipif_ibus_acc_deny (bmu_tcipif_ibus_acc_deny ),
.bmu_tcipif_ibus_addr (bmu_tcipif_ibus_addr ),
.bmu_tcipif_ibus_req (bmu_tcipif_ibus_req ),
.bmu_tcipif_ibus_req_dp (bmu_tcipif_ibus_req_dp ),
.bmu_tcipif_ibus_size (bmu_tcipif_ibus_size ),
.bmu_tcipif_ibus_supv_mode (bmu_tcipif_ibus_supv_mode ),
.bmu_tcipif_ibus_wdata (bmu_tcipif_ibus_wdata ),
.bmu_tcipif_ibus_write (bmu_tcipif_ibus_write ),
.clic_cpu_int_hv (clic_cpu_int_hv ),
.clic_cpu_int_id (clic_cpu_int_id ),
.clic_cpu_int_il (clic_cpu_int_il ),
.clic_cpu_int_priv (clic_cpu_int_priv ),
.cp0_biu_icg_en (cp0_biu_icg_en ),
.cp0_yy_priv_mode (cp0_yy_priv_mode ),
.cpu_clic_curid (cpu_clic_curid ),
.cpu_clic_int_exit (cpu_clic_int_exit ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ifu_clic_warm_up (ifu_clic_warm_up ),
.pad_clic_int_vld (pad_clic_int_vld ),
.pad_cpu_tcip_base (pad_cpu_tcip_base ),
.pad_yy_dft_clk_rst_b (pad_yy_dft_clk_rst_b ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.pad_yy_scan_mode (pad_yy_scan_mode ),
.rtu_yy_xx_dbgon (rtu_yy_xx_dbgon ),
.sysio_clint_me_int (sysio_clint_me_int ),
.sysio_clint_mtime (sysio_clint_mtime ),
.sysmap_tcipif_cmplt (sysmap_tcipif_cmplt ),
.sysmap_tcipif_rdata (sysmap_tcipif_rdata ),
.tcip_cp0_clic_base (tcip_cp0_clic_base ),
.tcipif_bmu_dbus_acc_err (tcipif_bmu_dbus_acc_err ),
.tcipif_bmu_dbus_data (tcipif_bmu_dbus_data ),
.tcipif_bmu_dbus_grnt (tcipif_bmu_dbus_grnt ),
.tcipif_bmu_dbus_trans_cmplt (tcipif_bmu_dbus_trans_cmplt),
.tcipif_bmu_ibus_acc_err (tcipif_bmu_ibus_acc_err ),
.tcipif_bmu_ibus_data (tcipif_bmu_ibus_data ),
.tcipif_bmu_ibus_grnt (tcipif_bmu_ibus_grnt ),
.tcipif_bmu_ibus_trans_cmplt (tcipif_bmu_ibus_trans_cmplt),
.tcipif_sysmap_addr (tcipif_sysmap_addr ),
.tcipif_sysmap_sel (tcipif_sysmap_sel ),
.tcipif_sysmap_wdata (tcipif_sysmap_wdata ),
.tcipif_sysmap_write (tcipif_sysmap_write )
);
// &Instance("pa_tcipif_top_dummy"); @82
// &Force("input", "pad_cpu_nmi"); @90
// &Force("input", "pad_cpu_rst_addr"); &Force("bus", "pad_cpu_rst_addr", 31, 0); @91
// &Force("input", "pad_cpu_wakeup_event"); @92
// &Force("nonport", "sysio_pad_srst"); @94
// &Force("output","biu_pad_arvalid"); @98
// &Force("output","biu_pad_rready"); @99
// &Force("output","biu_pad_awvalid"); @100
// &Force("output","biu_pad_bready"); @101
// &Force("output","cpu_pad_dfs_ack"); @102
// &Force("output","pahbl_pad_htrans"); @103
// &Force("input","pad_biu_arready"); @104
// &Force("input","pad_biu_rvalid"); @105
// &Force("input","pad_biu_rlast"); @106
// &Force("input","pad_pahbl_hready"); @107
// &Force("input","pad_biu_bvalid"); @108
// &Force("input","pad_biu_awready"); @109
// &Force("nonport","fencei_icache_inv_done"); @184
// &Force("nonport","lpmd_all_done"); @185
// &Force("nonport","srst_special_srst_cmplt"); @186
// &ModuleEnd; @191
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_cpu_top_golden_port(
biu_pad_haddr,
biu_pad_hburst,
biu_pad_hlock,
biu_pad_hprot,
biu_pad_hsize,
biu_pad_htrans,
biu_pad_hwdata,
biu_pad_hwrite,
clk_en,
cp0_pad_mcause,
cp0_pad_mintstatus,
cp0_pad_mstatus,
cpu_pad_dfs_ack,
cpu_pad_halted,
cpu_pad_lockup,
cpu_pad_soft_rst,
dahbl_pad_haddr,
dahbl_pad_hburst,
dahbl_pad_hlock,
dahbl_pad_hprot,
dahbl_pad_hsize,
dahbl_pad_htrans,
dahbl_pad_hwdata,
dahbl_pad_hwrite,
iahbl_pad_haddr,
iahbl_pad_hburst,
iahbl_pad_hlock,
iahbl_pad_hprot,
iahbl_pad_hsize,
iahbl_pad_htrans,
iahbl_pad_hwdata,
iahbl_pad_hwrite,
pad_biu_hrdata,
pad_biu_hready,
pad_biu_hresp,
pad_bmu_dahbl_base,
pad_bmu_dahbl_mask,
pad_bmu_iahbl_base,
pad_bmu_iahbl_mask,
pad_clic_int_vld,
pad_cpu_dfs_req,
pad_cpu_ext_int_b,
pad_cpu_nmi,
pad_cpu_rst_addr,
pad_cpu_rst_b,
pad_cpu_sys_cnt,
pad_cpu_sysmap_addr0,
pad_cpu_sysmap_addr0_attr,
pad_cpu_sysmap_addr1,
pad_cpu_sysmap_addr1_attr,
pad_cpu_sysmap_addr2,
pad_cpu_sysmap_addr2_attr,
pad_cpu_sysmap_addr3,
pad_cpu_sysmap_addr3_attr,
pad_cpu_sysmap_addr4,
pad_cpu_sysmap_addr4_attr,
pad_cpu_sysmap_addr5,
pad_cpu_sysmap_addr5_attr,
pad_cpu_sysmap_addr6,
pad_cpu_sysmap_addr6_attr,
pad_cpu_sysmap_addr7,
pad_cpu_sysmap_addr7_attr,
pad_cpu_tcip_base,
pad_cpu_wakeup_event,
pad_dahbl_hrdata,
pad_dahbl_hready,
pad_dahbl_hresp,
pad_iahbl_hrdata,
pad_iahbl_hready,
pad_iahbl_hresp,
pad_tdt_dm_core_unavail,
pad_yy_dft_clk_rst_b,
pad_yy_icg_scan_en,
pad_yy_scan_enable,
pad_yy_scan_mode,
pad_yy_scan_rst_b,
pll_core_cpuclk,
rtu_pad_inst_retire,
rtu_pad_inst_split,
rtu_pad_retire_pc,
rtu_pad_wb0_data,
rtu_pad_wb0_preg,
rtu_pad_wb0_vld,
rtu_pad_wb1_data,
rtu_pad_wb1_preg,
rtu_pad_wb1_vld,
rtu_pad_wb2_data,
rtu_pad_wb2_preg,
rtu_pad_wb2_vld,
rtu_pad_wb_freg,
rtu_pad_wb_freg_data,
rtu_pad_wb_freg_vld,
sys_apb_clk,
sys_apb_rst_b,
sysio_pad_lpmd_b,
tdt_dm_pad_hartreset_n,
tdt_dm_pad_ndmreset_n,
tdt_dmi_paddr,
tdt_dmi_penable,
tdt_dmi_prdata,
tdt_dmi_pready,
tdt_dmi_psel,
tdt_dmi_pslverr,
tdt_dmi_pwdata,
tdt_dmi_pwrite
);
// &Ports @3
input clk_en;
input [31 :0] pad_biu_hrdata;
input pad_biu_hready;
input pad_biu_hresp;
input [11 :0] pad_bmu_dahbl_base;
input [11 :0] pad_bmu_dahbl_mask;
input [11 :0] pad_bmu_iahbl_base;
input [11 :0] pad_bmu_iahbl_mask;
input [127:0] pad_clic_int_vld;
input pad_cpu_dfs_req;
input pad_cpu_ext_int_b;
input pad_cpu_nmi;
input [31 :0] pad_cpu_rst_addr;
input pad_cpu_rst_b;
input [63 :0] pad_cpu_sys_cnt;
input [19 :0] pad_cpu_sysmap_addr0;
input [2 :0] pad_cpu_sysmap_addr0_attr;
input [19 :0] pad_cpu_sysmap_addr1;
input [2 :0] pad_cpu_sysmap_addr1_attr;
input [19 :0] pad_cpu_sysmap_addr2;
input [2 :0] pad_cpu_sysmap_addr2_attr;
input [19 :0] pad_cpu_sysmap_addr3;
input [2 :0] pad_cpu_sysmap_addr3_attr;
input [19 :0] pad_cpu_sysmap_addr4;
input [2 :0] pad_cpu_sysmap_addr4_attr;
input [19 :0] pad_cpu_sysmap_addr5;
input [2 :0] pad_cpu_sysmap_addr5_attr;
input [19 :0] pad_cpu_sysmap_addr6;
input [2 :0] pad_cpu_sysmap_addr6_attr;
input [19 :0] pad_cpu_sysmap_addr7;
input [2 :0] pad_cpu_sysmap_addr7_attr;
input [31 :0] pad_cpu_tcip_base;
input pad_cpu_wakeup_event;
input [31 :0] pad_dahbl_hrdata;
input pad_dahbl_hready;
input pad_dahbl_hresp;
input [31 :0] pad_iahbl_hrdata;
input pad_iahbl_hready;
input pad_iahbl_hresp;
input pad_tdt_dm_core_unavail;
input pad_yy_dft_clk_rst_b;
input pad_yy_icg_scan_en;
input pad_yy_scan_enable;
input pad_yy_scan_mode;
input pad_yy_scan_rst_b;
input pll_core_cpuclk;
input sys_apb_clk;
input sys_apb_rst_b;
input [11 :0] tdt_dmi_paddr;
input tdt_dmi_penable;
input tdt_dmi_psel;
input [31 :0] tdt_dmi_pwdata;
input tdt_dmi_pwrite;
output [31 :0] biu_pad_haddr;
output [2 :0] biu_pad_hburst;
output biu_pad_hlock;
output [3 :0] biu_pad_hprot;
output [2 :0] biu_pad_hsize;
output [1 :0] biu_pad_htrans;
output [31 :0] biu_pad_hwdata;
output biu_pad_hwrite;
output [31 :0] cp0_pad_mcause;
output [31 :0] cp0_pad_mintstatus;
output [31 :0] cp0_pad_mstatus;
output cpu_pad_dfs_ack;
output cpu_pad_halted;
output cpu_pad_lockup;
output [1 :0] cpu_pad_soft_rst;
output [31 :0] dahbl_pad_haddr;
output [2 :0] dahbl_pad_hburst;
output dahbl_pad_hlock;
output [3 :0] dahbl_pad_hprot;
output [2 :0] dahbl_pad_hsize;
output [1 :0] dahbl_pad_htrans;
output [31 :0] dahbl_pad_hwdata;
output dahbl_pad_hwrite;
output [31 :0] iahbl_pad_haddr;
output [2 :0] iahbl_pad_hburst;
output iahbl_pad_hlock;
output [3 :0] iahbl_pad_hprot;
output [2 :0] iahbl_pad_hsize;
output [1 :0] iahbl_pad_htrans;
output [31 :0] iahbl_pad_hwdata;
output iahbl_pad_hwrite;
output rtu_pad_inst_retire;
output rtu_pad_inst_split;
output [31 :0] rtu_pad_retire_pc;
output [31 :0] rtu_pad_wb0_data;
output [5 :0] rtu_pad_wb0_preg;
output rtu_pad_wb0_vld;
output [31 :0] rtu_pad_wb1_data;
output [5 :0] rtu_pad_wb1_preg;
output rtu_pad_wb1_vld;
output [31 :0] rtu_pad_wb2_data;
output [5 :0] rtu_pad_wb2_preg;
output rtu_pad_wb2_vld;
output [4 :0] rtu_pad_wb_freg;
output [31 :0] rtu_pad_wb_freg_data;
output rtu_pad_wb_freg_vld;
output [1 :0] sysio_pad_lpmd_b;
output tdt_dm_pad_hartreset_n;
output tdt_dm_pad_ndmreset_n;
output [31 :0] tdt_dmi_prdata;
output tdt_dmi_pready;
output tdt_dmi_pslverr;
// &Force("input", "pad_yy_scan_mode"); @5
// &Force("input", "pad_yy_scan_enable"); @6
// &Force("input", "pad_yy_scan_rst_b"); @8
// &Force("input", "pad_yy_icg_scan_en"); @9
// &Force("input", "pad_yy_gate_clk_en_b"); @11
// &Force("input","mem_cfg_in"); &Force("bus", "mem_cfg_in",`MEM_CFG_IN_WIDTH-1,0); @15
// &Force("input","mem_cfg_in"); &Force("bus", "mem_cfg_in",`MEM_CFG_IN_WIDTH-1,0); @21
// &Force("input","mem_cfg_in"); &Force("bus", "mem_cfg_in",`MEM_CFG_IN_WIDTH-1,0); @27
// &Force("input", "clk_en"); @33
// &Force("input", "ilite_clk_en"); @36
// &Force("input", "dlite_clk_en"); @39
// &Force("input", "pad_bmu_dahbl_base"); &Force("bus", "pad_bmu_dahbl_base", 11, 0); @43
// &Force("input", "pad_bmu_dahbl_mask"); &Force("bus", "pad_bmu_dahbl_mask", 11, 0); @44
// &Force("input", "pad_dahbl_hrdata"); &Force("bus", "pad_dahbl_hrdata", 31, 0); @45
// &Force("input", "pad_dahbl_hready"); @46
// &Force("input", "pad_dahbl_hresp"); @47
// &Force("output", "dahbl_pad_haddr"); &Force("bus", "dahbl_pad_haddr",31,0); @48
// &Force("output", "dahbl_pad_hburst"); &Force("bus", "dahbl_pad_hburst",2,0); @49
// &Force("output", "dahbl_pad_hprot"); &Force("bus", "dahbl_pad_hprot",3,0); @50
// &Force("output", "dahbl_pad_hsize"); &Force("bus", "dahbl_pad_hsize",2,0); @51
// &Force("output", "dahbl_pad_htrans"); &Force("bus", "dahbl_pad_htrans",1,0); @52
// &Force("output", "dahbl_pad_hwdata"); &Force("bus", "dahbl_pad_hwdata",31,0); @53
// &Force("output", "dahbl_pad_hwrite"); @54
// &Force("output", "dahbl_pad_hlock"); @55
// &Force("input", "pad_bmu_iahbl_base"); &Force("bus", "pad_bmu_iahbl_base", 11, 0); @58
// &Force("input", "pad_bmu_iahbl_mask"); &Force("bus", "pad_bmu_iahbl_mask", 11, 0); @59
// &Force("input", "pad_iahbl_hrdata"); &Force("bus", "pad_iahbl_hrdata", 31, 0); @60
// &Force("input", "pad_iahbl_hready"); @61
// &Force("input", "pad_iahbl_hresp"); @62
// &Force("output", "iahbl_pad_haddr"); &Force("bus", "iahbl_pad_haddr",31,0); @63
// &Force("output", "iahbl_pad_hburst"); &Force("bus", "iahbl_pad_hburst",2,0); @64
// &Force("output", "iahbl_pad_hprot"); &Force("bus", "iahbl_pad_hprot",3,0); @65
// &Force("output", "iahbl_pad_hsize"); &Force("bus", "iahbl_pad_hsize",2,0); @66
// &Force("output", "iahbl_pad_htrans"); &Force("bus", "iahbl_pad_htrans",1,0); @67
// &Force("output", "iahbl_pad_hwdata"); &Force("bus", "iahbl_pad_hwdata",31,0); @68
// &Force("output", "iahbl_pad_hwrite"); @69
// &Force("output", "iahbl_pad_hlock"); @70
// &Force("input", "pad_cpu_dfs_req"); @73
// &Force("output", "cpu_pad_dfs_ack"); @74
// &Force("input", "axim_clk_en"); @78
// &Force("input", "pad_biu_arready"); @79
// &Force("input", "pad_biu_awready"); @80
// &Force("input", "pad_biu_wready"); @81
// &Force("input", "pad_biu_rvalid"); @82
// &Force("input", "pad_biu_rlast"); @83
// &Force("input", "pad_biu_rid"); &Force("bus", "pad_biu_rid",7,0); @84
// &Force("input", "pad_biu_rresp"); &Force("bus", "pad_biu_rresp",1,0); @85
// &Force("input", "pad_biu_rdata"); &Force("bus", "pad_biu_rdata",63,0); @86
// &Force("input", "pad_biu_bvalid"); @87
// &Force("input", "pad_biu_bid"); &Force("bus", "pad_biu_bid",7,0); @88
// &Force("input", "pad_biu_bresp"); &Force("bus", "pad_biu_bresp",1,0); @89
// &Force("input", "pad_cpu_tcip_base"); &Force("bus", "pad_cpu_tcip_base",31,0); @90
// &Force("output", "biu_pad_araddr"); &Force("bus", "biu_pad_araddr",31,0); @92
// &Force("output", "biu_pad_arburst"); &Force("bus", "biu_pad_arburst",1,0); @93
// &Force("output", "biu_pad_arcache"); &Force("bus", "biu_pad_arcache",3,0); @94
// &Force("output", "biu_pad_arid"); &Force("bus", "biu_pad_arid",7,0); @95
// &Force("output", "biu_pad_arlen"); &Force("bus", "biu_pad_arlen",7,0); @96
// &Force("output", "biu_pad_arlock"); @97
// &Force("output", "biu_pad_arprot"); &Force("bus", "biu_pad_arprot",2,0); @98
// &Force("output", "biu_pad_arsize"); &Force("bus", "biu_pad_arsize",2,0); @99
// &Force("output", "biu_pad_arvalid"); @100
// &Force("output", "biu_pad_awaddr"); &Force("bus", "biu_pad_awaddr",31,0); @101
// &Force("output", "biu_pad_awburst"); &Force("bus", "biu_pad_awburst",1,0); @102
// &Force("output", "biu_pad_awcache"); &Force("bus", "biu_pad_awcache",3,0); @103
// &Force("output", "biu_pad_awid"); &Force("bus", "biu_pad_awid",7,0); @104
// &Force("output", "biu_pad_awlen"); &Force("bus", "biu_pad_awlen",7,0); @105
// &Force("output", "biu_pad_awlock"); @106
// &Force("output", "biu_pad_awprot"); &Force("bus", "biu_pad_awprot",2,0); @107
// &Force("output", "biu_pad_awsize"); &Force("bus", "biu_pad_awsize",2,0); @108
// &Force("output", "biu_pad_awvalid"); @109
// &Force("output", "biu_pad_bready"); @110
// &Force("output", "biu_pad_rready"); @111
// &Force("output", "biu_pad_wdata"); &Force("bus", "biu_pad_wdata",63,0); @112
// &Force("output", "biu_pad_wlast"); @113
// &Force("output", "biu_pad_wstrb"); &Force("bus", "biu_pad_wstrb",7,0); @114
// &Force("output", "biu_pad_wvalid"); @115
// &Force("input", "pahbl_clk_en"); @118
// &Force("input", "pad_cpu_pahbl_base"); &Force("bus", "pad_cpu_pahbl_base", 11, 0); @119
// &Force("input", "pad_cpu_pahbl_mask"); &Force("bus", "pad_cpu_pahbl_mask", 11, 0); @120
// &Force("input", "pad_pahbl_hrdata"); &Force("bus", "pad_pahbl_hrdata", 31, 0); @121
// &Force("input", "pad_pahbl_hready"); @122
// &Force("input", "pad_pahbl_hresp"); @123
// &Force("input", "pad_pahbl_hexok"); @124
// &Force("output", "pahbl_pad_haddr"); &Force("bus", "pahbl_pad_haddr",31,0); @125
// &Force("output", "pahbl_pad_hburst"); &Force("bus", "pahbl_pad_hburst",2,0); @126
// &Force("output", "pahbl_pad_hprot"); &Force("bus", "pahbl_pad_hprot",6,0); @127
// &Force("output", "pahbl_pad_hsize"); &Force("bus", "pahbl_pad_hsize",2,0); @128
// &Force("output", "pahbl_pad_htrans"); &Force("bus", "pahbl_pad_htrans",1,0); @129
// &Force("output", "pahbl_pad_hwdata"); &Force("bus", "pahbl_pad_hwdata",31,0); @130
// &Force("output", "pahbl_pad_hwrite"); @131
// &Force("output", "pahbl_pad_hmastlock"); @132
// &Force("output", "pahbl_pad_hmaster"); &Force("bus", "pahbl_pad_hmaster",3,0); @133
// &Force("output", "pahbl_pad_hexcl"); @134
// &Force("output", "pahbl_pad_hnonsec"); @135
// &Force("input", "pad_biu_hrdata"); &Force("bus", "pad_biu_hrdata", 31, 0); @138
// &Force("input", "pad_biu_hready"); @139
// &Force("input", "pad_biu_hresp"); @140
// &Force("input", "pad_cpu_tcip_base"); &Force("bus", "pad_cpu_tcip_base",31,0); @141
// &Force("output", "biu_pad_haddr"); &Force("bus", "biu_pad_haddr",31,0); @143
// &Force("output", "biu_pad_hburst"); &Force("bus", "biu_pad_hburst",2,0); @144
// &Force("output", "biu_pad_hprot"); &Force("bus", "biu_pad_hprot",3,0); @145
// &Force("output", "biu_pad_hsize"); &Force("bus", "biu_pad_hsize",2,0); @146
// &Force("output", "biu_pad_htrans"); &Force("bus", "biu_pad_htrans",1,0); @147
// &Force("output", "biu_pad_hwdata"); &Force("bus", "biu_pad_hwdata",31,0); @148
// &Force("output", "biu_pad_hwrite"); @149
// &Force("output", "biu_pad_hlock"); @150
// &Force("input", "pll_core_cpuclk"); @153
// &Force("input", "pad_cpu_rst_b"); @154
// &Force("input", "pad_cpu_sys_cnt"); &Force("bus", "pad_cpu_sys_cnt", 63, 0); @155
// &Force("output", "cpu_pad_soft_rst"); &Force("bus", "cpu_pad_soft_rst", 1, 0); @156
// &Force("output", "cpu_pad_lockup"); @157
// &Force("output", "cpu_pad_halted"); @158
// &Force("input", "pad_cpu_nmi"); @159
// &Force("input", "pad_cpu_rst_addr"); &Force("bus", "pad_cpu_rst_addr", 31, 0); @160
// &Force("input", "pad_cpu_wakeup_event"); @161
//==========================================================
// TDT Ports
//==========================================================
// &Force("input","tdt_dmi_paddr"); &Force("bus","tdt_dmi_paddr",11,0); @166
// &Force("input","tdt_dmi_pwrite"); @167
// &Force("input","tdt_dmi_psel"); @169
// &Force("input","tdt_dmi_psel"); &Force("bus","tdt_dmi_psel",`TDT_COMP_NUM-1,0); @171
// &Force("input","tdt_dmi_penable"); @173
// &Force("input","tdt_dmi_pwdata"); &Force("bus","tdt_dmi_pwdata",31,0); @174
// &Force("output","tdt_dmi_prdata"); &Force("bus","tdt_dmi_prdata",`TDT_COMP_NUM*32-1,0); @175
// &Force("output","tdt_dmi_pready"); @177
// &Force("output","tdt_dmi_pslverr"); @178
// &Force("output","tdt_dmi_pready"); &Force("bus","tdt_dmi_pready",`TDT_COMP_NUM-1,0); @180
// &Force("output","tdt_dmi_pslverr"); &Force("bus","tdt_dmi_pslverr",`TDT_COMP_NUM-1,0); @181
// &Force("output","tdt_dm_pad_ndmreset_n"); @183
// &Force("output","tdt_dm_pad_hartreset_n"); @186
// &Force("input","pad_tdt_dm_core_unavail"); @187
// &Force("output","tdt_dm_pad_hartreset_n"); &Force("bus","tdt_dm_pad_hartreset_n",`TDT_DM_CORE_NUM-1,0); @189
// &Force("input","pad_tdt_dm_core_unavail"); &Force("bus","pad_tdt_dm_core_unavail",`TDT_DM_CORE_NUM-1,0); @190
// &Force("input","sys_apb_rst_b"); @193
// &Force("input","sys_apb_clk"); @195
// &Force("input","sys_apb_clk_en"); @198
// &Force("input","pad_tdt_dm_halt_req"); &Force("bus","pad_tdt_dm_halt_req",`TDT_DM_EXTHALTTRI_NUM-1,0); @202
// &Force("input","pad_tdt_dm_resume_req"); &Force("bus","pad_tdt_dm_resume_req",`TDT_DM_EXTRESUMETRI_NUM-1,0); @203
// &Force("output","tdt_dm_pad_halt_req"); &Force("bus","tdt_dm_pad_halt_req",`TDT_DM_EXTHALTTRI_NUM-1,0); @204
// &Force("output","tdt_dm_pad_resume_req"); &Force("bus","tdt_dm_pad_resume_req",`TDT_DM_EXTRESUMETRI_NUM-1,0); @205
// &Force("output","tdt_dm_pad_awid"); &Force("bus","tdt_dm_pad_awid",3,0); @209
// &Force("output","tdt_dm_pad_awaddr"); &Force("bus","tdt_dm_pad_awaddr",`TDT_DM_SBAW-1,0); @210
// &Force("output","tdt_dm_pad_awlen"); &Force("bus","tdt_dm_pad_awlen",3,0); @211
// &Force("output","tdt_dm_pad_awsize"); &Force("bus","tdt_dm_pad_awsize",2,0); @212
// &Force("output","tdt_dm_pad_awvalid"); @213
// &Force("input","pad_tdt_dm_awready"); @214
// &Force("output","tdt_dm_pad_wdata"); &Force("bus","tdt_dm_pad_wdata",`TDT_DM_SBA_DW-1,0); @215
// &Force("output","tdt_dm_pad_wvalid"); @216
// &Force("output","tdt_dm_pad_wlast"); @217
// &Force("output","tdt_dm_pad_wstrb"); &Force("bus","tdt_dm_pad_wstrb",`TDT_DM_SBA_BW-1,0); @218
// &Force("input","pad_tdt_dm_wready"); @219
// &Force("output","tdt_dm_pad_bready"); @220
// &Force("input","pad_tdt_dm_bid"); &Force("bus","pad_tdt_dm_bid",3,0); @221
// &Force("input","pad_tdt_dm_bresp"); &Force("bus","pad_tdt_dm_bresp",1,0); @222
// &Force("input","pad_tdt_dm_bvalid"); @223
// &Force("output","tdt_dm_pad_arid"); &Force("bus","tdt_dm_pad_arid",3,0); @225
// &Force("output","tdt_dm_pad_araddr"); &Force("bus","tdt_dm_pad_araddr",`TDT_DM_SBAW-1,0); @226
// &Force("output","tdt_dm_pad_arlen"); &Force("bus","tdt_dm_pad_arlen",3,0); @227
// &Force("output","tdt_dm_pad_arsize"); &Force("bus","tdt_dm_pad_arsize",2,0); @228
// &Force("output","tdt_dm_pad_arvalid"); @229
// &Force("input","pad_tdt_dm_arready"); @230
// &Force("input","pad_tdt_dm_rid"); &Force("bus","pad_tdt_dm_rid",3,0); @232
// &Force("input","pad_tdt_dm_rdata"); &Force("bus","pad_tdt_dm_rdata",`TDT_DM_SBA_DW-1,0); @233
// &Force("input","pad_tdt_dm_rvalid"); @234
// &Force("input","pad_tdt_dm_rlast"); @235
// &Force("input","pad_tdt_dm_rresp"); &Force("bus","pad_tdt_dm_rresp",1,0); @236
// &Force("output","tdt_dm_pad_rready"); @238
// &Force("output","tdt_dm_pad_awburst"); &Force("bus","tdt_dm_pad_awburst",1,0); @240
// &Force("output","tdt_dm_pad_awcache"); &Force("bus","tdt_dm_pad_awcache",3,0); @241
// &Force("output","tdt_dm_pad_awlock"); @242
// &Force("output","tdt_dm_pad_awprot"); &Force("bus","tdt_dm_pad_awprot",2,0); @243
// &Force("output","tdt_dm_pad_arburst"); &Force("bus","tdt_dm_pad_arburst",1,0); @244
// &Force("output","tdt_dm_pad_arcache"); &Force("bus","tdt_dm_pad_arcache",3,0); @245
// &Force("output","tdt_dm_pad_arlock"); @246
// &Force("output","tdt_dm_pad_arprot"); &Force("bus","tdt_dm_pad_arprot",2,0); @247
// &Force("output","tdt_dm_pad_htrans"); &Force("bus","tdt_dm_pad_htrans",1,0); @250
// &Force("output","tdt_dm_pad_haddr"); &Force("bus","tdt_dm_pad_haddr",`TDT_DM_SBAW-1,0); @251
// &Force("output","tdt_dm_pad_hwrite"); @252
// &Force("output","tdt_dm_pad_hburst"); &Force("bus","tdt_dm_pad_hburst",2,0); @253
// &Force("output","tdt_dm_pad_hsize"); &Force("bus","tdt_dm_pad_hsize",2,0); @254
// &Force("output","tdt_dm_pad_hwdata"); @255
// &Force("output","tdt_dm_pad_hprot"); &Force("bus","tdt_dm_pad_hprot",3,0); @256
// &Force("output","tdt_dm_pad_hmastlock"); &Force("bus","tdt_dm_pad_hwdata",`TDT_DM_SBA_DW-1,0); @257
// &Force("input","pad_tdt_dm_hrdata"); &Force("bus","pad_tdt_dm_hrdata",`TDT_DM_SBA_DW-1,0); @258
// &Force("input","pad_tdt_dm_hready"); @259
// &Force("input","pad_tdt_dm_hresp"); @260
// &Force("output", "rtu_pad_inst_retire"); @263
// &Force("output", "rtu_pad_inst_split"); @264
// &Force("output", "rtu_pad_retire_pc"); &Force("bus", "rtu_pad_retire_pc", 31, 0); @265
// &Force("output", "rtu_pad_wb0_data"); &Force("bus", "rtu_pad_wb0_data", 31, 0); @266
// &Force("output", "rtu_pad_wb0_preg"); &Force("bus", "rtu_pad_wb0_preg", 5, 0); @267
// &Force("output", "rtu_pad_wb0_vld"); @268
// &Force("output", "rtu_pad_wb1_data"); &Force("bus", "rtu_pad_wb1_data", 31, 0); @269
// &Force("output", "rtu_pad_wb1_preg"); &Force("bus", "rtu_pad_wb1_preg", 5, 0); @270
// &Force("output", "rtu_pad_wb1_vld"); @271
// &Force("output", "rtu_pad_wb2_data"); &Force("bus", "rtu_pad_wb2_data", 31, 0); @272
// &Force("output", "rtu_pad_wb2_preg"); &Force("bus", "rtu_pad_wb2_preg", 5, 0); @273
// &Force("output", "rtu_pad_wb2_vld"); @274
// &Force("output", "lsu_pad_sc_pass"); @276
// &Force("output", "cp0_pad_mcause"); &Force("bus", "cp0_pad_mcause", 31, 0); @278
// &Force("output", "cp0_pad_mstatus"); &Force("bus", "cp0_pad_mstatus", 31, 0); @279
// &Force("output","sysio_pad_lpmd_b"); &Force("bus", "sysio_pad_lpmd_b", 1, 0); @281
//==========================================================
// CLIC Ports
//==========================================================
// &Force("output", "cp0_pad_mintstatus"); &Force("bus", "cp0_pad_mintstatus", 31, 0); @286
// &Force("input", "pad_clic_int_vld"); &Force("bus", "pad_clic_int_vld", `CLIC_INTNUM-1-16, 0); @288
//==========================================================
// CLINT Ports
//==========================================================
// &Force("input", "pad_cpu_ext_int_b"); @295
// &Force("input","pad_yy_dft_clk_rst_b"); @298
//==========================================================
// FPU Ports
//==========================================================
// &Force("output", "rtu_pad_wb_freg_vld"); @305
// &Force("output", "rtu_pad_wb_freg"); &Force("bus", "rtu_pad_wb_freg", 4, 0); @306
// &Force("output", "rtu_pad_wb_freg_data"); &Force("bus", "rtu_pad_wb_freg_data", 63, 0); @308
// &Force("output", "rtu_pad_wb_freg_data"); &Force("bus", "rtu_pad_wb_freg_data", 31, 0); @310
// &Force("input","pad_cpu_sysmap_addr0"); &Force("bus","pad_cpu_sysmap_addr0",19,0); @314
// &Force("input","pad_cpu_sysmap_addr1"); &Force("bus","pad_cpu_sysmap_addr1",19,0); @315
// &Force("input","pad_cpu_sysmap_addr2"); &Force("bus","pad_cpu_sysmap_addr2",19,0); @316
// &Force("input","pad_cpu_sysmap_addr3"); &Force("bus","pad_cpu_sysmap_addr3",19,0); @317
// &Force("input","pad_cpu_sysmap_addr4"); &Force("bus","pad_cpu_sysmap_addr4",19,0); @318
// &Force("input","pad_cpu_sysmap_addr5"); &Force("bus","pad_cpu_sysmap_addr5",19,0); @319
// &Force("input","pad_cpu_sysmap_addr6"); &Force("bus","pad_cpu_sysmap_addr6",19,0); @320
// &Force("input","pad_cpu_sysmap_addr7"); &Force("bus","pad_cpu_sysmap_addr7",19,0); @321
// &Force("input","pad_cpu_sysmap_addr0_attr"); &Force("bus","pad_cpu_sysmap_addr0_attr",2,0); @322
// &Force("input","pad_cpu_sysmap_addr1_attr"); &Force("bus","pad_cpu_sysmap_addr1_attr",2,0); @323
// &Force("input","pad_cpu_sysmap_addr2_attr"); &Force("bus","pad_cpu_sysmap_addr2_attr",2,0); @324
// &Force("input","pad_cpu_sysmap_addr3_attr"); &Force("bus","pad_cpu_sysmap_addr3_attr",2,0); @325
// &Force("input","pad_cpu_sysmap_addr4_attr"); &Force("bus","pad_cpu_sysmap_addr4_attr",2,0); @326
// &Force("input","pad_cpu_sysmap_addr5_attr"); &Force("bus","pad_cpu_sysmap_addr5_attr",2,0); @327
// &Force("input","pad_cpu_sysmap_addr6_attr"); &Force("bus","pad_cpu_sysmap_addr6_attr",2,0); @328
// &Force("input","pad_cpu_sysmap_addr7_attr"); &Force("bus","pad_cpu_sysmap_addr7_attr",2,0); @329
// &ModuleEnd @331
endmodule

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opene906/E906_RTL_FACTORY/gen_rtl/cpu/rtl/pa_sys_io.v Normal file
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@ -0,0 +1,391 @@
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_sys_io(
biu_sysio_idle,
clk_en,
cp0_biu_icg_en,
cp0_sysio_ipend_b,
cp0_sysio_lpmd_b,
cp0_sysio_srst,
cpu_pad_dfs_ack,
cpu_pad_halted,
cpu_pad_lockup,
cpu_pad_soft_rst,
cpurst_b,
dahbl_sysio_idle,
dtu_cp0_wake_up,
forever_cpuclk,
iahbl_sysio_idle,
pad_cpu_dfs_req,
pad_cpu_ext_int_b,
pad_cpu_nmi,
pad_cpu_rst_addr,
pad_cpu_sys_cnt,
pad_cpu_wakeup_event,
pad_yy_icg_scan_en,
rtu_sysio_halted,
rtu_sysio_lockup_on,
rtu_yy_xx_dbgon,
sysio_clint_me_int,
sysio_clint_mtime,
sysio_cp0_clk_en,
sysio_cp0_clkratio,
sysio_cp0_rst_addr,
sysio_hpcp_time,
sysio_ifu_rst_addr,
sysio_ifu_rst_addr_done,
sysio_iu_rst_addr,
sysio_pad_lpmd_b,
sysio_rtu_nmi_int,
sysio_rtu_wk_event,
sysio_xx_halt_req
);
// &Ports; @24
input biu_sysio_idle;
input clk_en;
input cp0_biu_icg_en;
input cp0_sysio_ipend_b;
input [1 :0] cp0_sysio_lpmd_b;
input [1 :0] cp0_sysio_srst;
input cpurst_b;
input dahbl_sysio_idle;
input dtu_cp0_wake_up;
input forever_cpuclk;
input iahbl_sysio_idle;
input pad_cpu_dfs_req;
input pad_cpu_ext_int_b;
input pad_cpu_nmi;
input [31:0] pad_cpu_rst_addr;
input [63:0] pad_cpu_sys_cnt;
input pad_cpu_wakeup_event;
input pad_yy_icg_scan_en;
input rtu_sysio_halted;
input rtu_sysio_lockup_on;
input rtu_yy_xx_dbgon;
output cpu_pad_dfs_ack;
output cpu_pad_halted;
output cpu_pad_lockup;
output [1 :0] cpu_pad_soft_rst;
output sysio_clint_me_int;
output [63:0] sysio_clint_mtime;
output sysio_cp0_clk_en;
output [2 :0] sysio_cp0_clkratio;
output [31:0] sysio_cp0_rst_addr;
output [63:0] sysio_hpcp_time;
output [31:0] sysio_ifu_rst_addr;
output sysio_ifu_rst_addr_done;
output [31:0] sysio_iu_rst_addr;
output [1 :0] sysio_pad_lpmd_b;
output sysio_rtu_nmi_int;
output sysio_rtu_wk_event;
output sysio_xx_halt_req;
// &Regs; @25
reg [63:0] ccvr;
reg cpu_ext_int_b;
reg cpu_nmi;
reg [30:0] cpu_rst_addr_31;
reg cpu_wk_event;
reg pad_cpu_halt_ff1;
reg pad_cpu_halt_ff2;
reg sysio_pad_dbg_b;
reg sysio_pad_halted;
reg sysio_pad_ipend_b;
reg sysio_pad_lockup;
reg [1 :0] sysio_pad_lpmd_b;
reg [1 :0] sysio_pad_srst;
reg sysio_pad_wakeup_b;
// &Wires; @26
wire biu_sysio_idle;
wire ccvr_h_clk;
wire ccvr_h_clk_en;
wire ccvr_h_updt;
wire clk_en;
wire cp0_biu_icg_en;
wire cp0_sysio_ipend_b;
wire [1 :0] cp0_sysio_lpmd_b;
wire [1 :0] cp0_sysio_srst;
wire cpu_pad_dfs_ack;
wire cpu_pad_halted;
wire cpu_pad_lockup;
wire [1 :0] cpu_pad_soft_rst;
wire [31:0] cpu_rst_addr;
wire cpu_wake_up_b;
wire cpurst_b;
wire dahbl_sysio_idle;
wire dtu_cp0_wake_up;
wire forever_cpuclk;
wire halt_clk;
wire halt_clk_en;
wire iahbl_sysio_idle;
wire pad_cpu_dfs_req;
wire pad_cpu_ext_int_b;
wire pad_cpu_nmi;
wire [31:0] pad_cpu_rst_addr;
wire [63:0] pad_cpu_sys_cnt;
wire pad_cpu_wakeup_event;
wire [2 :0] pad_sysio_clkratio;
wire pad_yy_icg_scan_en;
wire rtu_sysio_halted;
wire rtu_sysio_lockup_on;
wire rtu_yy_xx_dbgon;
wire sample_clk;
wire sysio_clint_me_int;
wire [63:0] sysio_clint_mtime;
wire sysio_cp0_clk_en;
wire [2 :0] sysio_cp0_clkratio;
wire [31:0] sysio_cp0_rst_addr;
wire [63:0] sysio_hpcp_time;
wire [31:0] sysio_ifu_rst_addr;
wire sysio_ifu_rst_addr_done;
wire [31:0] sysio_iu_rst_addr;
wire sysio_lpmd_gated_clk;
wire sysio_lpmd_gated_en;
wire sysio_rst_addr_neq;
wire sysio_rtu_nmi_int;
wire sysio_rtu_wk_event;
wire sysio_xx_halt_req;
// &Instance("gated_clk_cell", "x_pa_gated_sysio_lpmd_cpuclk_cell"); @31
gated_clk_cell x_pa_gated_sysio_lpmd_cpuclk_cell (
.clk_in (forever_cpuclk ),
.clk_out (sysio_lpmd_gated_clk),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (sysio_lpmd_gated_en ),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk ), @32
// .global_en (1'b1 ), @33
// .module_en (cp0_biu_icg_en ), @34
// .local_en (sysio_lpmd_gated_en ), @35
// .external_en(1'b0 ), @36
// .clk_out (sysio_lpmd_gated_clk )); @37
assign sysio_lpmd_gated_en = ((sysio_pad_dbg_b ^ (~rtu_yy_xx_dbgon)) ||
|(sysio_pad_lpmd_b[1:0] ^ cp0_sysio_lpmd_b[1:0]) ||
(sysio_pad_ipend_b ^ cp0_sysio_ipend_b) ||
(sysio_pad_wakeup_b ^ cpu_wake_up_b) ||
|(sysio_pad_srst[1:0] ^ cp0_sysio_srst[1:0]) ||
(sysio_pad_lockup ^ rtu_sysio_lockup_on) ||
(rtu_sysio_halted ^ sysio_pad_halted) ||
(pad_cpu_ext_int_b ^ cpu_ext_int_b) ||
(pad_cpu_nmi ^ cpu_nmi) ||
(pad_cpu_wakeup_event ^ cpu_wk_event) ||
sysio_rst_addr_neq)
&& clk_en;
//=========================================
// input port
//=========================================
//synchronize signal
assign pad_sysio_clkratio[2:0] = 3'b0;
assign sysio_cp0_clkratio[2:0] = pad_sysio_clkratio[2:0];
assign halt_clk_en = pad_cpu_halt_ff1 ^ pad_cpu_dfs_req |
pad_cpu_halt_ff2 ^ pad_cpu_halt_ff1;
// &Instance("gated_clk_cell", "x_pa_halt_clk"); @62
gated_clk_cell x_pa_halt_clk (
.clk_in (forever_cpuclk ),
.clk_out (halt_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (halt_clk_en ),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @63
// .external_en (1'b0), @64
// .global_en (1'b1), @65
// .module_en (cp0_biu_icg_en), @66
// .local_en (halt_clk_en), @67
// .clk_out (halt_clk)); @68
always @ (posedge halt_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
pad_cpu_halt_ff1 <= 1'b0;
pad_cpu_halt_ff2 <= 1'b0;
end
else
begin
pad_cpu_halt_ff1 <= pad_cpu_dfs_req;
pad_cpu_halt_ff2 <= pad_cpu_halt_ff1;
end
end
assign cpu_pad_dfs_ack = iahbl_sysio_idle && dahbl_sysio_idle && biu_sysio_idle
&& pad_cpu_halt_ff2;
assign sysio_xx_halt_req = pad_cpu_halt_ff2;
assign ccvr_h_updt = |(ccvr[63:12] ^ pad_cpu_sys_cnt[63:12]) && clk_en;
always @ (posedge ccvr_h_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ccvr[63:12] <= 52'b0;
else if (ccvr_h_updt)
ccvr[63:12] <= pad_cpu_sys_cnt[63:12];
else
ccvr[63:12] <= ccvr[63:12];
end
assign ccvr_h_clk_en = ccvr_h_updt;
// &Instance("gated_clk_cell", "x_pa_ccvr_h_clk"); @106
gated_clk_cell x_pa_ccvr_h_clk (
.clk_in (forever_cpuclk ),
.clk_out (ccvr_h_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (ccvr_h_clk_en ),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @107
// .external_en (1'b0), @108
// .global_en (1'b1), @109
// .module_en (cp0_biu_icg_en), @110
// .local_en (ccvr_h_clk_en), @111
// .clk_out (ccvr_h_clk)); @112
always @ (posedge sample_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ccvr[11:0] <= 12'b0;
else if (clk_en)
ccvr[11:0] <= pad_cpu_sys_cnt[11:0];
else
ccvr[11:0] <= ccvr[11:0];
end
assign sysio_clint_mtime[63:0] = ccvr[63:0];
assign sysio_hpcp_time[63:0] = ccvr[63:0];
always @ (posedge sysio_lpmd_gated_clk or negedge cpurst_b)
begin
if (!cpurst_b)
cpu_rst_addr_31[30:0] <= 31'b0;
else if (clk_en)
cpu_rst_addr_31[30:0] <= pad_cpu_rst_addr[31:1];
else
cpu_rst_addr_31[30:0] <= cpu_rst_addr_31[30:0];
end
assign cpu_rst_addr[31:0] = {cpu_rst_addr_31[30:0], 1'b0};
assign sysio_rst_addr_neq = cpu_rst_addr_31[30:0] != pad_cpu_rst_addr[31:1];
// &Force("bus", "pad_cpu_rst_addr", 31, 0); @143
assign sysio_ifu_rst_addr_done = !sysio_rst_addr_neq;
assign sysio_cp0_rst_addr[31:0] = cpu_rst_addr[31:0];
assign sysio_ifu_rst_addr[31:0] = cpu_rst_addr[31:0];
assign sysio_iu_rst_addr[31:0] = cpu_rst_addr[31:0];
always @ (posedge sysio_lpmd_gated_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
cpu_ext_int_b <= 1'b1;
cpu_nmi <= 1'b0;
cpu_wk_event <= 1'b0;
end
else if(clk_en) begin
cpu_ext_int_b <= pad_cpu_ext_int_b;
cpu_nmi <= pad_cpu_nmi;
cpu_wk_event <= pad_cpu_wakeup_event;
end
else begin
cpu_ext_int_b <= cpu_ext_int_b;
cpu_nmi <= cpu_nmi;
cpu_wk_event <= cpu_wk_event;
end
end
assign sysio_clint_me_int = !cpu_ext_int_b;
assign sysio_rtu_nmi_int = cpu_nmi;
assign sysio_rtu_wk_event = cpu_wk_event;
// &Instance("gated_clk_cell", "x_pa_sample_clk"); @173
gated_clk_cell x_pa_sample_clk (
.clk_in (forever_cpuclk ),
.clk_out (sample_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (clk_en ),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @174
// .external_en (1'b0 ), @175
// .global_en (1'b1 ), @176
// .module_en (cp0_biu_icg_en), @177
// .local_en (clk_en ), @178
// .clk_out (sample_clk ) @179
// ); @180
//=========================================
// output port
//=========================================
// &Force("output","sysio_pad_ipend_b"); @185
// &Force("output","sysio_pad_dbg_b"); @186
// &Force("output","sysio_pad_lpmd_b"); @187
// &Force("output","sysio_pad_wakeup_b"); @188
assign cpu_wake_up_b = cp0_sysio_ipend_b && !dtu_cp0_wake_up;
always @(posedge sysio_lpmd_gated_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
sysio_pad_dbg_b <= 1'b1;
sysio_pad_lpmd_b[1:0] <= 2'b11;
sysio_pad_ipend_b <= 1'b0;
sysio_pad_wakeup_b <= 1'b0;
sysio_pad_srst[1:0] <= 2'b0;
sysio_pad_lockup <= 1'b0;
sysio_pad_halted <= 1'b0;
end
else if(clk_en)
begin
sysio_pad_dbg_b <= ~rtu_yy_xx_dbgon;
sysio_pad_lpmd_b[1:0] <= cp0_sysio_lpmd_b[1:0];
sysio_pad_ipend_b <= cp0_sysio_ipend_b;
sysio_pad_wakeup_b <= cpu_wake_up_b;
sysio_pad_srst[1:0] <= cp0_sysio_srst[1:0];
sysio_pad_lockup <= rtu_sysio_lockup_on;
sysio_pad_halted <= rtu_sysio_halted;
end
end
// &Force("nonport", "sysio_pad_dbg_b"); @215
// &Force("nonport", "sysio_pad_ipend_b"); @216
// &Force("nonport", "sysio_pad_wakeup_b"); @217
assign sysio_cp0_clk_en = clk_en;
assign cpu_pad_soft_rst[1:0] = sysio_pad_srst[1:0];
assign cpu_pad_lockup = sysio_pad_lockup;
assign cpu_pad_halted = sysio_pad_halted;
// &ModuleEnd; @225
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_dtu_cdc(
async_halt_req_wakeup,
cp0_yy_clk_en,
cpurst_b,
dscratch0,
dtu_ifu_debug_inst,
dtu_ifu_debug_inst_vld,
dtu_ifu_halt_on_reset,
dtu_rtu_async_halt_req,
dtu_rtu_resume_req,
dtu_rtu_sync_halt_req,
dtu_tdt_dm_halted,
dtu_tdt_dm_havereset,
dtu_tdt_dm_itr_done,
dtu_tdt_dm_retire_debug_expt_vld,
dtu_tdt_dm_rx_data,
dtu_tdt_dm_wr_ready,
forever_cpuclk,
latest_pc,
pad_yy_icg_scan_en,
rtu_dtu_retire_debug_expt_vld,
rtu_dtu_retire_vld,
rtu_yy_xx_dbgon,
sys_apb_clk,
sys_apb_rst_b,
tdt_dm_dtu_ack_havereset,
tdt_dm_dtu_async_halt_req,
tdt_dm_dtu_halt_on_reset,
tdt_dm_dtu_halt_req,
tdt_dm_dtu_itr,
tdt_dm_dtu_itr_vld,
tdt_dm_dtu_resume_req,
tdt_dm_dtu_wdata,
tdt_dm_dtu_wr_flg,
tdt_dm_dtu_wr_vld,
tdt_dm_wdata,
tdt_dm_wr_flg,
tdt_dm_wr_vld
);
// &Ports; @24
input cp0_yy_clk_en;
input cpurst_b;
input [31:0] dscratch0;
input forever_cpuclk;
input [31:0] latest_pc;
input pad_yy_icg_scan_en;
input rtu_dtu_retire_debug_expt_vld;
input rtu_dtu_retire_vld;
input rtu_yy_xx_dbgon;
input sys_apb_clk;
input sys_apb_rst_b;
input tdt_dm_dtu_ack_havereset;
input tdt_dm_dtu_async_halt_req;
input tdt_dm_dtu_halt_on_reset;
input tdt_dm_dtu_halt_req;
input [31:0] tdt_dm_dtu_itr;
input tdt_dm_dtu_itr_vld;
input tdt_dm_dtu_resume_req;
input [31:0] tdt_dm_dtu_wdata;
input [1 :0] tdt_dm_dtu_wr_flg;
input tdt_dm_dtu_wr_vld;
output async_halt_req_wakeup;
output [31:0] dtu_ifu_debug_inst;
output dtu_ifu_debug_inst_vld;
output dtu_ifu_halt_on_reset;
output dtu_rtu_async_halt_req;
output dtu_rtu_resume_req;
output dtu_rtu_sync_halt_req;
output dtu_tdt_dm_halted;
output dtu_tdt_dm_havereset;
output dtu_tdt_dm_itr_done;
output dtu_tdt_dm_retire_debug_expt_vld;
output [31:0] dtu_tdt_dm_rx_data;
output dtu_tdt_dm_wr_ready;
output [31:0] tdt_dm_wdata;
output [1 :0] tdt_dm_wr_flg;
output tdt_dm_wr_vld;
// &Regs; @25
reg [1 :0] cur_state;
reg debug_inst_vld_pulse_f;
reg [31:0] dm_rdata;
reg [31:0] dm_rdata_reg;
reg dtu_havereset;
reg dtu_rtu_async_halt_req_lvl_f;
reg dtu_rtu_async_halt_req_lvl_ff;
reg dtu_tdt_dm_wr_ready;
reg [31:0] itr_reg;
reg [1 :0] next_state;
reg rtu_yy_xx_dbgon_reg;
reg [31:0] rx_data;
reg [31:0] tdt_dm_wdata;
reg [1 :0] tdt_dm_wr_flg;
reg tdt_dm_wr_vld_f;
reg tdt_dm_wr_vld_pulse_f;
// &Wires; @26
wire async_halt_req_wakeup;
wire cp0_yy_clk_en;
wire cpurst_b;
wire debug_inst_vld_pulse;
wire [31:0] dscratch0;
wire dtu_cdc_clk;
wire [31:0] dtu_ifu_debug_inst;
wire dtu_ifu_debug_inst_vld;
wire dtu_ifu_halt_on_reset;
wire dtu_rtu_async_halt_req;
wire dtu_rtu_async_halt_req_lvl;
wire dtu_rtu_resume_req;
wire dtu_rtu_sync_halt_req;
wire dtu_tdt_dm_halted;
wire dtu_tdt_dm_havereset;
wire dtu_tdt_dm_itr_done;
wire dtu_tdt_dm_retire_debug_expt_vld;
wire [31:0] dtu_tdt_dm_rx_data;
wire dtu_tdt_dm_wr_ready_pulse;
wire forever_cpuclk;
wire [31:0] latest_pc;
wire [31:0] latest_pc_for_dm;
wire pad_yy_icg_scan_en;
wire rtu_dtu_retire_debug_expt_vld;
wire rtu_dtu_retire_vld;
wire rtu_dtu_retire_vld_dbgon;
wire rtu_yy_xx_dbgon;
wire sys_apb_clk;
wire sys_apb_rst_b;
wire tdt_dm_ack_havereset;
wire tdt_dm_dtu_ack_havereset;
wire tdt_dm_dtu_async_halt_req;
wire tdt_dm_dtu_halt_on_reset;
wire tdt_dm_dtu_halt_req;
wire [31:0] tdt_dm_dtu_itr;
wire tdt_dm_dtu_itr_vld;
wire tdt_dm_dtu_resume_req;
wire [31:0] tdt_dm_dtu_wdata;
wire [1 :0] tdt_dm_dtu_wr_flg;
wire tdt_dm_dtu_wr_vld;
wire tdt_dm_wr_vld;
wire tdt_dm_wr_vld_pulse;
//XLEN
parameter XLEN = `TDT_DM_CORE_MAX_XLEN;
//state machine parameter
parameter IDLE = 2'b00;
parameter PULSE = 2'b01;
parameter HAVE_RESET = 2'b10;
parameter PENDING = 2'b11;
//===============================================================
// CDC of DM to DTU
//===============================================================
//tdt_dm_dtu_halt_req to dtu_rtu_sync_halt_req
// &Instance("pa_dtu_cdc_lvl","x_pa_tdt_dm_dtu_halt_req_cdc"); @42
pa_dtu_cdc_lvl x_pa_tdt_dm_dtu_halt_req_cdc (
.clk (forever_cpuclk ),
.dst_lvl (dtu_rtu_sync_halt_req),
.rst_b (cpurst_b ),
.src_lvl (tdt_dm_dtu_halt_req )
);
// &Connect(.clk (forever_cpuclk), @43
// .rst_b (cpurst_b), @44
// .src_lvl (tdt_dm_dtu_halt_req), @45
// .dst_lvl (dtu_rtu_sync_halt_req)); @46
//tdt_dm_dtu_async_halt_req to dtu_rtu_async_halt_req
// &Instance("pa_dtu_cdc_lvl","x_pa_tdt_dm_dtu_async_halt_req_cdc"); @49
pa_dtu_cdc_lvl x_pa_tdt_dm_dtu_async_halt_req_cdc (
.clk (forever_cpuclk ),
.dst_lvl (dtu_rtu_async_halt_req_lvl),
.rst_b (cpurst_b ),
.src_lvl (tdt_dm_dtu_async_halt_req )
);
// &Connect(.clk (forever_cpuclk), @50
// .rst_b (cpurst_b), @51
// .src_lvl (tdt_dm_dtu_async_halt_req), @52
// .dst_lvl (dtu_rtu_async_halt_req_lvl)); @53
always @(posedge forever_cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
dtu_rtu_async_halt_req_lvl_f <= 1'b0;
dtu_rtu_async_halt_req_lvl_ff <= 1'b0;
end
else
begin
dtu_rtu_async_halt_req_lvl_f <= dtu_rtu_async_halt_req_lvl;
dtu_rtu_async_halt_req_lvl_ff <= dtu_rtu_async_halt_req_lvl_f;
end
end
assign async_halt_req_wakeup = dtu_rtu_async_halt_req_lvl && !dtu_rtu_async_halt_req_lvl_f;
assign dtu_rtu_async_halt_req = dtu_rtu_async_halt_req_lvl_f && !dtu_rtu_async_halt_req_lvl_ff;
//tdt_dm_dtu_halt_on_reset to dtu_ifu_halt_on_reset
// &Instance("pa_dtu_cdc_lvl","x_pa_tdt_dm_dtu_halt_on_reset_cdc"); @73
pa_dtu_cdc_lvl x_pa_tdt_dm_dtu_halt_on_reset_cdc (
.clk (dtu_cdc_clk ),
.dst_lvl (dtu_ifu_halt_on_reset ),
.rst_b (cpurst_b ),
.src_lvl (tdt_dm_dtu_halt_on_reset)
);
// &Connect(.clk (dtu_cdc_clk), @74
// .rst_b (cpurst_b), @75
// .src_lvl (tdt_dm_dtu_halt_on_reset), @76
// .dst_lvl (dtu_ifu_halt_on_reset)); @77
//tdt_dm_dtu_resume_req(pulse) to dtu_rtu_resume_req(pulse)
// &Instance("pa_dtu_cdc_pulse","x_pa_dtu_rtu_resume_req_cdc"); @80
pa_dtu_cdc_pulse x_pa_dtu_rtu_resume_req_cdc (
.dst_clk (dtu_cdc_clk ),
.dst_pulse (dtu_rtu_resume_req ),
.dst_rst_b (cpurst_b ),
.src_clk (sys_apb_clk ),
.src_pulse (tdt_dm_dtu_resume_req),
.src_rst_b (sys_apb_rst_b )
);
// &Connect(.src_clk (sys_apb_clk), @81
// .src_rst_b (sys_apb_rst_b), @82
// .dst_clk(dtu_cdc_clk), @83
// .dst_rst_b(cpurst_b), @84
// .src_pulse(tdt_dm_dtu_resume_req), @85
// .dst_pulse(dtu_rtu_resume_req)); @86
//tdt_dm_dtu_ack_havereset(pulse) to tdt_dm_ack_havereset(pulse)
// &Instance("pa_dtu_cdc_pulse","x_pa_tdt_dm_dtu_ack_havereset_cdc"); @89
pa_dtu_cdc_pulse x_pa_tdt_dm_dtu_ack_havereset_cdc (
.dst_clk (dtu_cdc_clk ),
.dst_pulse (tdt_dm_ack_havereset ),
.dst_rst_b (cpurst_b ),
.src_clk (sys_apb_clk ),
.src_pulse (tdt_dm_dtu_ack_havereset),
.src_rst_b (sys_apb_rst_b )
);
// &Connect(.src_clk (sys_apb_clk), @90
// .src_rst_b (sys_apb_rst_b), @91
// .dst_clk(dtu_cdc_clk), @92
// .dst_rst_b(cpurst_b), @93
// .src_pulse(tdt_dm_dtu_ack_havereset), @94
// .dst_pulse(tdt_dm_ack_havereset)); @95
//tdt_dm_dtu_itr_vld(pulse) to dtu_ifu_debug_inst_vld(pulse)
//tdt_dm_dtu_itr(32 bit) to dtu_ifu_debug_inst(32 bit)
// &Instance("pa_dtu_cdc_pulse","x_pa_tdt_dm_dtu_itr_vld_cdc"); @99
pa_dtu_cdc_pulse x_pa_tdt_dm_dtu_itr_vld_cdc (
.dst_clk (dtu_cdc_clk ),
.dst_pulse (debug_inst_vld_pulse),
.dst_rst_b (cpurst_b ),
.src_clk (sys_apb_clk ),
.src_pulse (tdt_dm_dtu_itr_vld ),
.src_rst_b (sys_apb_rst_b )
);
// &Connect(.src_clk (sys_apb_clk), @100
// .src_rst_b (sys_apb_rst_b), @101
// .dst_clk(dtu_cdc_clk), @102
// .dst_rst_b(cpurst_b), @103
// .src_pulse(tdt_dm_dtu_itr_vld), @104
// .dst_pulse(debug_inst_vld_pulse)); @105
always @(posedge dtu_cdc_clk or negedge cpurst_b)
begin
if(!cpurst_b)
debug_inst_vld_pulse_f <= 1'b0;
else
debug_inst_vld_pulse_f <= debug_inst_vld_pulse;
end
assign dtu_ifu_debug_inst_vld = debug_inst_vld_pulse_f;
always @(posedge dtu_cdc_clk or negedge cpurst_b)
begin
if(!cpurst_b)
itr_reg[31:0] <= 32'b0;
else if(debug_inst_vld_pulse)
itr_reg[31:0] <= tdt_dm_dtu_itr[31:0];
end
assign dtu_ifu_debug_inst[31:0] = itr_reg[31:0];
//tdt_dm_dtu_wr_vld
//tdt_dm_dtu_wr_flg
//tdt_dm_dtu_wdata
// &Instance("pa_dtu_cdc_pulse","x_pa_tdt_dm_dtu_wr_vld_cdc"); @128
pa_dtu_cdc_pulse x_pa_tdt_dm_dtu_wr_vld_cdc (
.dst_clk (dtu_cdc_clk ),
.dst_pulse (tdt_dm_wr_vld_pulse),
.dst_rst_b (cpurst_b ),
.src_clk (sys_apb_clk ),
.src_pulse (tdt_dm_dtu_wr_vld ),
.src_rst_b (sys_apb_rst_b )
);
// &Connect(.src_clk (sys_apb_clk), @129
// .src_rst_b (sys_apb_rst_b), @130
// .dst_clk(dtu_cdc_clk), @131
// .dst_rst_b(cpurst_b), @132
// .src_pulse(tdt_dm_dtu_wr_vld), @133
// .dst_pulse(tdt_dm_wr_vld_pulse)); @134
always @(posedge dtu_cdc_clk or negedge cpurst_b)
begin
if(!cpurst_b)
tdt_dm_wr_vld_pulse_f <= 1'b0;
else
tdt_dm_wr_vld_pulse_f <= tdt_dm_wr_vld_pulse;
end
assign tdt_dm_wr_vld = tdt_dm_wr_vld_pulse_f;
// &Force("output","tdt_dm_wr_vld"); @144
//when cpuclk = abp_clk, dtu_tdt_dm_wr_ready need wait dtu_tdt_dm_rx_data for a cycle
always @(posedge dtu_cdc_clk or negedge cpurst_b)
begin
if(!cpurst_b)
tdt_dm_wr_vld_f <= 1'b0;
else
tdt_dm_wr_vld_f <= tdt_dm_wr_vld;
end
always @(posedge dtu_cdc_clk or negedge cpurst_b)
begin
if(!cpurst_b)
tdt_dm_wr_flg[1:0] <= 2'b0;
else if(tdt_dm_wr_vld_pulse)
tdt_dm_wr_flg[1:0] <= tdt_dm_dtu_wr_flg[1:0];
end
// &Force("output","tdt_dm_wr_flg");&Force("bus","tdt_dm_wr_flg",1,0); @161
always @(posedge dtu_cdc_clk or negedge cpurst_b)
begin
if(!cpurst_b)
tdt_dm_wdata[XLEN-1:0] <= {XLEN{1'b0}};
else if(tdt_dm_wr_vld_pulse)
tdt_dm_wdata[XLEN-1:0] <= tdt_dm_dtu_wdata[XLEN-1:0];
end
//sample last_pc_for_dm
assign latest_pc_for_dm[`PA_WIDTH-1:0] = latest_pc[`PA_WIDTH-1:0];
//read data for dm
// &CombBeg; @179
always @( dscratch0[31:0]
or latest_pc_for_dm[31:0]
or tdt_dm_wr_flg[1:0])
begin
case(tdt_dm_wr_flg[1:0])
2'b00:dm_rdata[XLEN-1:0] = dscratch0[XLEN-1:0];
2'b01:dm_rdata[XLEN-1:0] = {XLEN{1'b0}};
2'b10:dm_rdata[XLEN-1:0] = latest_pc_for_dm[`PA_WIDTH-1:0];
2'b11:dm_rdata[XLEN-1:0] = {XLEN{1'b0}};
default:dm_rdata[XLEN-1:0] = {XLEN{1'bx}};
endcase
// &CombEnd; @187
end
always @(posedge dtu_cdc_clk or negedge cpurst_b)
begin
if(!cpurst_b)
dm_rdata_reg[XLEN-1:0] <= {XLEN{1'b0}};
else if(tdt_dm_wr_vld)
dm_rdata_reg[XLEN-1:0] <= dm_rdata[XLEN-1:0];
end
//===============================================================
// CDC of DTU to DM
//================================================================
//rtu_yy_xx_dbgon to dtu_tdt_dm_halted
always @(posedge dtu_cdc_clk or negedge cpurst_b)
begin
if(!cpurst_b)
rtu_yy_xx_dbgon_reg <= 1'b0;
else
rtu_yy_xx_dbgon_reg <= rtu_yy_xx_dbgon;
end
// &Instance("pa_dtu_cdc_lvl","x_pa_dtu_tdt_dm_halted_cdc"); @207
pa_dtu_cdc_lvl x_pa_dtu_tdt_dm_halted_cdc (
.clk (sys_apb_clk ),
.dst_lvl (dtu_tdt_dm_halted ),
.rst_b (sys_apb_rst_b ),
.src_lvl (rtu_yy_xx_dbgon_reg)
);
// &Connect(.clk (sys_apb_clk), @208
// .rst_b (sys_apb_rst_b), @209
// .src_lvl (rtu_yy_xx_dbgon_reg), @210
// .dst_lvl (dtu_tdt_dm_halted)); @211
//rtu_dtu_retire_vld(pluse) to dtu_tdt_dm_itr_done(pluse)
assign rtu_dtu_retire_vld_dbgon = rtu_dtu_retire_vld && rtu_yy_xx_dbgon;
// &Instance("pa_dtu_cdc_pulse","x_pa_dtu_tdt_dm_itr_done_cdc"); @215
pa_dtu_cdc_pulse x_pa_dtu_tdt_dm_itr_done_cdc (
.dst_clk (sys_apb_clk ),
.dst_pulse (dtu_tdt_dm_itr_done ),
.dst_rst_b (sys_apb_rst_b ),
.src_clk (dtu_cdc_clk ),
.src_pulse (rtu_dtu_retire_vld_dbgon),
.src_rst_b (cpurst_b )
);
// &Connect(.src_clk (dtu_cdc_clk), @216
// .src_rst_b (cpurst_b), @217
// .dst_clk(sys_apb_clk), @218
// .dst_rst_b(sys_apb_rst_b), @219
// .src_pulse(rtu_dtu_retire_vld_dbgon), @220
// .dst_pulse(dtu_tdt_dm_itr_done)); @221
//rtu_dtu_retire_debug_expt_vld(pulse) to dtu_tdt_dm_retire_debug_expt_vld(pulse)
// &Instance("pa_dtu_cdc_pulse","x_pa_dtu_tdt_dm_retire_debug_expt_vld_cdc"); @224
pa_dtu_cdc_pulse x_pa_dtu_tdt_dm_retire_debug_expt_vld_cdc (
.dst_clk (sys_apb_clk ),
.dst_pulse (dtu_tdt_dm_retire_debug_expt_vld),
.dst_rst_b (sys_apb_rst_b ),
.src_clk (dtu_cdc_clk ),
.src_pulse (rtu_dtu_retire_debug_expt_vld ),
.src_rst_b (cpurst_b )
);
// &Connect(.src_clk (dtu_cdc_clk), @225
// .src_rst_b (cpurst_b), @226
// .dst_clk(sys_apb_clk), @227
// .dst_rst_b(sys_apb_rst_b), @228
// .src_pulse(rtu_dtu_retire_debug_expt_vld), @229
// .dst_pulse(dtu_tdt_dm_retire_debug_expt_vld)); @230
//dtu_tdt_dm_wr_ready
//dtu_tdt_dm_Rx_data
// &Instance("pa_dtu_cdc_pulse","x_pa_dtu_tdt_dm_wr_ready_cdc"); @234
pa_dtu_cdc_pulse x_pa_dtu_tdt_dm_wr_ready_cdc (
.dst_clk (sys_apb_clk ),
.dst_pulse (dtu_tdt_dm_wr_ready_pulse),
.dst_rst_b (sys_apb_rst_b ),
.src_clk (dtu_cdc_clk ),
.src_pulse (tdt_dm_wr_vld_f ),
.src_rst_b (cpurst_b )
);
// &Connect(.src_clk (dtu_cdc_clk), @235
// .src_rst_b (cpurst_b), @236
// .dst_clk(sys_apb_clk), @237
// .dst_rst_b(sys_apb_rst_b), @238
// .src_pulse(tdt_dm_wr_vld_f), @239
// .dst_pulse(dtu_tdt_dm_wr_ready_pulse)); @240
always @(posedge sys_apb_clk or negedge sys_apb_rst_b)
begin
if(!sys_apb_rst_b)
dtu_tdt_dm_wr_ready <= 1'b0;
else
dtu_tdt_dm_wr_ready <= dtu_tdt_dm_wr_ready_pulse;
end
always @(posedge sys_apb_clk or negedge sys_apb_rst_b)
begin
if(!sys_apb_rst_b)
rx_data[XLEN-1:0] <= {XLEN{1'b0}};
else if(dtu_tdt_dm_wr_ready_pulse)
rx_data[XLEN-1:0] <= dm_rdata_reg[XLEN-1:0];
end
assign dtu_tdt_dm_rx_data[XLEN-1:0] = rx_data[XLEN-1:0];
//generate dtu_tdt_dm_havereset(lvl) when cpurst_b switch to 1
always @(posedge dtu_cdc_clk or negedge cpurst_b)
begin
if(!cpurst_b)
cur_state[1:0] <= IDLE;
else
cur_state[1:0] <= next_state[1:0];
end
// &CombBeg; @268
always @( cur_state[1:0]
or tdt_dm_ack_havereset)
begin
case(cur_state[1:0])
IDLE: next_state[1:0] = PULSE;
PULSE: next_state[1:0] = HAVE_RESET;
HAVE_RESET: if(tdt_dm_ack_havereset)
next_state[1:0] = PENDING;
else
next_state[1:0] = HAVE_RESET;
PENDING: next_state[1:0] = PENDING;
default: next_state[1:0] = IDLE;
endcase
// &CombEnd; @279
end
always @(posedge dtu_cdc_clk or negedge cpurst_b)
begin
if(!cpurst_b)
dtu_havereset <= 1'b0;
else
dtu_havereset <= cur_state[1:0] == HAVE_RESET;
end
// &Instance("pa_dtu_cdc_lvl","x_pa_dtu_tdt_dm_havereset_cdc"); @289
pa_dtu_cdc_lvl x_pa_dtu_tdt_dm_havereset_cdc (
.clk (sys_apb_clk ),
.dst_lvl (dtu_tdt_dm_havereset),
.rst_b (sys_apb_rst_b ),
.src_lvl (dtu_havereset )
);
// &Connect(.clk (sys_apb_clk), @290
// .rst_b (sys_apb_rst_b), @291
// .src_lvl (dtu_havereset), @292
// .dst_lvl (dtu_tdt_dm_havereset)); @293
// &Force("output","dtu_rtu_resume_req"); @349
// &Force("output","dtu_ifu_debug_inst_vld"); @373
// &Force("output","tdt_dm_wr_vld"); @395
// &Force("output","tdt_dm_wr_flg");&Force("bus","tdt_dm_wr_flg",1,0); @412
// &CombBeg; @430
// &CombEnd; @438
// &Instance("pa_dtu_cdc_pulse_div_fast_to_slow","x_pa_dtu_tdt_dm_itr_done_cdc"); @467
// &Connect(.src_clk (dtu_cdc_clk), @468
// .src_rst_b (cpurst_b), @469
// .clk_en(sys_apb_clk_en), @470
// .modify(itr_done_modify), @471
// .src_pulse(rtu_dtu_retire_vld_dbgon), @472
// .dst_pulse(dtu_tdt_dm_itr_done)); @473
// &Force("nonport","itr_done_modify"); @474
// &Instance("pa_dtu_cdc_pulse_div_fast_to_slow","x_pa_dtu_tdt_dm_retire_debug_expt_vld_cdc"); @477
// &Connect(.src_clk (dtu_cdc_clk), @478
// .src_rst_b (cpurst_b), @479
// .clk_en(sys_apb_clk_en), @480
// .modify(retire_debug_expt_vld_modify), @481
// .src_pulse(rtu_dtu_retire_debug_expt_vld), @482
// .dst_pulse(dtu_tdt_dm_retire_debug_expt_vld)); @483
// &Force("nonport","retire_debug_expt_vld_modify"); @484
// &Instance("pa_dtu_cdc_pulse_div_fast_to_slow","x_pa_dtu_tdt_dm_wr_ready_cdc"); @488
// &Connect(.src_clk (dtu_cdc_clk), @489
// .src_rst_b (cpurst_b), @490
// .clk_en(sys_apb_clk_en), @491
// .modify(wr_ready_modify), @492
// .src_pulse(tdt_dm_wr_vld_f), @493
// .dst_pulse(dtu_tdt_dm_wr_ready)); @494
// &CombBeg; @514
// &CombEnd; @525
// &Instance("gated_clk_cell", "x_reg_gated_clk"); @544
gated_clk_cell x_reg_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (dtu_cdc_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (1'b1 ),
.module_en (1'b1 ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @545
// .external_en (1'b0), @546
// .global_en (cp0_yy_clk_en), @547
// //.module_en (cp0_dtu_icg_en), @548
// .module_en (1'b1), @549
// .local_en (1'b1), @550
// .clk_out (dtu_cdc_clk)); @551
// &ModuleEnd; @560
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_dtu_cdc_lvl(
clk,
dst_lvl,
rst_b,
src_lvl
);
// &Ports; @21
input clk;
input rst_b;
input src_lvl;
output dst_lvl;
// &Regs; @22
reg sync1;
reg sync2;
reg sync3;
// &Wires; @23
wire clk;
wire dst_lvl;
wire rst_b;
wire src_lvl;
always @(posedge clk or negedge rst_b)
begin
if(!rst_b)
begin
sync1 <= 1'b0;
sync2 <= 1'b0;
sync3 <= 1'b0;
end
else
begin
sync1 <= src_lvl;
sync2 <= sync1;
sync3 <= sync2;
end
end
assign dst_lvl = sync3;
// &ModuleEnd; @42
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_dtu_cdc_pulse(
dst_clk,
dst_pulse,
dst_rst_b,
src_clk,
src_pulse,
src_rst_b
);
// &Ports; @21
input dst_clk;
input dst_rst_b;
input src_clk;
input src_pulse;
input src_rst_b;
output dst_pulse;
// &Regs; @22
reg dst_sync1;
reg dst_sync2;
reg dst_sync3;
reg dst_sync4;
reg src_lvl;
reg src_sync1;
reg src_sync2;
reg src_sync3;
reg src_sync4;
// &Wires; @23
wire clear_src_lvl;
wire dst_clk;
wire dst_pulse;
wire dst_rst_b;
wire src_clk;
wire src_pulse;
wire src_rst_b;
always @(posedge src_clk or negedge src_rst_b)
begin
if(!src_rst_b)
src_lvl <= 1'b0;
else if(src_pulse)
src_lvl <= 1'b1;
else if(clear_src_lvl)
src_lvl <= 1'b0;
end
always @(posedge dst_clk or negedge dst_rst_b)
begin
if(!dst_rst_b)
begin
dst_sync1 <= 1'b0;
dst_sync2 <= 1'b0;
dst_sync3 <= 1'b0;
dst_sync4 <= 1'b0;
end
else
begin
dst_sync1 <= src_lvl;
dst_sync2 <= dst_sync1;
dst_sync3 <= dst_sync2;
dst_sync4 <= dst_sync3;
end
end
always @(posedge src_clk or negedge src_rst_b)
begin
if(!src_rst_b)
begin
src_sync1 <= 1'b0;
src_sync2 <= 1'b0;
src_sync3 <= 1'b0;
src_sync4 <= 1'b0;
end
else
begin
src_sync1 <= dst_sync3;
src_sync2 <= src_sync1;
src_sync3 <= src_sync2;
src_sync4 <= src_sync3;
end
end
assign clear_src_lvl = src_sync3 && !src_sync4;
assign dst_pulse = dst_sync3 && !dst_sync4;
// &ModuleEnd; @74
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//---------------------Minimum Define-----------------------
`ifdef TDT_TM_MINIMUM
//mcontrol trigger legal number is 0/1/2/3/4/5/6/7/8, there is
//no mcontrol when define "TDT_TM_MCONTROL_TRI_NUM_0"
//`define TDT_TM_MCONTROL_TRI_NUM_0
`define TDT_TM_MCONTROL_TRI_NUM_1
//`define TDT_TM_MCONTROL_TRI_NUM_2
//`define TDT_TM_MCONTROL_TRI_NUM_3
//`define TDT_TM_MCONTROL_TRI_NUM_4
//`define TDT_TM_MCONTROL_TRI_NUM_5
//`define TDT_TM_MCONTROL_TRI_NUM_6
//`define TDT_TM_MCONTROL_TRI_NUM_7
//`define TDT_TM_MCONTROL_TRI_NUM_8
//`define TDT_TM_MCONTROL_CHAIN
//mcontrol trigger configuration
//when MCONTROL_TRI_NUM >= 1, macros of MCONTROL0 are used
`define TDT_TM_MCONTROL0_EXE
//`define TDT_TM_MCONTROL0_LDST
`define TDT_TM_MCONTROL0_ADDR
//`define TDT_TM_MCONTROL0_DATA
`define TDT_TM_MCONTROL0_MATCH_TYP0
//`define TDT_TM_MCONTROL0_MATCH_TYP1
//`define TDT_TM_MCONTROL0_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 2, macros of MCONTROL1 are used
//`define TDT_TM_MCONTROL1_EXE
//`define TDT_TM_MCONTROL1_LDST
//`define TDT_TM_MCONTROL1_ADDR
//`define TDT_TM_MCONTROL1_DATA
//`define TDT_TM_MCONTROL1_MATCH_TYP0
//`define TDT_TM_MCONTROL1_MATCH_TYP1
//`define TDT_TM_MCONTROL1_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 3, macros of MCONTROL2 are used
//`define TDT_TM_MCONTROL2_EXE
//`define TDT_TM_MCONTROL2_LDST
//`define TDT_TM_MCONTROL2_ADDR
//`define TDT_TM_MCONTROL2_DATA
//`define TDT_TM_MCONTROL2_MATCH_TYP0
//`define TDT_TM_MCONTROL2_MATCH_TYP1
//`define TDT_TM_MCONTROL2_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 4, macros of MCONTROL3 are used
//`define TDT_TM_MCONTROL3_EXE
//`define TDT_TM_MCONTROL3_LDST
//`define TDT_TM_MCONTROL3_ADDR
//`define TDT_TM_MCONTROL3_DATA
//`define TDT_TM_MCONTROL3_MATCH_TYP0
//`define TDT_TM_MCONTROL3_MATCH_TYP1
//`define TDT_TM_MCONTROL3_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 5, macros of MCONTROL4 are used
//`define TDT_TM_MCONTROL4_EXE
//`define TDT_TM_MCONTROL4_LDST
//`define TDT_TM_MCONTROL4_ADDR
//`define TDT_TM_MCONTROL4_DATA
//`define TDT_TM_MCONTROL4_MATCH_TYP0
//`define TDT_TM_MCONTROL4_MATCH_TYP1
//`define TDT_TM_MCONTROL4_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 6, macros of MCONTROL5 are used
//`define TDT_TM_MCONTROL5_EXE
//`define TDT_TM_MCONTROL5_LDST
//`define TDT_TM_MCONTROL5_ADDR
//`define TDT_TM_MCONTROL5_DATA
//`define TDT_TM_MCONTROL5_MATCH_TYP0
//`define TDT_TM_MCONTROL5_MATCH_TYP1
//`define TDT_TM_MCONTROL5_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 7, macros of MCONTROL6 are used
//`define TDT_TM_MCONTROL6_EXE
//`define TDT_TM_MCONTROL6_LDST
//`define TDT_TM_MCONTROL6_ADDR
//`define TDT_TM_MCONTROL6_DATA
//`define TDT_TM_MCONTROL6_MATCH_TYP0
//`define TDT_TM_MCONTROL6_MATCH_TYP1
//`define TDT_TM_MCONTROL6_MATCH_TYP2
//when MCONTROL_TRI_NUM = 8, macros of MCONTROL7 are used
//`define TDT_TM_MCONTROL7_EXE
//`define TDT_TM_MCONTROL7_LDST
//`define TDT_TM_MCONTROL7_ADDR
//`define TDT_TM_MCONTROL7_DATA
//`define TDT_TM_MCONTROL7_MATCH_TYP0
//`define TDT_TM_MCONTROL7_MATCH_TYP1
//`define TDT_TM_MCONTROL7_MATCH_TYP2
//icount/int/expt shared trigger legal number is 0/1/2, there is
//no icount/int/expt shared trigger when define "TDT_TM_OTHER_TRI_NUM_0"
`define TDT_TM_OTHER_TRI_NUM_0
//`define TDT_TM_OTHER_TRI_NUM_1
//`define TDT_TM_OTHER_TRI_NUM_2
`endif
//---------------------Typical Define-----------------------
`ifdef TDT_TM_TYPICAL
//mcontrol trigger legal number is 0/1/2/3/4/5/6/7/8, there is
//no mcontrol when define "TDT_TM_MCONTROL_TRI_NUM_0"
//`define TDT_TM_MCONTROL_TRI_NUM_0
//`define TDT_TM_MCONTROL_TRI_NUM_1
//`define TDT_TM_MCONTROL_TRI_NUM_2
`define TDT_TM_MCONTROL_TRI_NUM_3
//`define TDT_TM_MCONTROL_TRI_NUM_4
//`define TDT_TM_MCONTROL_TRI_NUM_5
//`define TDT_TM_MCONTROL_TRI_NUM_6
//`define TDT_TM_MCONTROL_TRI_NUM_7
//`define TDT_TM_MCONTROL_TRI_NUM_8
//`define TDT_TM_MCONTROL_CHAIN
//mcontrol trigger configuration
//when MCONTROL_TRI_NUM >= 1, macros of MCONTROL0 are used
`define TDT_TM_MCONTROL0_EXE
`define TDT_TM_MCONTROL0_LDST
`define TDT_TM_MCONTROL0_ADDR
//`define TDT_TM_MCONTROL0_DATA
`define TDT_TM_MCONTROL0_MATCH_TYP0
//`define TDT_TM_MCONTROL0_MATCH_TYP1
//`define TDT_TM_MCONTROL0_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 2, macros of MCONTROL1 are used
`define TDT_TM_MCONTROL1_EXE
`define TDT_TM_MCONTROL1_LDST
`define TDT_TM_MCONTROL1_ADDR
//`define TDT_TM_MCONTROL1_DATA
`define TDT_TM_MCONTROL1_MATCH_TYP0
//`define TDT_TM_MCONTROL1_MATCH_TYP1
//`define TDT_TM_MCONTROL1_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 3, macros of MCONTROL2 are used
`define TDT_TM_MCONTROL2_EXE
`define TDT_TM_MCONTROL2_LDST
`define TDT_TM_MCONTROL2_ADDR
//`define TDT_TM_MCONTROL2_DATA
`define TDT_TM_MCONTROL2_MATCH_TYP0
//`define TDT_TM_MCONTROL2_MATCH_TYP1
//`define TDT_TM_MCONTROL2_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 4, macros of MCONTROL3 are used
//`define TDT_TM_MCONTROL3_EXE
//`define TDT_TM_MCONTROL3_LDST
//`define TDT_TM_MCONTROL3_ADDR
//`define TDT_TM_MCONTROL3_DATA
//`define TDT_TM_MCONTROL3_MATCH_TYP0
//`define TDT_TM_MCONTROL3_MATCH_TYP1
//`define TDT_TM_MCONTROL3_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 5, macros of MCONTROL4 are used
//`define TDT_TM_MCONTROL4_EXE
//`define TDT_TM_MCONTROL4_LDST
//`define TDT_TM_MCONTROL4_ADDR
//`define TDT_TM_MCONTROL4_DATA
//`define TDT_TM_MCONTROL4_MATCH_TYP0
//`define TDT_TM_MCONTROL4_MATCH_TYP1
//`define TDT_TM_MCONTROL4_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 6, macros of MCONTROL5 are used
//`define TDT_TM_MCONTROL5_EXE
//`define TDT_TM_MCONTROL5_LDST
//`define TDT_TM_MCONTROL5_ADDR
//`define TDT_TM_MCONTROL5_DATA
//`define TDT_TM_MCONTROL5_MATCH_TYP0
//`define TDT_TM_MCONTROL5_MATCH_TYP1
//`define TDT_TM_MCONTROL5_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 7, macros of MCONTROL6 are used
//`define TDT_TM_MCONTROL6_EXE
//`define TDT_TM_MCONTROL6_LDST
//`define TDT_TM_MCONTROL6_ADDR
//`define TDT_TM_MCONTROL6_DATA
//`define TDT_TM_MCONTROL6_MATCH_TYP0
//`define TDT_TM_MCONTROL6_MATCH_TYP1
//`define TDT_TM_MCONTROL6_MATCH_TYP2
//when MCONTROL_TRI_NUM = 8, macros of MCONTROL7 are used
//`define TDT_TM_MCONTROL7_EXE
//`define TDT_TM_MCONTROL7_LDST
//`define TDT_TM_MCONTROL7_ADDR
//`define TDT_TM_MCONTROL7_DATA
//`define TDT_TM_MCONTROL7_MATCH_TYP0
//`define TDT_TM_MCONTROL7_MATCH_TYP1
//`define TDT_TM_MCONTROL7_MATCH_TYP2
//icount/int/expt shared trigger legal number is 0/1/2, there is
//no icount/int/expt shared trigger when define "TDT_TM_OTHER_TRI_NUM_0"
`define TDT_TM_OTHER_TRI_NUM_0
//`define TDT_TM_OTHER_TRI_NUM_1
//`define TDT_TM_OTHER_TRI_NUM_2
`endif
//---------------------Maximum Define-----------------------
`ifdef TDT_TM_MAXIMUM
//mcontrol trigger legal number is 0/1/2/3/4/5/6/7/8, there is
//no mcontrol when define "TDT_TM_MCONTROL_TRI_NUM_0"
//`define TDT_TM_MCONTROL_TRI_NUM_0
//`define TDT_TM_MCONTROL_TRI_NUM_1
//`define TDT_TM_MCONTROL_TRI_NUM_2
//`define TDT_TM_MCONTROL_TRI_NUM_3
//`define TDT_TM_MCONTROL_TRI_NUM_4
//`define TDT_TM_MCONTROL_TRI_NUM_5
//`define TDT_TM_MCONTROL_TRI_NUM_6
//`define TDT_TM_MCONTROL_TRI_NUM_7
`define TDT_TM_MCONTROL_TRI_NUM_8
`define TDT_TM_MCONTROL_CHAIN
//mcontrol trigger configuration
//when MCONTROL_TRI_NUM >= 1, macros of MCONTROL0 are used
`define TDT_TM_MCONTROL0_EXE
`define TDT_TM_MCONTROL0_LDST
`define TDT_TM_MCONTROL0_ADDR
`define TDT_TM_MCONTROL0_DATA
//`define TDT_TM_MCONTROL0_MATCH_TYP0
//`define TDT_TM_MCONTROL0_MATCH_TYP1
`define TDT_TM_MCONTROL0_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 2, macros of MCONTROL1 are used
`define TDT_TM_MCONTROL1_EXE
`define TDT_TM_MCONTROL1_LDST
`define TDT_TM_MCONTROL1_ADDR
`define TDT_TM_MCONTROL1_DATA
//`define TDT_TM_MCONTROL1_MATCH_TYP0
//`define TDT_TM_MCONTROL1_MATCH_TYP1
`define TDT_TM_MCONTROL1_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 3, macros of MCONTROL2 are used
`define TDT_TM_MCONTROL2_EXE
`define TDT_TM_MCONTROL2_LDST
`define TDT_TM_MCONTROL2_ADDR
`define TDT_TM_MCONTROL2_DATA
//`define TDT_TM_MCONTROL2_MATCH_TYP0
//`define TDT_TM_MCONTROL2_MATCH_TYP1
`define TDT_TM_MCONTROL2_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 4, macros of MCONTROL3 are used
`define TDT_TM_MCONTROL3_EXE
`define TDT_TM_MCONTROL3_LDST
`define TDT_TM_MCONTROL3_ADDR
`define TDT_TM_MCONTROL3_DATA
//`define TDT_TM_MCONTROL3_MATCH_TYP0
//`define TDT_TM_MCONTROL3_MATCH_TYP1
`define TDT_TM_MCONTROL3_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 5, macros of MCONTROL4 are used
`define TDT_TM_MCONTROL4_EXE
`define TDT_TM_MCONTROL4_LDST
`define TDT_TM_MCONTROL4_ADDR
`define TDT_TM_MCONTROL4_DATA
//`define TDT_TM_MCONTROL4_MATCH_TYP0
//`define TDT_TM_MCONTROL4_MATCH_TYP1
`define TDT_TM_MCONTROL4_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 6, macros of MCONTROL5 are used
`define TDT_TM_MCONTROL5_EXE
`define TDT_TM_MCONTROL5_LDST
`define TDT_TM_MCONTROL5_ADDR
`define TDT_TM_MCONTROL5_DATA
//`define TDT_TM_MCONTROL5_MATCH_TYP0
//`define TDT_TM_MCONTROL5_MATCH_TYP1
`define TDT_TM_MCONTROL5_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 7, macros of MCONTROL6 are used
`define TDT_TM_MCONTROL6_EXE
`define TDT_TM_MCONTROL6_LDST
`define TDT_TM_MCONTROL6_ADDR
`define TDT_TM_MCONTROL6_DATA
//`define TDT_TM_MCONTROL6_MATCH_TYP0
//`define TDT_TM_MCONTROL6_MATCH_TYP1
`define TDT_TM_MCONTROL6_MATCH_TYP2
//when MCONTROL_TRI_NUM = 8, macros of MCONTROL7 are used
`define TDT_TM_MCONTROL7_EXE
`define TDT_TM_MCONTROL7_LDST
`define TDT_TM_MCONTROL7_ADDR
`define TDT_TM_MCONTROL7_DATA
//`define TDT_TM_MCONTROL7_MATCH_TYP0
//`define TDT_TM_MCONTROL7_MATCH_TYP1
`define TDT_TM_MCONTROL7_MATCH_TYP2
//icount/int/expt shared trigger legal number is 0/1/2, there is
//no icount/int/expt shared trigger when define "TDT_TM_OTHER_TRI_NUM_0"
//`define TDT_TM_OTHER_TRI_NUM_0
//`define TDT_TM_OTHER_TRI_NUM_1
`define TDT_TM_OTHER_TRI_NUM_2
`endif
//---------------------Self Define-----------------------
`ifdef TDT_TM_SELF_DEF
//mcontrol trigger legal number is 0/1/2/3/4/5/6/7/8, there is
//no mcontrol when define "TDT_TM_MCONTROL_TRI_NUM_0"
//`define TDT_TM_MCONTROL_TRI_NUM_0
//`define TDT_TM_MCONTROL_TRI_NUM_1
//`define TDT_TM_MCONTROL_TRI_NUM_2
`define TDT_TM_MCONTROL_TRI_NUM_3
//`define TDT_TM_MCONTROL_TRI_NUM_4
//`define TDT_TM_MCONTROL_TRI_NUM_5
//`define TDT_TM_MCONTROL_TRI_NUM_6
//`define TDT_TM_MCONTROL_TRI_NUM_7
//`define TDT_TM_MCONTROL_TRI_NUM_8
//`define TDT_TM_MCONTROL_CHAIN
//mcontrol trigger configuration
//when MCONTROL_TRI_NUM >= 1, macros of MCONTROL0 are used
`define TDT_TM_MCONTROL0_EXE
`define TDT_TM_MCONTROL0_LDST
`define TDT_TM_MCONTROL0_ADDR
//`define TDT_TM_MCONTROL0_DATA
`define TDT_TM_MCONTROL0_MATCH_TYP0
//`define TDT_TM_MCONTROL0_MATCH_TYP1
//`define TDT_TM_MCONTROL0_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 2, macros of MCONTROL1 are used
`define TDT_TM_MCONTROL1_EXE
`define TDT_TM_MCONTROL1_LDST
`define TDT_TM_MCONTROL1_ADDR
//`define TDT_TM_MCONTROL1_DATA
`define TDT_TM_MCONTROL1_MATCH_TYP0
//`define TDT_TM_MCONTROL1_MATCH_TYP1
//`define TDT_TM_MCONTROL1_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 3, macros of MCONTROL2 are used
`define TDT_TM_MCONTROL2_EXE
`define TDT_TM_MCONTROL2_LDST
`define TDT_TM_MCONTROL2_ADDR
//`define TDT_TM_MCONTROL2_DATA
`define TDT_TM_MCONTROL2_MATCH_TYP0
//`define TDT_TM_MCONTROL2_MATCH_TYP1
//`define TDT_TM_MCONTROL2_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 4, macros of MCONTROL3 are used
//`define TDT_TM_MCONTROL3_EXE
//`define TDT_TM_MCONTROL3_LDST
//`define TDT_TM_MCONTROL3_ADDR
//`define TDT_TM_MCONTROL3_DATA
//`define TDT_TM_MCONTROL3_MATCH_TYP0
//`define TDT_TM_MCONTROL3_MATCH_TYP1
//`define TDT_TM_MCONTROL3_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 5, macros of MCONTROL4 are used
//`define TDT_TM_MCONTROL4_EXE
//`define TDT_TM_MCONTROL4_LDST
//`define TDT_TM_MCONTROL4_ADDR
//`define TDT_TM_MCONTROL4_DATA
//`define TDT_TM_MCONTROL4_MATCH_TYP0
//`define TDT_TM_MCONTROL4_MATCH_TYP1
//`define TDT_TM_MCONTROL4_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 6, macros of MCONTROL5 are used
//`define TDT_TM_MCONTROL5_EXE
//`define TDT_TM_MCONTROL5_LDST
//`define TDT_TM_MCONTROL5_ADDR
//`define TDT_TM_MCONTROL5_DATA
//`define TDT_TM_MCONTROL5_MATCH_TYP0
//`define TDT_TM_MCONTROL5_MATCH_TYP1
//`define TDT_TM_MCONTROL5_MATCH_TYP2
//when MCONTROL_TRI_NUM >= 7, macros of MCONTROL6 are used
//`define TDT_TM_MCONTROL6_EXE
//`define TDT_TM_MCONTROL6_LDST
//`define TDT_TM_MCONTROL6_ADDR
//`define TDT_TM_MCONTROL6_DATA
//`define TDT_TM_MCONTROL6_MATCH_TYP0
//`define TDT_TM_MCONTROL6_MATCH_TYP1
//`define TDT_TM_MCONTROL6_MATCH_TYP2
//when MCONTROL_TRI_NUM = 8, macros of MCONTROL7 are used
//`define TDT_TM_MCONTROL7_EXE
//`define TDT_TM_MCONTROL7_LDST
//`define TDT_TM_MCONTROL7_ADDR
//`define TDT_TM_MCONTROL7_DATA
//`define TDT_TM_MCONTROL7_MATCH_TYP0
//`define TDT_TM_MCONTROL7_MATCH_TYP1
//`define TDT_TM_MCONTROL7_MATCH_TYP2
//icount/int/expt shared trigger legal number is 0/1/2, there is
//no icount/int/expt shared trigger when define "TDT_TM_OTHER_TRI_NUM_0"
`define TDT_TM_OTHER_TRI_NUM_0
//`define TDT_TM_OTHER_TRI_NUM_1
//`define TDT_TM_OTHER_TRI_NUM_2
`endif
//---------------------------------------------------------
// TM Trigger Number Configuration
//---------------------------------------------------------
`ifdef TDT_TM_OTHER_TRI_NUM_0
`define TDT_TM_OTHER_TRI_NUM 0
`else
`ifdef TDT_TM_OTHER_TRI_NUM_1
`define TDT_TM_OTHER_TRI_NUM 1
`else
`ifdef TDT_TM_OTHER_TRI_NUM_2
`define TDT_TM_OTHER_TRI_NUM 2
`endif
`endif
`endif
`ifdef TDT_TM_MCONTROL_TRI_NUM_0
`define TDT_TM_MCONTROL_TRI_NUM 0
`else
`ifdef TDT_TM_MCONTROL_TRI_NUM_1
`define TDT_TM_MCONTROL_TRI_NUM 1
`else
`ifdef TDT_TM_MCONTROL_TRI_NUM_2
`define TDT_TM_MCONTROL_TRI_NUM 2
`else
`ifdef TDT_TM_MCONTROL_TRI_NUM_3
`define TDT_TM_MCONTROL_TRI_NUM 3
`else
`ifdef TDT_TM_MCONTROL_TRI_NUM_4
`define TDT_TM_MCONTROL_TRI_NUM 4
`else
`ifdef TDT_TM_MCONTROL_TRI_NUM_5
`define TDT_TM_MCONTROL_TRI_NUM 5
`else
`ifdef TDT_TM_MCONTROL_TRI_NUM_6
`define TDT_TM_MCONTROL_TRI_NUM 6
`else
`ifdef TDT_TM_MCONTROL_TRI_NUM_7
`define TDT_TM_MCONTROL_TRI_NUM 7
`else
`ifdef TDT_TM_MCONTROL_TRI_NUM_8
`define TDT_TM_MCONTROL_TRI_NUM 8
`endif
`endif
`endif
`endif
`endif
`endif
`endif
`endif
`endif
`ifdef TDT_TM_MCONTROL_TRI_NUM_0
`ifdef TDT_TM_OTHER_TRI_NUM_1
`define TDT_TM_SINGLE_TRI
`endif
`else
`ifdef TDT_TM_MCONTROL_TRI_NUM_1
`ifdef TDT_TM_OTHER_TRI_NUM_0
`define TDT_TM_SINGLE_TRI
`endif
`endif
`endif
//==========================================================
// DTU Configuration
//==========================================================
//---------------------------------------------------------
// TM Trigger Configuration
//---------------------------------------------------------
`define TDT_TM_TRIGGER_NUM `TDT_TM_MCONTROL_TRI_NUM + `TDT_TM_OTHER_TRI_NUM
//----------------------------------------------------------
// HALT INFO Define
//----------------------------------------------------------
`define TDT_HINFO_WIDTH `TDT_HINFO_TRIGGER + 1
`define TDT_HINFO_TRIGGER `TDT_HINFO_CAUSE + `TDT_TM_TRIGGER_NUM
`define TDT_HINFO_CAUSE `TDT_HINFO_PENDING_HALT + 4
`define TDT_HINFO_PENDING_HALT `TDT_HINFO_TIMING + 1
`define TDT_HINFO_TIMING `TDT_HINFO_ACTION01 + 1
`define TDT_HINFO_ACTION01 `TDT_HINFO_ACTION + 1
`define TDT_HINFO_ACTION `TDT_HINFO_CHAIN + 1
`define TDT_HINFO_CHAIN `TDT_HINFO_LDST + 1
`define TDT_HINFO_LDST `TDT_HINFO_MATCH + 1
`define TDT_HINFO_MATCH `TDT_HINFO_CANCEL + 1
`define TDT_HINFO_CANCEL 0
//----------------------------------------------------------
// DTU Define
//----------------------------------------------------------
`define TDT_DM_CORE_HALF_XLEN 16
`define HALF_PA_WIDTH 16
//debuginfo define
`ifdef AXI
`define TDT_DBGINFO_WIDTH 278
`define TDT_DBGINFO_DEPTH 10
`else
`define TDT_DBGINFO_WIDTH 298
`define TDT_DBGINFO_DEPTH 11
`endif
//pcfifo define
`ifdef TDT_DEBUG_PCFIFO_8_ENTRY
`define TDT_PCFIFO_DEPTH 8
`define TDT_PCFIFO_PTR_WIDTH 3
`else
`ifdef TDT_DEBUG_PCFIFO_16_ENTRY
`define TDT_PCFIFO_DEPTH 16
`define TDT_PCFIFO_PTR_WIDTH 4
`endif
`endif
//for fix tselect trigger number legalization(to fix lint warning)
`define MCONTROL_NUM 4'd`TDT_TM_MCONTROL_TRI_NUM
`define IIE_NUM 4'd`TDT_TM_OTHER_TRI_NUM

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opene906/E906_RTL_FACTORY/gen_rtl/dtu/rtl/pa_dtu_ctrl.v Normal file
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_dtu_ctrl(
async_halt_req_wakeup,
bmu_dtu_debug_info,
cp0_dtu_addr,
cp0_dtu_debug_info,
cp0_dtu_icg_en,
cp0_dtu_mexpt_vld,
cp0_dtu_pcfifo_frz,
cp0_dtu_rreg,
cp0_dtu_wdata,
cp0_dtu_wreg,
cp0_yy_clk_en,
cp0_yy_priv_mode,
cpurst_b,
dahbl_dtu_debug_info,
dcsr_mprven,
dcsr_prv,
dcsr_step,
dcsr_stopcount,
dpc,
dscratch0,
dtu_cp0_rdata,
dtu_ifu_halt_info0,
dtu_ifu_halt_info1,
dtu_ifu_halt_info_vld,
dtu_lsu_halt_info,
dtu_lsu_halt_info_vld,
dtu_rtu_async_halt_req,
dtu_rtu_pending_tval,
dtu_rtu_sync_halt_req,
ebreak_action,
forever_cpuclk,
fpu_dtu_debug_info,
iahbl_dtu_debug_info,
icount_enable,
idu_dtu_debug_info,
idu_dtu_fpr_info,
ifu_dtu_addr_vld0,
ifu_dtu_addr_vld1,
ifu_dtu_data_vld0,
ifu_dtu_data_vld1,
ifu_dtu_debug_info,
ifu_dtu_exe_addr0,
ifu_dtu_exe_addr1,
ifu_dtu_exe_data0,
ifu_dtu_exe_data1,
int_mask,
iu_dtu_debug_info,
latest_pc,
ldst_addr_mcontrol,
ldst_data_mcontrol,
low_power_wakeup,
lsu_dtu_debug_info,
lsu_dtu_halt_info,
lsu_dtu_last_check,
lsu_dtu_ldst_addr,
lsu_dtu_ldst_addr_vld,
lsu_dtu_ldst_bytes_vld,
lsu_dtu_ldst_data,
lsu_dtu_ldst_data_vld,
lsu_dtu_ldst_type,
lsu_dtu_mem_access_size,
pad_yy_icg_scan_en,
rtu_dtu_debug_info,
rtu_dtu_dpc,
rtu_dtu_halt_ack,
rtu_dtu_nmi_pending,
rtu_dtu_pending_ack,
rtu_dtu_retire_chgflw,
rtu_dtu_retire_halt_info,
rtu_dtu_retire_mret,
rtu_dtu_retire_next_pc,
rtu_dtu_retire_vld,
rtu_dtu_tval,
rtu_yy_xx_dbgon,
sahbl_dtu_debug_info,
tdt_dm_wdata,
tdt_dm_wr_flg,
tdt_dm_wr_vld
);
// &Ports; @24
input async_halt_req_wakeup;
input [3 :0] bmu_dtu_debug_info;
input [11:0] cp0_dtu_addr;
input [5 :0] cp0_dtu_debug_info;
input cp0_dtu_icg_en;
input cp0_dtu_mexpt_vld;
input cp0_dtu_pcfifo_frz;
input cp0_dtu_rreg;
input [31:0] cp0_dtu_wdata;
input cp0_dtu_wreg;
input cp0_yy_clk_en;
input [1 :0] cp0_yy_priv_mode;
input cpurst_b;
input [10:0] dahbl_dtu_debug_info;
input dtu_rtu_async_halt_req;
input dtu_rtu_sync_halt_req;
input forever_cpuclk;
input [7 :0] fpu_dtu_debug_info;
input [10:0] iahbl_dtu_debug_info;
input [21:0] idu_dtu_debug_info;
input [95:0] idu_dtu_fpr_info;
input ifu_dtu_addr_vld0;
input ifu_dtu_addr_vld1;
input ifu_dtu_data_vld0;
input ifu_dtu_data_vld1;
input [26:0] ifu_dtu_debug_info;
input [31:0] ifu_dtu_exe_addr0;
input [31:0] ifu_dtu_exe_addr1;
input [31:0] ifu_dtu_exe_data0;
input [31:0] ifu_dtu_exe_data1;
input [8 :0] iu_dtu_debug_info;
input [78:0] lsu_dtu_debug_info;
input [14:0] lsu_dtu_halt_info;
input lsu_dtu_last_check;
input [31:0] lsu_dtu_ldst_addr;
input lsu_dtu_ldst_addr_vld;
input [7 :0] lsu_dtu_ldst_bytes_vld;
input [31:0] lsu_dtu_ldst_data;
input lsu_dtu_ldst_data_vld;
input [1 :0] lsu_dtu_ldst_type;
input [1 :0] lsu_dtu_mem_access_size;
input pad_yy_icg_scan_en;
input [13:0] rtu_dtu_debug_info;
input [31:0] rtu_dtu_dpc;
input rtu_dtu_halt_ack;
input rtu_dtu_nmi_pending;
input rtu_dtu_pending_ack;
input rtu_dtu_retire_chgflw;
input [14:0] rtu_dtu_retire_halt_info;
input rtu_dtu_retire_mret;
input [31:0] rtu_dtu_retire_next_pc;
input rtu_dtu_retire_vld;
input [31:0] rtu_dtu_tval;
input rtu_yy_xx_dbgon;
input [10:0] sahbl_dtu_debug_info;
input [31:0] tdt_dm_wdata;
input [1 :0] tdt_dm_wr_flg;
input tdt_dm_wr_vld;
output dcsr_mprven;
output [1 :0] dcsr_prv;
output dcsr_step;
output dcsr_stopcount;
output [31:0] dpc;
output [31:0] dscratch0;
output [31:0] dtu_cp0_rdata;
output [14:0] dtu_ifu_halt_info0;
output [14:0] dtu_ifu_halt_info1;
output dtu_ifu_halt_info_vld;
output [14:0] dtu_lsu_halt_info;
output dtu_lsu_halt_info_vld;
output [31:0] dtu_rtu_pending_tval;
output ebreak_action;
output icount_enable;
output int_mask;
output [31:0] latest_pc;
output ldst_addr_mcontrol;
output ldst_data_mcontrol;
output low_power_wakeup;
// &Regs; @25
reg [2 :0] dcsr_cause;
reg dcsr_ebreakm;
reg dcsr_ebreaku;
reg dcsr_mprven;
reg [1 :0] dcsr_prv;
reg dcsr_step;
reg dcsr_stepie;
reg dcsr_stopcount;
reg [31:0] dpc;
reg [31:0] dscratch0;
reg [31:0] dscratch1;
reg [31:0] dtu_cp0_rdata;
reg [3 :0] haltcause;
// &Wires; @26
wire async_halt_req_wakeup;
wire [3 :0] bmu_dtu_debug_info;
wire [11:0] cp0_dtu_addr;
wire [5 :0] cp0_dtu_debug_info;
wire cp0_dtu_icg_en;
wire cp0_dtu_mexpt_vld;
wire cp0_dtu_pcfifo_frz;
wire cp0_dtu_rreg;
wire [31:0] cp0_dtu_wdata;
wire cp0_dtu_wreg;
wire cp0_write_dcsr;
wire cp0_write_dpc;
wire cp0_write_dscratch0;
wire cp0_write_dscratch1;
wire cp0_yy_clk_en;
wire [1 :0] cp0_yy_priv_mode;
wire cpurst_b;
wire [10:0] dahbl_dtu_debug_info;
wire [31:0] dbgfifo_regs_data;
wire [31:0] dcsr;
wire dcsr_dpc_haltcause_clk;
wire dcsr_dpc_haltcause_clk_en;
wire dcsr_nmip;
wire [3 :0] dcsr_xdebugver;
wire dscratch01_clk;
wire dscratch01_clk_en;
wire [3 :0] dtu_cause;
wire [14:0] dtu_ifu_halt_info0;
wire [14:0] dtu_ifu_halt_info1;
wire dtu_ifu_halt_info_vld;
wire [14:0] dtu_lsu_halt_info;
wire dtu_lsu_halt_info_vld;
wire dtu_rtu_async_halt_req;
wire [31:0] dtu_rtu_pending_tval;
wire dtu_rtu_sync_halt_req;
wire ebreak_action;
wire forever_cpuclk;
wire [7 :0] fpu_dtu_debug_info;
wire [10:0] iahbl_dtu_debug_info;
wire icount_enable;
wire [21:0] idu_dtu_debug_info;
wire [95:0] idu_dtu_fpr_info;
wire ifu_dtu_addr_vld0;
wire ifu_dtu_addr_vld1;
wire ifu_dtu_data_vld0;
wire ifu_dtu_data_vld1;
wire [26:0] ifu_dtu_debug_info;
wire [31:0] ifu_dtu_exe_addr0;
wire [31:0] ifu_dtu_exe_addr1;
wire [31:0] ifu_dtu_exe_data0;
wire [31:0] ifu_dtu_exe_data1;
wire int_mask;
wire [8 :0] iu_dtu_debug_info;
wire [31:0] latest_pc;
wire ldst_addr_mcontrol;
wire ldst_data_mcontrol;
wire low_power_wakeup;
wire [78:0] lsu_dtu_debug_info;
wire [14:0] lsu_dtu_halt_info;
wire lsu_dtu_last_check;
wire [31:0] lsu_dtu_ldst_addr;
wire lsu_dtu_ldst_addr_vld;
wire [7 :0] lsu_dtu_ldst_bytes_vld;
wire [31:0] lsu_dtu_ldst_data;
wire lsu_dtu_ldst_data_vld;
wire [1 :0] lsu_dtu_ldst_type;
wire [1 :0] lsu_dtu_mem_access_size;
wire [31:0] mcontext;
wire pad_yy_icg_scan_en;
wire [31:0] pcfifo_regs_data;
wire pending_halt;
wire [13:0] rtu_dtu_debug_info;
wire [31:0] rtu_dtu_dpc;
wire rtu_dtu_halt_ack;
wire rtu_dtu_nmi_pending;
wire rtu_dtu_pending_ack;
wire rtu_dtu_retire_chgflw;
wire [14:0] rtu_dtu_retire_halt_info;
wire rtu_dtu_retire_mret;
wire [31:0] rtu_dtu_retire_next_pc;
wire rtu_dtu_retire_vld;
wire [31:0] rtu_dtu_tval;
wire rtu_yy_xx_dbgon;
wire [10:0] sahbl_dtu_debug_info;
wire [31:0] tcontrol;
wire [31:0] tdata1;
wire [31:0] tdata2;
wire [31:0] tdata3;
wire [31:0] tdt_dm_wdata;
wire [1 :0] tdt_dm_wr_flg;
wire tdt_dm_wr_vld;
wire tdt_dm_write_dscratch0;
wire [31:0] tinfo;
wire [31:0] tselect;
wire updata_tval;
//XLEN
parameter XLEN = `TDT_DM_CORE_MAX_XLEN;
//dcsr parameter
parameter PRV = 1;
parameter STEP = 2;
parameter MPRVEN = 4;
//parameter DCSR_CAUSE = 8;
//parameter STOPTIME = 9;
parameter STOPCOUNT = 10;
parameter STEPIE = 11;
parameter EBREAKU = 12;
parameter EBREAKS = 13;
parameter EBREAKM = 15;
//===============================================================
//Core Debug Register
//
//dcsr, dpc, dscratch0, dscratch1, hatlcause, dbginfo, pcfifo
//===============================================================
//core csr and write req
assign cp0_write_dcsr = cp0_dtu_wreg && cp0_dtu_addr[11:0] == 12'h7b0 && rtu_yy_xx_dbgon;
assign cp0_write_dpc = cp0_dtu_wreg && cp0_dtu_addr[11:0] == 12'h7b1 && rtu_yy_xx_dbgon;
assign cp0_write_dscratch0 = cp0_dtu_wreg && cp0_dtu_addr[11:0] == 12'h7b2 && rtu_yy_xx_dbgon;
assign cp0_write_dscratch1 = cp0_dtu_wreg && cp0_dtu_addr[11:0] == 12'h7b3 && rtu_yy_xx_dbgon;
assign tdt_dm_write_dscratch0 = tdt_dm_wr_vld && tdt_dm_wr_flg[1:0] == 2'b01 && rtu_yy_xx_dbgon;
//===============================================================
// Define the DCSR
//===============================================================
assign dcsr_nmip = rtu_dtu_nmi_pending;//nmip
assign dcsr_xdebugver[3:0] = 4'b0100;//xdebugver
always @(posedge dcsr_dpc_haltcause_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
dcsr_step <= 1'b0;
dcsr_mprven <= 1'b0;
dcsr_stopcount <= 1'b0;
dcsr_stepie <= 1'b0;
dcsr_ebreaku <= 1'b0;
//dcsr_ebreaks <= 1'b0;
dcsr_ebreakm <= 1'b0;
end
else if(cp0_write_dcsr)
begin
dcsr_step <= cp0_dtu_wdata[STEP];
dcsr_mprven <= cp0_dtu_wdata[MPRVEN];
dcsr_stopcount <= cp0_dtu_wdata[STOPCOUNT];
dcsr_stepie <= cp0_dtu_wdata[STEPIE];
dcsr_ebreaku <= cp0_dtu_wdata[EBREAKU];
//dcsr_ebreaks <= cp0_dtu_wdata[EBREAKS];
dcsr_ebreakm <= cp0_dtu_wdata[EBREAKM];
end
end
// &Force("output","dcsr_mprven"); @85
// &Force("output","dcsr_stopcount"); @86
// &Force("output","dcsr_step"); @87
always @(posedge dcsr_dpc_haltcause_clk or negedge cpurst_b)
begin
if(!cpurst_b)
dcsr_prv[1:0] <= 2'b0;
else if(rtu_dtu_halt_ack)
dcsr_prv[1:0] <= cp0_yy_priv_mode[1:0];
else if(cp0_write_dcsr)
dcsr_prv[1:0] <= cp0_dtu_wdata[PRV:0];
end
// &Force("output","dcsr_prv"); @98
always @(posedge dcsr_dpc_haltcause_clk or negedge cpurst_b)
begin
if(!cpurst_b)
dcsr_cause[2:0] <= 3'b0;
else if(rtu_dtu_halt_ack)
dcsr_cause[2:0] <= dtu_cause[2:0];
end
assign dcsr[31:0] ={dcsr_xdebugver[3:0],{12{1'b0}},dcsr_ebreakm,1'b0,1'b0,dcsr_ebreaku,
dcsr_stepie,dcsr_stopcount,1'b0,dcsr_cause[2:0],1'b0,dcsr_mprven,
dcsr_nmip,dcsr_step,dcsr_prv[1:0]};
//generate int_mask and ebreak_action for rtu
assign int_mask = dcsr_step && !dcsr_stepie;
assign ebreak_action = cp0_yy_priv_mode[1:0] == 2'b00 && dcsr_ebreaku ||
//cp0_yy_priv_mode[1:0] == 2'b01 && dcsr_ebreaks ||
cp0_yy_priv_mode[1:0] == 2'b11 && dcsr_ebreakm;
//===============================================================
// Define the DPC
//===============================================================
always @(posedge dcsr_dpc_haltcause_clk or negedge cpurst_b)
begin
if(!cpurst_b)
dpc[XLEN-1:0] <= {XLEN{1'b0}};
else if(cp0_write_dpc)
dpc[XLEN-1:0] <= cp0_dtu_wdata[XLEN-1:0];
else if(rtu_dtu_halt_ack)
dpc[XLEN-1:0] <= rtu_dtu_dpc[XLEN-1:0];
end
// &Force("output","dpc"); @129
//===============================================================
// Define the DSCRATCH0
//===============================================================
always @(posedge dscratch01_clk or negedge cpurst_b)
begin
if(!cpurst_b)
dscratch0[XLEN-1:0] <= {XLEN{1'b0}};
else if(updata_tval)
dscratch0[XLEN-1:0] <= rtu_dtu_tval[XLEN-1:0];
else if(cp0_write_dscratch0)
dscratch0[XLEN-1:0] <= cp0_dtu_wdata[XLEN-1:0];
else if(tdt_dm_write_dscratch0)
dscratch0[XLEN-1:0] <= tdt_dm_wdata[XLEN-1:0];
end
// &Force("output","dscratch0"); @145
assign dtu_rtu_pending_tval[XLEN-1:0] = dscratch0[XLEN-1:0];
//===============================================================
// Define the DSCRATCH1
//===============================================================
always @(posedge dscratch01_clk or negedge cpurst_b)
begin
if(!cpurst_b)
dscratch1[XLEN-1:0] <= {XLEN{1'b0}};
else if(cp0_write_dscratch1)
dscratch1[XLEN-1:0] <= cp0_dtu_wdata[XLEN-1:0];
end
//===============================================================
// Define the HALTCAUSE
//===============================================================
always @(posedge dcsr_dpc_haltcause_clk or negedge cpurst_b)
begin
if(!cpurst_b)
haltcause[3:0] <= {4{1'b0}};
else if(rtu_dtu_halt_ack)
haltcause[3:0] <= dtu_cause[3:0];
end
//===============================================================
// Define the pcfifo
//===============================================================
// &Instance("pa_dtu_pcfifo"); @173
pa_dtu_pcfifo x_pa_dtu_pcfifo (
.cp0_dtu_addr (cp0_dtu_addr ),
.cp0_dtu_icg_en (cp0_dtu_icg_en ),
.cp0_dtu_pcfifo_frz (cp0_dtu_pcfifo_frz ),
.cp0_dtu_rreg (cp0_dtu_rreg ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.latest_pc (latest_pc ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.pcfifo_regs_data (pcfifo_regs_data ),
.rtu_dtu_halt_ack (rtu_dtu_halt_ack ),
.rtu_dtu_retire_chgflw (rtu_dtu_retire_chgflw ),
.rtu_dtu_retire_next_pc (rtu_dtu_retire_next_pc),
.rtu_dtu_retire_vld (rtu_dtu_retire_vld )
);
// &Force("input","cp0_dtu_pcfifo_frz"); @175
// &Force("input","rtu_dtu_retire_chgflw"); @176
// &Force("input","rtu_dtu_retire_next_pc");&Force("bus","rtu_dtu_retire_next_pc",`PA_WIDTH-1,0); @177
//===============================================================
// Define the dbginfo
//===============================================================
// &Instance("pa_dtu_dbginfo"); @184
pa_dtu_dbginfo x_pa_dtu_dbginfo (
.bmu_dtu_debug_info (bmu_dtu_debug_info ),
.cp0_dtu_addr (cp0_dtu_addr ),
.cp0_dtu_debug_info (cp0_dtu_debug_info ),
.cp0_dtu_icg_en (cp0_dtu_icg_en ),
.cp0_dtu_rreg (cp0_dtu_rreg ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.dahbl_dtu_debug_info (dahbl_dtu_debug_info ),
.dbgfifo_regs_data (dbgfifo_regs_data ),
.dtu_rtu_async_halt_req (dtu_rtu_async_halt_req),
.forever_cpuclk (forever_cpuclk ),
.fpu_dtu_debug_info (fpu_dtu_debug_info ),
.iahbl_dtu_debug_info (iahbl_dtu_debug_info ),
.idu_dtu_debug_info (idu_dtu_debug_info ),
.idu_dtu_fpr_info (idu_dtu_fpr_info ),
.ifu_dtu_debug_info (ifu_dtu_debug_info ),
.iu_dtu_debug_info (iu_dtu_debug_info ),
.lsu_dtu_debug_info (lsu_dtu_debug_info ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_dtu_debug_info (rtu_dtu_debug_info ),
.sahbl_dtu_debug_info (sahbl_dtu_debug_info )
);
// &Force("input","pahbl_dtu_debug_info");&Force("bus","pahbl_dtu_debug_info",6,0); @187
// &Force("input","biu_dtu_debug_info");&Force("bus","biu_dtu_debug_info",9,0); @188
// &Force("input","sahbl_dtu_debug_info");&Force("bus","sahbl_dtu_debug_info",10,0); @190
// &Force("input","dahbl_dtu_debug_info");&Force("bus","dahbl_dtu_debug_info",10,0); @191
// &Force("input","iahbl_dtu_debug_info");&Force("bus","iahbl_dtu_debug_info",10,0); @192
// &Force("input","bmu_dtu_debug_info");&Force("bus","bmu_dtu_debug_info",3,0); @193
// &Force("input","idu_dtu_fpr_info");&Force("bus","idu_dtu_fpr_info",95,0); @195
// &Force("input","fpu_dtu_debug_info");&Force("bus","fpu_dtu_debug_info",7,0); @197
// &Force("input","cp0_dtu_debug_info");&Force("bus","cp0_dtu_debug_info",5,0); @200
// &Force("input","rtu_dtu_debug_info");&Force("bus","rtu_dtu_debug_info",13,0); @201
// &Force("input","iu_dtu_debug_info");&Force("bus","iu_dtu_debug_info",8,0); @202
// &Force("input","lsu_dtu_debug_info");&Force("bus","lsu_dtu_debug_info",78,0); @203
// &Force("input","idu_dtu_debug_info");&Force("bus","idu_dtu_debug_info",21,0); @204
// &Force("input","ifu_dtu_debug_info");&Force("bus","ifu_dtu_debug_info",26,0); @205
//csr and read req
//===============================================================
// Define the Trigger Module
//===============================================================
// &Instance("pa_dtu_trigger_module"); @212
pa_dtu_trigger_module x_pa_dtu_trigger_module (
.cp0_dtu_addr (cp0_dtu_addr ),
.cp0_dtu_icg_en (cp0_dtu_icg_en ),
.cp0_dtu_mexpt_vld (cp0_dtu_mexpt_vld ),
.cp0_dtu_wdata (cp0_dtu_wdata ),
.cp0_dtu_wreg (cp0_dtu_wreg ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cp0_yy_priv_mode (cp0_yy_priv_mode ),
.cpurst_b (cpurst_b ),
.dtu_cause (dtu_cause ),
.dtu_ifu_halt_info0 (dtu_ifu_halt_info0 ),
.dtu_ifu_halt_info1 (dtu_ifu_halt_info1 ),
.dtu_ifu_halt_info_vld (dtu_ifu_halt_info_vld ),
.dtu_lsu_halt_info (dtu_lsu_halt_info ),
.dtu_lsu_halt_info_vld (dtu_lsu_halt_info_vld ),
.forever_cpuclk (forever_cpuclk ),
.icount_enable (icount_enable ),
.ifu_dtu_addr_vld0 (ifu_dtu_addr_vld0 ),
.ifu_dtu_addr_vld1 (ifu_dtu_addr_vld1 ),
.ifu_dtu_data_vld0 (ifu_dtu_data_vld0 ),
.ifu_dtu_data_vld1 (ifu_dtu_data_vld1 ),
.ifu_dtu_exe_addr0 (ifu_dtu_exe_addr0 ),
.ifu_dtu_exe_addr1 (ifu_dtu_exe_addr1 ),
.ifu_dtu_exe_data0 (ifu_dtu_exe_data0 ),
.ifu_dtu_exe_data1 (ifu_dtu_exe_data1 ),
.ldst_addr_mcontrol (ldst_addr_mcontrol ),
.ldst_data_mcontrol (ldst_data_mcontrol ),
.lsu_dtu_halt_info (lsu_dtu_halt_info ),
.lsu_dtu_last_check (lsu_dtu_last_check ),
.lsu_dtu_ldst_addr (lsu_dtu_ldst_addr ),
.lsu_dtu_ldst_addr_vld (lsu_dtu_ldst_addr_vld ),
.lsu_dtu_ldst_bytes_vld (lsu_dtu_ldst_bytes_vld ),
.lsu_dtu_ldst_data (lsu_dtu_ldst_data ),
.lsu_dtu_ldst_data_vld (lsu_dtu_ldst_data_vld ),
.lsu_dtu_ldst_type (lsu_dtu_ldst_type ),
.lsu_dtu_mem_access_size (lsu_dtu_mem_access_size ),
.mcontext (mcontext ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.pending_halt (pending_halt ),
.rtu_dtu_halt_ack (rtu_dtu_halt_ack ),
.rtu_dtu_pending_ack (rtu_dtu_pending_ack ),
.rtu_dtu_retire_halt_info (rtu_dtu_retire_halt_info),
.rtu_dtu_retire_mret (rtu_dtu_retire_mret ),
.rtu_dtu_retire_vld (rtu_dtu_retire_vld ),
.rtu_yy_xx_dbgon (rtu_yy_xx_dbgon ),
.tcontrol (tcontrol ),
.tdata1 (tdata1 ),
.tdata2 (tdata2 ),
.tdata3 (tdata3 ),
.tinfo (tinfo ),
.tselect (tselect ),
.updata_tval (updata_tval )
);
// &CombBeg; @214
always @( dpc[31:0]
or tdata1[31:0]
or tinfo[31:0]
or dbgfifo_regs_data[31:0]
or dcsr[31:0]
or tdata2[31:0]
or cp0_dtu_addr[11:0]
or haltcause[3:0]
or dscratch0[31:0]
or tselect[31:0]
or pcfifo_regs_data[31:0]
or tdata3[31:0]
or tcontrol[31:0]
or dscratch1[31:0]
or mcontext[31:0])
begin
case(cp0_dtu_addr[11:0])
12'h7a0:
dtu_cp0_rdata[XLEN-1:0] = tselect[XLEN-1:0];
12'h7a1:
dtu_cp0_rdata[XLEN-1:0] = tdata1[XLEN-1:0];
12'h7a2:
dtu_cp0_rdata[XLEN-1:0] = tdata2[XLEN-1:0];
12'h7a3:
dtu_cp0_rdata[XLEN-1:0] = tdata3[XLEN-1:0];
12'h7a4:
dtu_cp0_rdata[XLEN-1:0] = tinfo[XLEN-1:0];
12'h7a5:
dtu_cp0_rdata[XLEN-1:0] = tcontrol[XLEN-1:0];
12'h7a8:
dtu_cp0_rdata[XLEN-1:0] = mcontext[XLEN-1:0];
12'h7b0:
dtu_cp0_rdata[XLEN-1:0] = dcsr[31:0];
12'h7b1:
dtu_cp0_rdata[XLEN-1:0] = dpc[XLEN-1:0];
12'h7b2:
dtu_cp0_rdata[XLEN-1:0] = dscratch0[XLEN-1:0];
12'h7b3:
dtu_cp0_rdata[XLEN-1:0] = dscratch1[XLEN-1:0];
12'hfe0:
dtu_cp0_rdata[XLEN-1:0] = {{XLEN-4{1'b0}},haltcause[3:0]};
12'hfe1:
dtu_cp0_rdata[XLEN-1:0] = dbgfifo_regs_data[XLEN-1:0];
12'hfe2:
dtu_cp0_rdata[XLEN-1:0] = pcfifo_regs_data[XLEN-1:0];
default:
dtu_cp0_rdata[XLEN-1:0] = {XLEN{1'bx}};
endcase
// &CombEnd; @295
end
//low power wakeup
assign low_power_wakeup = dtu_rtu_sync_halt_req ||
async_halt_req_wakeup ||
dcsr_step ||
pending_halt;
//==========================================================
// gate clk
//==========================================================
//make dcsr, dpc, haltcause a gated clk cell
assign dcsr_dpc_haltcause_clk_en = rtu_dtu_halt_ack ||
cp0_write_dcsr ||
cp0_write_dpc;
// &Instance("gated_clk_cell", "x_dcsr_dpc_haltcause_reg_gated_clk"); @310
gated_clk_cell x_dcsr_dpc_haltcause_reg_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (dcsr_dpc_haltcause_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (dcsr_dpc_haltcause_clk_en),
.module_en (cp0_dtu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk), @311
// .external_en (1'b0), @312
// .global_en (cp0_yy_clk_en), @313
// .module_en (cp0_dtu_icg_en), @314
// .local_en (dcsr_dpc_haltcause_clk_en), @315
// //.local_en (1'b1), @316
// .clk_out (dcsr_dpc_haltcause_clk)); @317
//make dscratch0, dscratch1 a gated clk cell
assign dscratch01_clk_en = cp0_write_dscratch0 || tdt_dm_write_dscratch0 || updata_tval ||
cp0_write_dscratch1;
// &Instance("gated_clk_cell", "x_dscratch01_reg_gated_clk"); @322
gated_clk_cell x_dscratch01_reg_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (dscratch01_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (dscratch01_clk_en ),
.module_en (cp0_dtu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @323
// .external_en (1'b0), @324
// .global_en (cp0_yy_clk_en), @325
// .module_en (cp0_dtu_icg_en), @326
// .local_en (dscratch01_clk_en), @327
// //.local_en (1'b1), @328
// .clk_out (dscratch01_clk)); @329
// &ModuleEnd; @338
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_dtu_dbginfo(
bmu_dtu_debug_info,
cp0_dtu_addr,
cp0_dtu_debug_info,
cp0_dtu_icg_en,
cp0_dtu_rreg,
cp0_yy_clk_en,
cpurst_b,
dahbl_dtu_debug_info,
dbgfifo_regs_data,
dtu_rtu_async_halt_req,
forever_cpuclk,
fpu_dtu_debug_info,
iahbl_dtu_debug_info,
idu_dtu_debug_info,
idu_dtu_fpr_info,
ifu_dtu_debug_info,
iu_dtu_debug_info,
lsu_dtu_debug_info,
pad_yy_icg_scan_en,
rtu_dtu_debug_info,
sahbl_dtu_debug_info
);
// &Ports; @24
input [3 :0] bmu_dtu_debug_info;
input [11 :0] cp0_dtu_addr;
input [5 :0] cp0_dtu_debug_info;
input cp0_dtu_icg_en;
input cp0_dtu_rreg;
input cp0_yy_clk_en;
input cpurst_b;
input [10 :0] dahbl_dtu_debug_info;
input dtu_rtu_async_halt_req;
input forever_cpuclk;
input [7 :0] fpu_dtu_debug_info;
input [10 :0] iahbl_dtu_debug_info;
input [21 :0] idu_dtu_debug_info;
input [95 :0] idu_dtu_fpr_info;
input [26 :0] ifu_dtu_debug_info;
input [8 :0] iu_dtu_debug_info;
input [78 :0] lsu_dtu_debug_info;
input pad_yy_icg_scan_en;
input [13 :0] rtu_dtu_debug_info;
input [10 :0] sahbl_dtu_debug_info;
output [31 :0] dbgfifo_regs_data;
// &Regs; @25
reg [3 :0] dbg_rptr;
reg [297:0] xx_dbg_info_reg;
// &Wires; @26
wire [3 :0] bmu_dtu_debug_info;
wire [11 :0] cp0_dtu_addr;
wire [5 :0] cp0_dtu_debug_info;
wire cp0_dtu_icg_en;
wire cp0_dtu_rreg;
wire cp0_read_dbginfo;
wire cp0_yy_clk_en;
wire cpurst_b;
wire [10 :0] dahbl_dtu_debug_info;
wire dbg_info_record;
wire [31 :0] dbgfifo_regs_data;
wire dbginfo_clk;
wire dbginfo_clk_en;
wire [31 :0] dbginfo_out;
wire dtu_rtu_async_halt_req;
wire forever_cpuclk;
wire [7 :0] fpu_dtu_debug_info;
wire [10 :0] iahbl_dtu_debug_info;
wire [21 :0] idu_dtu_debug_info;
wire [95 :0] idu_dtu_fpr_info;
wire [26 :0] ifu_dtu_debug_info;
wire [8 :0] iu_dtu_debug_info;
wire [78 :0] lsu_dtu_debug_info;
wire pad_yy_icg_scan_en;
wire [13 :0] rtu_dtu_debug_info;
wire [10 :0] sahbl_dtu_debug_info;
wire [297:0] xx_dbg_info;
wire [307:0] xx_dbg_info_reg_padding;
parameter DBG_INFO_WIDTH = `TDT_DBGINFO_WIDTH;
parameter DBG_WIDTH = `TDT_DM_CORE_MAX_XLEN;
parameter DBGINFO_RPTR_WIDTH = 4;
parameter DBGINFO_READ_WIDTH = 28;
parameter DBGINFO_DEPTH = `TDT_DBGINFO_DEPTH;
//==========================================================
// DBGINFO FIFO Read
//==========================================================
//csky vperl_off
wire [DBGINFO_READ_WIDTH -1:0] dbginfo_reg[DBGINFO_DEPTH-1:0];
genvar i;
generate
for (i = 0; i < DBGINFO_DEPTH; i = i+1)
begin: DBG_FIFO
assign dbginfo_reg[i][DBGINFO_READ_WIDTH -1:0] = xx_dbg_info_reg_padding[DBGINFO_READ_WIDTH *i+DBGINFO_READ_WIDTH-1:DBGINFO_READ_WIDTH *i];
end
endgenerate
//vperl_on
assign dbginfo_out[DBG_WIDTH-1:0] = {dbginfo_reg[dbg_rptr[DBGINFO_RPTR_WIDTH-1:0]][DBGINFO_READ_WIDTH-1:0],dbg_rptr[DBGINFO_RPTR_WIDTH-1:0]};
//csky vperl_on
// &Force("nonport","dbginfo_out"); @53
assign dbgfifo_regs_data[DBG_WIDTH -1:0] = dbginfo_out[DBG_WIDTH-1:0];
assign cp0_read_dbginfo = cp0_dtu_rreg && cp0_dtu_addr[11:0] == 12'hfe1;
//==========================================================
// DBGINFO FIFO Write
//==========================================================
assign dbg_info_record = dtu_rtu_async_halt_req;
assign xx_dbg_info[DBG_INFO_WIDTH-1:0] = {
idu_dtu_fpr_info[95:0],
fpu_dtu_debug_info[7:0],
cp0_dtu_debug_info[5:0],
rtu_dtu_debug_info[13:0],
iu_dtu_debug_info[8:0],
sahbl_dtu_debug_info[10:0],
dahbl_dtu_debug_info[10:0],
iahbl_dtu_debug_info[10:0],
bmu_dtu_debug_info[3:0],
lsu_dtu_debug_info[78:0],
idu_dtu_debug_info[21:0],
ifu_dtu_debug_info[26:0]
};
always @ (posedge dbginfo_clk or negedge cpurst_b)
begin
if (!cpurst_b)
xx_dbg_info_reg[DBG_INFO_WIDTH-1:0] <= {DBG_INFO_WIDTH{1'b0}};
else if (dbg_info_record)
xx_dbg_info_reg[DBG_INFO_WIDTH-1:0] <= xx_dbg_info[DBG_INFO_WIDTH-1:0];
end
assign xx_dbg_info_reg_padding[DBGINFO_READ_WIDTH *DBGINFO_DEPTH-1:0] = {
{(DBGINFO_READ_WIDTH *DBGINFO_DEPTH-DBG_INFO_WIDTH){1'b0}},
xx_dbg_info_reg[DBG_INFO_WIDTH-1:0]
};
// &Force("nonport", "xx_dbg_info_reg"); @111
// &Force("nonport", "xx_dbg_info_reg_padding"); @112
//==========================================================
// DBGINFO FIFO Read Pointer
//==========================================================
always @ (posedge dbginfo_clk or negedge cpurst_b)
begin
if (!cpurst_b)
dbg_rptr[DBGINFO_RPTR_WIDTH-1:0] <= {DBGINFO_RPTR_WIDTH{1'b0}};
else if (cp0_read_dbginfo && dbg_rptr[DBGINFO_RPTR_WIDTH-1:0] == 4'd10)
dbg_rptr[DBGINFO_RPTR_WIDTH-1:0] <= {DBGINFO_RPTR_WIDTH{1'b0}};
else if (cp0_read_dbginfo)
dbg_rptr[DBGINFO_RPTR_WIDTH-1:0] <= dbg_rptr[DBGINFO_RPTR_WIDTH-1:0] + 1'b1;
end
//==========================================================
// gate clk
//==========================================================
assign dbginfo_clk_en = dtu_rtu_async_halt_req ||
cp0_read_dbginfo;
// &Force("nonport","dbginfo_clk_en"); @136
// &Instance("gated_clk_cell", "x_reg_gated_clk"); @138
gated_clk_cell x_reg_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (dbginfo_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (dbginfo_clk_en ),
.module_en (cp0_dtu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @139
// .external_en (1'b0), @140
// .global_en (cp0_yy_clk_en), @141
// .module_en (cp0_dtu_icg_en), @142
// .local_en (dbginfo_clk_en), @143
// //.local_en (1'b1), @144
// .clk_out (dbginfo_clk)); @145
// &ModuleEnd; @147
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_dtu_m_iie_all(
cp0_dtu_icg_en,
cp0_dtu_mexpt_vld,
cp0_dtu_wdata,
cp0_write_mcontext,
cp0_write_tcontrol,
cp0_write_tdata1,
cp0_write_tdata2,
cp0_write_tdata3,
cp0_write_tselect,
cp0_yy_clk_en,
cpurst_b,
dtu_cause,
dtu_ifu_halt_info0,
dtu_ifu_halt_info1,
dtu_ifu_halt_info_vld,
dtu_lsu_halt_info,
dtu_lsu_halt_info_vld,
exe0_16bit,
exe0_32bit,
exe1_16bit,
exe1_32bit,
forever_cpuclk,
icount_enable,
ifu_dtu_addr_vld0,
ifu_dtu_addr_vld1,
ifu_dtu_data_vld0,
ifu_dtu_data_vld1,
ifu_dtu_exe_addr0,
ifu_dtu_exe_addr1,
ldst_16bit,
ldst_32bit,
ldst_8bit,
ldst_addr_mcontrol,
ldst_data_mcontrol,
load_addr_vld,
load_data_vld,
lsu_dtu_halt_info,
lsu_dtu_last_check,
lsu_dtu_ldst_addr,
lsu_dtu_ldst_addr_vld,
lsu_dtu_ldst_bytes_vld,
lsu_dtu_ldst_data,
lsu_dtu_ldst_data_vld,
m_mode,
mcontext,
pad_yy_icg_scan_en,
pending_halt,
rtu_dtu_halt_ack,
rtu_dtu_pending_ack,
rtu_dtu_retire_halt_info,
rtu_dtu_retire_mret,
rtu_dtu_retire_vld,
rtu_yy_xx_dbgon,
store_addr_vld,
store_data_vld,
tcontrol,
tdata1,
tdata2,
tdata3,
tinfo,
tselect,
u_mode,
updata_tval
);
// &Ports; @24
input cp0_dtu_icg_en;
input cp0_dtu_mexpt_vld;
input [31:0] cp0_dtu_wdata;
input cp0_write_mcontext;
input cp0_write_tcontrol;
input cp0_write_tdata1;
input cp0_write_tdata2;
input cp0_write_tdata3;
input cp0_write_tselect;
input cp0_yy_clk_en;
input cpurst_b;
input exe0_16bit;
input exe0_32bit;
input exe1_16bit;
input exe1_32bit;
input forever_cpuclk;
input ifu_dtu_addr_vld0;
input ifu_dtu_addr_vld1;
input ifu_dtu_data_vld0;
input ifu_dtu_data_vld1;
input [31:0] ifu_dtu_exe_addr0;
input [31:0] ifu_dtu_exe_addr1;
input ldst_16bit;
input ldst_32bit;
input ldst_8bit;
input load_addr_vld;
input load_data_vld;
input [14:0] lsu_dtu_halt_info;
input lsu_dtu_last_check;
input [31:0] lsu_dtu_ldst_addr;
input lsu_dtu_ldst_addr_vld;
input [7 :0] lsu_dtu_ldst_bytes_vld;
input [31:0] lsu_dtu_ldst_data;
input lsu_dtu_ldst_data_vld;
input m_mode;
input pad_yy_icg_scan_en;
input rtu_dtu_halt_ack;
input rtu_dtu_pending_ack;
input [14:0] rtu_dtu_retire_halt_info;
input rtu_dtu_retire_mret;
input rtu_dtu_retire_vld;
input rtu_yy_xx_dbgon;
input store_addr_vld;
input store_data_vld;
input u_mode;
output [3 :0] dtu_cause;
output [14:0] dtu_ifu_halt_info0;
output [14:0] dtu_ifu_halt_info1;
output dtu_ifu_halt_info_vld;
output [14:0] dtu_lsu_halt_info;
output dtu_lsu_halt_info_vld;
output icount_enable;
output ldst_addr_mcontrol;
output ldst_data_mcontrol;
output [31:0] mcontext;
output pending_halt;
output [31:0] tcontrol;
output [31:0] tdata1;
output [31:0] tdata2;
output [31:0] tdata3;
output [31:0] tinfo;
output [31:0] tselect;
output updata_tval;
// &Regs; @25
reg [3 :0] dtu_cause;
reg [5 :0] mcontext_lowbits;
reg mpte_reg;
reg mte_reg;
reg pending_halt;
reg record_action01_reg;
reg record_action_reg;
reg [3 :0] record_cause_reg;
reg [2 :0] record_hit_reg;
reg record_ldst_reg;
reg retire_action01;
reg [31:0] tdata1;
reg [31:0] tdata2;
reg [31:0] tdata3;
reg [31:0] tinfo;
reg [2 :0] triggers_hit;
reg [3 :0] tselect_lowbits;
reg [9 :0] tselect_wr_en;
// &Wires; @26
wire [2 :0] action0_match_trigger;
wire [2 :0] action0_mcontrol;
wire [2 :0] action0_triggers;
wire [2 :0] action1_match_trigger;
wire [2 :0] action1_mcontrol;
wire [2 :0] action1_triggers;
wire clear_action01_reg;
wire clear_record;
wire cp0_dtu_icg_en;
wire cp0_dtu_mexpt_vld;
wire [31:0] cp0_dtu_wdata;
wire cp0_write_mcontext;
wire cp0_write_tcontrol;
wire cp0_write_tdata1;
wire cp0_write_tdata2;
wire cp0_write_tdata3;
wire cp0_write_tselect;
wire cp0_yy_clk_en;
wire cpurst_b;
wire [14:0] dtu_ifu_halt_info0;
wire [14:0] dtu_ifu_halt_info1;
wire dtu_ifu_halt_info_vld;
wire [14:0] dtu_lsu_halt_info;
wire dtu_lsu_halt_info_vld;
wire exe0_16bit;
wire exe0_32bit;
wire exe1_16bit;
wire exe1_32bit;
wire forever_cpuclk;
wire generate_pending_halt;
wire generate_retire_action01;
wire generate_timing0;
wire give_action01_halt_info;
wire icount_enable;
wire ifu_dtu_addr_vld0;
wire ifu_dtu_addr_vld1;
wire ifu_dtu_data_vld0;
wire ifu_dtu_data_vld1;
wire [31:0] ifu_dtu_exe_addr0;
wire [31:0] ifu_dtu_exe_addr1;
wire iie_pending_halt;
wire ldst_16bit;
wire ldst_32bit;
wire ldst_8bit;
wire ldst_addr_mcontrol;
wire ldst_data_mcontrol;
wire load_addr_vld;
wire load_data_vld;
wire [14:0] lsu_dtu_halt_info;
wire lsu_dtu_last_check;
wire [31:0] lsu_dtu_ldst_addr;
wire lsu_dtu_ldst_addr_vld;
wire [7 :0] lsu_dtu_ldst_bytes_vld;
wire [31:0] lsu_dtu_ldst_data;
wire lsu_dtu_ldst_data_vld;
wire [31:0] m0_tdata1;
wire [31:0] m0_tdata2;
wire [31:0] m0_tdata3;
wire [31:0] m0_tinfo;
wire [31:0] m1_tdata1;
wire [31:0] m1_tdata2;
wire [31:0] m1_tdata3;
wire [31:0] m1_tinfo;
wire [31:0] m2_tdata1;
wire [31:0] m2_tdata2;
wire [31:0] m2_tdata3;
wire [31:0] m2_tinfo;
wire [31:0] m3_tdata1;
wire [31:0] m3_tdata2;
wire [31:0] m3_tdata3;
wire [31:0] m3_tinfo;
wire [31:0] m4_tdata1;
wire [31:0] m4_tdata2;
wire [31:0] m4_tdata3;
wire [31:0] m4_tinfo;
wire [31:0] m5_tdata1;
wire [31:0] m5_tdata2;
wire [31:0] m5_tdata3;
wire [31:0] m5_tinfo;
wire [31:0] m6_tdata1;
wire [31:0] m6_tdata2;
wire [31:0] m6_tdata3;
wire [31:0] m6_tinfo;
wire [31:0] m7_tdata1;
wire [31:0] m7_tdata2;
wire [31:0] m7_tdata3;
wire [31:0] m7_tinfo;
wire m_iie_clk;
wire m_iie_clk_en;
wire m_mode;
wire [31:0] mcontext;
wire [14:0] mcontrol_halt_info0;
wire [14:0] mcontrol_halt_info1;
wire [2 :0] mcontrol_hit;
wire other_pending_halt;
wire pad_yy_icg_scan_en;
wire pending_halt_action;
wire [2 :0] pending_halt_hit;
wire penging_halt_action01;
wire record_aciton01;
wire record_action;
wire [3 :0] record_cause;
wire [14:0] record_halt_info;
wire [2 :0] record_hit;
wire record_ldst;
wire record_match;
wire record_pending_halt;
wire [3 :0] rtu_cause;
wire rtu_dtu_halt_ack;
wire rtu_dtu_pending_ack;
wire [14:0] rtu_dtu_retire_halt_info;
wire rtu_dtu_retire_mret;
wire rtu_dtu_retire_vld;
wire rtu_pending_ack;
wire rtu_pending_halt;
wire [14:0] rtu_retire_halt_info;
wire rtu_yy_xx_dbgon;
wire store_addr_vld;
wire store_data_vld;
wire [31:0] tcontrol;
wire timing0_mcontrol_match;
wire [2 :0] triggers_match;
wire [31:0] tselect;
wire u_mode;
wire updata_tval;
wire use_record_halt_info;
wire wdata_bigger_than_trigger_num;
//XLEN
parameter XLEN = `TDT_DM_CORE_MAX_XLEN;
parameter TRIGGER_NUM = `MCONTROL_NUM + `IIE_NUM - 4'd1;
//tcontrol parameter
parameter MPTE = 7;
parameter MTE = 3;
//=========================================================
// tselect write
//=========================================================
//tselect write. When wdata > TRIGGER_NUM, write TRIGGER_NUM to tselsect.
assign wdata_bigger_than_trigger_num = cp0_dtu_wdata[3:0] >= TRIGGER_NUM || (|cp0_dtu_wdata[XLEN-1:4]);
always @(posedge m_iie_clk or negedge cpurst_b)
begin
if(!cpurst_b)
tselect_lowbits[3:0] <= 4'b0;
else if(cp0_write_tselect && wdata_bigger_than_trigger_num)
tselect_lowbits[3:0] <= TRIGGER_NUM;
else if(cp0_write_tselect && !wdata_bigger_than_trigger_num)
tselect_lowbits[3:0] <= cp0_dtu_wdata[3:0];
end
assign tselect[XLEN-1:0] = {{XLEN-4{1'b0}},tselect_lowbits[3:0]};
// &Force("output","tselect");&Force("bus","tselect",XLEN-1,0); @69
//select trigger
// &CombBeg; @72
always @( tselect[3:0])
begin
case(tselect[3:0])
4'b0000:tselect_wr_en[9:0] = 10'b0000000001;
4'b0001:tselect_wr_en[9:0] = 10'b0000000010;
4'b0010:tselect_wr_en[9:0] = 10'b0000000100;
4'b0011:tselect_wr_en[9:0] = 10'b0000001000;
4'b0100:tselect_wr_en[9:0] = 10'b0000010000;
4'b0101:tselect_wr_en[9:0] = 10'b0000100000;
4'b0110:tselect_wr_en[9:0] = 10'b0001000000;
4'b0111:tselect_wr_en[9:0] = 10'b0010000000;
4'b1000:tselect_wr_en[9:0] = 10'b0100000000;
4'b1001:tselect_wr_en[9:0] = 10'b1000000000;
default:tselect_wr_en[9:0] = {10{1'bx}};
endcase
// &CombEnd; @86
end
//=========================================================
// trigger csr read
//=========================================================
// &CombBeg; @91
always @( tselect[3:0]
or m1_tinfo[31:0]
or m2_tinfo[31:0]
or m3_tdata1[31:0]
or m3_tdata2[31:0]
or m7_tinfo[31:0]
or m6_tdata3[31:0]
or m0_tinfo[31:0]
or m6_tdata2[31:0]
or m3_tdata3[31:0]
or m5_tinfo[31:0]
or m5_tdata1[31:0]
or m0_tdata1[31:0]
or m7_tdata1[31:0]
or m4_tdata1[31:0]
or m2_tdata1[31:0]
or m5_tdata2[31:0]
or m6_tinfo[31:0]
or m1_tdata3[31:0]
or m7_tdata3[31:0]
or m5_tdata3[31:0]
or m2_tdata2[31:0]
or m3_tinfo[31:0]
or m1_tdata1[31:0]
or m6_tdata1[31:0]
or m4_tdata2[31:0]
or m2_tdata3[31:0]
or m4_tinfo[31:0]
or m0_tdata2[31:0]
or m7_tdata2[31:0]
or m1_tdata2[31:0]
or m0_tdata3[31:0]
or m4_tdata3[31:0])
begin
// &Force("nonport","m0_tdata1");&Force("nonport","m0_tdata2"); @125
// &Force("nonport","m0_tdata3");&Force("nonport","m0_tinfo"); @126
// &Force("nonport","m0_tdata1");&Force("nonport","m0_tdata2"); @143
// &Force("nonport","m0_tdata3");&Force("nonport","m0_tinfo"); @144
// &Force("nonport","m1_tdata1");&Force("nonport","m1_tdata2"); @145
// &Force("nonport","m1_tdata3");&Force("nonport","m1_tinfo"); @146
// &Force("nonport","m1_tdata1");&Force("nonport","m1_tdata2"); @240
// &Force("nonport","m1_tdata3");&Force("nonport","m1_tinfo"); @241
// &Force("nonport","m1_tdata1");&Force("nonport","m1_tdata2"); @258
// &Force("nonport","m1_tdata3");&Force("nonport","m1_tinfo"); @259
// &Force("nonport","m2_tdata1");&Force("nonport","m2_tdata2"); @260
// &Force("nonport","m2_tdata3");&Force("nonport","m2_tinfo"); @261
// &Force("nonport","m2_tdata1");&Force("nonport","m2_tdata2"); @355
// &Force("nonport","m2_tdata3");&Force("nonport","m2_tinfo"); @356
// &Force("nonport","m2_tdata1");&Force("nonport","m2_tdata2"); @373
// &Force("nonport","m2_tdata3");&Force("nonport","m2_tinfo"); @374
// &Force("nonport","m3_tdata1");&Force("nonport","m3_tdata2"); @375
// &Force("nonport","m3_tdata3");&Force("nonport","m3_tinfo"); @376
case(tselect[3:0])
4'b0000:
begin
tdata1[XLEN-1:0] = m0_tdata1[XLEN-1:0];
tdata2[XLEN-1:0] = m0_tdata2[XLEN-1:0];
tdata3[XLEN-1:0] = m0_tdata3[XLEN-1:0];
tinfo[XLEN-1:0] = m0_tinfo[XLEN-1:0];
end
4'b0001:
begin
tdata1[XLEN-1:0] = m1_tdata1[XLEN-1:0];
tdata2[XLEN-1:0] = m1_tdata2[XLEN-1:0];
tdata3[XLEN-1:0] = m1_tdata3[XLEN-1:0];
tinfo[XLEN-1:0] = m1_tinfo[XLEN-1:0];
end
4'b0010:
begin
tdata1[XLEN-1:0] = m2_tdata1[XLEN-1:0];
tdata2[XLEN-1:0] = m2_tdata2[XLEN-1:0];
tdata3[XLEN-1:0] = m2_tdata3[XLEN-1:0];
tinfo[XLEN-1:0] = m2_tinfo[XLEN-1:0];
end
4'b0011:
begin
tdata1[XLEN-1:0] = m3_tdata1[XLEN-1:0];
tdata2[XLEN-1:0] = m3_tdata2[XLEN-1:0];
tdata3[XLEN-1:0] = m3_tdata3[XLEN-1:0];
tinfo[XLEN-1:0] = m3_tinfo[XLEN-1:0];
end
4'b0100:
begin
tdata1[XLEN-1:0] = m4_tdata1[XLEN-1:0];
tdata2[XLEN-1:0] = m4_tdata2[XLEN-1:0];
tdata3[XLEN-1:0] = m4_tdata3[XLEN-1:0];
tinfo[XLEN-1:0] = m4_tinfo[XLEN-1:0];
end
// &Force("nonport","m3_tdata1");&Force("nonport","m3_tdata2"); @470
// &Force("nonport","m3_tdata3");&Force("nonport","m3_tinfo"); @471
// &Force("nonport","m3_tdata1");&Force("nonport","m3_tdata2"); @488
// &Force("nonport","m3_tdata3");&Force("nonport","m3_tinfo"); @489
// &Force("nonport","m4_tdata1");&Force("nonport","m4_tdata2"); @490
// &Force("nonport","m4_tdata3");&Force("nonport","m4_tinfo"); @491
4'b0101:
begin
tdata1[XLEN-1:0] = m5_tdata1[XLEN-1:0];
tdata2[XLEN-1:0] = m5_tdata2[XLEN-1:0];
tdata3[XLEN-1:0] = m5_tdata3[XLEN-1:0];
tinfo[XLEN-1:0] = m5_tinfo[XLEN-1:0];
end
4'b0110:
begin
tdata1[XLEN-1:0] = m6_tdata1[XLEN-1:0];
tdata2[XLEN-1:0] = m6_tdata2[XLEN-1:0];
tdata3[XLEN-1:0] = m6_tdata3[XLEN-1:0];
tinfo[XLEN-1:0] = m6_tinfo[XLEN-1:0];
end
4'b0111:
begin
tdata1[XLEN-1:0] = m7_tdata1[XLEN-1:0];
tdata2[XLEN-1:0] = m7_tdata2[XLEN-1:0];
tdata3[XLEN-1:0] = m7_tdata3[XLEN-1:0];
tinfo[XLEN-1:0] = m7_tinfo[XLEN-1:0];
end
default:
begin
tdata1[XLEN-1:0] = {XLEN{1'bx}};
tdata2[XLEN-1:0] = {XLEN{1'bx}};
tdata3[XLEN-1:0] = {XLEN{1'bx}};
tinfo[XLEN-1:0] = {XLEN{1'bx}};
end
endcase
// &Force("nonport","m4_tdata1");&Force("nonport","m4_tdata2"); @585
// &Force("nonport","m4_tdata3");&Force("nonport","m4_tinfo"); @586
// &Force("nonport","m4_tdata1");&Force("nonport","m4_tdata2"); @603
// &Force("nonport","m4_tdata3");&Force("nonport","m4_tinfo"); @604
// &Force("nonport","m5_tdata1");&Force("nonport","m5_tdata2"); @605
// &Force("nonport","m5_tdata3");&Force("nonport","m5_tinfo"); @606
// &Force("nonport","m5_tdata1");&Force("nonport","m5_tdata2"); @700
// &Force("nonport","m5_tdata3");&Force("nonport","m5_tinfo"); @701
// &Force("nonport","m5_tdata1");&Force("nonport","m5_tdata2"); @718
// &Force("nonport","m5_tdata3");&Force("nonport","m5_tinfo"); @719
// &Force("nonport","m6_tdata1");&Force("nonport","m6_tdata2"); @720
// &Force("nonport","m6_tdata3");&Force("nonport","m6_tinfo"); @721
// &Force("nonport","m6_tdata1");&Force("nonport","m6_tdata2"); @815
// &Force("nonport","m6_tdata3");&Force("nonport","m6_tinfo"); @816
// &Force("nonport","m6_tdata1");&Force("nonport","m6_tdata2"); @833
// &Force("nonport","m6_tdata3");&Force("nonport","m6_tinfo"); @834
// &Force("nonport","m7_tdata1");&Force("nonport","m7_tdata2"); @835
// &Force("nonport","m7_tdata3");&Force("nonport","m7_tinfo"); @836
// &Force("nonport","m7_tdata1");&Force("nonport","m7_tdata2"); @915
// &Force("nonport","m7_tdata3");&Force("nonport","m7_tinfo"); @916
// &Force("nonport","m7_tdata1");&Force("nonport","m7_tdata2"); @933
// &Force("nonport","m7_tdata3");&Force("nonport","m7_tinfo"); @934
// &CombEnd; @1038
end
//=========================================================
// trigger instance
//=========================================================
//--------------mcontrol instance--------------------------
// &Instance("pa_dtu_mcontrol_output_select"); @1043
pa_dtu_mcontrol_output_select x_pa_dtu_mcontrol_output_select (
.action0_mcontrol (action0_mcontrol ),
.action1_mcontrol (action1_mcontrol ),
.cp0_dtu_icg_en (cp0_dtu_icg_en ),
.cp0_dtu_wdata (cp0_dtu_wdata ),
.cp0_write_tdata1 (cp0_write_tdata1 ),
.cp0_write_tdata2 (cp0_write_tdata2 ),
.cp0_write_tdata3 (cp0_write_tdata3 ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.dtu_ifu_halt_info_vld (dtu_ifu_halt_info_vld ),
.dtu_lsu_halt_info (dtu_lsu_halt_info ),
.dtu_lsu_halt_info_vld (dtu_lsu_halt_info_vld ),
.exe0_16bit (exe0_16bit ),
.exe0_32bit (exe0_32bit ),
.exe1_16bit (exe1_16bit ),
.exe1_32bit (exe1_32bit ),
.forever_cpuclk (forever_cpuclk ),
.ifu_dtu_addr_vld0 (ifu_dtu_addr_vld0 ),
.ifu_dtu_addr_vld1 (ifu_dtu_addr_vld1 ),
.ifu_dtu_data_vld0 (ifu_dtu_data_vld0 ),
.ifu_dtu_data_vld1 (ifu_dtu_data_vld1 ),
.ifu_dtu_exe_addr0 (ifu_dtu_exe_addr0 ),
.ifu_dtu_exe_addr1 (ifu_dtu_exe_addr1 ),
.ldst_16bit (ldst_16bit ),
.ldst_32bit (ldst_32bit ),
.ldst_8bit (ldst_8bit ),
.ldst_addr_mcontrol (ldst_addr_mcontrol ),
.ldst_data_mcontrol (ldst_data_mcontrol ),
.load_addr_vld (load_addr_vld ),
.load_data_vld (load_data_vld ),
.lsu_dtu_halt_info (lsu_dtu_halt_info ),
.lsu_dtu_last_check (lsu_dtu_last_check ),
.lsu_dtu_ldst_addr (lsu_dtu_ldst_addr ),
.lsu_dtu_ldst_addr_vld (lsu_dtu_ldst_addr_vld ),
.lsu_dtu_ldst_bytes_vld (lsu_dtu_ldst_bytes_vld),
.lsu_dtu_ldst_data (lsu_dtu_ldst_data ),
.lsu_dtu_ldst_data_vld (lsu_dtu_ldst_data_vld ),
.m0_tdata1 (m0_tdata1 ),
.m0_tdata2 (m0_tdata2 ),
.m0_tdata3 (m0_tdata3 ),
.m0_tinfo (m0_tinfo ),
.m1_tdata1 (m1_tdata1 ),
.m1_tdata2 (m1_tdata2 ),
.m1_tdata3 (m1_tdata3 ),
.m1_tinfo (m1_tinfo ),
.m2_tdata1 (m2_tdata1 ),
.m2_tdata2 (m2_tdata2 ),
.m2_tdata3 (m2_tdata3 ),
.m2_tinfo (m2_tinfo ),
.m3_tdata1 (m3_tdata1 ),
.m3_tdata2 (m3_tdata2 ),
.m3_tdata3 (m3_tdata3 ),
.m3_tinfo (m3_tinfo ),
.m4_tdata1 (m4_tdata1 ),
.m4_tdata2 (m4_tdata2 ),
.m4_tdata3 (m4_tdata3 ),
.m4_tinfo (m4_tinfo ),
.m5_tdata1 (m5_tdata1 ),
.m5_tdata2 (m5_tdata2 ),
.m5_tdata3 (m5_tdata3 ),
.m5_tinfo (m5_tinfo ),
.m6_tdata1 (m6_tdata1 ),
.m6_tdata2 (m6_tdata2 ),
.m6_tdata3 (m6_tdata3 ),
.m6_tinfo (m6_tinfo ),
.m7_tdata1 (m7_tdata1 ),
.m7_tdata2 (m7_tdata2 ),
.m7_tdata3 (m7_tdata3 ),
.m7_tinfo (m7_tinfo ),
.m_mode (m_mode ),
.mcontext (mcontext ),
.mcontrol_halt_info0 (mcontrol_halt_info0 ),
.mcontrol_halt_info1 (mcontrol_halt_info1 ),
.mcontrol_hit (mcontrol_hit ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_yy_xx_dbgon (rtu_yy_xx_dbgon ),
.store_addr_vld (store_addr_vld ),
.store_data_vld (store_data_vld ),
.tcontrol (tcontrol ),
.tselect_wr_en (tselect_wr_en ),
.u_mode (u_mode )
);
//--------------iie trigger instance--------------------------
// &Instance("pa_dtu_iie_trigger","x_pa_dtu_iie_trigger_0"); @1047
// &Connect( @1048
// .trigger_selected(tselect_wr_en[`TDT_TM_MCONTROL_TRI_NUM]), @1049
// .set_trigger_hit(iie_hit), @1050
// .exception_codes_onehot(exception_codes_onehot), @1051
// .icount_enable (iie0_icount_enable), @1052
// .tdata1_action0 (iie0_tdata1_action0), @1053
// .tdata1_action1 (iie0_tdata1_action1), @1054
// .trigger_match (iie0_match) @1055
// .tdata1 (iie0_tdata1), @1056
// .tdata2 (iie0_tdata2), @1057
// .tdata3 (iie0_tdata3), @1058
// .tinfo (iie0_tinfo)); @1059
// &Force("input","rtu_yy_xx_expt_vec");&Force("bus","rtu_yy_xx_expt_vec",11,0); @1072
// &Force("input","cp0_dtu_int_id");&Force("bus","cp0_dtu_int_id",11,0); @1073
// &Instance("pa_dtu_iie_trigger","x_pa_dtu_iie_trigger_0"); @1077
// &Connect( @1078
// .trigger_selected(tselect_wr_en[`TDT_TM_MCONTROL_TRI_NUM]), @1079
// .set_trigger_hit(iie_hit[0]), @1080
// .exception_codes_onehot(exception_codes_onehot), @1081
// .icount_enable (iie0_icount_enable), @1082
// .tdata1_action0 (iie0_tdata1_action0), @1083
// .tdata1_action1 (iie0_tdata1_action1), @1084
// .trigger_match (iie0_match) @1085
// .tdata1 (iie0_tdata1), @1086
// .tdata2 (iie0_tdata2), @1087
// .tdata3 (iie0_tdata3), @1088
// .tinfo (iie0_tinfo)); @1089
// &Instance("pa_dtu_iie_trigger","x_pa_dtu_iie_trigger_1"); @1091
// &Connect( @1092
// .trigger_selected(tselect_wr_en[`TDT_TM_MCONTROL_TRI_NUM + 1]), @1093
// .set_trigger_hit(iie_hit[1]), @1094
// .exception_codes_onehot(exception_codes_onehot), @1095
// .icount_enable (iie1_icount_enable), @1096
// .tdata1_action0 (iie1_tdata1_action0), @1097
// .tdata1_action1 (iie1_tdata1_action1), @1098
// .trigger_match (iie1_match) @1099
// .tdata1 (iie1_tdata1), @1100
// .tdata2 (iie1_tdata2), @1101
// .tdata3 (iie1_tdata3), @1102
// .tinfo (iie1_tinfo)); @1103
// &Force("input","rtu_yy_xx_expt_vec");&Force("bus","rtu_yy_xx_expt_vec",11,0); @1115
// &Force("input","cp0_dtu_int_id");&Force("bus","cp0_dtu_int_id",11,0); @1116
//-------tcontrol,mcontext for triggers---------
//write tcontrol
always @(posedge m_iie_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
mte_reg <= 1'b0;
mpte_reg <= 1'b0;
end
else if(cp0_dtu_mexpt_vld && rtu_dtu_retire_mret && rtu_dtu_retire_vld)
begin
mte_reg <= 1'b0;
mpte_reg <= mpte_reg;
end
else if(cp0_dtu_mexpt_vld)//A trap into m mode is taken, set MPTE to MTE,set MTE to 0.
begin
mte_reg <= 1'b0;
mpte_reg <= mte_reg;
end
else if(rtu_dtu_retire_mret && rtu_dtu_retire_vld)//mret is executed, set MTE to MPTE.
begin
mte_reg <= mpte_reg;
mpte_reg <= mpte_reg;
end
else if(cp0_write_tcontrol)
begin
mte_reg <= cp0_dtu_wdata[MTE];
mpte_reg <= cp0_dtu_wdata[MPTE];
end
end
assign tcontrol[XLEN-1:0] = {{XLEN-8{1'b0}},mpte_reg,{3{1'b0}},mte_reg,{3{1'b0}}};
// &Force("output","tcontrol");&Force("bus","tcontrol",XLEN-1,0); @1149
//write mcontext
always @(posedge m_iie_clk or negedge cpurst_b)
begin
if(!cpurst_b)
mcontext_lowbits[5:0] <= 6'b0;
else if(cp0_write_mcontext)
mcontext_lowbits[5:0] <= cp0_dtu_wdata[5:0];
end
assign mcontext[XLEN-1:0] = {{XLEN-6{1'b0}},mcontext_lowbits[5:0]};
// &Force("output","mcontext");&Force("bus","mcontext",XLEN-1,0); @1159
//=========================================================
// mcontrol hit info from rtu
//=========================================================
// &Force("input","rtu_dtu_retire_halt_info");&Force("bus","rtu_dtu_retire_halt_info",`TDT_HINFO_WIDTH-1,0); @1164
assign rtu_retire_halt_info[`TDT_HINFO_WIDTH-1:0] = (rtu_dtu_retire_vld || rtu_dtu_halt_ack) ?
rtu_dtu_retire_halt_info[`TDT_HINFO_WIDTH-1:0] :
{`TDT_HINFO_WIDTH{1'b0}};
assign timing0_mcontrol_match = rtu_retire_halt_info[`TDT_HINFO_MATCH] &&
!rtu_retire_halt_info[`TDT_HINFO_CHAIN] &&
!rtu_retire_halt_info[`TDT_HINFO_TIMING];
assign rtu_pending_ack = rtu_dtu_pending_ack;
assign rtu_pending_halt = rtu_retire_halt_info[`TDT_HINFO_PENDING_HALT];
assign generate_timing0 = rtu_dtu_halt_ack || timing0_mcontrol_match;
assign triggers_match[`TDT_TM_TRIGGER_NUM-1:0] =
rtu_retire_halt_info[`TDT_HINFO_TRIGGER:`TDT_HINFO_TRIGGER-`TDT_TM_MCONTROL_TRI_NUM-`TDT_TM_OTHER_TRI_NUM+1];
assign action1_triggers[`TDT_TM_TRIGGER_NUM-1:0] = action1_mcontrol[`TDT_TM_MCONTROL_TRI_NUM-1:0];
assign action0_triggers[`TDT_TM_TRIGGER_NUM-1:0] = action0_mcontrol[`TDT_TM_MCONTROL_TRI_NUM-1:0];
assign action1_match_trigger[`TDT_TM_TRIGGER_NUM-1:0] = triggers_match[`TDT_TM_TRIGGER_NUM-1:0] & action1_triggers[`TDT_TM_TRIGGER_NUM-1:0];
assign action0_match_trigger[`TDT_TM_TRIGGER_NUM-1:0] = triggers_match[`TDT_TM_TRIGGER_NUM-1:0] & action0_triggers[`TDT_TM_TRIGGER_NUM-1:0];
//trigger hit
// &CombBeg; @1230
// &CombEnd; @1237
// &CombBeg; @1239
always @( generate_timing0
or action0_match_trigger[2:0]
or triggers_match[2:0]
or rtu_retire_halt_info[5])
begin
if(generate_timing0 && !rtu_retire_halt_info[`TDT_HINFO_ACTION01])
triggers_hit[`TDT_TM_TRIGGER_NUM-1:0] = triggers_match[`TDT_TM_TRIGGER_NUM-1:0];
else if(generate_timing0 && rtu_retire_halt_info[`TDT_HINFO_ACTION01])
triggers_hit[`TDT_TM_TRIGGER_NUM-1:0] = action0_match_trigger[`TDT_TM_TRIGGER_NUM-1:0];
else
triggers_hit[`TDT_TM_TRIGGER_NUM-1:0] = {`TDT_TM_TRIGGER_NUM{1'b0}};
// &CombEnd; @1246
end
//mcontrol hit
assign mcontrol_hit[`TDT_TM_MCONTROL_TRI_NUM-1:0] = triggers_hit[`TDT_TM_TRIGGER_NUM-1:`TDT_TM_TRIGGER_NUM-`TDT_TM_MCONTROL_TRI_NUM];
//iie trigger hit
//&CombBeg;
// if(rtu_pending_ack)
// mcontrol_hit[`TDT_TM_MCONTROL_TRI_NUM-1:0] = pending_halt_mhit_reg[`TDT_TM_MCONTROL_TRI_NUM-1:0];
// else if(generate_timing0 && !rtu_retire_halt_info[`TDT_HINFO_ACTION01])
// mcontrol_hit[`TDT_TM_MCONTROL_TRI_NUM-1:0] = mcontrols_match[`TDT_TM_MCONTROL_TRI_NUM-1:0];
// else if(generate_timing0 && rtu_retire_halt_info[`TDT_HINFO_ACTION01])
// mcontrol_hit[`TDT_TM_MCONTROL_TRI_NUM-1:0] = action1_match_trigger[`TDT_TM_MCONTROL_TRI_NUM-1:0];
// else
// mcontrol_hit[`TDT_TM_MCONTROL_TRI_NUM-1:0] = {`TDT_TM_MCONTROL_TRI_NUM{1'b0}};
//&CombEnd;
//iie trigger hit
//&CombBeg;
// if(rtu_pending_ack)
// iie_hit[`TDT_TM_OTHER_TRI_NUM-1:0] = pending_halt_iie_hit_reg[`TDT_TM_OTHER_TRI_NUM-1:0];
// else
// iie_hit[`TDT_TM_OTHER_TRI_NUM-1:0]= {`TDT_TM_OTHER_TRI_NUM{1'b0}};
//&CombEnd;
//=========================================================
// updata pending tval
//=========================================================
assign updata_tval = rtu_retire_halt_info[`TDT_HINFO_MATCH] &&
!rtu_retire_halt_info[`TDT_HINFO_CHAIN] &&
rtu_retire_halt_info[`TDT_HINFO_TIMING] &&
!rtu_retire_halt_info[`TDT_HINFO_ACTION];
//always @(posedge m_iie_clk or negedge cpurst_b)
//begin
// if(!cpurst_b)
// pending_tval[XLEN-1:0] <= {XLEN{1'b0}};
// else if(updata_tval)
// pending_tval[XLEN-1:0] <= rtu_dtu_tval[XLEN-1:0];
//end
//assign dtu_rtu_pending_tval[XLEN-1:0] = pending_tval[XLEN-1:0];
//=========================================================
// cause
//=========================================================
assign rtu_cause[3:0] = rtu_retire_halt_info[`TDT_HINFO_CAUSE:`TDT_HINFO_CAUSE-3];
// &CombBeg; @1334
always @( rtu_cause[3:0]
or rtu_dtu_halt_ack)
begin
if(rtu_dtu_halt_ack)
dtu_cause[3:0] = rtu_cause[3:0];
else
dtu_cause[3:0] = rtu_cause[3:0];
// &CombEnd; @1344
end
// &Force("output","dtu_cause"); @1345
//=========================================================
// pending halt
//=========================================================
//icount_enable for rtu
assign icount_enable = 1'b0;
//assign step_match = dcsr_step && rtu_dtu_retire_step_fire;
//pending halt source
assign iie_pending_halt = 1'b0;
//assign step_pending_halt = !generate_timing0 && step_match;
assign other_pending_halt = rtu_pending_halt;//include mcontrol pending, and other pending
assign generate_pending_halt = iie_pending_halt || other_pending_halt;
//pending halt flg
always @(posedge m_iie_clk or negedge cpurst_b)
begin
if(!cpurst_b)
pending_halt <= 1'b0;
else if(generate_pending_halt)
pending_halt <= 1'b1;
else if(rtu_pending_ack)
pending_halt <= 1'b0;
end
// &Force("output","pending_halt"); @1382
//action select
assign pending_halt_action = rtu_retire_halt_info[`TDT_HINFO_ACTION];
assign penging_halt_action01 = rtu_retire_halt_info[`TDT_HINFO_ACTION01];
//assign pending_halt_ldst = rtu_retire_halt_info[`TDT_HINFO_LDST];
//pending halt info record
assign pending_halt_hit[`TDT_TM_TRIGGER_NUM-1:0] = triggers_match[`TDT_TM_TRIGGER_NUM-1:`TDT_TM_TRIGGER_NUM-`TDT_TM_MCONTROL_TRI_NUM];
//=========================================================
// retire action01
//=========================================================
//retire action01 source
assign generate_retire_action01 = generate_timing0 && rtu_retire_halt_info[`TDT_HINFO_ACTION01];
//retire action01 flg
assign clear_action01_reg = rtu_yy_xx_dbgon && retire_action01;//(ifu_dtu_addr_vld0 || ifu_dtu_data_vld0 || ifu_dtu_addr_vld1 || ifu_dtu_data_vld1);
always @(posedge m_iie_clk or negedge cpurst_b)
begin
if(!cpurst_b)
retire_action01 <= 1'b0;
else if(generate_retire_action01)
retire_action01 <= 1'b1;
else if(clear_action01_reg)
retire_action01 <= 1'b0;
end
assign give_action01_halt_info = retire_action01 && !rtu_yy_xx_dbgon;
//record hatl_info of pending halt and action01
assign record_hit[`TDT_TM_TRIGGER_NUM-1:0] = generate_pending_halt ? pending_halt_hit[`TDT_TM_TRIGGER_NUM-1:0] :
action1_match_trigger[`TDT_TM_TRIGGER_NUM-1:0];
assign record_action = generate_pending_halt ? pending_halt_action : 1'b1;
assign record_aciton01 = generate_pending_halt ? penging_halt_action01 : 1'b0;
assign record_ldst = rtu_retire_halt_info[`TDT_HINFO_LDST];
assign record_cause[3:0] = dtu_cause[3:0];
assign clear_record = pending_halt && rtu_pending_ack ||
clear_action01_reg;
always @(posedge m_iie_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
record_hit_reg[`TDT_TM_TRIGGER_NUM-1:0] <= {`TDT_TM_TRIGGER_NUM{1'b0}};
record_action_reg <= 1'b0;
record_action01_reg <= 1'b0;
record_ldst_reg <= 1'b0;
record_cause_reg[3:0] <= 4'b0;
end
else if(generate_pending_halt || generate_retire_action01)
begin
record_hit_reg[`TDT_TM_TRIGGER_NUM-1:0] <= record_hit[`TDT_TM_TRIGGER_NUM-1:0];
record_action_reg <= record_action;
record_action01_reg <= record_aciton01;
record_ldst_reg <= record_ldst;
record_cause_reg[3:0] <= record_cause[3:0];
end
else if(clear_record)
begin
record_hit_reg[`TDT_TM_TRIGGER_NUM-1:0] <= {`TDT_TM_TRIGGER_NUM{1'b0}};
record_action_reg <= 1'b0;
record_action01_reg <= 1'b0;
record_ldst_reg <= 1'b0;
record_cause_reg[3:0] <= 4'b0;
end
end
assign record_match = |record_hit_reg[`TDT_TM_TRIGGER_NUM-1:0];
assign record_pending_halt = pending_halt || retire_action01;
assign record_halt_info[`TDT_HINFO_WIDTH-1:0] = rtu_yy_xx_dbgon ?
{`TDT_HINFO_WIDTH{1'b0}} :
{record_hit_reg[`TDT_TM_TRIGGER_NUM-1:0],//match[7:0]
record_cause_reg[3:0],//cause
record_pending_halt, //pengding halt
1'b0, //timing
record_action01_reg, //action01
record_action_reg, //action
1'b0, //chain
record_ldst_reg, //ldst
record_match, //match
1'b1}; //cancel
//halt_info for ifu
assign use_record_halt_info = give_action01_halt_info || pending_halt;
assign dtu_ifu_halt_info0[`TDT_HINFO_WIDTH-1:0] = use_record_halt_info ?
record_halt_info[`TDT_HINFO_WIDTH-1:0] :
mcontrol_halt_info0[`TDT_HINFO_WIDTH-1:0];
assign dtu_ifu_halt_info1[`TDT_HINFO_WIDTH-1:0] = use_record_halt_info ?
record_halt_info[`TDT_HINFO_WIDTH-1:0] :
mcontrol_halt_info1[`TDT_HINFO_WIDTH-1:0];
//==========================================================
// gate clk
//==========================================================
assign m_iie_clk_en =cp0_write_tselect || cp0_write_tcontrol || cp0_write_mcontext ||
cp0_dtu_mexpt_vld || (rtu_dtu_retire_mret && rtu_dtu_retire_vld) || //cp0_dtu_mret_vld_f ||
// updata_tval ||
generate_pending_halt || rtu_pending_ack ||
generate_retire_action01 || clear_action01_reg;
// &Force("nonport","m_iie_clk_en"); @1576
// &Instance("gated_clk_cell", "x_reg_gated_clk"); @1579
gated_clk_cell x_reg_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (m_iie_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (m_iie_clk_en ),
.module_en (cp0_dtu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @1580
// .external_en (1'b0), @1581
// .global_en (cp0_yy_clk_en), @1582
// .module_en (cp0_dtu_icg_en), @1583
// .local_en (m_iie_clk_en), @1584
// //.local_en (1'b1), @1585
// .clk_out (m_iie_clk)); @1586
// &ModuleEnd; @1599
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_dtu_pcfifo(
cp0_dtu_addr,
cp0_dtu_icg_en,
cp0_dtu_pcfifo_frz,
cp0_dtu_rreg,
cp0_yy_clk_en,
cpurst_b,
forever_cpuclk,
latest_pc,
pad_yy_icg_scan_en,
pcfifo_regs_data,
rtu_dtu_halt_ack,
rtu_dtu_retire_chgflw,
rtu_dtu_retire_next_pc,
rtu_dtu_retire_vld
);
// &Ports; @24
input [11:0] cp0_dtu_addr;
input cp0_dtu_icg_en;
input cp0_dtu_pcfifo_frz;
input cp0_dtu_rreg;
input cp0_yy_clk_en;
input cpurst_b;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input rtu_dtu_halt_ack;
input rtu_dtu_retire_chgflw;
input [31:0] rtu_dtu_retire_next_pc;
input rtu_dtu_retire_vld;
output [31:0] latest_pc;
output [31:0] pcfifo_regs_data;
// &Regs; @25
reg [2 :0] rptr;
reg [2 :0] wptr;
// &Wires; @26
wire [11:0] cp0_dtu_addr;
wire cp0_dtu_icg_en;
wire cp0_dtu_pcfifo_frz;
wire cp0_dtu_rreg;
wire cp0_yy_clk_en;
wire cpurst_b;
wire ctrl_pcfifo_ren;
wire ctrl_pcfifo_wen;
wire forever_cpuclk;
wire [31:0] latest_pc;
wire [2 :0] latest_pc_ptr;
wire pad_yy_icg_scan_en;
wire pcfifo_clk;
wire pcfifo_clk_en;
wire [31:0] pcfifo_din;
wire [31:0] pcfifo_out;
wire [31:0] pcfifo_reg_latest_pc;
wire [31:0] pcfifo_reg_rptr_pc;
wire [31:0] pcfifo_regs_data;
wire read_first_pc;
wire rtu_dtu_halt_ack;
wire rtu_dtu_retire_chgflw;
wire [31:0] rtu_dtu_retire_next_pc;
wire rtu_dtu_retire_vld;
parameter DATAW = `TDT_DM_CORE_MAX_XLEN;
parameter DEPTH = `TDT_PCFIFO_DEPTH;
parameter PTR_WIDTH = `TDT_PCFIFO_PTR_WIDTH;
assign ctrl_pcfifo_wen = rtu_dtu_retire_vld && rtu_dtu_retire_chgflw && !cp0_dtu_pcfifo_frz;
assign ctrl_pcfifo_ren = cp0_dtu_rreg && cp0_dtu_addr[11:0] == 12'hfe2 && !cp0_dtu_pcfifo_frz;
//==========================================================
// PCFIFO write
//==========================================================
// when a branch or jump inst retires in normal mode,
// the target pc will be pushed into pcfifo
assign pcfifo_din[`PA_WIDTH-1:0] = rtu_dtu_retire_next_pc[`PA_WIDTH-1:0];
// //&Force("mem","pcfifo_reg",`PA_WIDTH-1,0,DEPTH-1,0); @44
// //&Force("output","pcfifo_reg");&Force("bus","pcfifo_reg",`PA_WIDTH-1,0); @45
//csky vperl_off
reg [`PA_WIDTH-1:0] pcfifo_reg [DEPTH-1:0];
integer i;//pcfifo entry number
always @(posedge pcfifo_clk or negedge cpurst_b)
begin
if (!cpurst_b)
begin
for (i=0; i<DEPTH; i=i+1)
pcfifo_reg[i] <= {`PA_WIDTH{1'b0}};
end
else if (ctrl_pcfifo_wen)
pcfifo_reg[wptr[PTR_WIDTH-1:0]] <= pcfifo_din[`PA_WIDTH-1:0];
end
assign pcfifo_reg_rptr_pc[`PA_WIDTH-1:0] = pcfifo_reg[rptr[PTR_WIDTH-1:0]];
assign pcfifo_reg_latest_pc[`PA_WIDTH-1:0] = pcfifo_reg[latest_pc_ptr[PTR_WIDTH-1:0]];
//csky vperl_on
// &Force("nonport","pcfifo_reg_rptr_pc"); @64
// &Force("nonport","pcfifo_reg_latest_pc"); @65
//==========================================================
// PCFIFO read
//==========================================================
assign pcfifo_out[`PA_WIDTH-1:0] = read_first_pc ? {pcfifo_reg_rptr_pc[`PA_WIDTH-1:1],1'b1} : pcfifo_reg_rptr_pc[`PA_WIDTH-1:0];
assign pcfifo_regs_data[DATAW-1:0] = pcfifo_out[`PA_WIDTH-1:0];
//==========================================================
// PCFIFO wptr maintenance
//==========================================================
//assign pcfifo_full = (wptr[PTR_WIDTH-2:0] == first_pc_ptr[PTR_WIDTH-2:0]) &&
// (wptr[PTR_WIDTH-1] ^ first_pc_ptr[PTR_WIDTH-1]);
// wptr increase conditon:
// write enable
always @(posedge pcfifo_clk or negedge cpurst_b)
begin
if (!cpurst_b)
wptr[PTR_WIDTH-1:0] <= {PTR_WIDTH{1'b0}};
else if (ctrl_pcfifo_wen)
wptr[PTR_WIDTH-1:0] <= wptr[PTR_WIDTH-1:0] + 1'b1;
else
wptr[PTR_WIDTH-1:0] <= wptr[PTR_WIDTH-1:0];
end
//latest_pc ptr is behind wptr
assign latest_pc_ptr[PTR_WIDTH-1:0] = wptr[PTR_WIDTH-1:0] - 1'b1;
// &Force("nonport","latest_pc_ptr"); @93
//==========================================================
// PCFIFO first_pc_ptr maintenance
//==========================================================
// first_pc_ptr increase conditon:
// wptr is overwriting a entry
//always @(posedge pcfifo_clk or negedge cpurst_b)
//begin
// if (!cpurst_b)
// first_pc_ptr[PTR_WIDTH-1:0] <= {PTR_WIDTH{1'b0}};
// else if (ctrl_pcfifo_wen && pcfifo_full)
// first_pc_ptr[PTR_WIDTH-1:0] <= first_pc_ptr[PTR_WIDTH-1:0] + 1'b1;
// else
// first_pc_ptr[PTR_WIDTH-1:0] <= first_pc_ptr[PTR_WIDTH-1:0];
//end
//==========================================================
// PCFIFO rptr maintenance
//==========================================================
// rptr increase condition:
// read enable
always @(posedge pcfifo_clk or negedge cpurst_b)
begin
if (!cpurst_b)
rptr[PTR_WIDTH-1:0] <= {PTR_WIDTH{1'b0}};
else if(rtu_dtu_halt_ack)
rptr[PTR_WIDTH-1:0] <= wptr[PTR_WIDTH-1:0];
else if (ctrl_pcfifo_ren)
rptr[PTR_WIDTH-1:0] <= rptr[PTR_WIDTH-1:0] + 1'b1;
else
rptr[PTR_WIDTH-1:0] <= rptr[PTR_WIDTH-1:0];
end
assign read_first_pc = rptr[PTR_WIDTH-1:0] == wptr[PTR_WIDTH-1:0];
//==========================================================
// latest pc for dm
//==========================================================
assign latest_pc[`PA_WIDTH-1:0] = ctrl_pcfifo_wen ? pcfifo_din[`PA_WIDTH-1:0] : pcfifo_reg_latest_pc[`PA_WIDTH-1:0];
//==========================================================
// gate clk
//==========================================================
assign pcfifo_clk_en = ctrl_pcfifo_wen ||
ctrl_pcfifo_ren ||
rtu_dtu_halt_ack;
// &Force("nonport","pcfifo_clk_en"); @140
// &Instance("gated_clk_cell", "x_reg_gated_clk"); @143
gated_clk_cell x_reg_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (pcfifo_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (pcfifo_clk_en ),
.module_en (cp0_dtu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @144
// .external_en (1'b0), @145
// .global_en (cp0_yy_clk_en), @146
// .module_en (cp0_dtu_icg_en), @147
// .local_en (pcfifo_clk_en), @148
// //.local_en (1'b1), @149
// .clk_out (pcfifo_clk)); @150
// &ModuleEnd; @151
endmodule

523
opene906/E906_RTL_FACTORY/gen_rtl/dtu/rtl/pa_dtu_top.v Normal file
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@ -0,0 +1,523 @@
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_dtu_top(
bmu_dtu_debug_info,
cp0_dtu_addr,
cp0_dtu_debug_info,
cp0_dtu_icg_en,
cp0_dtu_int_id,
cp0_dtu_mexpt_vld,
cp0_dtu_pcfifo_frz,
cp0_dtu_rreg,
cp0_dtu_wdata,
cp0_dtu_wreg,
cp0_yy_clk_en,
cp0_yy_priv_mode,
cpurst_b,
dahbl_dtu_debug_info,
dtu_cp0_dcsr_mprven,
dtu_cp0_dcsr_prv,
dtu_cp0_rdata,
dtu_cp0_wake_up,
dtu_hpcp_dcsr_stopcount,
dtu_ifu_debug_inst,
dtu_ifu_debug_inst_vld,
dtu_ifu_halt_info0,
dtu_ifu_halt_info1,
dtu_ifu_halt_info_vld,
dtu_ifu_halt_on_reset,
dtu_lsu_addr_trig_en,
dtu_lsu_data_trig_en,
dtu_lsu_halt_info,
dtu_lsu_halt_info_vld,
dtu_rtu_async_halt_req,
dtu_rtu_dpc,
dtu_rtu_ebreak_action,
dtu_rtu_int_mask,
dtu_rtu_pending_tval,
dtu_rtu_resume_req,
dtu_rtu_step_en,
dtu_rtu_sync_flush,
dtu_rtu_sync_halt_req,
dtu_tdt_dm_halted,
dtu_tdt_dm_havereset,
dtu_tdt_dm_itr_done,
dtu_tdt_dm_retire_debug_expt_vld,
dtu_tdt_dm_rx_data,
dtu_tdt_dm_wr_ready,
forever_cpuclk,
fpu_dtu_debug_info,
iahbl_dtu_debug_info,
idu_dtu_debug_info,
idu_dtu_fpr_info,
idu_yy_xx_tail_ack,
ifu_dtu_addr_vld0,
ifu_dtu_addr_vld1,
ifu_dtu_data_vld0,
ifu_dtu_data_vld1,
ifu_dtu_debug_info,
ifu_dtu_exe_addr0,
ifu_dtu_exe_addr1,
ifu_dtu_exe_data0,
ifu_dtu_exe_data1,
iu_dtu_debug_info,
lsu_dtu_debug_info,
lsu_dtu_halt_info,
lsu_dtu_last_check,
lsu_dtu_ldst_addr,
lsu_dtu_ldst_addr_vld,
lsu_dtu_ldst_bytes_vld,
lsu_dtu_ldst_data,
lsu_dtu_ldst_data_vld,
lsu_dtu_ldst_type,
lsu_dtu_mem_access_size,
pad_yy_icg_scan_en,
rtu_dtu_debug_info,
rtu_dtu_dpc,
rtu_dtu_halt_ack,
rtu_dtu_nmi_pending,
rtu_dtu_pending_ack,
rtu_dtu_retire_chgflw,
rtu_dtu_retire_debug_expt_vld,
rtu_dtu_retire_halt_info,
rtu_dtu_retire_mret,
rtu_dtu_retire_next_pc,
rtu_dtu_retire_vld,
rtu_dtu_tval,
rtu_yy_xx_dbgon,
rtu_yy_xx_expt_int,
rtu_yy_xx_expt_vec,
rtu_yy_xx_expt_vld,
sahbl_dtu_debug_info,
sys_apb_clk,
sys_apb_rst_b,
tdt_dm_dtu_ack_havereset,
tdt_dm_dtu_async_halt_req,
tdt_dm_dtu_halt_on_reset,
tdt_dm_dtu_halt_req,
tdt_dm_dtu_itr,
tdt_dm_dtu_itr_vld,
tdt_dm_dtu_resume_req,
tdt_dm_dtu_wdata,
tdt_dm_dtu_wr_flg,
tdt_dm_dtu_wr_vld
);
// &Ports; @24
input [3 :0] bmu_dtu_debug_info;
input [11:0] cp0_dtu_addr;
input [5 :0] cp0_dtu_debug_info;
input cp0_dtu_icg_en;
input [11:0] cp0_dtu_int_id;
input cp0_dtu_mexpt_vld;
input cp0_dtu_pcfifo_frz;
input cp0_dtu_rreg;
input [31:0] cp0_dtu_wdata;
input cp0_dtu_wreg;
input cp0_yy_clk_en;
input [1 :0] cp0_yy_priv_mode;
input cpurst_b;
input [10:0] dahbl_dtu_debug_info;
input forever_cpuclk;
input [7 :0] fpu_dtu_debug_info;
input [10:0] iahbl_dtu_debug_info;
input [21:0] idu_dtu_debug_info;
input [95:0] idu_dtu_fpr_info;
input idu_yy_xx_tail_ack;
input ifu_dtu_addr_vld0;
input ifu_dtu_addr_vld1;
input ifu_dtu_data_vld0;
input ifu_dtu_data_vld1;
input [26:0] ifu_dtu_debug_info;
input [31:0] ifu_dtu_exe_addr0;
input [31:0] ifu_dtu_exe_addr1;
input [31:0] ifu_dtu_exe_data0;
input [31:0] ifu_dtu_exe_data1;
input [8 :0] iu_dtu_debug_info;
input [78:0] lsu_dtu_debug_info;
input [14:0] lsu_dtu_halt_info;
input lsu_dtu_last_check;
input [31:0] lsu_dtu_ldst_addr;
input lsu_dtu_ldst_addr_vld;
input [7 :0] lsu_dtu_ldst_bytes_vld;
input [31:0] lsu_dtu_ldst_data;
input lsu_dtu_ldst_data_vld;
input [1 :0] lsu_dtu_ldst_type;
input [1 :0] lsu_dtu_mem_access_size;
input pad_yy_icg_scan_en;
input [13:0] rtu_dtu_debug_info;
input [31:0] rtu_dtu_dpc;
input rtu_dtu_halt_ack;
input rtu_dtu_nmi_pending;
input rtu_dtu_pending_ack;
input rtu_dtu_retire_chgflw;
input rtu_dtu_retire_debug_expt_vld;
input [14:0] rtu_dtu_retire_halt_info;
input rtu_dtu_retire_mret;
input [31:0] rtu_dtu_retire_next_pc;
input rtu_dtu_retire_vld;
input [31:0] rtu_dtu_tval;
input rtu_yy_xx_dbgon;
input rtu_yy_xx_expt_int;
input [11:0] rtu_yy_xx_expt_vec;
input rtu_yy_xx_expt_vld;
input [10:0] sahbl_dtu_debug_info;
input sys_apb_clk;
input sys_apb_rst_b;
input tdt_dm_dtu_ack_havereset;
input tdt_dm_dtu_async_halt_req;
input tdt_dm_dtu_halt_on_reset;
input tdt_dm_dtu_halt_req;
input [31:0] tdt_dm_dtu_itr;
input tdt_dm_dtu_itr_vld;
input tdt_dm_dtu_resume_req;
input [31:0] tdt_dm_dtu_wdata;
input [1 :0] tdt_dm_dtu_wr_flg;
input tdt_dm_dtu_wr_vld;
output dtu_cp0_dcsr_mprven;
output [1 :0] dtu_cp0_dcsr_prv;
output [31:0] dtu_cp0_rdata;
output dtu_cp0_wake_up;
output dtu_hpcp_dcsr_stopcount;
output [31:0] dtu_ifu_debug_inst;
output dtu_ifu_debug_inst_vld;
output [14:0] dtu_ifu_halt_info0;
output [14:0] dtu_ifu_halt_info1;
output dtu_ifu_halt_info_vld;
output dtu_ifu_halt_on_reset;
output dtu_lsu_addr_trig_en;
output dtu_lsu_data_trig_en;
output [14:0] dtu_lsu_halt_info;
output dtu_lsu_halt_info_vld;
output dtu_rtu_async_halt_req;
output [31:0] dtu_rtu_dpc;
output dtu_rtu_ebreak_action;
output dtu_rtu_int_mask;
output [31:0] dtu_rtu_pending_tval;
output dtu_rtu_resume_req;
output dtu_rtu_step_en;
output dtu_rtu_sync_flush;
output dtu_rtu_sync_halt_req;
output dtu_tdt_dm_halted;
output dtu_tdt_dm_havereset;
output dtu_tdt_dm_itr_done;
output dtu_tdt_dm_retire_debug_expt_vld;
output [31:0] dtu_tdt_dm_rx_data;
output dtu_tdt_dm_wr_ready;
// &Regs; @25
// &Wires; @26
wire async_halt_req_wakeup;
wire [3 :0] bmu_dtu_debug_info;
wire [11:0] cp0_dtu_addr;
wire [5 :0] cp0_dtu_debug_info;
wire cp0_dtu_icg_en;
wire cp0_dtu_mexpt_vld;
wire cp0_dtu_pcfifo_frz;
wire cp0_dtu_rreg;
wire [31:0] cp0_dtu_wdata;
wire cp0_dtu_wreg;
wire cp0_yy_clk_en;
wire [1 :0] cp0_yy_priv_mode;
wire cpurst_b;
wire [10:0] dahbl_dtu_debug_info;
wire dcsr_mprven;
wire [1 :0] dcsr_prv;
wire dcsr_step;
wire dcsr_stopcount;
wire [31:0] dpc;
wire [31:0] dscratch0;
wire dtu_cp0_dcsr_mprven;
wire [1 :0] dtu_cp0_dcsr_prv;
wire [31:0] dtu_cp0_rdata;
wire dtu_cp0_wake_up;
wire dtu_hpcp_dcsr_stopcount;
wire [31:0] dtu_ifu_debug_inst;
wire dtu_ifu_debug_inst_vld;
wire [14:0] dtu_ifu_halt_info0;
wire [14:0] dtu_ifu_halt_info1;
wire dtu_ifu_halt_info_vld;
wire dtu_ifu_halt_on_reset;
wire dtu_lsu_addr_trig_en;
wire dtu_lsu_data_trig_en;
wire [14:0] dtu_lsu_halt_info;
wire dtu_lsu_halt_info_vld;
wire dtu_rtu_async_halt_req;
wire [31:0] dtu_rtu_dpc;
wire dtu_rtu_ebreak_action;
wire dtu_rtu_int_mask;
wire [31:0] dtu_rtu_pending_tval;
wire dtu_rtu_resume_req;
wire dtu_rtu_step_en;
wire dtu_rtu_sync_flush;
wire dtu_rtu_sync_halt_req;
wire dtu_tdt_dm_halted;
wire dtu_tdt_dm_havereset;
wire dtu_tdt_dm_itr_done;
wire dtu_tdt_dm_retire_debug_expt_vld;
wire [31:0] dtu_tdt_dm_rx_data;
wire dtu_tdt_dm_wr_ready;
wire ebreak_action;
wire forever_cpuclk;
wire [7 :0] fpu_dtu_debug_info;
wire [10:0] iahbl_dtu_debug_info;
wire icount_enable;
wire [21:0] idu_dtu_debug_info;
wire [95:0] idu_dtu_fpr_info;
wire ifu_dtu_addr_vld0;
wire ifu_dtu_addr_vld1;
wire ifu_dtu_data_vld0;
wire ifu_dtu_data_vld1;
wire [26:0] ifu_dtu_debug_info;
wire [31:0] ifu_dtu_exe_addr0;
wire [31:0] ifu_dtu_exe_addr1;
wire [31:0] ifu_dtu_exe_data0;
wire [31:0] ifu_dtu_exe_data1;
wire int_mask;
wire [8 :0] iu_dtu_debug_info;
wire [31:0] latest_pc;
wire ldst_addr_mcontrol;
wire ldst_data_mcontrol;
wire low_power_wakeup;
wire [78:0] lsu_dtu_debug_info;
wire [14:0] lsu_dtu_halt_info;
wire lsu_dtu_last_check;
wire [31:0] lsu_dtu_ldst_addr;
wire lsu_dtu_ldst_addr_vld;
wire [7 :0] lsu_dtu_ldst_bytes_vld;
wire [31:0] lsu_dtu_ldst_data;
wire lsu_dtu_ldst_data_vld;
wire [1 :0] lsu_dtu_ldst_type;
wire [1 :0] lsu_dtu_mem_access_size;
wire pad_yy_icg_scan_en;
wire [13:0] rtu_dtu_debug_info;
wire [31:0] rtu_dtu_dpc;
wire rtu_dtu_halt_ack;
wire rtu_dtu_nmi_pending;
wire rtu_dtu_pending_ack;
wire rtu_dtu_retire_chgflw;
wire rtu_dtu_retire_debug_expt_vld;
wire [14:0] rtu_dtu_retire_halt_info;
wire rtu_dtu_retire_mret;
wire [31:0] rtu_dtu_retire_next_pc;
wire rtu_dtu_retire_vld;
wire [31:0] rtu_dtu_tval;
wire rtu_yy_xx_dbgon;
wire [10:0] sahbl_dtu_debug_info;
wire sys_apb_clk;
wire sys_apb_rst_b;
wire tdt_dm_dtu_ack_havereset;
wire tdt_dm_dtu_async_halt_req;
wire tdt_dm_dtu_halt_on_reset;
wire tdt_dm_dtu_halt_req;
wire [31:0] tdt_dm_dtu_itr;
wire tdt_dm_dtu_itr_vld;
wire tdt_dm_dtu_resume_req;
wire [31:0] tdt_dm_dtu_wdata;
wire [1 :0] tdt_dm_dtu_wr_flg;
wire tdt_dm_dtu_wr_vld;
wire [31:0] tdt_dm_wdata;
wire [1 :0] tdt_dm_wr_flg;
wire tdt_dm_wr_vld;
//XLEN
parameter XLEN = `TDT_DM_CORE_MAX_XLEN;
//halt_info parameter
parameter CANCLE = `TDT_HINFO_CANCEL;
parameter MATCH = `TDT_HINFO_MATCH;
parameter ACTION = `TDT_HINFO_ACTION;
parameter ACTION_01 = `TDT_HINFO_ACTION01;
parameter TIMING = `TDT_HINFO_TIMING;
parameter PENDING_HALT = `TDT_HINFO_PENDING_HALT;
parameter CAUSE = `TDT_HINFO_CAUSE;
parameter MATCH_TRIGGER = `TDT_HINFO_TRIGGER;
parameter HINFO_WIDTH = `TDT_HINFO_WIDTH;
//===============================================================
//assign output
//===============================================================
// CP0
// &Force("input","cp0_dtu_wreg"); @46
// &Force("input","cp0_dtu_rreg"); @47
// &Force("input","cp0_dtu_mexpt_vld"); @48
// &Force("input","idu_yy_xx_tail_ack"); @49
// &Force("input","cp0_dtu_int_id");&Force("bus","cp0_dtu_int_id",11,0); @50
assign dtu_cp0_dcsr_mprven = dcsr_mprven;
assign dtu_cp0_dcsr_prv[1:0] = dcsr_prv[1:0];
assign dtu_cp0_wake_up = low_power_wakeup;
//IFU
// &Force("input","ifu_dtu_addr_vld0"); @56
// &Force("input","ifu_dtu_data_vld0"); @57
// &Force("input","ifu_dtu_exe_addr0");&Force("bus","ifu_dtu_exe_addr0",`PA_WIDTH-1,0); @58
// &Force("input","ifu_dtu_exe_data0");&Force("bus","ifu_dtu_exe_data0",31,0); @59
// &Force("input","ifu_dtu_addr_vld1"); @60
// &Force("input","ifu_dtu_data_vld1"); @61
// &Force("input","ifu_dtu_exe_addr1");&Force("bus","ifu_dtu_exe_addr1",`PA_WIDTH-1,0); @62
// &Force("input","ifu_dtu_exe_data1");&Force("bus","ifu_dtu_exe_data1",31,0); @63
//LSU
assign dtu_lsu_addr_trig_en = ldst_addr_mcontrol;
assign dtu_lsu_data_trig_en = ldst_data_mcontrol;
//RTU
// &Force("input","rtu_yy_xx_expt_int"); @70
// &Force("input","rtu_yy_xx_expt_vld"); @71
// &Force("input","rtu_yy_xx_expt_vec");&Force("bus","rtu_yy_xx_expt_vec",11,0); @72
assign dtu_rtu_ebreak_action = ebreak_action;
assign dtu_rtu_int_mask = int_mask;
assign dtu_rtu_step_en = dcsr_step;
assign dtu_rtu_sync_flush = icount_enable;
assign dtu_rtu_dpc[XLEN-1:0] = dpc[XLEN-1:0];
//HPCP
assign dtu_hpcp_dcsr_stopcount = dcsr_stopcount;
// &Instance("pa_dtu_ctrl"); @82
pa_dtu_ctrl x_pa_dtu_ctrl (
.async_halt_req_wakeup (async_halt_req_wakeup ),
.bmu_dtu_debug_info (bmu_dtu_debug_info ),
.cp0_dtu_addr (cp0_dtu_addr ),
.cp0_dtu_debug_info (cp0_dtu_debug_info ),
.cp0_dtu_icg_en (cp0_dtu_icg_en ),
.cp0_dtu_mexpt_vld (cp0_dtu_mexpt_vld ),
.cp0_dtu_pcfifo_frz (cp0_dtu_pcfifo_frz ),
.cp0_dtu_rreg (cp0_dtu_rreg ),
.cp0_dtu_wdata (cp0_dtu_wdata ),
.cp0_dtu_wreg (cp0_dtu_wreg ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cp0_yy_priv_mode (cp0_yy_priv_mode ),
.cpurst_b (cpurst_b ),
.dahbl_dtu_debug_info (dahbl_dtu_debug_info ),
.dcsr_mprven (dcsr_mprven ),
.dcsr_prv (dcsr_prv ),
.dcsr_step (dcsr_step ),
.dcsr_stopcount (dcsr_stopcount ),
.dpc (dpc ),
.dscratch0 (dscratch0 ),
.dtu_cp0_rdata (dtu_cp0_rdata ),
.dtu_ifu_halt_info0 (dtu_ifu_halt_info0 ),
.dtu_ifu_halt_info1 (dtu_ifu_halt_info1 ),
.dtu_ifu_halt_info_vld (dtu_ifu_halt_info_vld ),
.dtu_lsu_halt_info (dtu_lsu_halt_info ),
.dtu_lsu_halt_info_vld (dtu_lsu_halt_info_vld ),
.dtu_rtu_async_halt_req (dtu_rtu_async_halt_req ),
.dtu_rtu_pending_tval (dtu_rtu_pending_tval ),
.dtu_rtu_sync_halt_req (dtu_rtu_sync_halt_req ),
.ebreak_action (ebreak_action ),
.forever_cpuclk (forever_cpuclk ),
.fpu_dtu_debug_info (fpu_dtu_debug_info ),
.iahbl_dtu_debug_info (iahbl_dtu_debug_info ),
.icount_enable (icount_enable ),
.idu_dtu_debug_info (idu_dtu_debug_info ),
.idu_dtu_fpr_info (idu_dtu_fpr_info ),
.ifu_dtu_addr_vld0 (ifu_dtu_addr_vld0 ),
.ifu_dtu_addr_vld1 (ifu_dtu_addr_vld1 ),
.ifu_dtu_data_vld0 (ifu_dtu_data_vld0 ),
.ifu_dtu_data_vld1 (ifu_dtu_data_vld1 ),
.ifu_dtu_debug_info (ifu_dtu_debug_info ),
.ifu_dtu_exe_addr0 (ifu_dtu_exe_addr0 ),
.ifu_dtu_exe_addr1 (ifu_dtu_exe_addr1 ),
.ifu_dtu_exe_data0 (ifu_dtu_exe_data0 ),
.ifu_dtu_exe_data1 (ifu_dtu_exe_data1 ),
.int_mask (int_mask ),
.iu_dtu_debug_info (iu_dtu_debug_info ),
.latest_pc (latest_pc ),
.ldst_addr_mcontrol (ldst_addr_mcontrol ),
.ldst_data_mcontrol (ldst_data_mcontrol ),
.low_power_wakeup (low_power_wakeup ),
.lsu_dtu_debug_info (lsu_dtu_debug_info ),
.lsu_dtu_halt_info (lsu_dtu_halt_info ),
.lsu_dtu_last_check (lsu_dtu_last_check ),
.lsu_dtu_ldst_addr (lsu_dtu_ldst_addr ),
.lsu_dtu_ldst_addr_vld (lsu_dtu_ldst_addr_vld ),
.lsu_dtu_ldst_bytes_vld (lsu_dtu_ldst_bytes_vld ),
.lsu_dtu_ldst_data (lsu_dtu_ldst_data ),
.lsu_dtu_ldst_data_vld (lsu_dtu_ldst_data_vld ),
.lsu_dtu_ldst_type (lsu_dtu_ldst_type ),
.lsu_dtu_mem_access_size (lsu_dtu_mem_access_size ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_dtu_debug_info (rtu_dtu_debug_info ),
.rtu_dtu_dpc (rtu_dtu_dpc ),
.rtu_dtu_halt_ack (rtu_dtu_halt_ack ),
.rtu_dtu_nmi_pending (rtu_dtu_nmi_pending ),
.rtu_dtu_pending_ack (rtu_dtu_pending_ack ),
.rtu_dtu_retire_chgflw (rtu_dtu_retire_chgflw ),
.rtu_dtu_retire_halt_info (rtu_dtu_retire_halt_info),
.rtu_dtu_retire_mret (rtu_dtu_retire_mret ),
.rtu_dtu_retire_next_pc (rtu_dtu_retire_next_pc ),
.rtu_dtu_retire_vld (rtu_dtu_retire_vld ),
.rtu_dtu_tval (rtu_dtu_tval ),
.rtu_yy_xx_dbgon (rtu_yy_xx_dbgon ),
.sahbl_dtu_debug_info (sahbl_dtu_debug_info ),
.tdt_dm_wdata (tdt_dm_wdata ),
.tdt_dm_wr_flg (tdt_dm_wr_flg ),
.tdt_dm_wr_vld (tdt_dm_wr_vld )
);
// &Instance("pa_dtu_cdc"); @84
pa_dtu_cdc x_pa_dtu_cdc (
.async_halt_req_wakeup (async_halt_req_wakeup ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.dscratch0 (dscratch0 ),
.dtu_ifu_debug_inst (dtu_ifu_debug_inst ),
.dtu_ifu_debug_inst_vld (dtu_ifu_debug_inst_vld ),
.dtu_ifu_halt_on_reset (dtu_ifu_halt_on_reset ),
.dtu_rtu_async_halt_req (dtu_rtu_async_halt_req ),
.dtu_rtu_resume_req (dtu_rtu_resume_req ),
.dtu_rtu_sync_halt_req (dtu_rtu_sync_halt_req ),
.dtu_tdt_dm_halted (dtu_tdt_dm_halted ),
.dtu_tdt_dm_havereset (dtu_tdt_dm_havereset ),
.dtu_tdt_dm_itr_done (dtu_tdt_dm_itr_done ),
.dtu_tdt_dm_retire_debug_expt_vld (dtu_tdt_dm_retire_debug_expt_vld),
.dtu_tdt_dm_rx_data (dtu_tdt_dm_rx_data ),
.dtu_tdt_dm_wr_ready (dtu_tdt_dm_wr_ready ),
.forever_cpuclk (forever_cpuclk ),
.latest_pc (latest_pc ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_dtu_retire_debug_expt_vld (rtu_dtu_retire_debug_expt_vld ),
.rtu_dtu_retire_vld (rtu_dtu_retire_vld ),
.rtu_yy_xx_dbgon (rtu_yy_xx_dbgon ),
.sys_apb_clk (sys_apb_clk ),
.sys_apb_rst_b (sys_apb_rst_b ),
.tdt_dm_dtu_ack_havereset (tdt_dm_dtu_ack_havereset ),
.tdt_dm_dtu_async_halt_req (tdt_dm_dtu_async_halt_req ),
.tdt_dm_dtu_halt_on_reset (tdt_dm_dtu_halt_on_reset ),
.tdt_dm_dtu_halt_req (tdt_dm_dtu_halt_req ),
.tdt_dm_dtu_itr (tdt_dm_dtu_itr ),
.tdt_dm_dtu_itr_vld (tdt_dm_dtu_itr_vld ),
.tdt_dm_dtu_resume_req (tdt_dm_dtu_resume_req ),
.tdt_dm_dtu_wdata (tdt_dm_dtu_wdata ),
.tdt_dm_dtu_wr_flg (tdt_dm_dtu_wr_flg ),
.tdt_dm_dtu_wr_vld (tdt_dm_dtu_wr_vld ),
.tdt_dm_wdata (tdt_dm_wdata ),
.tdt_dm_wr_flg (tdt_dm_wr_flg ),
.tdt_dm_wr_vld (tdt_dm_wr_vld )
);
// &Force("output","dtu_rtu_sync_halt_req"); @85
// &Force("output","dtu_rtu_async_halt_req"); @86
// &ModuleEnd; @88
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_dtu_trigger_module(
cp0_dtu_addr,
cp0_dtu_icg_en,
cp0_dtu_mexpt_vld,
cp0_dtu_wdata,
cp0_dtu_wreg,
cp0_yy_clk_en,
cp0_yy_priv_mode,
cpurst_b,
dtu_cause,
dtu_ifu_halt_info0,
dtu_ifu_halt_info1,
dtu_ifu_halt_info_vld,
dtu_lsu_halt_info,
dtu_lsu_halt_info_vld,
forever_cpuclk,
icount_enable,
ifu_dtu_addr_vld0,
ifu_dtu_addr_vld1,
ifu_dtu_data_vld0,
ifu_dtu_data_vld1,
ifu_dtu_exe_addr0,
ifu_dtu_exe_addr1,
ifu_dtu_exe_data0,
ifu_dtu_exe_data1,
ldst_addr_mcontrol,
ldst_data_mcontrol,
lsu_dtu_halt_info,
lsu_dtu_last_check,
lsu_dtu_ldst_addr,
lsu_dtu_ldst_addr_vld,
lsu_dtu_ldst_bytes_vld,
lsu_dtu_ldst_data,
lsu_dtu_ldst_data_vld,
lsu_dtu_ldst_type,
lsu_dtu_mem_access_size,
mcontext,
pad_yy_icg_scan_en,
pending_halt,
rtu_dtu_halt_ack,
rtu_dtu_pending_ack,
rtu_dtu_retire_halt_info,
rtu_dtu_retire_mret,
rtu_dtu_retire_vld,
rtu_yy_xx_dbgon,
tcontrol,
tdata1,
tdata2,
tdata3,
tinfo,
tselect,
updata_tval
);
// &Ports; @24
input [11:0] cp0_dtu_addr;
input cp0_dtu_icg_en;
input cp0_dtu_mexpt_vld;
input [31:0] cp0_dtu_wdata;
input cp0_dtu_wreg;
input cp0_yy_clk_en;
input [1 :0] cp0_yy_priv_mode;
input cpurst_b;
input forever_cpuclk;
input ifu_dtu_addr_vld0;
input ifu_dtu_addr_vld1;
input ifu_dtu_data_vld0;
input ifu_dtu_data_vld1;
input [31:0] ifu_dtu_exe_addr0;
input [31:0] ifu_dtu_exe_addr1;
input [31:0] ifu_dtu_exe_data0;
input [31:0] ifu_dtu_exe_data1;
input [14:0] lsu_dtu_halt_info;
input lsu_dtu_last_check;
input [31:0] lsu_dtu_ldst_addr;
input lsu_dtu_ldst_addr_vld;
input [7 :0] lsu_dtu_ldst_bytes_vld;
input [31:0] lsu_dtu_ldst_data;
input lsu_dtu_ldst_data_vld;
input [1 :0] lsu_dtu_ldst_type;
input [1 :0] lsu_dtu_mem_access_size;
input pad_yy_icg_scan_en;
input rtu_dtu_halt_ack;
input rtu_dtu_pending_ack;
input [14:0] rtu_dtu_retire_halt_info;
input rtu_dtu_retire_mret;
input rtu_dtu_retire_vld;
input rtu_yy_xx_dbgon;
output [3 :0] dtu_cause;
output [14:0] dtu_ifu_halt_info0;
output [14:0] dtu_ifu_halt_info1;
output dtu_ifu_halt_info_vld;
output [14:0] dtu_lsu_halt_info;
output dtu_lsu_halt_info_vld;
output icount_enable;
output ldst_addr_mcontrol;
output ldst_data_mcontrol;
output [31:0] mcontext;
output pending_halt;
output [31:0] tcontrol;
output [31:0] tdata1;
output [31:0] tdata2;
output [31:0] tdata3;
output [31:0] tinfo;
output [31:0] tselect;
output updata_tval;
// &Regs; @25
// &Wires; @26
wire [11:0] cp0_dtu_addr;
wire cp0_dtu_icg_en;
wire cp0_dtu_mexpt_vld;
wire [31:0] cp0_dtu_wdata;
wire cp0_dtu_wreg;
wire cp0_write_mcontext;
wire cp0_write_tcontrol;
wire cp0_write_tdata1;
wire cp0_write_tdata2;
wire cp0_write_tdata3;
wire cp0_write_tselect;
wire cp0_yy_clk_en;
wire [1 :0] cp0_yy_priv_mode;
wire cpurst_b;
wire [3 :0] dtu_cause;
wire [14:0] dtu_ifu_halt_info0;
wire [14:0] dtu_ifu_halt_info1;
wire dtu_ifu_halt_info_vld;
wire [14:0] dtu_lsu_halt_info;
wire dtu_lsu_halt_info_vld;
wire exe0_16bit;
wire exe0_32bit;
wire exe1_16bit;
wire exe1_32bit;
wire forever_cpuclk;
wire icount_enable;
wire ifu_dtu_addr_vld0;
wire ifu_dtu_addr_vld1;
wire ifu_dtu_data_vld0;
wire ifu_dtu_data_vld1;
wire [31:0] ifu_dtu_exe_addr0;
wire [31:0] ifu_dtu_exe_addr1;
wire [31:0] ifu_dtu_exe_data0;
wire [31:0] ifu_dtu_exe_data1;
wire ldst_16bit;
wire ldst_32bit;
wire ldst_8bit;
wire ldst_addr_mcontrol;
wire ldst_data_mcontrol;
wire load_addr_vld;
wire load_data_vld;
wire [14:0] lsu_dtu_halt_info;
wire lsu_dtu_last_check;
wire [31:0] lsu_dtu_ldst_addr;
wire lsu_dtu_ldst_addr_vld;
wire [7 :0] lsu_dtu_ldst_bytes_vld;
wire [31:0] lsu_dtu_ldst_data;
wire lsu_dtu_ldst_data_vld;
wire [1 :0] lsu_dtu_ldst_type;
wire [1 :0] lsu_dtu_mem_access_size;
wire m_mode;
wire [31:0] mcontext;
wire pad_yy_icg_scan_en;
wire pending_halt;
wire rtu_dtu_halt_ack;
wire rtu_dtu_pending_ack;
wire [14:0] rtu_dtu_retire_halt_info;
wire rtu_dtu_retire_mret;
wire rtu_dtu_retire_vld;
wire rtu_yy_xx_dbgon;
wire store_addr_vld;
wire store_data_vld;
wire [31:0] tcontrol;
wire [31:0] tdata1;
wire [31:0] tdata2;
wire [31:0] tdata3;
wire [31:0] tinfo;
wire [31:0] tselect;
wire u_mode;
wire updata_tval;
parameter XLEN = `TDT_DM_CORE_MAX_XLEN;
//=========================================================
// information from core
//=========================================================
//privileg mode
assign m_mode = cp0_yy_priv_mode[1:0] == 2'b11 || rtu_dtu_retire_mret;
//assign s_mode = (cp0_yy_priv_mode[1:0] == 2'b01 || rtu_dtu_retire_sret) && !rtu_dtu_retire_mret;
assign u_mode = cp0_yy_priv_mode[1:0] == 2'b00 && !rtu_dtu_retire_mret;
//cp0 write trigger csrm req
assign cp0_write_tselect = cp0_dtu_wreg && cp0_dtu_addr[11:0] == 12'h7a0;
assign cp0_write_tdata1 = cp0_dtu_wreg && cp0_dtu_addr[11:0] == 12'h7a1;
assign cp0_write_tdata2 = cp0_dtu_wreg && cp0_dtu_addr[11:0] == 12'h7a2;
assign cp0_write_tdata3 = cp0_dtu_wreg && cp0_dtu_addr[11:0] == 12'h7a3;
assign cp0_write_tcontrol = cp0_dtu_wreg && cp0_dtu_addr[11:0] == 12'h7a5;
assign cp0_write_mcontext = cp0_dtu_wreg && cp0_dtu_addr[11:0] == 12'h7a8;
//int or expt vld
//exe, store or load vld
assign store_addr_vld = lsu_dtu_ldst_addr_vld && lsu_dtu_ldst_type[0];
assign store_data_vld = lsu_dtu_ldst_data_vld && lsu_dtu_ldst_type[0];
assign load_addr_vld = lsu_dtu_ldst_addr_vld && lsu_dtu_ldst_type[1];
assign load_data_vld = lsu_dtu_ldst_data_vld && lsu_dtu_ldst_type[1];
//mem access or execution size
// &Force("input","ifu_dtu_exe_data0");&Force("bus","ifu_dtu_exe_data0",31,0); @81
// &Force("input","ifu_dtu_exe_data1");&Force("bus","ifu_dtu_exe_data1",31,0); @82
assign exe0_16bit = !(ifu_dtu_exe_data0[0] && ifu_dtu_exe_data0[1]);
assign exe0_32bit = ifu_dtu_exe_data0[0] && ifu_dtu_exe_data0[1];
assign exe1_16bit = !(ifu_dtu_exe_data1[0] && ifu_dtu_exe_data1[1]);
assign exe1_32bit = ifu_dtu_exe_data1[0] && ifu_dtu_exe_data1[1];
assign ldst_8bit = lsu_dtu_mem_access_size[1:0] == 2'b00;
assign ldst_16bit = lsu_dtu_mem_access_size[1:0] == 2'b01;
assign ldst_32bit = lsu_dtu_mem_access_size[1:0] == 2'b10;
// &Instance("pa_dtu_0m_0iie"); @95
// &Instance("pa_dtu_m_iie_all"); @97
// &Instance("pa_dtu_m_iie_all"); @100
pa_dtu_m_iie_all x_pa_dtu_m_iie_all (
.cp0_dtu_icg_en (cp0_dtu_icg_en ),
.cp0_dtu_mexpt_vld (cp0_dtu_mexpt_vld ),
.cp0_dtu_wdata (cp0_dtu_wdata ),
.cp0_write_mcontext (cp0_write_mcontext ),
.cp0_write_tcontrol (cp0_write_tcontrol ),
.cp0_write_tdata1 (cp0_write_tdata1 ),
.cp0_write_tdata2 (cp0_write_tdata2 ),
.cp0_write_tdata3 (cp0_write_tdata3 ),
.cp0_write_tselect (cp0_write_tselect ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.dtu_cause (dtu_cause ),
.dtu_ifu_halt_info0 (dtu_ifu_halt_info0 ),
.dtu_ifu_halt_info1 (dtu_ifu_halt_info1 ),
.dtu_ifu_halt_info_vld (dtu_ifu_halt_info_vld ),
.dtu_lsu_halt_info (dtu_lsu_halt_info ),
.dtu_lsu_halt_info_vld (dtu_lsu_halt_info_vld ),
.exe0_16bit (exe0_16bit ),
.exe0_32bit (exe0_32bit ),
.exe1_16bit (exe1_16bit ),
.exe1_32bit (exe1_32bit ),
.forever_cpuclk (forever_cpuclk ),
.icount_enable (icount_enable ),
.ifu_dtu_addr_vld0 (ifu_dtu_addr_vld0 ),
.ifu_dtu_addr_vld1 (ifu_dtu_addr_vld1 ),
.ifu_dtu_data_vld0 (ifu_dtu_data_vld0 ),
.ifu_dtu_data_vld1 (ifu_dtu_data_vld1 ),
.ifu_dtu_exe_addr0 (ifu_dtu_exe_addr0 ),
.ifu_dtu_exe_addr1 (ifu_dtu_exe_addr1 ),
.ldst_16bit (ldst_16bit ),
.ldst_32bit (ldst_32bit ),
.ldst_8bit (ldst_8bit ),
.ldst_addr_mcontrol (ldst_addr_mcontrol ),
.ldst_data_mcontrol (ldst_data_mcontrol ),
.load_addr_vld (load_addr_vld ),
.load_data_vld (load_data_vld ),
.lsu_dtu_halt_info (lsu_dtu_halt_info ),
.lsu_dtu_last_check (lsu_dtu_last_check ),
.lsu_dtu_ldst_addr (lsu_dtu_ldst_addr ),
.lsu_dtu_ldst_addr_vld (lsu_dtu_ldst_addr_vld ),
.lsu_dtu_ldst_bytes_vld (lsu_dtu_ldst_bytes_vld ),
.lsu_dtu_ldst_data (lsu_dtu_ldst_data ),
.lsu_dtu_ldst_data_vld (lsu_dtu_ldst_data_vld ),
.m_mode (m_mode ),
.mcontext (mcontext ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.pending_halt (pending_halt ),
.rtu_dtu_halt_ack (rtu_dtu_halt_ack ),
.rtu_dtu_pending_ack (rtu_dtu_pending_ack ),
.rtu_dtu_retire_halt_info (rtu_dtu_retire_halt_info),
.rtu_dtu_retire_mret (rtu_dtu_retire_mret ),
.rtu_dtu_retire_vld (rtu_dtu_retire_vld ),
.rtu_yy_xx_dbgon (rtu_yy_xx_dbgon ),
.store_addr_vld (store_addr_vld ),
.store_data_vld (store_data_vld ),
.tcontrol (tcontrol ),
.tdata1 (tdata1 ),
.tdata2 (tdata2 ),
.tdata3 (tdata3 ),
.tinfo (tinfo ),
.tselect (tselect ),
.u_mode (u_mode ),
.updata_tval (updata_tval )
);
// &ModuleEnd; @109
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @22
module pa_fadd_lop_s1_s(
ff1_mask,
ff1_pred,
ff1_pred_d,
ff1_pred_onehot,
src0_adder,
src1_adder
);
// &Ports; @23
input [27:0] ff1_mask;
input [27:0] src0_adder;
input [27:0] src1_adder;
output [4 :0] ff1_pred;
output [4 :0] ff1_pred_d;
output [27:0] ff1_pred_onehot;
// &Regs; @24
reg [4 :0] ff1_pred_e_d;
reg [4 :0] ff1_pred_t0_d;
reg [27:0] ff1_pred_t0_d_onehot;
// &Wires; @25
wire [27:0] close_adder0_t0;
wire [27:0] close_adder1_t0;
wire [27:0] close_ff1_a_t0;
wire [27:0] close_ff1_b_t0;
wire [27:0] close_ff1_c_t0;
wire [27:0] close_ff1_f_t0;
wire [27:0] close_ff1_g_t0;
wire [27:0] close_ff1_t_t0;
wire [27:0] close_ff1_z_t0;
wire [27:0] ff1_code;
wire [27:0] ff1_mask;
wire [4 :0] ff1_pred;
wire [4 :0] ff1_pred_d;
wire [27:0] ff1_pred_onehot;
wire [27:0] src0_adder;
wire [27:0] src1_adder;
assign ff1_pred_onehot[27:0] = ff1_pred_t0_d_onehot[27:0];
assign ff1_pred[4:0] = ff1_pred_t0_d[4:0];
//assign ff1_pred_s[5:0] = {1'b0,//ff1_pred_t0_s[4:0]};
assign ff1_pred_d[4:0] = ff1_pred_e_d[4:0];
assign close_adder0_t0[27:0] = src0_adder[27:0];
assign close_adder1_t0[27:0] = src1_adder[27:0];
//close_sum0 for F1-F0
//close_sum select, keep sum not negative
//close_sum0_m1
//assign close_sum_m1_t0[53:0] = $unsigned($signed(close_adder0_t0[53:0])
// - $signed(close_adder1_t0[53:0])
// + $signed(close_m1_oper2[53:0]));
//csky vperl_on
//FF1 Logic of Close Path S0
//If predict first 1 set at r[n]
//Actual first 1 may set at r[n+1] or r[n]
//A and B are to oprand
assign close_ff1_a_t0[27:0] = close_adder0_t0[27:0];
assign close_ff1_b_t0[27:0] = close_adder1_t0[27:0];
//C = B && act_add || ~B && act_sub
assign close_ff1_c_t0[27:0] = ~close_ff1_b_t0[27:0];
//T = A^C G=A&C Z=(~A)&(~C)
assign close_ff1_t_t0[27:0] = close_ff1_a_t0[27:0] ^ close_ff1_c_t0[27:0];
assign close_ff1_g_t0[27:0] = close_ff1_a_t0[27:0] & close_ff1_c_t0[27:0];
assign close_ff1_z_t0[27:0] = (~close_ff1_a_t0[27:0]) & (~close_ff1_c_t0[27:0]);
//F :
//fn-1 = En[gi(~zi-1) + zi(~gi-1)] + (~En)[gi(~gi-1) + zi(~zi-1)], En=act_sub
//f0 = t1(g0En+z0) + (~t1)(z0En+g0)
//fi = ti+1[gi(~zi-1) + zi(~gi-1)] + (~ti+1)[gi(~gi-1) + zi(~zi-1)]
assign close_ff1_f_t0[27] = ( close_ff1_g_t0[27] & (~close_ff1_z_t0[26])) |
( close_ff1_z_t0[27] & (~close_ff1_g_t0[26]));
assign close_ff1_f_t0[0] = (( close_ff1_t_t0[1]) & (close_ff1_g_t0[0] | close_ff1_z_t0[0])) |
((~close_ff1_t_t0[1]) & (close_ff1_z_t0[0] | close_ff1_g_t0[0]));
assign close_ff1_f_t0[26:1] = (( close_ff1_t_t0[27:2]) & ((close_ff1_g_t0[26:1] & (~close_ff1_z_t0[25:0])) |
( close_ff1_z_t0[26:1] & (~close_ff1_g_t0[25:0])))) |
((~close_ff1_t_t0[27:2]) & ((close_ff1_g_t0[26:1] & (~close_ff1_g_t0[25:0])) |
( close_ff1_z_t0[26:1] & (~close_ff1_z_t0[25:0]))));
assign ff1_code[27:0] = close_ff1_f_t0[27:0] | ff1_mask[27:0];
// &CombBeg; @70
always @( ff1_code[27:0])
begin
casez(ff1_code[27:0])
28'b1???_????_????_????_????_????_????: begin
ff1_pred_t0_d_onehot[27:0] = 28'b1000_0000_0000_0000_0000_0000_0000;
ff1_pred_t0_d[4:0] = 5'd0;
ff1_pred_e_d[4:0] = 5'b0;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b01??_????_????_????_????_????_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0100_0000_0000_0000_0000_0000_0000;
ff1_pred_t0_d[4:0] = 5'd1;
ff1_pred_e_d[4:0] = 5'd0;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b001?_????_????_????_????_????_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0010_0000_0000_0000_0000_0000_0000;
ff1_pred_t0_d[4:0] = 5'd2;
ff1_pred_e_d[4:0] = 5'd1;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0001_????_????_????_????_????_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0001_0000_0000_0000_0000_0000_0000;
ff1_pred_t0_d[4:0] = 5'd3;
ff1_pred_e_d[4:0] = 5'd2;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_1???_????_????_????_????_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_1000_0000_0000_0000_0000_0000;
ff1_pred_t0_d[4:0] = 5'd4;
ff1_pred_e_d[4:0] = 5'd3;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_01??_????_????_????_????_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0100_0000_0000_0000_0000_0000;
ff1_pred_t0_d[4:0] = 5'd5;
ff1_pred_e_d[4:0] = 5'd4;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_001?_????_????_????_????_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0010_0000_0000_0000_0000_0000;
ff1_pred_t0_d[4:0] = 5'd6;
ff1_pred_e_d[4:0] = 5'd5;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_0001_????_????_????_????_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0001_0000_0000_0000_0000_0000;
ff1_pred_t0_d[4:0] = 5'd7;
ff1_pred_e_d[4:0] = 5'd6;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_0000_1???_????_????_????_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0000_1000_0000_0000_0000_0000;
ff1_pred_t0_d[4:0] = 5'd8;
ff1_pred_e_d[4:0] = 5'd7;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_0000_01??_????_????_????_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0000_0100_0000_0000_0000_0000;
ff1_pred_t0_d[4:0] = 5'd9;
ff1_pred_e_d[4:0] = 5'd8;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_0000_001?_????_????_????_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0000_0010_0000_0000_0000_0000;
ff1_pred_t0_d[4:0] = 5'd10;
ff1_pred_e_d[4:0] = 5'd9;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_0000_0001_????_????_????_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0000_0001_0000_0000_0000_0000;
ff1_pred_t0_d[4:0] = 5'd11;
ff1_pred_e_d[4:0] = 5'd10;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_0000_0000_1???_????_????_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0000_0000_1000_0000_0000_0000;
ff1_pred_t0_d[4:0] = 5'd12;
ff1_pred_e_d[4:0] = 5'd11;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_0000_0000_01??_????_????_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0000_0000_0100_0000_0000_0000;
ff1_pred_t0_d[4:0] = 5'd13;
ff1_pred_e_d[4:0] = 5'd12;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_0000_0000_001?_????_????_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0000_0000_0010_0000_0000_0000;
ff1_pred_t0_d[4:0] = 5'd14;
ff1_pred_e_d[4:0] = 5'd13;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_0000_0000_0001_????_????_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0000_0000_0001_0000_0000_0000;
ff1_pred_t0_d[4:0] = 5'd15;
ff1_pred_e_d[4:0] = 5'd14;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_0000_0000_0000_1???_????_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0000_0000_0000_1000_0000_0000;
ff1_pred_t0_d[4:0] = 5'd16;
ff1_pred_e_d[4:0] = 5'd15;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_0000_0000_0000_01??_????_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0000_0000_0000_0100_0000_0000;
ff1_pred_t0_d[4:0] = 5'd17;
ff1_pred_e_d[4:0] = 5'd16;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_0000_0000_0000_001?_????_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0000_0000_0000_0010_0000_0000;
ff1_pred_t0_d[4:0] = 5'd18;
ff1_pred_e_d[4:0] = 5'd17;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_0000_0000_0000_0001_????_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0000_0000_0000_0001_0000_0000;
ff1_pred_t0_d[4:0] = 5'd19;
ff1_pred_e_d[4:0] = 5'd18;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_0000_0000_0000_0000_1???_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0000_0000_0000_0000_1000_0000;
ff1_pred_t0_d[4:0] = 5'd20;
ff1_pred_e_d[4:0] = 5'd19;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_0000_0000_0000_0000_01??_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0000_0000_0000_0000_0100_0000;
ff1_pred_t0_d[4:0] = 5'd21;
ff1_pred_e_d[4:0] = 5'd20;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_0000_0000_0000_0000_001?_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0000_0000_0000_0000_0010_0000;
ff1_pred_t0_d[4:0] = 5'd22;
ff1_pred_e_d[4:0] = 5'd21;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_0000_0000_0000_0000_0001_???? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0000_0000_0000_0000_0001_0000;
ff1_pred_t0_d[4:0] = 5'd23;
ff1_pred_e_d[4:0] = 5'd22;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_0000_0000_0000_0000_0000_1??? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0000_0000_0000_0000_0000_1000;
ff1_pred_t0_d[4:0] = 5'd24;
ff1_pred_e_d[4:0] = 5'd23;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_0000_0000_0000_0000_0000_01?? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0000_0000_0000_0000_0000_0100;
ff1_pred_t0_d[4:0] = 5'd25;
ff1_pred_e_d[4:0] = 5'd24;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_0000_0000_0000_0000_0000_001? : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0000_0000_0000_0000_0000_0010;
ff1_pred_t0_d[4:0] = 5'd26;
ff1_pred_e_d[4:0] = 5'd25;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
28'b0000_0000_0000_0000_0000_0000_0001 : begin
ff1_pred_t0_d_onehot[27:0] = 28'b0000_0000_0000_0000_0000_0000_0001;
ff1_pred_t0_d[4:0] = 5'd27;
ff1_pred_e_d[4:0] = 5'd26;
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
default : begin
ff1_pred_t0_d_onehot[27:0] = {28{1'bx}};
ff1_pred_t0_d[4:0] = {5{1'bx}};
ff1_pred_e_d[4:0] = {5{1'bx}};
//ff1_pred_t0_s[4:0] = {5{1'bx}};
end
endcase
// &CombEnd; @247
end
// &ModuleEnd; @249
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_fadd_nm_shift_single(
data_cnt,
data_g_out,
data_in,
data_out,
data_r_out,
data_s_out
);
// &Ports; @24
input [7 :0] data_cnt;
input [23:0] data_in;
output data_g_out;
output [23:0] data_out;
output data_r_out;
output data_s_out;
// &Regs; @25
reg data_g_out;
reg [23:0] data_out;
reg data_r_out;
reg data_s_out;
// &Wires; @26
wire [7 :0] data_cnt;
wire [23:0] data_in;
wire [7 :0] shift_cnt;
wire [23:0] shift_pre;
assign shift_pre[23:0] = data_in[23:0];
assign shift_cnt[7:0] = data_cnt[7:0];
// &CombBeg; @32
always @( shift_pre[23:0]
or shift_cnt[7:0])
begin
case(shift_cnt[7:0])
8'd0 : begin
data_out[23:0] = { shift_pre[23:0]};
data_g_out = 1'b0;
data_r_out = 1'b0;
data_s_out = 1'b0;
end
8'd1 : begin
data_out[23:0] = {1'b0, shift_pre[23:1]};
data_g_out = shift_pre[0];
data_r_out = 1'b0;
data_s_out = 1'b0;
end
8'd2 : begin
data_out[23:0] = {2'b0, shift_pre[23:2]};
data_g_out = shift_pre[1];
data_r_out = shift_pre[0];
data_s_out = 1'b0;
end
8'd3 : begin
data_out[23:0] = {3'b0, shift_pre[23:3]};
data_g_out = shift_pre[2];
data_r_out = shift_pre[1];
data_s_out = shift_pre[0];
end
8'd4 : begin
data_out[23:0] = {4'b0, shift_pre[23:4]};
data_g_out = shift_pre[3];
data_r_out = shift_pre[2];
data_s_out = |shift_pre[1:0];
end
8'd5 : begin
data_out[23:0] = {5'b0, shift_pre[23:5]};
data_g_out = shift_pre[4];
data_r_out = shift_pre[3];
data_s_out = |shift_pre[2:0];
end
8'd6 : begin
data_out[23:0] = {6'b0, shift_pre[23:6]};
data_g_out = shift_pre[5];
data_r_out = shift_pre[4];
data_s_out = |shift_pre[3:0];
end
8'd7 : begin
data_out[23:0] = {7'b0, shift_pre[23:7]};
data_g_out = shift_pre[6];
data_r_out = shift_pre[5];
data_s_out = |shift_pre[4:0];
end
8'd8 : begin
data_out[23:0] = {8'b0, shift_pre[23:8]};
data_g_out = shift_pre[7];
data_r_out = shift_pre[6];
data_s_out = |shift_pre[5:0];
end
8'd9 : begin
data_out[23:0] = {9'b0, shift_pre[23:9]};
data_g_out = shift_pre[8];
data_r_out = shift_pre[7];
data_s_out = |shift_pre[6:0];
end
8'd10 : begin
data_out[23:0] = {10'b0, shift_pre[23:10]};
data_g_out = shift_pre[9];
data_r_out = shift_pre[8];
data_s_out = |shift_pre[7:0];
end
8'd11 : begin
data_out[23:0] = {11'b0, shift_pre[23:11]};
data_g_out = shift_pre[10];
data_r_out = shift_pre[9];
data_s_out = |shift_pre[8:0];
end
8'd12 : begin
data_out[23:0] = {12'b0, shift_pre[23:12]};
data_g_out = shift_pre[11];
data_r_out = shift_pre[10];
data_s_out = |shift_pre[9:0];
end
8'd13 : begin
data_out[23:0] = {13'b0, shift_pre[23:13]};
data_g_out = shift_pre[12];
data_r_out = shift_pre[11];
data_s_out = |shift_pre[10:0];
end
8'd14 : begin
data_out[23:0] = {14'b0, shift_pre[23:14]};
data_g_out = shift_pre[13];
data_r_out = shift_pre[12];
data_s_out = |shift_pre[11:0];
end
8'd15 : begin
data_out[23:0] = {15'b0, shift_pre[23:15]};
data_g_out = shift_pre[14];
data_r_out = shift_pre[13];
data_s_out = |shift_pre[12:0];
end
8'd16 : begin
data_out[23:0] = {16'b0, shift_pre[23:16]};
data_g_out = shift_pre[15];
data_r_out = shift_pre[14];
data_s_out = |shift_pre[13:0];
end
8'd17 : begin
data_out[23:0] = {17'b0, shift_pre[23:17]};
data_g_out = shift_pre[16];
data_r_out = shift_pre[15];
data_s_out = |shift_pre[14:0];
end
8'd18 : begin
data_out[23:0] = {18'b0, shift_pre[23:18]};
data_g_out = shift_pre[17];
data_r_out = shift_pre[16];
data_s_out = |shift_pre[15:0];
end
8'd19 : begin
data_out[23:0] = {19'b0, shift_pre[23:19]};
data_g_out = shift_pre[18];
data_r_out = shift_pre[17];
data_s_out = |shift_pre[16:0];
end
8'd20 : begin
data_out[23:0] = {20'b0, shift_pre[23:20]};
data_g_out = shift_pre[19];
data_r_out = shift_pre[18];
data_s_out = |shift_pre[17:0];
end
8'd21 : begin
data_out[23:0] = {21'b0, shift_pre[23:21]};
data_g_out = shift_pre[20];
data_r_out = shift_pre[19];
data_s_out = |shift_pre[18:0];
end
8'd22 : begin
data_out[23:0] = {22'b0, shift_pre[23:22]};
data_g_out = shift_pre[21];
data_r_out = shift_pre[20];
data_s_out = |shift_pre[19:0];
end
8'd23 : begin
data_out[23:0] = {23'b0, shift_pre[23]};
data_g_out = shift_pre[22];
data_r_out = shift_pre[21];
data_s_out = |shift_pre[20:0];
end
8'd24 : begin
data_out[23:0] = 24'b0;
data_g_out = shift_pre[23];
data_r_out = shift_pre[22];
data_s_out = |shift_pre[21:0];
end
8'd25 : begin
data_out[23:0] = 24'b0;
data_g_out = 1'b0;
data_r_out = shift_pre[23];
data_s_out = |shift_pre[22:0];
end
default : begin
data_out[23:0] = 24'b0;
data_g_out = 1'b0;
data_r_out = 1'b0;
data_s_out = |shift_pre[23:0];
end
endcase
// &CombEnd; @197
end
// &ModuleEnd; @200
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_fadd_shift_sub_single(
data_in,
data_out,
shift_cnt
);
// &Ports; @24
input [27:0] data_in;
input [4 :0] shift_cnt;
output [27:0] data_out;
// &Regs; @25
reg [27:0] data_shift;
// &Wires; @26
wire [4 :0] cnt;
wire [27:0] data_in;
wire [27:0] data_out;
wire [27:0] data_shift_pre;
wire [4 :0] shift_cnt;
assign data_shift_pre[27:0] = data_in[27:0];
assign data_out[27:0] = data_shift[27:0];
assign cnt[4:0] = shift_cnt[4:0];
// &CombBeg; @33
always @( cnt[4:0]
or data_shift_pre[27:0])
begin
case(cnt[4:0])
5'd0 : data_shift[27:0] = data_shift_pre[27:0];
5'd1 : data_shift[27:0] = {data_shift_pre[26:0], 1'b0};
5'd2 : data_shift[27:0] = {data_shift_pre[25:0], 2'b0};
5'd3 : data_shift[27:0] = {data_shift_pre[24:0], 3'b0};
5'd4 : data_shift[27:0] = {data_shift_pre[23:0], 4'b0};
5'd5 : data_shift[27:0] = {data_shift_pre[22:0], 5'b0};
5'd6 : data_shift[27:0] = {data_shift_pre[21:0], 6'b0};
5'd7 : data_shift[27:0] = {data_shift_pre[20:0], 7'b0};
5'd8 : data_shift[27:0] = {data_shift_pre[19:0], 8'b0};
5'd9 : data_shift[27:0] = {data_shift_pre[18:0], 9'b0};
5'd10 : data_shift[27:0] = {data_shift_pre[17:0],10'b0};
5'd11 : data_shift[27:0] = {data_shift_pre[16:0],11'b0};
5'd12 : data_shift[27:0] = {data_shift_pre[15:0],12'b0};
5'd13 : data_shift[27:0] = {data_shift_pre[14:0],13'b0};
5'd14 : data_shift[27:0] = {data_shift_pre[13:0],14'b0};
5'd15 : data_shift[27:0] = {data_shift_pre[12:0],15'b0};
5'd16 : data_shift[27:0] = {data_shift_pre[11:0],16'b0};
5'd17 : data_shift[27:0] = {data_shift_pre[10:0],17'b0};
5'd18 : data_shift[27:0] = {data_shift_pre[9:0],18'b0};
5'd19 : data_shift[27:0] = {data_shift_pre[8:0],19'b0};
5'd20 : data_shift[27:0] = {data_shift_pre[7:0],20'b0};
5'd21 : data_shift[27:0] = {data_shift_pre[6:0],21'b0};
5'd22 : data_shift[27:0] = {data_shift_pre[5:0],22'b0};
5'd23 : data_shift[27:0] = {data_shift_pre[4:0],23'b0};
5'd24 : data_shift[27:0] = {data_shift_pre[3:0],24'b0};
5'd25 : data_shift[27:0] = {data_shift_pre[2:0],25'b0};
5'd26 : data_shift[27:0] = {data_shift_pre[1:0],26'b0};
5'd27 : data_shift[27:0] = {data_shift_pre[0],27'b0};
default: data_shift[27:0] = 28'b0;
endcase
// &CombEnd; @65
end
// &ModuleEnd; @71
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_falu_ctrl(
cp0_fpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
ctrl_falu_ex1_sel,
ctrl_falu_ex1_sel_dp,
ctrl_falu_ex1_sel_gate,
ctrl_xx_ex1_cmplt_dp,
ctrl_xx_ex1_inst_vld,
ctrl_xx_ex1_stall,
ctrl_xx_ex1_warm_up,
ctrl_xx_ex2_cancel,
ctrl_xx_ex2_stall,
ctrl_xx_ex2_warm_up,
ctrl_xx_ex3_stall,
fadd_ex1_dp_fflags,
fadd_ex1_dp_special_result,
fadd_ex1_dp_special_sel,
fadd_ex1_dp_special_sign,
fadd_ex1_dp_wb_vld,
fadd_ex1_pipe_clk,
fadd_ex1_pipedown,
fadd_ex1_sel,
fadd_ex1_sel_dp,
fadd_ex2_dp_fflags,
fadd_ex2_dp_rst,
fadd_ex2_dp_wb_vld,
fadd_ex2_nocmp,
fadd_ex2_nocmp_pipe_clk,
fadd_ex2_nocmp_pipedown,
fadd_ex2_pipe_clk,
fadd_ex2_pipedown,
fadd_ex2_sel,
fadd_ex3_dp_fflags,
fadd_ex3_dp_rst,
fadd_ex3_dp_wb_vld,
fadd_ex3_rtu_fflags,
fadd_ex3_rtu_rst,
fadd_ex3_rtu_wb_vld,
fadd_ex3_sel,
falu_ctrl_xx_ex1_vld,
falu_ctrl_xx_ex2_vld,
falu_ctrl_xx_ex3_vld,
falu_fpu_ex1_cmplt,
falu_fpu_ex1_cmplt_dp,
falu_fpu_ex1_fflags,
falu_fpu_ex1_result,
falu_fpu_ex1_special_sel,
falu_fpu_ex1_special_sign,
falu_fpu_ex1_wb_gpr,
falu_fpu_ex2_fflags,
falu_fpu_ex2_result,
falu_fpu_ex2_result_vld,
falu_fpu_ex3_fflags,
falu_fpu_ex3_result,
falu_fpu_ex3_result_vld,
falu_fpu_ex3_stall,
falu_fpu_ex3_wb_gpr,
fcnvt_ex1_dp_fflags,
fcnvt_ex1_dp_special_result,
fcnvt_ex1_dp_special_sel,
fcnvt_ex1_dp_special_sign,
fcnvt_ex1_dp_wb_vld,
fcnvt_ex1_pipe_clk,
fcnvt_ex1_pipedown,
fcnvt_ex1_sel,
fcnvt_ex1_sel_dp,
fcnvt_ex2_pipe_clk,
fcnvt_ex2_pipedown,
fcnvt_ex3_dp_fflags,
fcnvt_ex3_dp_rst,
fcnvt_ex3_dp_wb_vld,
fcnvt_ex3_fspu_vld,
fcnvt_ex3_rtu_fflags,
fcnvt_ex3_rtu_rst,
fcnvt_ex3_rtu_wb_vld,
fcnvt_ex3_sel,
forever_cpuclk,
fpu_rtu_ex3_wb_data,
fpu_rtu_ex3_wb_fflags,
fpu_rtu_ex3_wb_fflags_vld,
fpu_rtu_ex3_wb_preg,
fpu_rtu_ex3_wb_vld,
fspu_ex1_dp_fflags,
fspu_ex1_dp_special_result,
fspu_ex1_dp_special_sel,
fspu_ex1_dp_special_sign,
fspu_ex1_dp_wb_vld,
fspu_ex1_rtu_wb_vld,
fspu_ex1_rtu_wb_vld_gate,
fspu_sel,
fspu_sel_dp,
fspu_sel_gate,
idu_fpu_ex1_dst_preg,
idu_fpu_ex1_eu_sel,
idu_fpu_ex1_func,
pad_yy_icg_scan_en,
rtu_fpu_ex3_wb_grant,
rtu_xx_ex1_cancel
);
// &Ports; @23
input cp0_fpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input ctrl_falu_ex1_sel;
input ctrl_falu_ex1_sel_dp;
input ctrl_falu_ex1_sel_gate;
input ctrl_xx_ex1_cmplt_dp;
input ctrl_xx_ex1_inst_vld;
input ctrl_xx_ex1_stall;
input ctrl_xx_ex1_warm_up;
input ctrl_xx_ex2_cancel;
input ctrl_xx_ex2_stall;
input ctrl_xx_ex2_warm_up;
input ctrl_xx_ex3_stall;
input [4 :0] fadd_ex1_dp_fflags;
input [31:0] fadd_ex1_dp_special_result;
input [7 :0] fadd_ex1_dp_special_sel;
input [2 :0] fadd_ex1_dp_special_sign;
input fadd_ex1_dp_wb_vld;
input [4 :0] fadd_ex2_dp_fflags;
input [31:0] fadd_ex2_dp_rst;
input fadd_ex2_dp_wb_vld;
input fadd_ex2_nocmp;
input [4 :0] fadd_ex3_dp_fflags;
input [31:0] fadd_ex3_dp_rst;
input fadd_ex3_dp_wb_vld;
input [4 :0] fadd_ex3_rtu_fflags;
input [31:0] fadd_ex3_rtu_rst;
input fadd_ex3_rtu_wb_vld;
input [4 :0] fcnvt_ex1_dp_fflags;
input [31:0] fcnvt_ex1_dp_special_result;
input [7 :0] fcnvt_ex1_dp_special_sel;
input [2 :0] fcnvt_ex1_dp_special_sign;
input fcnvt_ex1_dp_wb_vld;
input [4 :0] fcnvt_ex3_dp_fflags;
input [31:0] fcnvt_ex3_dp_rst;
input fcnvt_ex3_dp_wb_vld;
input fcnvt_ex3_fspu_vld;
input [4 :0] fcnvt_ex3_rtu_fflags;
input [31:0] fcnvt_ex3_rtu_rst;
input fcnvt_ex3_rtu_wb_vld;
input forever_cpuclk;
input [4 :0] fspu_ex1_dp_fflags;
input [31:0] fspu_ex1_dp_special_result;
input [7 :0] fspu_ex1_dp_special_sel;
input [2 :0] fspu_ex1_dp_special_sign;
input fspu_ex1_dp_wb_vld;
input fspu_ex1_rtu_wb_vld;
input fspu_ex1_rtu_wb_vld_gate;
input [4 :0] idu_fpu_ex1_dst_preg;
input [2 :0] idu_fpu_ex1_eu_sel;
input [9 :0] idu_fpu_ex1_func;
input pad_yy_icg_scan_en;
input rtu_fpu_ex3_wb_grant;
input rtu_xx_ex1_cancel;
output fadd_ex1_pipe_clk;
output fadd_ex1_pipedown;
output fadd_ex1_sel;
output fadd_ex1_sel_dp;
output fadd_ex2_nocmp_pipe_clk;
output fadd_ex2_nocmp_pipedown;
output fadd_ex2_pipe_clk;
output fadd_ex2_pipedown;
output fadd_ex2_sel;
output fadd_ex3_sel;
output falu_ctrl_xx_ex1_vld;
output falu_ctrl_xx_ex2_vld;
output falu_ctrl_xx_ex3_vld;
output falu_fpu_ex1_cmplt;
output falu_fpu_ex1_cmplt_dp;
output [4 :0] falu_fpu_ex1_fflags;
output [31:0] falu_fpu_ex1_result;
output [8 :0] falu_fpu_ex1_special_sel;
output [3 :0] falu_fpu_ex1_special_sign;
output falu_fpu_ex1_wb_gpr;
output [4 :0] falu_fpu_ex2_fflags;
output [31:0] falu_fpu_ex2_result;
output falu_fpu_ex2_result_vld;
output [4 :0] falu_fpu_ex3_fflags;
output [31:0] falu_fpu_ex3_result;
output falu_fpu_ex3_result_vld;
output falu_fpu_ex3_stall;
output falu_fpu_ex3_wb_gpr;
output fcnvt_ex1_pipe_clk;
output fcnvt_ex1_pipedown;
output fcnvt_ex1_sel;
output fcnvt_ex1_sel_dp;
output fcnvt_ex2_pipe_clk;
output fcnvt_ex2_pipedown;
output fcnvt_ex3_sel;
output [31:0] fpu_rtu_ex3_wb_data;
output [4 :0] fpu_rtu_ex3_wb_fflags;
output fpu_rtu_ex3_wb_fflags_vld;
output [4 :0] fpu_rtu_ex3_wb_preg;
output fpu_rtu_ex3_wb_vld;
output fspu_sel;
output fspu_sel_dp;
output fspu_sel_gate;
// &Regs; @24
reg ctrl_xx_ex2_vld;
reg ctrl_xx_ex3_vld;
reg fadd_ex2_sel;
reg fadd_ex3_sel;
reg [4 :0] falu_preg_ex2;
reg [4 :0] falu_preg_ex3;
reg fcnvt_ex2_sel;
reg fcnvt_ex3_sel;
// &Wires; @25
wire cp0_fpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire ctrl_falu_ex1_sel;
wire ctrl_falu_ex1_sel_dp;
wire ctrl_falu_ex1_sel_gate;
wire ctrl_xx_ex1_cmplt_dp;
wire ctrl_xx_ex1_inst_vld;
wire ctrl_xx_ex1_stall;
wire ctrl_xx_ex1_warm_up;
wire ctrl_xx_ex2_cancel;
wire ctrl_xx_ex2_stall;
wire ctrl_xx_ex2_warm_up;
wire ctrl_xx_ex3_stall;
wire [4 :0] fadd_ex1_dp_fflags;
wire [31:0] fadd_ex1_dp_special_result;
wire [7 :0] fadd_ex1_dp_special_sel;
wire [2 :0] fadd_ex1_dp_special_sign;
wire fadd_ex1_dp_wb_vld;
wire fadd_ex1_pipe_clk;
wire fadd_ex1_pipedown;
wire fadd_ex1_pipedown_gate;
wire fadd_ex1_sel;
wire fadd_ex1_sel_dp;
wire fadd_ex1_sel_gate;
wire [4 :0] fadd_ex2_dp_fflags;
wire [31:0] fadd_ex2_dp_rst;
wire fadd_ex2_dp_wb_vld;
wire fadd_ex2_nocmp;
wire fadd_ex2_nocmp_pipe_clk;
wire fadd_ex2_nocmp_pipedown;
wire fadd_ex2_pipe_clk;
wire fadd_ex2_pipedown;
wire [4 :0] fadd_ex3_dp_fflags;
wire [31:0] fadd_ex3_dp_rst;
wire fadd_ex3_dp_wb_vld;
wire [4 :0] fadd_ex3_rtu_fflags;
wire [31:0] fadd_ex3_rtu_rst;
wire fadd_ex3_rtu_wb_vld;
wire falu_ctrl_ex1_pipe_clk;
wire falu_ctrl_ex1_pipedown_clk_en;
wire falu_ctrl_ex2_pipe_clk;
wire falu_ctrl_ex2_pipedown_clk_en;
wire falu_ctrl_xx_ex1_vld;
wire falu_ctrl_xx_ex2_vld;
wire falu_ctrl_xx_ex3_vld;
wire falu_ex1_wb_vld;
wire [4 :0] falu_ex2_preg_dest;
wire falu_ex2_wb_vld;
wire [4 :0] falu_ex3_preg_dest;
wire falu_fpu_ex1_cmplt;
wire falu_fpu_ex1_cmplt_dp;
wire [4 :0] falu_fpu_ex1_fflags;
wire [31:0] falu_fpu_ex1_result;
wire [8 :0] falu_fpu_ex1_special_sel;
wire [7 :0] falu_fpu_ex1_special_sel_t;
wire [3 :0] falu_fpu_ex1_special_sign;
wire [2 :0] falu_fpu_ex1_special_sign_t;
wire falu_fpu_ex1_wb_gpr;
wire [4 :0] falu_fpu_ex2_fflags;
wire [31:0] falu_fpu_ex2_result;
wire falu_fpu_ex2_result_vld;
wire [4 :0] falu_fpu_ex3_fflags;
wire [31:0] falu_fpu_ex3_result;
wire falu_fpu_ex3_result_vld;
wire falu_fpu_ex3_stall;
wire falu_fpu_ex3_wb_gpr;
wire falu_inst_ex1_raw;
wire falu_inst_ex2_raw;
wire falu_inst_vld_ex1_pipedown;
wire falu_inst_vld_ex1_pipedown_gate;
wire falu_inst_vld_ex2_pipedown;
wire falu_preg_ex1_pipedown;
wire falu_preg_ex2_pipedown;
wire falu_sel;
wire [4 :0] fcnvt_ex1_dp_fflags;
wire [31:0] fcnvt_ex1_dp_special_result;
wire [7 :0] fcnvt_ex1_dp_special_sel;
wire [2 :0] fcnvt_ex1_dp_special_sign;
wire fcnvt_ex1_dp_wb_vld;
wire fcnvt_ex1_pipe_clk;
wire fcnvt_ex1_pipedown;
wire fcnvt_ex1_pipedown_gate;
wire fcnvt_ex1_sel;
wire fcnvt_ex1_sel_dp;
wire fcnvt_ex1_sel_gate;
wire fcnvt_ex2_pipe_clk;
wire fcnvt_ex2_pipedown;
wire [4 :0] fcnvt_ex3_dp_fflags;
wire [31:0] fcnvt_ex3_dp_rst;
wire fcnvt_ex3_dp_wb_vld;
wire fcnvt_ex3_fspu_vld;
wire [4 :0] fcnvt_ex3_rtu_fflags;
wire [31:0] fcnvt_ex3_rtu_rst;
wire fcnvt_ex3_rtu_wb_vld;
wire forever_cpuclk;
wire fpu_rtu_ex1_wb_vld;
wire [31:0] fpu_rtu_ex3_wb_data;
wire [4 :0] fpu_rtu_ex3_wb_fflags;
wire fpu_rtu_ex3_wb_fflags_vld;
wire [4 :0] fpu_rtu_ex3_wb_preg;
wire fpu_rtu_ex3_wb_vld;
wire [4 :0] fspu_ex1_dp_fflags;
wire [31:0] fspu_ex1_dp_special_result;
wire [7 :0] fspu_ex1_dp_special_sel;
wire [2 :0] fspu_ex1_dp_special_sign;
wire fspu_ex1_dp_wb_vld;
wire fspu_ex1_rtu_wb_vld;
wire fspu_ex1_rtu_wb_vld_gate;
wire fspu_sel;
wire fspu_sel_dp;
wire fspu_sel_gate;
wire [4 :0] idu_fpu_ex1_dst_preg;
wire [2 :0] idu_fpu_ex1_eu_sel;
wire [9 :0] idu_fpu_ex1_func;
wire pad_yy_icg_scan_en;
wire rtu_fpu_ex3_wb_grant;
wire rtu_xx_ex1_cancel;
wire sel_ex1_pipedown;
wire sel_ex2_pipedown;
// &Force("bus", "idu_fpu_ex1_func", 9, 0); @27
// &Force("output", "fadd_ex1_pipedown"); @28
// &Force("output", "fadd_ex2_pipedown"); @29
// &Force("output", "fcnvt_ex1_pipedown"); @30
// &Force("output", "fcnvt_ex2_pipedown"); @31
// &Force("output", "fadd_ex2_nocmp_pipedown"); @32
// &Force("output", "fpu_rtu_ex3_wb_vld"); @33
// &Force("output", "fadd_ex2_sel"); @34
// &Force("output", "fcnvt_ex3_sel"); @35
// &Force("output", "fadd_ex3_sel"); @36
// &Force("output", "fcnvt_ex1_sel"); @37
// &Force("output", "fadd_ex1_sel"); @38
// &Force("output", "falu_ctrl_xx_ex1_vld"); @39
// &Force("output", "falu_ctrl_xx_ex2_vld"); @40
// &Force("output", "falu_ctrl_xx_ex3_vld"); @41
//==============================================================================
// Ctrl For FALU Pipedown:
//==============================================================================
//------------------------------------------------------------------------------
// fadd pipedown ctrl:
//------------------------------------------------------------------------------
assign falu_sel = ctrl_falu_ex1_sel;
assign fadd_ex1_pipedown = fadd_ex1_sel && falu_inst_ex1_raw && !ctrl_xx_ex2_stall || ctrl_xx_ex1_warm_up;
assign fadd_ex1_pipedown_gate = fadd_ex1_sel_gate && !ctrl_xx_ex2_stall || ctrl_xx_ex1_warm_up;
assign fadd_ex2_pipedown = fadd_ex2_sel && falu_inst_ex2_raw && !ctrl_xx_ex3_stall || ctrl_xx_ex2_warm_up;
// &Instance("gated_clk_cell", "x_fadd_ex1_pipe_clk"); @53
gated_clk_cell x_fadd_ex1_pipe_clk (
.clk_in (forever_cpuclk ),
.clk_out (fadd_ex1_pipe_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (fadd_ex1_pipedown_gate),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk ), @54
// .external_en (1'b0 ), @55
// .global_en (cp0_yy_clk_en ), @56
// .module_en (cp0_fpu_icg_en ), @57
// .local_en (fadd_ex1_pipedown_gate ), @58
// .clk_out (fadd_ex1_pipe_clk )); @59
// &Instance("gated_clk_cell", "x_fadd_ex2_pipe_clk"); @62
gated_clk_cell x_fadd_ex2_pipe_clk (
.clk_in (forever_cpuclk ),
.clk_out (fadd_ex2_pipe_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (fadd_ex2_pipedown ),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @63
// .external_en (1'b0 ), @64
// .global_en (cp0_yy_clk_en ), @65
// .module_en (cp0_fpu_icg_en ), @66
// .local_en (fadd_ex2_pipedown ), @67
// .clk_out (fadd_ex2_pipe_clk )); @68
// when fadd ex2 is not fle/flt/feq
assign fadd_ex2_nocmp_pipedown = fadd_ex2_sel && falu_inst_ex2_raw && !ctrl_xx_ex3_stall && fadd_ex2_nocmp || ctrl_xx_ex2_warm_up;
// &Instance("gated_clk_cell", "x_fadd_ex1_nocmp_pipe_clk"); @73
gated_clk_cell x_fadd_ex1_nocmp_pipe_clk (
.clk_in (forever_cpuclk ),
.clk_out (fadd_ex2_nocmp_pipe_clk),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (fadd_ex2_nocmp_pipedown),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk ), @74
// .external_en (1'b0 ), @75
// .global_en (cp0_yy_clk_en ), @76
// .module_en (cp0_fpu_icg_en ), @77
// .local_en (fadd_ex2_nocmp_pipedown ), @78
// .clk_out (fadd_ex2_nocmp_pipe_clk )); @79
//------------------------------------------------------------------------------
// fcnvt pipedown ctrl:
//------------------------------------------------------------------------------
assign fcnvt_ex1_pipedown = (fspu_ex1_rtu_wb_vld || fcnvt_ex1_sel && falu_inst_ex1_raw) && !ctrl_xx_ex2_stall || ctrl_xx_ex1_warm_up ;
assign fcnvt_ex1_pipedown_gate = (fspu_ex1_rtu_wb_vld_gate || fcnvt_ex1_sel_gate) && !ctrl_xx_ex2_stall || ctrl_xx_ex1_warm_up ;
assign fcnvt_ex2_pipedown = fcnvt_ex2_sel && falu_inst_ex2_raw && !ctrl_xx_ex3_stall || ctrl_xx_ex2_warm_up;
// &Instance("gated_clk_cell", "x_fcnvt_ex1_pipe_clk"); @89
gated_clk_cell x_fcnvt_ex1_pipe_clk (
.clk_in (forever_cpuclk ),
.clk_out (fcnvt_ex1_pipe_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (fcnvt_ex1_pipedown_gate),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk ), @90
// .external_en (1'b0 ), @91
// .global_en (cp0_yy_clk_en ), @92
// .module_en (cp0_fpu_icg_en ), @93
// .local_en (fcnvt_ex1_pipedown_gate ), @94
// .clk_out (fcnvt_ex1_pipe_clk )); @95
// &Instance("gated_clk_cell", "x_fcnvt_ex2_pipe_clk"); @97
gated_clk_cell x_fcnvt_ex2_pipe_clk (
.clk_in (forever_cpuclk ),
.clk_out (fcnvt_ex2_pipe_clk),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (fcnvt_ex2_pipedown),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @98
// .external_en (1'b0 ), @99
// .global_en (cp0_yy_clk_en ), @100
// .module_en (cp0_fpu_icg_en ), @101
// .local_en (fcnvt_ex2_pipedown ), @102
// .clk_out (fcnvt_ex2_pipe_clk )); @103
//assign fspu_ex1_pipedown = fspu_sel && falu_inst_ex1_raw && !ctrl_xx_ex2_stall || ctrl_xx_ex1_warm_up;
//assign fspu_ex2_pipedown = fcnvt_ex2_sel && falu_inst_ex2_raw && !ctrl_xx_ex3_stall || ctrl_xx_ex2_warm_up;
assign falu_preg_ex1_pipedown = fadd_ex1_pipedown || fcnvt_ex1_pipedown;
assign falu_preg_ex2_pipedown = fadd_ex2_pipedown || fcnvt_ex2_pipedown;
//------------------------------------------------------------------------------
// FALU EX1 Interface with RTU:
//------------------------------------------------------------------------------
//assign fpu_rtu_ex1_wb_vld = fadd_ex1_rtu_wb_vld || fcnvt_ex1_rtu_wb_vld || fspu_ex1_rtu_wb_vld;
//assign fpu_rtu_ex1_wb_data[31:0] = {32{fadd_ex1_rtu_wb_vld}} & fadd_ex1_rtu_rst[31:0] |
// {32{fcnvt_ex1_rtu_wb_vld}} & fcnvt_ex1_rtu_rst[31:0] |
// {32{fspu_ex1_rtu_wb_vld}} & fspu_ex1_rtu_rst[31:0];
// here the spu value will borrow the fcnvt ftoi path
//assign fpu_rtu_ex1_fflags_updt = fadd_ex1_rtu_wb_vld || fcnvt_ex1_rtu_wb_vld;
//assign fpu_rtu_ex1_wb_fflags[4:0] = {5{fadd_ex1_rtu_wb_vld}} & fadd_ex1_rtu_fflags[4:0] |
// {5{fcnvt_ex1_rtu_wb_vld}} & fcnvt_ex1_rtu_fflags[4:0] |
// {5{fspu_ex1_rtu_wb_vld}} & fspu_ex1_rtu_fflags[4:0];
//assign fpu_rtu_ex1_wb_preg[4:0] = idu_fpu_ex1_dst_preg[4:0];
assign fpu_rtu_ex1_wb_vld = 1'b0;
//------------------------------------------------------------------------------
// FALU EX3 Interface with RTU:
//------------------------------------------------------------------------------
assign fpu_rtu_ex3_wb_vld = fadd_ex3_rtu_wb_vld || fcnvt_ex3_rtu_wb_vld;
assign fpu_rtu_ex3_wb_fflags_vld = fadd_ex3_rtu_wb_vld || (fcnvt_ex3_rtu_wb_vld && ~fcnvt_ex3_fspu_vld);
assign fpu_rtu_ex3_wb_data[31:0] = {32{fadd_ex3_rtu_wb_vld}} & fadd_ex3_rtu_rst[31:0] |
{32{fcnvt_ex3_rtu_wb_vld}} & fcnvt_ex3_rtu_rst[31:0];
assign fpu_rtu_ex3_wb_fflags[4:0] = {5{fadd_ex3_rtu_wb_vld}} & fadd_ex3_rtu_fflags[4:0] |
{5{fcnvt_ex3_rtu_wb_vld}} & fcnvt_ex3_rtu_fflags[4:0];
assign fpu_rtu_ex3_wb_preg[4:0] = falu_ex3_preg_dest[4:0];
//------------------------------------------------------------------------------
// FALU EX1 Interface with FPU:
//------------------------------------------------------------------------------
assign falu_fpu_ex1_special_sel_t[7:0] = {8{fadd_ex1_dp_wb_vld}} & fadd_ex1_dp_special_sel[7:0] |
{8{fcnvt_ex1_dp_wb_vld}} & fcnvt_ex1_dp_special_sel[7:0] |
{8{fspu_ex1_dp_wb_vld}} & fspu_ex1_dp_special_sel[7:0];
assign falu_fpu_ex1_special_sel[8:0] = {falu_fpu_ex1_special_sel_t[7:3], 1'b0, falu_fpu_ex1_special_sel_t[2:0]};
assign falu_fpu_ex1_special_sign_t[2:0] = {3{fadd_ex1_dp_wb_vld}} & fadd_ex1_dp_special_sign[2:0] |
{3{fcnvt_ex1_dp_wb_vld}} & fcnvt_ex1_dp_special_sign[2:0] |
{3{fspu_ex1_dp_wb_vld}} & fspu_ex1_dp_special_sign[2:0];
assign falu_fpu_ex1_special_sign[3:0] = {1'b0, falu_fpu_ex1_special_sign_t[2:0]};
assign falu_fpu_ex1_fflags[4:0] = {5{fadd_ex1_dp_wb_vld}} & fadd_ex1_dp_fflags[4:0] |
{5{fcnvt_ex1_dp_wb_vld}} & fcnvt_ex1_dp_fflags[4:0] |
{5{fspu_ex1_dp_wb_vld}} & fspu_ex1_dp_fflags[4:0];
assign falu_fpu_ex1_wb_gpr = 1'b0;
assign falu_fpu_ex1_cmplt = ctrl_xx_ex1_inst_vld && falu_sel;
assign falu_fpu_ex1_cmplt_dp = ctrl_xx_ex1_cmplt_dp && idu_fpu_ex1_eu_sel[0];
// &Force("bus","idu_fpu_ex1_eu_sel",2,0); @160
//------------------------------------------------------------------------------
// FALU EX2 Interface with FPU:
//------------------------------------------------------------------------------
assign falu_fpu_ex2_result_vld = fadd_ex2_dp_wb_vld;
assign falu_fpu_ex2_fflags[4:0] = fadd_ex2_dp_fflags[4:0];
//------------------------------------------------------------------------------
// FALU EX3 Interface with FPU:
//------------------------------------------------------------------------------
assign falu_fpu_ex3_result_vld = fadd_ex3_dp_wb_vld || fcnvt_ex3_dp_wb_vld;
assign falu_fpu_ex3_fflags[4:0] = fadd_ex3_dp_wb_vld ? fadd_ex3_dp_fflags[4:0] : fcnvt_ex3_dp_fflags[4:0];
assign falu_fpu_ex3_wb_gpr = fadd_ex3_rtu_wb_vld || fcnvt_ex3_rtu_wb_vld;
assign falu_fpu_ex3_stall = fpu_rtu_ex3_wb_vld && !rtu_fpu_ex3_wb_grant;
//------------------------------------------------------------------------------
// FALU Data Path Interface with FPU:
//------------------------------------------------------------------------------
assign falu_fpu_ex1_result[31:0] = {32{fadd_ex1_dp_wb_vld}} & fadd_ex1_dp_special_result[31:0] |
{32{fcnvt_ex1_dp_wb_vld}} & fcnvt_ex1_dp_special_result[31:0] |
{32{fspu_ex1_dp_wb_vld}} & fspu_ex1_dp_special_result[31:0];
assign falu_fpu_ex2_result[31:0] = fadd_ex2_dp_rst[31:0];
assign falu_fpu_ex3_result[31:0] = fadd_ex3_dp_wb_vld ? fadd_ex3_dp_rst[31:0] : fcnvt_ex3_dp_rst[31:0];
//------------------------------------------------------------------------------
// ctrl for inst_vld and sel signals:
//------------------------------------------------------------------------------
assign fadd_ex1_sel = ctrl_falu_ex1_sel && idu_fpu_ex1_func[0];
assign fadd_ex1_sel_gate = ctrl_falu_ex1_sel_gate && idu_fpu_ex1_func[0];
assign fcnvt_ex1_sel = ctrl_falu_ex1_sel && idu_fpu_ex1_func[1];
assign fcnvt_ex1_sel_gate= ctrl_falu_ex1_sel_gate && idu_fpu_ex1_func[1];
assign fspu_sel = ctrl_falu_ex1_sel && idu_fpu_ex1_func[2];
assign fspu_sel_gate = ctrl_falu_ex1_sel_gate && idu_fpu_ex1_func[2];
assign fadd_ex1_sel_dp = ctrl_falu_ex1_sel_dp && idu_fpu_ex1_func[0];
assign fcnvt_ex1_sel_dp = ctrl_falu_ex1_sel_dp && idu_fpu_ex1_func[1];
assign fspu_sel_dp = ctrl_falu_ex1_sel_dp && idu_fpu_ex1_func[2];
// &Force("output","fspu_sel"); @215
assign sel_ex1_pipedown = ctrl_falu_ex1_sel && !falu_ex1_wb_vld && !ctrl_xx_ex2_stall || ctrl_xx_ex1_warm_up;
assign sel_ex2_pipedown = fadd_ex2_pipedown || fcnvt_ex2_pipedown;
assign falu_ex1_wb_vld = fadd_ex1_dp_wb_vld || fpu_rtu_ex1_wb_vld || fcnvt_ex1_dp_wb_vld || fspu_sel & ~fspu_ex1_rtu_wb_vld;
assign falu_ex2_wb_vld = fadd_ex2_dp_wb_vld;
assign falu_inst_ex1_raw = falu_ctrl_xx_ex1_vld && !falu_ex1_wb_vld;
assign falu_inst_ex2_raw = falu_ctrl_xx_ex2_vld && !falu_ex2_wb_vld;
assign falu_inst_vld_ex1_pipedown = !ctrl_xx_ex2_stall && (falu_inst_ex1_raw || falu_ctrl_xx_ex2_vld || fspu_ex1_rtu_wb_vld);
assign falu_inst_vld_ex1_pipedown_gate = !ctrl_xx_ex2_stall && (ctrl_falu_ex1_sel_gate || falu_ctrl_xx_ex2_vld || fspu_ex1_rtu_wb_vld_gate);
assign falu_inst_vld_ex2_pipedown = !ctrl_xx_ex3_stall && (falu_inst_ex2_raw || falu_ctrl_xx_ex3_vld);
assign falu_ctrl_ex1_pipedown_clk_en = falu_inst_vld_ex1_pipedown_gate || ctrl_xx_ex1_warm_up;
assign falu_ctrl_ex2_pipedown_clk_en = falu_inst_vld_ex2_pipedown || ctrl_xx_ex2_warm_up;
// &Instance("gated_clk_cell", "x_falu_ctrl_ex1_pipe_clk"); @231
gated_clk_cell x_falu_ctrl_ex1_pipe_clk (
.clk_in (forever_cpuclk ),
.clk_out (falu_ctrl_ex1_pipe_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (falu_ctrl_ex1_pipedown_clk_en),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk ), @232
// .external_en (1'b0 ), @233
// .global_en (cp0_yy_clk_en ), @234
// .module_en (cp0_fpu_icg_en ), @235
// .local_en (falu_ctrl_ex1_pipedown_clk_en ), @236
// .clk_out (falu_ctrl_ex1_pipe_clk ) @237
// ); @238
// &Instance("gated_clk_cell", "x_falu_ctrl_ex2_pipe_clk"); @240
gated_clk_cell x_falu_ctrl_ex2_pipe_clk (
.clk_in (forever_cpuclk ),
.clk_out (falu_ctrl_ex2_pipe_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (falu_ctrl_ex2_pipedown_clk_en),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk ), @241
// .external_en (1'b0 ), @242
// .global_en (cp0_yy_clk_en ), @243
// .module_en (cp0_fpu_icg_en ), @244
// .local_en (falu_ctrl_ex2_pipedown_clk_en ), @245
// .clk_out (falu_ctrl_ex2_pipe_clk ) @246
// ); @247
//------------------------------------------------------------------------------
// sel signals pipedown:
//------------------------------------------------------------------------------
always @(posedge falu_ctrl_ex1_pipe_clk)
begin
if(sel_ex1_pipedown) begin
fcnvt_ex2_sel <= fcnvt_ex1_sel || fspu_ex1_rtu_wb_vld;
fadd_ex2_sel <= fadd_ex1_sel;
end
end
always @(posedge falu_ctrl_ex2_pipe_clk)
begin
if(sel_ex2_pipedown) begin
fcnvt_ex3_sel <= fcnvt_ex2_sel;
fadd_ex3_sel <= fadd_ex2_sel;
end
end
//------------------------------------------------------------------------------
// inst_vld signals pipedown:
//------------------------------------------------------------------------------
always @(posedge falu_ctrl_ex1_pipe_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ctrl_xx_ex2_vld <= 1'b0;
else if(falu_inst_vld_ex1_pipedown)
ctrl_xx_ex2_vld <= falu_inst_ex1_raw && !ctrl_xx_ex1_stall && !rtu_xx_ex1_cancel;
end
always @(posedge falu_ctrl_ex2_pipe_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ctrl_xx_ex3_vld <= 1'b0;
else if(falu_inst_vld_ex2_pipedown)
ctrl_xx_ex3_vld <= falu_inst_ex2_raw && !ctrl_xx_ex2_cancel;
end
//------------------------------------------------------------------------------
// preg pipedown:
//------------------------------------------------------------------------------
assign falu_ex2_preg_dest[4:0] = falu_preg_ex2[4:0];
assign falu_ex3_preg_dest[4:0] = falu_preg_ex3[4:0];
always @(posedge falu_ctrl_ex1_pipe_clk)
begin
if(falu_preg_ex1_pipedown) begin
falu_preg_ex2[4:0] <= idu_fpu_ex1_dst_preg[4:0];
end
end
always @(posedge falu_ctrl_ex2_pipe_clk)
begin
if(falu_preg_ex2_pipedown) begin
falu_preg_ex3[4:0] <= falu_ex2_preg_dest[4:0];
end
end
//------------------------------------------------------------------------------
// Rename for output:
//------------------------------------------------------------------------------
assign falu_ctrl_xx_ex1_vld = ctrl_falu_ex1_sel;
assign falu_ctrl_xx_ex2_vld = ctrl_xx_ex2_vld;
assign falu_ctrl_xx_ex3_vld = ctrl_xx_ex3_vld;
// &ModuleEnd; @370
endmodule

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opene906/E906_RTL_FACTORY/gen_rtl/falu/rtl/pa_falu_top.v Normal file
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_falu_top(
cp0_fpu_icg_en,
cp0_fpu_xx_dqnan,
cp0_yy_clk_en,
cpurst_b,
ctrl_falu_ex1_sel,
ctrl_falu_ex1_sel_dp,
ctrl_falu_ex1_sel_gate,
ctrl_xx_ex1_cmplt_dp,
ctrl_xx_ex1_inst_vld,
ctrl_xx_ex1_stall,
ctrl_xx_ex1_warm_up,
ctrl_xx_ex2_cancel,
ctrl_xx_ex2_stall,
ctrl_xx_ex2_warm_up,
ctrl_xx_ex3_stall,
dp_xx_ex1_cnan,
dp_xx_ex1_id,
dp_xx_ex1_inf,
dp_xx_ex1_norm,
dp_xx_ex1_qnan,
dp_xx_ex1_rm,
dp_xx_ex1_snan,
dp_xx_ex1_zero,
dp_xx_ex2_rm,
dp_xx_ex2_srcf2,
dp_xx_ex3_rm,
falu_fpu_ex1_cmplt,
falu_fpu_ex1_cmplt_dp,
falu_fpu_ex1_fflags,
falu_fpu_ex1_result,
falu_fpu_ex1_special_sel,
falu_fpu_ex1_special_sign,
falu_fpu_ex1_src_reuse,
falu_fpu_ex1_src_reuse_data,
falu_fpu_ex1_wb_gpr,
falu_fpu_ex2_fflags,
falu_fpu_ex2_result,
falu_fpu_ex2_result_vld,
falu_fpu_ex3_fflags,
falu_fpu_ex3_result,
falu_fpu_ex3_result_vld,
falu_fpu_ex3_stall,
falu_fpu_ex3_wb_gpr,
forever_cpuclk,
fpu_rtu_ex3_wb_data,
fpu_rtu_ex3_wb_fflags,
fpu_rtu_ex3_wb_fflags_vld,
fpu_rtu_ex3_wb_preg,
fpu_rtu_ex3_wb_vld,
idu_fpu_ex1_dst_preg,
idu_fpu_ex1_eu_sel,
idu_fpu_ex1_func,
idu_fpu_ex1_srcf0,
idu_fpu_ex1_srcf1,
idu_fpu_ex1_srci,
pad_yy_icg_scan_en,
rtu_fpu_ex3_wb_grant,
rtu_xx_ex1_cancel
);
// &Ports; @24
input cp0_fpu_icg_en;
input cp0_fpu_xx_dqnan;
input cp0_yy_clk_en;
input cpurst_b;
input ctrl_falu_ex1_sel;
input ctrl_falu_ex1_sel_dp;
input ctrl_falu_ex1_sel_gate;
input ctrl_xx_ex1_cmplt_dp;
input ctrl_xx_ex1_inst_vld;
input ctrl_xx_ex1_stall;
input ctrl_xx_ex1_warm_up;
input ctrl_xx_ex2_cancel;
input ctrl_xx_ex2_stall;
input ctrl_xx_ex2_warm_up;
input ctrl_xx_ex3_stall;
input [2 :0] dp_xx_ex1_cnan;
input [2 :0] dp_xx_ex1_id;
input [2 :0] dp_xx_ex1_inf;
input [2 :0] dp_xx_ex1_norm;
input [2 :0] dp_xx_ex1_qnan;
input [2 :0] dp_xx_ex1_rm;
input [2 :0] dp_xx_ex1_snan;
input [2 :0] dp_xx_ex1_zero;
input [2 :0] dp_xx_ex2_rm;
input [31:0] dp_xx_ex2_srcf2;
input [2 :0] dp_xx_ex3_rm;
input forever_cpuclk;
input [4 :0] idu_fpu_ex1_dst_preg;
input [2 :0] idu_fpu_ex1_eu_sel;
input [9 :0] idu_fpu_ex1_func;
input [31:0] idu_fpu_ex1_srcf0;
input [31:0] idu_fpu_ex1_srcf1;
input [31:0] idu_fpu_ex1_srci;
input pad_yy_icg_scan_en;
input rtu_fpu_ex3_wb_grant;
input rtu_xx_ex1_cancel;
output falu_fpu_ex1_cmplt;
output falu_fpu_ex1_cmplt_dp;
output [4 :0] falu_fpu_ex1_fflags;
output [31:0] falu_fpu_ex1_result;
output [8 :0] falu_fpu_ex1_special_sel;
output [3 :0] falu_fpu_ex1_special_sign;
output falu_fpu_ex1_src_reuse;
output [31:0] falu_fpu_ex1_src_reuse_data;
output falu_fpu_ex1_wb_gpr;
output [4 :0] falu_fpu_ex2_fflags;
output [31:0] falu_fpu_ex2_result;
output falu_fpu_ex2_result_vld;
output [4 :0] falu_fpu_ex3_fflags;
output [31:0] falu_fpu_ex3_result;
output falu_fpu_ex3_result_vld;
output falu_fpu_ex3_stall;
output falu_fpu_ex3_wb_gpr;
output [31:0] fpu_rtu_ex3_wb_data;
output [4 :0] fpu_rtu_ex3_wb_fflags;
output fpu_rtu_ex3_wb_fflags_vld;
output [4 :0] fpu_rtu_ex3_wb_preg;
output fpu_rtu_ex3_wb_vld;
// &Regs; @25
// &Wires; @26
wire cp0_fpu_icg_en;
wire cp0_fpu_xx_dqnan;
wire cp0_yy_clk_en;
wire cpurst_b;
wire ctrl_falu_ex1_sel;
wire ctrl_falu_ex1_sel_dp;
wire ctrl_falu_ex1_sel_gate;
wire ctrl_xx_ex1_cmplt_dp;
wire ctrl_xx_ex1_inst_vld;
wire ctrl_xx_ex1_stall;
wire ctrl_xx_ex1_warm_up;
wire ctrl_xx_ex2_cancel;
wire ctrl_xx_ex2_stall;
wire ctrl_xx_ex2_warm_up;
wire ctrl_xx_ex3_stall;
wire [2 :0] dp_xx_ex1_cnan;
wire [2 :0] dp_xx_ex1_id;
wire [2 :0] dp_xx_ex1_inf;
wire [2 :0] dp_xx_ex1_norm;
wire [2 :0] dp_xx_ex1_qnan;
wire [2 :0] dp_xx_ex1_rm;
wire [2 :0] dp_xx_ex1_snan;
wire [2 :0] dp_xx_ex1_zero;
wire [2 :0] dp_xx_ex2_rm;
wire [31:0] dp_xx_ex2_srcf2;
wire [2 :0] dp_xx_ex3_rm;
wire [4 :0] fadd_ex1_dp_fflags;
wire [31:0] fadd_ex1_dp_special_result;
wire [7 :0] fadd_ex1_dp_special_sel;
wire [2 :0] fadd_ex1_dp_special_sign;
wire fadd_ex1_dp_wb_vld;
wire fadd_ex1_pipe_clk;
wire fadd_ex1_pipedown;
wire fadd_ex1_sel;
wire fadd_ex1_sel_dp;
wire [4 :0] fadd_ex2_dp_fflags;
wire [31:0] fadd_ex2_dp_rst;
wire fadd_ex2_dp_wb_vld;
wire fadd_ex2_nocmp;
wire fadd_ex2_nocmp_pipe_clk;
wire fadd_ex2_nocmp_pipedown;
wire fadd_ex2_pipe_clk;
wire fadd_ex2_pipedown;
wire fadd_ex2_sel;
wire [4 :0] fadd_ex3_dp_fflags;
wire [31:0] fadd_ex3_dp_rst;
wire fadd_ex3_dp_wb_vld;
wire [4 :0] fadd_ex3_rtu_fflags;
wire [31:0] fadd_ex3_rtu_rst;
wire fadd_ex3_rtu_wb_vld;
wire fadd_ex3_sel;
wire falu_ctrl_xx_ex1_vld;
wire falu_ctrl_xx_ex2_vld;
wire falu_ctrl_xx_ex3_vld;
wire falu_fpu_ex1_cmplt;
wire falu_fpu_ex1_cmplt_dp;
wire [4 :0] falu_fpu_ex1_fflags;
wire [31:0] falu_fpu_ex1_result;
wire [8 :0] falu_fpu_ex1_special_sel;
wire [3 :0] falu_fpu_ex1_special_sign;
wire falu_fpu_ex1_src_reuse;
wire [31:0] falu_fpu_ex1_src_reuse_data;
wire falu_fpu_ex1_wb_gpr;
wire [4 :0] falu_fpu_ex2_fflags;
wire [31:0] falu_fpu_ex2_result;
wire falu_fpu_ex2_result_vld;
wire [4 :0] falu_fpu_ex3_fflags;
wire [31:0] falu_fpu_ex3_result;
wire falu_fpu_ex3_result_vld;
wire falu_fpu_ex3_stall;
wire falu_fpu_ex3_wb_gpr;
wire [4 :0] fcnvt_ex1_dp_fflags;
wire [31:0] fcnvt_ex1_dp_special_result;
wire [7 :0] fcnvt_ex1_dp_special_sel;
wire [2 :0] fcnvt_ex1_dp_special_sign;
wire fcnvt_ex1_dp_wb_vld;
wire fcnvt_ex1_pipe_clk;
wire fcnvt_ex1_pipedown;
wire fcnvt_ex1_sel;
wire fcnvt_ex1_sel_dp;
wire fcnvt_ex2_pipe_clk;
wire fcnvt_ex2_pipedown;
wire [4 :0] fcnvt_ex3_dp_fflags;
wire [31:0] fcnvt_ex3_dp_rst;
wire fcnvt_ex3_dp_wb_vld;
wire fcnvt_ex3_fspu_vld;
wire [4 :0] fcnvt_ex3_rtu_fflags;
wire [31:0] fcnvt_ex3_rtu_rst;
wire fcnvt_ex3_rtu_wb_vld;
wire fcnvt_ex3_sel;
wire forever_cpuclk;
wire [31:0] fpu_rtu_ex3_wb_data;
wire [4 :0] fpu_rtu_ex3_wb_fflags;
wire fpu_rtu_ex3_wb_fflags_vld;
wire [4 :0] fpu_rtu_ex3_wb_preg;
wire fpu_rtu_ex3_wb_vld;
wire [4 :0] fspu_ex1_dp_fflags;
wire [31:0] fspu_ex1_dp_special_result;
wire [7 :0] fspu_ex1_dp_special_sel;
wire [2 :0] fspu_ex1_dp_special_sign;
wire fspu_ex1_dp_wb_vld;
wire [31:0] fspu_ex1_rtu_rst;
wire fspu_ex1_rtu_wb_vld;
wire fspu_ex1_rtu_wb_vld_gate;
wire fspu_sel;
wire fspu_sel_dp;
wire fspu_sel_gate;
wire [4 :0] idu_fpu_ex1_dst_preg;
wire [2 :0] idu_fpu_ex1_eu_sel;
wire [9 :0] idu_fpu_ex1_func;
wire [31:0] idu_fpu_ex1_srcf0;
wire [31:0] idu_fpu_ex1_srcf1;
wire [31:0] idu_fpu_ex1_srci;
wire pad_yy_icg_scan_en;
wire rtu_fpu_ex3_wb_grant;
wire rtu_xx_ex1_cancel;
// &Instance("pa_fcnvt_double"); @30
// &Instance("pa_fadd_double"); @31
// &Instance("pa_fspu_double"); @32
// &Instance("pa_fcnvt_single"); @34
pa_fcnvt_single x_pa_fcnvt_single (
.ctrl_xx_ex1_warm_up (ctrl_xx_ex1_warm_up ),
.dp_xx_ex1_cnan (dp_xx_ex1_cnan ),
.dp_xx_ex1_inf (dp_xx_ex1_inf ),
.dp_xx_ex1_qnan (dp_xx_ex1_qnan ),
.dp_xx_ex1_snan (dp_xx_ex1_snan ),
.dp_xx_ex1_zero (dp_xx_ex1_zero ),
.dp_xx_ex2_rm (dp_xx_ex2_rm ),
.falu_ctrl_xx_ex1_vld (falu_ctrl_xx_ex1_vld ),
.falu_ctrl_xx_ex3_vld (falu_ctrl_xx_ex3_vld ),
.fcnvt_ex1_dp_fflags (fcnvt_ex1_dp_fflags ),
.fcnvt_ex1_dp_special_result (fcnvt_ex1_dp_special_result),
.fcnvt_ex1_dp_special_sel (fcnvt_ex1_dp_special_sel ),
.fcnvt_ex1_dp_special_sign (fcnvt_ex1_dp_special_sign ),
.fcnvt_ex1_dp_wb_vld (fcnvt_ex1_dp_wb_vld ),
.fcnvt_ex1_pipe_clk (fcnvt_ex1_pipe_clk ),
.fcnvt_ex1_pipedown (fcnvt_ex1_pipedown ),
.fcnvt_ex1_sel (fcnvt_ex1_sel ),
.fcnvt_ex1_sel_dp (fcnvt_ex1_sel_dp ),
.fcnvt_ex2_pipe_clk (fcnvt_ex2_pipe_clk ),
.fcnvt_ex2_pipedown (fcnvt_ex2_pipedown ),
.fcnvt_ex3_dp_fflags (fcnvt_ex3_dp_fflags ),
.fcnvt_ex3_dp_rst (fcnvt_ex3_dp_rst ),
.fcnvt_ex3_dp_wb_vld (fcnvt_ex3_dp_wb_vld ),
.fcnvt_ex3_fspu_vld (fcnvt_ex3_fspu_vld ),
.fcnvt_ex3_rtu_fflags (fcnvt_ex3_rtu_fflags ),
.fcnvt_ex3_rtu_rst (fcnvt_ex3_rtu_rst ),
.fcnvt_ex3_rtu_wb_vld (fcnvt_ex3_rtu_wb_vld ),
.fcnvt_ex3_sel (fcnvt_ex3_sel ),
.fspu_ex1_rtu_rst (fspu_ex1_rtu_rst ),
.fspu_ex1_rtu_wb_vld (fspu_ex1_rtu_wb_vld ),
.idu_fpu_ex1_func (idu_fpu_ex1_func ),
.idu_fpu_ex1_srcf0 (idu_fpu_ex1_srcf0 ),
.idu_fpu_ex1_srci (idu_fpu_ex1_srci )
);
// &Instance("pa_fadd_single"); @35
pa_fadd_single x_pa_fadd_single (
.cp0_fpu_xx_dqnan (cp0_fpu_xx_dqnan ),
.ctrl_xx_ex1_warm_up (ctrl_xx_ex1_warm_up ),
.ctrl_xx_ex2_warm_up (ctrl_xx_ex2_warm_up ),
.dp_xx_ex1_id (dp_xx_ex1_id ),
.dp_xx_ex1_inf (dp_xx_ex1_inf ),
.dp_xx_ex1_norm (dp_xx_ex1_norm ),
.dp_xx_ex1_qnan (dp_xx_ex1_qnan ),
.dp_xx_ex1_rm (dp_xx_ex1_rm ),
.dp_xx_ex1_snan (dp_xx_ex1_snan ),
.dp_xx_ex1_zero (dp_xx_ex1_zero ),
.dp_xx_ex2_srcf2 (dp_xx_ex2_srcf2 ),
.dp_xx_ex3_rm (dp_xx_ex3_rm ),
.fadd_ex1_dp_fflags (fadd_ex1_dp_fflags ),
.fadd_ex1_dp_special_result (fadd_ex1_dp_special_result ),
.fadd_ex1_dp_special_sel (fadd_ex1_dp_special_sel ),
.fadd_ex1_dp_special_sign (fadd_ex1_dp_special_sign ),
.fadd_ex1_dp_wb_vld (fadd_ex1_dp_wb_vld ),
.fadd_ex1_pipe_clk (fadd_ex1_pipe_clk ),
.fadd_ex1_pipedown (fadd_ex1_pipedown ),
.fadd_ex1_sel (fadd_ex1_sel ),
.fadd_ex1_sel_dp (fadd_ex1_sel_dp ),
.fadd_ex2_dp_fflags (fadd_ex2_dp_fflags ),
.fadd_ex2_dp_rst (fadd_ex2_dp_rst ),
.fadd_ex2_dp_wb_vld (fadd_ex2_dp_wb_vld ),
.fadd_ex2_nocmp (fadd_ex2_nocmp ),
.fadd_ex2_nocmp_pipe_clk (fadd_ex2_nocmp_pipe_clk ),
.fadd_ex2_nocmp_pipedown (fadd_ex2_nocmp_pipedown ),
.fadd_ex2_pipe_clk (fadd_ex2_pipe_clk ),
.fadd_ex2_pipedown (fadd_ex2_pipedown ),
.fadd_ex2_sel (fadd_ex2_sel ),
.fadd_ex3_dp_fflags (fadd_ex3_dp_fflags ),
.fadd_ex3_dp_rst (fadd_ex3_dp_rst ),
.fadd_ex3_dp_wb_vld (fadd_ex3_dp_wb_vld ),
.fadd_ex3_rtu_fflags (fadd_ex3_rtu_fflags ),
.fadd_ex3_rtu_rst (fadd_ex3_rtu_rst ),
.fadd_ex3_rtu_wb_vld (fadd_ex3_rtu_wb_vld ),
.fadd_ex3_sel (fadd_ex3_sel ),
.falu_ctrl_xx_ex1_vld (falu_ctrl_xx_ex1_vld ),
.falu_ctrl_xx_ex2_vld (falu_ctrl_xx_ex2_vld ),
.falu_ctrl_xx_ex3_vld (falu_ctrl_xx_ex3_vld ),
.falu_fpu_ex1_src_reuse (falu_fpu_ex1_src_reuse ),
.falu_fpu_ex1_src_reuse_data (falu_fpu_ex1_src_reuse_data),
.idu_fpu_ex1_func (idu_fpu_ex1_func ),
.idu_fpu_ex1_srcf0 (idu_fpu_ex1_srcf0 ),
.idu_fpu_ex1_srcf1 (idu_fpu_ex1_srcf1 )
);
// &Instance("pa_fspu_single"); @36
pa_fspu_single x_pa_fspu_single (
.dp_xx_ex1_id (dp_xx_ex1_id ),
.dp_xx_ex1_inf (dp_xx_ex1_inf ),
.dp_xx_ex1_norm (dp_xx_ex1_norm ),
.dp_xx_ex1_qnan (dp_xx_ex1_qnan ),
.dp_xx_ex1_snan (dp_xx_ex1_snan ),
.dp_xx_ex1_zero (dp_xx_ex1_zero ),
.falu_ctrl_xx_ex1_vld (falu_ctrl_xx_ex1_vld ),
.fspu_ex1_dp_fflags (fspu_ex1_dp_fflags ),
.fspu_ex1_dp_special_result (fspu_ex1_dp_special_result),
.fspu_ex1_dp_special_sel (fspu_ex1_dp_special_sel ),
.fspu_ex1_dp_special_sign (fspu_ex1_dp_special_sign ),
.fspu_ex1_dp_wb_vld (fspu_ex1_dp_wb_vld ),
.fspu_ex1_rtu_rst (fspu_ex1_rtu_rst ),
.fspu_ex1_rtu_wb_vld (fspu_ex1_rtu_wb_vld ),
.fspu_ex1_rtu_wb_vld_gate (fspu_ex1_rtu_wb_vld_gate ),
.fspu_sel (fspu_sel ),
.fspu_sel_dp (fspu_sel_dp ),
.fspu_sel_gate (fspu_sel_gate ),
.idu_fpu_ex1_func (idu_fpu_ex1_func ),
.idu_fpu_ex1_srcf0 (idu_fpu_ex1_srcf0 ),
.idu_fpu_ex1_srcf1 (idu_fpu_ex1_srcf1 ),
.idu_fpu_ex1_srci (idu_fpu_ex1_srci )
);
// &Instance("pa_falu_ctrl"); @39
pa_falu_ctrl x_pa_falu_ctrl (
.cp0_fpu_icg_en (cp0_fpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ctrl_falu_ex1_sel (ctrl_falu_ex1_sel ),
.ctrl_falu_ex1_sel_dp (ctrl_falu_ex1_sel_dp ),
.ctrl_falu_ex1_sel_gate (ctrl_falu_ex1_sel_gate ),
.ctrl_xx_ex1_cmplt_dp (ctrl_xx_ex1_cmplt_dp ),
.ctrl_xx_ex1_inst_vld (ctrl_xx_ex1_inst_vld ),
.ctrl_xx_ex1_stall (ctrl_xx_ex1_stall ),
.ctrl_xx_ex1_warm_up (ctrl_xx_ex1_warm_up ),
.ctrl_xx_ex2_cancel (ctrl_xx_ex2_cancel ),
.ctrl_xx_ex2_stall (ctrl_xx_ex2_stall ),
.ctrl_xx_ex2_warm_up (ctrl_xx_ex2_warm_up ),
.ctrl_xx_ex3_stall (ctrl_xx_ex3_stall ),
.fadd_ex1_dp_fflags (fadd_ex1_dp_fflags ),
.fadd_ex1_dp_special_result (fadd_ex1_dp_special_result ),
.fadd_ex1_dp_special_sel (fadd_ex1_dp_special_sel ),
.fadd_ex1_dp_special_sign (fadd_ex1_dp_special_sign ),
.fadd_ex1_dp_wb_vld (fadd_ex1_dp_wb_vld ),
.fadd_ex1_pipe_clk (fadd_ex1_pipe_clk ),
.fadd_ex1_pipedown (fadd_ex1_pipedown ),
.fadd_ex1_sel (fadd_ex1_sel ),
.fadd_ex1_sel_dp (fadd_ex1_sel_dp ),
.fadd_ex2_dp_fflags (fadd_ex2_dp_fflags ),
.fadd_ex2_dp_rst (fadd_ex2_dp_rst ),
.fadd_ex2_dp_wb_vld (fadd_ex2_dp_wb_vld ),
.fadd_ex2_nocmp (fadd_ex2_nocmp ),
.fadd_ex2_nocmp_pipe_clk (fadd_ex2_nocmp_pipe_clk ),
.fadd_ex2_nocmp_pipedown (fadd_ex2_nocmp_pipedown ),
.fadd_ex2_pipe_clk (fadd_ex2_pipe_clk ),
.fadd_ex2_pipedown (fadd_ex2_pipedown ),
.fadd_ex2_sel (fadd_ex2_sel ),
.fadd_ex3_dp_fflags (fadd_ex3_dp_fflags ),
.fadd_ex3_dp_rst (fadd_ex3_dp_rst ),
.fadd_ex3_dp_wb_vld (fadd_ex3_dp_wb_vld ),
.fadd_ex3_rtu_fflags (fadd_ex3_rtu_fflags ),
.fadd_ex3_rtu_rst (fadd_ex3_rtu_rst ),
.fadd_ex3_rtu_wb_vld (fadd_ex3_rtu_wb_vld ),
.fadd_ex3_sel (fadd_ex3_sel ),
.falu_ctrl_xx_ex1_vld (falu_ctrl_xx_ex1_vld ),
.falu_ctrl_xx_ex2_vld (falu_ctrl_xx_ex2_vld ),
.falu_ctrl_xx_ex3_vld (falu_ctrl_xx_ex3_vld ),
.falu_fpu_ex1_cmplt (falu_fpu_ex1_cmplt ),
.falu_fpu_ex1_cmplt_dp (falu_fpu_ex1_cmplt_dp ),
.falu_fpu_ex1_fflags (falu_fpu_ex1_fflags ),
.falu_fpu_ex1_result (falu_fpu_ex1_result ),
.falu_fpu_ex1_special_sel (falu_fpu_ex1_special_sel ),
.falu_fpu_ex1_special_sign (falu_fpu_ex1_special_sign ),
.falu_fpu_ex1_wb_gpr (falu_fpu_ex1_wb_gpr ),
.falu_fpu_ex2_fflags (falu_fpu_ex2_fflags ),
.falu_fpu_ex2_result (falu_fpu_ex2_result ),
.falu_fpu_ex2_result_vld (falu_fpu_ex2_result_vld ),
.falu_fpu_ex3_fflags (falu_fpu_ex3_fflags ),
.falu_fpu_ex3_result (falu_fpu_ex3_result ),
.falu_fpu_ex3_result_vld (falu_fpu_ex3_result_vld ),
.falu_fpu_ex3_stall (falu_fpu_ex3_stall ),
.falu_fpu_ex3_wb_gpr (falu_fpu_ex3_wb_gpr ),
.fcnvt_ex1_dp_fflags (fcnvt_ex1_dp_fflags ),
.fcnvt_ex1_dp_special_result (fcnvt_ex1_dp_special_result),
.fcnvt_ex1_dp_special_sel (fcnvt_ex1_dp_special_sel ),
.fcnvt_ex1_dp_special_sign (fcnvt_ex1_dp_special_sign ),
.fcnvt_ex1_dp_wb_vld (fcnvt_ex1_dp_wb_vld ),
.fcnvt_ex1_pipe_clk (fcnvt_ex1_pipe_clk ),
.fcnvt_ex1_pipedown (fcnvt_ex1_pipedown ),
.fcnvt_ex1_sel (fcnvt_ex1_sel ),
.fcnvt_ex1_sel_dp (fcnvt_ex1_sel_dp ),
.fcnvt_ex2_pipe_clk (fcnvt_ex2_pipe_clk ),
.fcnvt_ex2_pipedown (fcnvt_ex2_pipedown ),
.fcnvt_ex3_dp_fflags (fcnvt_ex3_dp_fflags ),
.fcnvt_ex3_dp_rst (fcnvt_ex3_dp_rst ),
.fcnvt_ex3_dp_wb_vld (fcnvt_ex3_dp_wb_vld ),
.fcnvt_ex3_fspu_vld (fcnvt_ex3_fspu_vld ),
.fcnvt_ex3_rtu_fflags (fcnvt_ex3_rtu_fflags ),
.fcnvt_ex3_rtu_rst (fcnvt_ex3_rtu_rst ),
.fcnvt_ex3_rtu_wb_vld (fcnvt_ex3_rtu_wb_vld ),
.fcnvt_ex3_sel (fcnvt_ex3_sel ),
.forever_cpuclk (forever_cpuclk ),
.fpu_rtu_ex3_wb_data (fpu_rtu_ex3_wb_data ),
.fpu_rtu_ex3_wb_fflags (fpu_rtu_ex3_wb_fflags ),
.fpu_rtu_ex3_wb_fflags_vld (fpu_rtu_ex3_wb_fflags_vld ),
.fpu_rtu_ex3_wb_preg (fpu_rtu_ex3_wb_preg ),
.fpu_rtu_ex3_wb_vld (fpu_rtu_ex3_wb_vld ),
.fspu_ex1_dp_fflags (fspu_ex1_dp_fflags ),
.fspu_ex1_dp_special_result (fspu_ex1_dp_special_result ),
.fspu_ex1_dp_special_sel (fspu_ex1_dp_special_sel ),
.fspu_ex1_dp_special_sign (fspu_ex1_dp_special_sign ),
.fspu_ex1_dp_wb_vld (fspu_ex1_dp_wb_vld ),
.fspu_ex1_rtu_wb_vld (fspu_ex1_rtu_wb_vld ),
.fspu_ex1_rtu_wb_vld_gate (fspu_ex1_rtu_wb_vld_gate ),
.fspu_sel (fspu_sel ),
.fspu_sel_dp (fspu_sel_dp ),
.fspu_sel_gate (fspu_sel_gate ),
.idu_fpu_ex1_dst_preg (idu_fpu_ex1_dst_preg ),
.idu_fpu_ex1_eu_sel (idu_fpu_ex1_eu_sel ),
.idu_fpu_ex1_func (idu_fpu_ex1_func ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_fpu_ex3_wb_grant (rtu_fpu_ex3_wb_grant ),
.rtu_xx_ex1_cancel (rtu_xx_ex1_cancel )
);
// &Force("bus", "dp_xx_ex1_cnan", 2, 0); @42
// &Force("bus", "dp_xx_ex1_snan", 2, 0); @43
// &Force("bus", "dp_xx_ex1_qnan", 2, 0); @44
// &Force("bus", "dp_xx_ex1_norm", 2, 0); @45
// &Force("bus", "dp_xx_ex1_zero", 2, 0); @46
// &Force("bus", "dp_xx_ex1_inf", 2, 0); @47
// &Force("bus", "dp_xx_ex1_id", 2, 0); @48
// &Force("bus", "idu_fpu_ex1_func", 9, 0); @49
// &ModuleEnd; @52
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @22
module pa_fcnvt_ftoi_s(
fsh_cnt,
fsh_i_v_nm,
fsh_i_x_nm,
fsh_src
);
// &Ports; @23
input [5 :0] fsh_cnt;
input [23:0] fsh_src;
output [31:0] fsh_i_v_nm;
output [24:0] fsh_i_x_nm;
// &Regs; @24
reg [31:0] fsh_i_v_nm;
reg [24:0] fsh_i_x_nm;
// &Wires; @25
wire [5 :0] fsh_cnt;
wire [23:0] fsh_src;
// &CombBeg; @27
always @( fsh_src[23:0]
or fsh_cnt[5:0])
begin
case(fsh_cnt[5:0])
6'h3f : begin //for actual exponent = -1, should consider rouding
fsh_i_v_nm[31:0] = 32'd0;
fsh_i_x_nm[24:0] = {fsh_src[23:0], 1'd0};
end
6'd0 : begin
fsh_i_v_nm[31:0] = {31'd0, fsh_src[23]};
fsh_i_x_nm[24:0] = {fsh_src[22:0], 2'd0};
end
6'd1 : begin
fsh_i_v_nm[31:0] = {30'd0, fsh_src[23:22]};
fsh_i_x_nm[24:0] = {fsh_src[21:0], 3'd0};
end
6'd2 : begin
fsh_i_v_nm[31:0] = {29'd0, fsh_src[23:21]};
fsh_i_x_nm[24:0] = {fsh_src[20:0], 4'd0};
end
6'd3 : begin
fsh_i_v_nm[31:0] = {28'd0, fsh_src[23:20]};
fsh_i_x_nm[24:0] = {fsh_src[19:0], 5'd0};
end
6'd4 : begin
fsh_i_v_nm[31:0] = {27'd0, fsh_src[23:19]};
fsh_i_x_nm[24:0] = {fsh_src[18:0], 6'd0};
end
6'd5 : begin
fsh_i_v_nm[31:0] = {26'd0, fsh_src[23:18]};
fsh_i_x_nm[24:0] = {fsh_src[17:0], 7'd0};
end
6'd6 : begin
fsh_i_v_nm[31:0] = {25'd0, fsh_src[23:17]};
fsh_i_x_nm[24:0] = {fsh_src[16:0], 8'd0};
end
6'd7 : begin
fsh_i_v_nm[31:0] = {24'd0, fsh_src[23:16]};
fsh_i_x_nm[24:0] = {fsh_src[15:0], 9'd0};
end
6'd8 : begin
fsh_i_v_nm[31:0] = {23'd0, fsh_src[23:15]};
fsh_i_x_nm[24:0] = {fsh_src[14:0], 10'd0};
end
6'd9 : begin
fsh_i_v_nm[31:0] = {22'd0, fsh_src[23:14]};
fsh_i_x_nm[24:0] = {fsh_src[13:0], 11'd0};
end
6'd10 : begin
fsh_i_v_nm[31:0] = {21'd0, fsh_src[23:13]};
fsh_i_x_nm[24:0] = {fsh_src[12:0], 12'd0};
end
6'd11 : begin
fsh_i_v_nm[31:0] = {20'd0, fsh_src[23:12]};
fsh_i_x_nm[24:0] = {fsh_src[11:0], 13'd0};
end
6'd12 : begin
fsh_i_v_nm[31:0] = {19'd0, fsh_src[23:11]};
fsh_i_x_nm[24:0] = {fsh_src[10:0], 14'd0};
end
6'd13 : begin
fsh_i_v_nm[31:0] = {18'd0, fsh_src[23:10]};
fsh_i_x_nm[24:0] = {fsh_src[9:0], 15'd0};
end
6'd14 : begin
fsh_i_v_nm[31:0] = {17'd0, fsh_src[23:9]};
fsh_i_x_nm[24:0] = {fsh_src[8:0], 16'd0};
end
6'd15 : begin
fsh_i_v_nm[31:0] = {16'd0, fsh_src[23:8]};
fsh_i_x_nm[24:0] = {fsh_src[7:0], 17'd0};
end
6'd16 : begin
fsh_i_v_nm[31:0] = {15'd0, fsh_src[23:7]};
fsh_i_x_nm[24:0] = {fsh_src[6:0], 18'd0};
end
6'd17 : begin
fsh_i_v_nm[31:0] = {14'd0, fsh_src[23:6]};
fsh_i_x_nm[24:0] = {fsh_src[5:0], 19'd0};
end
6'd18 : begin
fsh_i_v_nm[31:0] = {13'd0, fsh_src[23:5]};
fsh_i_x_nm[24:0] = {fsh_src[4:0], 20'd0};
end
6'd19 : begin
fsh_i_v_nm[31:0] = {12'd0, fsh_src[23:4]};
fsh_i_x_nm[24:0] = {fsh_src[3:0], 21'd0};
end
6'd20 : begin
fsh_i_v_nm[31:0] = {11'd0, fsh_src[23:3]};
fsh_i_x_nm[24:0] = {fsh_src[2:0], 22'd0};
end
6'd21 : begin
fsh_i_v_nm[31:0] = {10'd0, fsh_src[23:2]};
fsh_i_x_nm[24:0] = {fsh_src[1:0], 23'd0};
end
6'd22 : begin
fsh_i_v_nm[31:0] = {9'd0, fsh_src[23:1]};
fsh_i_x_nm[24:0] = {fsh_src[0], 24'd0};
end
6'd23 : begin
fsh_i_v_nm[31:0] = {8'd0, fsh_src[23:0]};
fsh_i_x_nm[24:0] = 25'd0;
end
6'd24 : begin
fsh_i_v_nm[31:0] = {7'd0, fsh_src[23:0], 1'b0};
fsh_i_x_nm[24:0] = 25'b0;
end
6'd25 : begin
fsh_i_v_nm[31:0] = {6'd0, fsh_src[23:0], 2'b0};
fsh_i_x_nm[24:0] = 25'd0;
end
6'd26 : begin
fsh_i_v_nm[31:0] = {5'd0, fsh_src[23:0], 3'b0};
fsh_i_x_nm[24:0] = 25'b0;
end
6'd27 : begin
fsh_i_v_nm[31:0] = {4'd0, fsh_src[23:0], 4'b0};
fsh_i_x_nm[24:0] = 25'd0;
end
6'd28 : begin
fsh_i_v_nm[31:0] = {3'd0, fsh_src[23:0], 5'b0};
fsh_i_x_nm[24:0] = 25'd0;
end
6'd29 : begin
fsh_i_v_nm[31:0] = {2'd0, fsh_src[23:0], 6'b0};
fsh_i_x_nm[24:0] = 25'd0;
end
6'd30 : begin
fsh_i_v_nm[31:0] = {1'd0, fsh_src[23:0], 7'b0};
fsh_i_x_nm[24:0] = 25'd0;
end
6'd31 : begin
fsh_i_v_nm[31:0] = {fsh_src[23:0], 8'b0};
fsh_i_x_nm[24:0] = 25'b0;
end
default : begin
fsh_i_v_nm[31:0] = {32{1'bx}};
fsh_i_x_nm[24:0] = {25{1'bx}};
end
endcase
// &CombEnd; @166
end
// &ModuleEnd; @168
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_fcnvt_itof_s(
ff1_sh_cnt,
ff1_sh_f_v,
ff1_sh_src
);
// &Ports; @24
input [31:0] ff1_sh_src;
output [4 :0] ff1_sh_cnt;
output [31:0] ff1_sh_f_v;
// &Regs; @25
reg [4 :0] ff1_sh_cnt;
reg [31:0] ff1_sh_f_v;
// &Wires; @26
wire [31:0] ff1_sh_src;
// &CombBeg; @29
always @( ff1_sh_src[31:0])
begin
casez(ff1_sh_src[31:0])
32'b1???_????_????_????_????_????_????_???? : begin
ff1_sh_cnt[4:0] = 5'd31;
ff1_sh_f_v[31:0] = {ff1_sh_src[31:0]};
end
32'b01??_????_????_????_????_????_????_???? : begin
ff1_sh_cnt[4:0] = 5'd30;
ff1_sh_f_v[31:0] = {ff1_sh_src[30:0],1'b0};
end
32'b001?_????_????_????_????_????_????_???? : begin
ff1_sh_cnt[4:0] = 5'd29;
ff1_sh_f_v[31:0] = {ff1_sh_src[29:0],2'b0};
end
32'b0001_????_????_????_????_????_????_???? : begin
ff1_sh_cnt[4:0] = 5'd28;
ff1_sh_f_v[31:0] = {ff1_sh_src[28:0],3'b0};
end
32'b0000_1???_????_????_????_????_????_???? : begin
ff1_sh_cnt[4:0] = 5'd27;
ff1_sh_f_v[31:0] = {ff1_sh_src[27:0],4'b0};
end
32'b0000_01??_????_????_????_????_????_???? : begin
ff1_sh_cnt[4:0] = 5'd26;
ff1_sh_f_v[31:0] = {ff1_sh_src[26:0],5'b0};
end
32'b0000_001?_????_????_????_????_????_???? : begin
ff1_sh_cnt[4:0] = 5'd25;
ff1_sh_f_v[31:0] = {ff1_sh_src[25:0],6'b0};
end
32'b0000_0001_????_????_????_????_????_???? : begin
ff1_sh_cnt[4:0] = 5'd24;
ff1_sh_f_v[31:0] = {ff1_sh_src[24:0],7'b0};
end
32'b0000_0000_1???_????_????_????_????_???? : begin
ff1_sh_cnt[4:0] = 5'd23;
ff1_sh_f_v[31:0] = {ff1_sh_src[23:0],8'b0};
end
32'b0000_0000_01??_????_????_????_????_???? : begin
ff1_sh_cnt[4:0] = 5'd22;
ff1_sh_f_v[31:0] = {ff1_sh_src[22:0],9'b0};
end
32'b0000_0000_001?_????_????_????_????_???? : begin
ff1_sh_cnt[4:0] = 5'd21;
ff1_sh_f_v[31:0] = {ff1_sh_src[21:0],10'b0};
end
32'b0000_0000_0001_????_????_????_????_???? : begin
ff1_sh_cnt[4:0] = 5'd20;
ff1_sh_f_v[31:0] = {ff1_sh_src[20:0],11'b0};
end
32'b0000_0000_0000_1???_????_????_????_????: begin
ff1_sh_cnt[4:0] = 5'd19;
ff1_sh_f_v[31:0] = {ff1_sh_src[19:0],12'b0};
end
32'b0000_0000_0000_01??_????_????_????_???? : begin
ff1_sh_cnt[4:0] = 5'd18;
ff1_sh_f_v[31:0] = {ff1_sh_src[18:0],13'b0};
end
32'b0000_0000_0000_001?_????_????_????_???? : begin
ff1_sh_cnt[4:0] = 5'd17;
ff1_sh_f_v[31:0] = {ff1_sh_src[17:0],14'b0};
end
32'b0000_0000_0000_0001_????_????_????_???? : begin
ff1_sh_cnt[4:0] = 5'd16;
ff1_sh_f_v[31:0] = {ff1_sh_src[16:0],15'b0};
end
32'b0000_0000_0000_0000_1???_????_????_???? : begin
ff1_sh_cnt[4:0] = 5'd15;
ff1_sh_f_v[31:0] = {ff1_sh_src[15:0],16'b0};
end
32'b0000_0000_0000_0000_01??_????_????_???? : begin
ff1_sh_cnt[4:0] = 5'd14;
ff1_sh_f_v[31:0] = {ff1_sh_src[14:0],17'b0};
end
32'b0000_0000_0000_0000_001?_????_????_???? : begin
ff1_sh_cnt[4:0] = 5'd13;
ff1_sh_f_v[31:0] = {ff1_sh_src[13:0],18'b0};
end
32'b0000_0000_0000_0000_0001_????_????_???? : begin
ff1_sh_cnt[4:0] = 5'd12;
ff1_sh_f_v[31:0] = {ff1_sh_src[12:0],19'b0};
end
32'b0000_0000_0000_0000_0000_1???_????_???? : begin
ff1_sh_cnt[4:0] = 5'd11;
ff1_sh_f_v[31:0] = {ff1_sh_src[11:0],20'b0};
end
32'b0000_0000_0000_0000_0000_01??_????_???? : begin
ff1_sh_cnt[4:0] = 5'd10;
ff1_sh_f_v[31:0] = {ff1_sh_src[10:0],21'b0};
end
32'b0000_0000_0000_0000_0000_001?_????_???? : begin
ff1_sh_cnt[4:0] = 5'd9;
ff1_sh_f_v[31:0] = {ff1_sh_src[9:0],22'b0};
end
32'b0000_0000_0000_0000_0000_0001_????_???? : begin
ff1_sh_cnt[4:0] = 5'd8;
ff1_sh_f_v[31:0] = {ff1_sh_src[8:0],23'b0};
end
32'b0000_0000_0000_0000_0000_0000_1???_????: begin
ff1_sh_cnt[4:0] = 5'd7;
ff1_sh_f_v[31:0] = {ff1_sh_src[7:0],24'b0};
end
32'b0000_0000_0000_0000_0000_0000_01??_???? : begin
ff1_sh_cnt[4:0] = 5'd6;
ff1_sh_f_v[31:0] = {ff1_sh_src[6:0],25'b0};
end
32'b0000_0000_0000_0000_0000_0000_001?_???? : begin
ff1_sh_cnt[4:0] = 5'd5;
ff1_sh_f_v[31:0] = {ff1_sh_src[5:0],26'b0};
end
32'b0000_0000_0000_0000_0000_0000_0001_???? : begin
ff1_sh_cnt[4:0] = 5'd4;
ff1_sh_f_v[31:0] = {ff1_sh_src[4:0],27'b0};
end
32'b0000_0000_0000_0000_0000_0000_0000_1??? : begin
ff1_sh_cnt[4:0] = 5'd3;
ff1_sh_f_v[31:0] = {ff1_sh_src[3:0],28'b0};
end
32'b0000_0000_0000_0000_0000_0000_0000_01?? : begin
ff1_sh_cnt[4:0] = 5'd2;
ff1_sh_f_v[31:0] = {ff1_sh_src[2:0],29'b0};
end
32'b0000_0000_0000_0000_0000_0000_0000_001? : begin
ff1_sh_cnt[4:0] = 5'd1;
ff1_sh_f_v[31:0] = {ff1_sh_src[1:0],30'b0};
end
32'b0000_0000_0000_0000_0000_0000_0000_0001 : begin
ff1_sh_cnt[4:0] = 5'd0;
ff1_sh_f_v[31:0] = {ff1_sh_src[0],31'b0};
end
default : begin
ff1_sh_cnt[4:0] = 5'b0;
ff1_sh_f_v[31:0] = 32'b0;
end
endcase
// &CombEnd; @164
end
// &ModuleEnd; @166
endmodule

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opene906/E906_RTL_FACTORY/gen_rtl/falu/rtl/pa_fcnvt_single.v Normal file
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @25
module pa_fcnvt_single(
ctrl_xx_ex1_warm_up,
dp_xx_ex1_cnan,
dp_xx_ex1_inf,
dp_xx_ex1_qnan,
dp_xx_ex1_snan,
dp_xx_ex1_zero,
dp_xx_ex2_rm,
falu_ctrl_xx_ex1_vld,
falu_ctrl_xx_ex3_vld,
fcnvt_ex1_dp_fflags,
fcnvt_ex1_dp_special_result,
fcnvt_ex1_dp_special_sel,
fcnvt_ex1_dp_special_sign,
fcnvt_ex1_dp_wb_vld,
fcnvt_ex1_pipe_clk,
fcnvt_ex1_pipedown,
fcnvt_ex1_sel,
fcnvt_ex1_sel_dp,
fcnvt_ex2_pipe_clk,
fcnvt_ex2_pipedown,
fcnvt_ex3_dp_fflags,
fcnvt_ex3_dp_rst,
fcnvt_ex3_dp_wb_vld,
fcnvt_ex3_fspu_vld,
fcnvt_ex3_rtu_fflags,
fcnvt_ex3_rtu_rst,
fcnvt_ex3_rtu_wb_vld,
fcnvt_ex3_sel,
fspu_ex1_rtu_rst,
fspu_ex1_rtu_wb_vld,
idu_fpu_ex1_func,
idu_fpu_ex1_srcf0,
idu_fpu_ex1_srci
);
// &Ports; @26
input ctrl_xx_ex1_warm_up;
input [2 :0] dp_xx_ex1_cnan;
input [2 :0] dp_xx_ex1_inf;
input [2 :0] dp_xx_ex1_qnan;
input [2 :0] dp_xx_ex1_snan;
input [2 :0] dp_xx_ex1_zero;
input [2 :0] dp_xx_ex2_rm;
input falu_ctrl_xx_ex1_vld;
input falu_ctrl_xx_ex3_vld;
input fcnvt_ex1_pipe_clk;
input fcnvt_ex1_pipedown;
input fcnvt_ex1_sel;
input fcnvt_ex1_sel_dp;
input fcnvt_ex2_pipe_clk;
input fcnvt_ex2_pipedown;
input fcnvt_ex3_sel;
input [31:0] fspu_ex1_rtu_rst;
input fspu_ex1_rtu_wb_vld;
input [9 :0] idu_fpu_ex1_func;
input [31:0] idu_fpu_ex1_srcf0;
input [31:0] idu_fpu_ex1_srci;
output [4 :0] fcnvt_ex1_dp_fflags;
output [31:0] fcnvt_ex1_dp_special_result;
output [7 :0] fcnvt_ex1_dp_special_sel;
output [2 :0] fcnvt_ex1_dp_special_sign;
output fcnvt_ex1_dp_wb_vld;
output [4 :0] fcnvt_ex3_dp_fflags;
output [31:0] fcnvt_ex3_dp_rst;
output fcnvt_ex3_dp_wb_vld;
output fcnvt_ex3_fspu_vld;
output [4 :0] fcnvt_ex3_rtu_fflags;
output [31:0] fcnvt_ex3_rtu_rst;
output fcnvt_ex3_rtu_wb_vld;
// &Regs; @27
reg [2 :0] ex1_special_sel_2;
reg ex2_dest_float;
reg ex2_dest_si;
reg [8 :0] ex2_exp;
reg [23:0] ex2_frac;
reg ex2_fspu_vld;
reg [31:0] ex2_int_r;
reg ex2_sign;
reg ex2_special_nv;
reg ex2_special_vld;
reg ex2_src_is_0;
reg [24:0] ex2_tail;
reg ex3_dest_float;
reg [3 :0] ex3_expt;
reg ex3_fspu_vld;
reg [31:0] ex3_result;
reg ex3_special_vld;
// &Wires; @28
wire ctrl_xx_ex1_warm_up;
wire [2 :0] dp_xx_ex1_cnan;
wire [2 :0] dp_xx_ex1_inf;
wire [2 :0] dp_xx_ex1_qnan;
wire [2 :0] dp_xx_ex1_snan;
wire [2 :0] dp_xx_ex1_zero;
wire [2 :0] dp_xx_ex2_rm;
wire ex1_dest_float;
wire ex1_dest_si;
wire [8 :0] ex1_e_without_bias;
wire [8 :0] ex1_exp_bias;
wire [4 :0] ex1_ff1_d_cnt;
wire [31:0] ex1_ff1_sh_f_v;
wire [8 :0] ex1_final_exp;
wire [23:0] ex1_final_frac;
wire ex1_final_sign;
wire [24:0] ex1_final_tail;
wire [24:0] ex1_final_tail_t;
wire [31:0] ex1_fsh_i_v_nm;
wire [24:0] ex1_fsh_i_x_nm;
wire [31:0] ex1_ftoi_0;
wire [31:0] ex1_ftoi_int;
wire [24:0] ex1_ftoi_int_tail;
wire [31:0] ex1_ftoi_max;
wire [31:0] ex1_ftoi_min;
wire [31:0] ex1_ftoi_specail;
wire [23:0] ex1_ftoi_trans;
wire [31:0] ex1_ftosi_max;
wire [31:0] ex1_ftosi_min;
wire [31:0] ex1_ftoui_max;
wire [31:0] ex1_ftoui_min;
wire ex1_ia_0;
wire [23:0] ex1_itof_dest_frac;
wire [24:0] ex1_itof_dest_tail;
wire [8 :0] ex1_itof_expnt;
wire [31:0] ex1_itof_neg_i;
wire [31:0] ex1_itof_src;
wire ex1_op_ftoi;
wire ex1_op_itof;
wire [22:0] ex1_single_f;
wire ex1_special_i_nv;
wire ex1_special_nv;
wire [7 :0] ex1_src_e;
wire [22:0] ex1_src_f;
wire ex1_src_f_0;
wire ex1_src_f_cnan;
wire ex1_src_f_inf;
wire ex1_src_f_qnan;
wire ex1_src_f_snan;
wire ex1_src_float;
wire ex1_src_i;
wire ex1_src_i_sign;
wire [31:0] ex1_src_int;
wire ex1_src_is_0;
wire ex1_src_neg_shf;
wire ex1_src_s;
wire ex1_src_si;
wire ex2_dest_sel_float;
wire [8 :0] ex2_eadder_bias;
wire [8 :0] ex2_eadder_bias1;
wire [8 :0] ex2_expnt;
wire ex2_expnt_add1;
wire [8 :0] ex2_expnt_src1;
wire [3 :0] ex2_expt;
wire ex2_expt_nv;
wire ex2_expt_nv_f;
wire ex2_expt_nv_i;
wire ex2_expt_nx;
wire ex2_expt_nx_t;
wire ex2_expt_of;
wire ex2_expt_uf;
wire [31:0] ex2_float_result;
wire ex2_frac_lst;
wire [31:0] ex2_int;
wire ex2_int_lst;
wire [32:0] ex2_int_nm_result;
wire [31:0] ex2_int_result;
wire [8 :0] ex2_norm_expnt;
wire [23:0] ex2_orig_f;
wire ex2_rm_rdn;
wire ex2_rm_rmm;
wire ex2_rm_rne;
wire ex2_rm_rup;
wire [32:0] ex2_rnd_adder_f_p1;
wire [32:0] ex2_rnd_adder_f_src0;
wire [32:0] ex2_rnd_adder_f_src1;
wire [32:0] ex2_rnd_adder_i_p1;
wire [32:0] ex2_rnd_adder_i_src0;
wire ex2_rnd_lst;
wire ex2_round_add;
wire [31:0] ex2_si_result;
wire [22:0] ex2_single_f;
wire [31:0] ex2_single_norm_result;
wire ex2_single_of;
wire [31:0] ex2_single_result;
wire ex2_single_uf;
wire ex2_tosi_neg_exp_crit_of;
wire ex2_tosi_neg_exp_of;
wire ex2_tosi_of;
wire ex2_tosi_pos_exp_of;
wire ex2_tosi_uf;
wire [31:0] ex2_total_result;
wire ex2_toui_exp_of;
wire ex2_toui_of;
wire ex2_toui_uf;
wire [31:0] ex2_ui_result;
wire [32:0] ex2_uint_nm_result;
wire ex2_x_eq_0p5;
wire ex2_x_gt_0p5;
wire ex2_x_zero;
wire falu_ctrl_xx_ex1_vld;
wire falu_ctrl_xx_ex3_vld;
wire fcnvt_dest_f;
wire [31:0] fcnvt_ex1_borrow_rslt;
wire fcnvt_ex1_borrow_vld;
wire [31:0] fcnvt_ex1_comb_int_rslt;
wire [4 :0] fcnvt_ex1_dp_fflags;
wire [31:0] fcnvt_ex1_dp_special_result;
wire [7 :0] fcnvt_ex1_dp_special_sel;
wire [2 :0] fcnvt_ex1_dp_special_sign;
wire fcnvt_ex1_dp_wb_vld;
wire fcnvt_ex1_op_ftoi;
wire fcnvt_ex1_pipe_clk;
wire fcnvt_ex1_pipedown;
wire [31:0] fcnvt_ex1_rslt_rst;
wire fcnvt_ex1_rslt_wb_vld;
wire fcnvt_ex1_sel;
wire fcnvt_ex1_sel_dp;
wire fcnvt_ex2_pipe_clk;
wire fcnvt_ex2_pipedown;
wire [4 :0] fcnvt_ex3_dp_fflags;
wire [31:0] fcnvt_ex3_dp_rst;
wire fcnvt_ex3_dp_wb_vld;
wire [4 :0] fcnvt_ex3_expt;
wire fcnvt_ex3_fspu_vld;
wire [31:0] fcnvt_ex3_result;
wire [4 :0] fcnvt_ex3_rtu_fflags;
wire [31:0] fcnvt_ex3_rtu_rst;
wire fcnvt_ex3_rtu_wb_vld;
wire fcnvt_ex3_sel;
wire [31:0] fcnvt_src0;
wire [31:0] fspu_ex1_rtu_rst;
wire fspu_ex1_rtu_wb_vld;
wire [9 :0] idu_fpu_ex1_func;
wire [31:0] idu_fpu_ex1_srcf0;
wire [31:0] idu_fpu_ex1_srci;
wire int_dest_max_si;
wire int_dest_max_ui;
wire int_dest_min_si;
wire [23:0] itof_dest_single_f;
wire [24:0] itof_dest_single_t;
wire single_expnt_add;
wire single_norm_f_all_1;
// &Force("bus", "dp_xx_ex1_cnan", 2, 0); @30
// &Force("bus", "dp_xx_ex1_snan", 2, 0); @31
// &Force("bus", "dp_xx_ex1_qnan", 2, 0); @32
// &Force("bus", "dp_xx_ex1_norm", 2, 0); @33
// &Force("bus", "dp_xx_ex1_zero", 2, 0); @34
// &Force("bus", "dp_xx_ex1_inf", 2, 0); @35
// &Force("bus", "dp_xx_ex1_id", 2, 0); @36
// &Force("bus", "idu_fpu_ex1_func", 9, 0); @37
//==============================================================================
// EX1 Operation
//==============================================================================
//------------------------------------------------------------------------------
// Interface with idu :
//------------------------------------------------------------------------------
assign ex1_op_ftoi = idu_fpu_ex1_func[6] || idu_fpu_ex1_func[5];
assign ex1_op_itof = idu_fpu_ex1_func[3] || idu_fpu_ex1_func[4];
assign ex1_dest_si = idu_fpu_ex1_func[6];
assign ex1_src_int[31:0] = {32{fcnvt_ex1_sel_dp}} & idu_fpu_ex1_srci[31:0];
assign fcnvt_src0[31:0] = {32{fcnvt_ex1_sel_dp}} & idu_fpu_ex1_srcf0[31:0];
assign ex1_src_float = idu_fpu_ex1_func[6] || idu_fpu_ex1_func[5];
assign ex1_dest_float = |idu_fpu_ex1_func[4:3];
assign ex1_src_si = idu_fpu_ex1_func[4];
assign ex1_src_i = idu_fpu_ex1_func[3] || idu_fpu_ex1_func[4];
assign ex1_ia_0 = ~|ex1_src_int[31:0];
assign ex1_src_s = ex1_src_si ? ex1_src_int[31] : fcnvt_src0[31];
// inf/nan only for float
assign ex1_src_f_inf = dp_xx_ex1_inf[0];
assign ex1_src_f_qnan = dp_xx_ex1_qnan[0];
assign ex1_src_f_cnan = dp_xx_ex1_cnan[0];
assign ex1_src_f_snan = dp_xx_ex1_snan[0];
assign ex1_src_f_0 = dp_xx_ex1_zero[0];
assign ex1_src_e[7:0] = fcnvt_src0[30:23];
assign ex1_exp_bias[8:0] = 9'h181; // -127
//float or int equal 0
assign ex1_src_is_0 = ex1_src_f_0 && ex1_src_float || ex1_ia_0 && ex1_src_i;
assign ex1_single_f[22:0] = fcnvt_src0[22:0];
//------------------------------------------------------------------------------
// expnt adjust:
//------------------------------------------------------------------------------
assign ex1_e_without_bias[8:0] = {1'b0, ex1_src_e[7:0]} + ex1_exp_bias[8:0];
//------------------------------------------------------------------------------
// EX1 FTOI Path:
//------------------------------------------------------------------------------
//In FTOI, generate int and tail, shift by ex1_e_without_bias
//Corner: when ex1_e_without_bias == -1, round bits is different with other
//case
assign ex1_src_f[22:0] = ex1_single_f[22:0];
assign ex1_ftoi_trans[23:0] = {~ex1_src_is_0, ex1_src_f[22:0]};
// &Instance("pa_fcnvt_ftoi_s","x_pa_fcnvt_ftoi_s"); @87
pa_fcnvt_ftoi_s x_pa_fcnvt_ftoi_s (
.fsh_cnt (ex1_e_without_bias[5:0]),
.fsh_i_v_nm (ex1_fsh_i_v_nm ),
.fsh_i_x_nm (ex1_fsh_i_x_nm ),
.fsh_src (ex1_ftoi_trans )
);
// &Connect( @88
// .fsh_cnt (ex1_e_without_bias[5:0]), @89
// .fsh_src (ex1_ftoi_trans), @90
// .fsh_i_v_nm (ex1_fsh_i_v_nm), @91
// .fsh_i_x_nm (ex1_fsh_i_x_nm) @92
// ); @93
assign ex1_ftoi_int[31:0] = ex1_e_without_bias[8] ? 32'b0 : ex1_fsh_i_v_nm[31:0];
assign ex1_ftoi_int_tail[24:0] = ex1_e_without_bias[8] && ex1_e_without_bias[7:0] != 8'hff ? {1'b0,ex1_ftoi_trans[23:0]}
: ex1_fsh_i_x_nm[24:0];
assign ex1_src_i_sign = idu_fpu_ex1_srci[31];
//------------------------------------------------------------------------------
// EX1 ITOF Path:
//------------------------------------------------------------------------------
//In ITOF, if dest is single, need rounding
assign ex1_src_neg_shf = ex1_src_i_sign && ex1_src_si;
assign ex1_itof_neg_i[31:0] = ~ex1_src_int[31:0] + 32'b1;
assign ex1_itof_src[31:0] = ex1_src_neg_shf ? ex1_itof_neg_i[31:0] : ex1_src_int[31:0];
// &Instance("pa_fcnvt_itof_s","x_pa_fcnvt_itof_s"); @108
pa_fcnvt_itof_s x_pa_fcnvt_itof_s (
.ff1_sh_cnt (ex1_ff1_d_cnt ),
.ff1_sh_f_v (ex1_ff1_sh_f_v),
.ff1_sh_src (ex1_itof_src )
);
// &Connect( @109
// .ff1_sh_src (ex1_itof_src ), // input data @110
// .ff1_sh_cnt (ex1_ff1_d_cnt ), // find fist 1 @111
// .ff1_sh_f_v (ex1_ff1_sh_f_v ) // output frac @112
// ); @113
// i to f: f is frac of float, and t is for rounding
assign itof_dest_single_f[23:0] = {ex1_ff1_sh_f_v[31:8]};
assign itof_dest_single_t[24:0] = {ex1_ff1_sh_f_v[7:0], 17'b0};
assign ex1_itof_expnt[8:0] = {4'b0, ex1_ff1_d_cnt[4:0]};
assign ex1_itof_dest_frac[23:0] = itof_dest_single_f[23:0];
assign ex1_itof_dest_tail[24:0] = itof_dest_single_t[24:0];
//------------------------------------------------------------------------------
// EX1 final result:
//------------------------------------------------------------------------------
assign ex1_final_frac[23:0] = ex1_itof_dest_frac[23:0];
assign ex1_final_tail_t[24:0] = ex1_op_itof ? ex1_itof_dest_tail[24:0]
: 25'b0;
// merge dest int and float result
assign ex1_final_tail[24:0] = ex1_op_ftoi ? ex1_ftoi_int_tail[24:0] : ex1_final_tail_t[24:0];
assign ex1_final_exp[8:0] = ex1_op_itof ? ex1_itof_expnt[8:0] : ex1_e_without_bias[8:0];
// merge dest float expnt and dest int
assign ex1_final_sign = ex1_src_s && !(ex1_src_float && !ex1_dest_float && ex1_src_is_0
|| !ex1_src_float && !ex1_src_si);
//------------------------------------------------------------------------------
// EX1 special result:
//------------------------------------------------------------------------------
//In fcnvt single, here is no float to float convert, so it is impossiblt to
//generate special float result
assign fcnvt_ex1_dp_wb_vld = 1'b0;
assign fcnvt_ex1_dp_fflags[4:0] = 5'b0;
assign fcnvt_ex1_dp_special_sel[7:0] = 8'b0;
assign fcnvt_ex1_dp_special_sign[2:0] = 3'b0;
assign fcnvt_ex1_dp_special_result[31:0] = 32'b0;
//f to i
//max, min, 0
// &CombBeg; @152
always @( ex1_src_f_qnan
or ex1_src_f_inf
or ex1_src_f_snan
or ex1_src_s)
begin
if(ex1_src_f_snan)
ex1_special_sel_2[2:0] = {1'b1, 2'b0}; // max
else if(ex1_src_f_qnan)
ex1_special_sel_2[2:0] = {1'b1, 2'b0}; // max
else if(ex1_src_f_inf && ex1_src_s)
ex1_special_sel_2[2:0] = {1'b0, 1'b1, 1'b0}; // min
else if(ex1_src_f_inf && !ex1_src_s)
ex1_special_sel_2[2:0] = {1'b1, 2'b0}; // max
else //if(ex1_src_f_0)
ex1_special_sel_2[2:0] = {2'b0, 1'b1}; // 0
// &CombEnd; @163
end
assign ex1_ftosi_max[31:0] = {1'b0, 31'h7fffffff};
assign ex1_ftosi_min[31:0] = {1'b1, 31'b0};
assign ex1_ftoi_0[31:0] = 32'b0;
assign ex1_ftoui_max[31:0] = 32'hffffffff;
assign ex1_ftoui_min[31:0] = 32'b0;
assign ex1_ftoi_min[31:0] = ex1_dest_si ? ex1_ftosi_min[31:0] : ex1_ftoui_min[31:0];
assign ex1_ftoi_max[31:0] = ex1_dest_si ? ex1_ftosi_max[31:0] : ex1_ftoui_max[31:0];
assign ex1_ftoi_specail[31:0] = {32{ex1_special_sel_2[2]}} & ex1_ftoi_max[31:0] |
{32{ex1_special_sel_2[1]}} & ex1_ftoi_min[31:0] |
{32{ex1_special_sel_2[0]}} & ex1_ftoi_0[31:0];
assign ex1_special_i_nv = ex1_src_f_snan || ex1_src_f_qnan || ex1_src_f_inf;
//------------------------------------------------------------------------------
// EX1 int result rename for output:
//------------------------------------------------------------------------------
assign fcnvt_ex1_rslt_rst[31:0] = ex1_ftoi_specail[31:0];
//assign fcnvt_ex1_rtu_fflags[4:0] = {ex1_special_i_nv, 4'b0};
assign fcnvt_ex1_rslt_wb_vld = ex1_op_ftoi && (ex1_src_f_snan || ex1_src_f_cnan || ex1_src_f_qnan || ex1_src_f_inf || ex1_src_f_0)
&& fcnvt_ex1_sel && falu_ctrl_xx_ex1_vld;
assign fcnvt_ex1_borrow_vld = fcnvt_ex1_rslt_wb_vld | fspu_ex1_rtu_wb_vld;
assign fcnvt_ex1_borrow_rslt[31:0] = fspu_ex1_rtu_wb_vld ? fspu_ex1_rtu_rst[31:0]
: fcnvt_ex1_rslt_rst[31:0];
assign fcnvt_ex1_comb_int_rslt[31:0] = fcnvt_ex1_borrow_vld ? fcnvt_ex1_borrow_rslt[31:0]
: ex1_ftoi_int[31:0];
assign ex1_special_nv = fspu_ex1_rtu_wb_vld ? 1'b0
: ex1_special_i_nv;
//Output for icg
assign fcnvt_ex1_op_ftoi = ex1_op_ftoi;
assign fcnvt_dest_f = ex1_dest_float;
//------------------------------------------------------------------------------
// EX1 pipedown to EX2:
//------------------------------------------------------------------------------
always @(posedge fcnvt_ex1_pipe_clk)
begin
if(fcnvt_ex1_pipedown) begin
ex2_tail[24:0] <= ex1_final_tail[24:0];
ex2_sign <= ex1_final_sign;
ex2_dest_float <= ex1_dest_float;
ex2_dest_si <= ex1_dest_si;
ex2_src_is_0 <= ex1_src_is_0;
ex2_exp[8:0] <= ex1_final_exp[8:0];
ex2_special_nv <= ex1_special_nv;
ex2_special_vld <= fcnvt_ex1_borrow_vld;
ex2_fspu_vld <= fspu_ex1_rtu_wb_vld;
end
end
always @(posedge fcnvt_ex1_pipe_clk)
begin
if(fcnvt_ex1_pipedown && (fcnvt_ex1_op_ftoi || fcnvt_ex1_borrow_vld) || ctrl_xx_ex1_warm_up ) begin
ex2_int_r[31:0] <= fcnvt_ex1_comb_int_rslt[31:0];
end
end
always @(posedge fcnvt_ex1_pipe_clk)
begin
if(fcnvt_ex1_pipedown && fcnvt_dest_f || ctrl_xx_ex1_warm_up) begin
ex2_frac[23:0] <= ex1_final_frac[23:0];
end
end
//==============================================================================
// EX2 Operation:
//==============================================================================
assign ex2_expnt[8:0] = ex2_exp[8:0];
assign ex2_int[31:0] = ex2_int_r[31:0];
assign ex2_rm_rne = dp_xx_ex2_rm[2:0] == 3'b000;
assign ex2_rm_rup = dp_xx_ex2_rm[2:0] == 3'b011;
assign ex2_rm_rdn = dp_xx_ex2_rm[2:0] == 3'b010;
assign ex2_rm_rmm = dp_xx_ex2_rm[2:0] == 3'b100;
//frac rounding
assign ex2_x_zero = ~|ex2_tail[24:0];
assign ex2_x_eq_0p5 = ex2_tail[24] && (~|ex2_tail[23:0]);
assign ex2_x_gt_0p5 = ex2_tail[24] && (|ex2_tail[23:0]);
//------------------------------------------------------------------------------
// EX2 rounding:
//------------------------------------------------------------------------------
assign ex2_int_lst = ex2_int[0];
assign ex2_frac_lst = ex2_frac[0];
assign ex2_rnd_lst = ex2_dest_float ? ex2_frac_lst : ex2_int_lst;
assign ex2_round_add = (ex2_rm_rup && !ex2_sign && (!ex2_x_zero)) ||
(ex2_rm_rdn && ex2_sign && (!ex2_x_zero)) ||
(ex2_rm_rmm) && (ex2_x_gt_0p5 || ex2_x_eq_0p5) ||
(ex2_rm_rne && (ex2_x_gt_0p5 || (ex2_x_eq_0p5 && ex2_rnd_lst))); // round add 1
assign ex2_rnd_adder_f_src0[32:0] = ex2_dest_float ? {9'b0, ex2_frac[23:0]} : {ex2_rnd_adder_i_src0[32:0]};
assign ex2_rnd_adder_f_src1[32:0] = 33'b1;
assign ex2_rnd_adder_f_p1[32:0] = ex2_rnd_adder_f_src0[32:0] + ex2_rnd_adder_f_src1[32:0];
assign ex2_rnd_adder_i_p1[32:0] = ex2_rnd_adder_f_p1[32:0];
assign ex2_rnd_adder_i_src0[32:0] = ex2_dest_si && ex2_sign ? {1'b1, ~ex2_int[31:0]}
: {1'b0, ex2_int[31:0]};
assign ex2_orig_f[23:0] = ex2_frac[23:0];
assign ex2_single_f[22:0] = ex2_round_add ? ex2_rnd_adder_f_p1[22:0] : ex2_orig_f[22:0];
//------------------------------------------------------------------------------
// EX2 normal result:
//------------------------------------------------------------------------------
// int normal result
assign ex2_int_nm_result[32:0] = ex2_sign ^ ex2_round_add ? ex2_rnd_adder_i_p1[32:0]
: ex2_rnd_adder_i_src0[32:0];
assign ex2_uint_nm_result[32:0] = (ex2_round_add ? ex2_rnd_adder_i_p1[32:0]
: ex2_rnd_adder_i_src0[32:0]) & {33{!ex2_sign}};
assign ex2_eadder_bias[8:0] = 9'd127;
assign ex2_eadder_bias1[8:0] = 9'd128;
assign ex2_expnt_add1 = single_expnt_add;
assign ex2_expnt_src1[8:0] = ex2_expnt_add1 ? ex2_eadder_bias1[8:0] : ex2_eadder_bias[8:0];
assign ex2_norm_expnt[8:0] = ex2_expnt[8:0] + ex2_expnt_src1[8:0];
//assign ex2_single_denorm = ex2_norm_expnt[8];
// normal result
//assign ex2_double_norm_result[63:0] = {ex2_sign, ex2_norm_expnt[10:0], ex2_double_f[51:0]};
assign ex2_single_norm_result[31:0] = {ex2_sign, ex2_norm_expnt[7:0], ex2_single_f[22:0]};
//------------------------------------------------------------------------------
// EX2 exception:
//------------------------------------------------------------------------------
//1. Dest is Int:
//NV : 1. the float number is out of range of int
//NX : 1. tail is not zero
//2. Int to Float
//NX : 1. tail is not zero
//3. Double to Single
//NX : 1. tail is not zero
// 2. of
// 3. uf
//OF : 1. input is not nan or inf, and e > 8'b11111110
//UF : 1. input is not zero, and e < 381
// Dest is float
assign single_norm_f_all_1 = &ex2_frac[22:0];
assign single_expnt_add = single_norm_f_all_1 && ex2_round_add;
assign ex2_single_of = 1'b0;
assign ex2_single_uf = 1'b0;
assign ex2_expt_of = ex2_single_of;
assign ex2_expt_uf = ex2_single_uf;
assign ex2_expt_nx_t = !ex2_x_zero; // including int nx
assign ex2_expt_nv_f = 1'b0;
// Dest is int
assign ex2_tosi_pos_exp_of = !ex2_expnt[8] && (ex2_expnt[7:0] > 8'd30);
assign ex2_tosi_neg_exp_of = !ex2_expnt[8] && (ex2_expnt[7:0] > 8'd31);
assign ex2_tosi_neg_exp_crit_of = ex2_expnt[8:0] == 9'd31;
assign ex2_tosi_of = ex2_dest_si && !ex2_sign && (ex2_tosi_pos_exp_of || ex2_int_nm_result[31]);
assign ex2_tosi_uf = ex2_dest_si && ex2_sign && (ex2_tosi_neg_exp_of || ex2_tosi_neg_exp_crit_of && !ex2_int_nm_result[31]);
assign ex2_toui_exp_of = !ex2_expnt[8] && (ex2_expnt[7:0] > 8'd31);
assign ex2_toui_of = !ex2_dest_si && !ex2_sign && (ex2_toui_exp_of || ex2_uint_nm_result[32]);
assign ex2_toui_uf = !ex2_dest_si && ex2_sign && (!ex2_expnt[8] || ex2_round_add);
assign ex2_expt_nv_i = ex2_tosi_of || ex2_tosi_uf ||
ex2_toui_of || ex2_toui_uf;
assign ex2_expt_nv = !ex2_dest_float && ex2_expt_nv_i || ex2_expt_nv_f;
// Finally, NX expt, here nx_t include uf
assign ex2_expt_nx = !ex2_expt_nv && (ex2_expt_of || ex2_expt_nx_t);
assign ex2_expt[3:0] = ex2_special_vld ? {ex2_special_nv,3'b0}
: {ex2_expt_nv, ex2_expt_of, ex2_expt_uf, ex2_expt_nx};
//------------------------------------------------------------------------------
// EX2 special result:
//------------------------------------------------------------------------------
assign ex2_single_result[31:0] = ex2_src_is_0 ? 32'b0 : ex2_single_norm_result[31:0];
//------------------------------------------------------------------------------
// EX2 Merge final results:
//------------------------------------------------------------------------------
assign ex2_float_result[31:0] = ex2_single_result[31:0];
//int result
assign int_dest_max_si = ex2_dest_si && (ex2_tosi_of);
assign int_dest_min_si = ex2_dest_si && ex2_tosi_uf;
assign ex2_si_result[31:0] = int_dest_max_si ? {1'b0,{31{1'b1}}} :
int_dest_min_si ? {1'b1,31'b0}
: ex2_int_nm_result[31:0];
assign int_dest_max_ui = !ex2_dest_si && (ex2_toui_of);
assign ex2_ui_result[31:0] = int_dest_max_ui ? {32{1'b1}} :
ex2_toui_uf ? {32{1'b0}}
: ex2_uint_nm_result[31:0];
assign ex2_int_result[31:0] = ex2_special_vld ? ex2_int_r[31:0] :
ex2_dest_si ? ex2_si_result[31:0]
: ex2_ui_result[31:0];
assign ex2_dest_sel_float = ex2_dest_float ;
assign ex2_total_result[31:0] = ex2_dest_sel_float
& ~ex2_special_vld ? ex2_float_result[31:0]
: ex2_int_result[31:0];
//------------------------------------------------------------------------------
// EX2 pipedown to EX3:
//------------------------------------------------------------------------------
always @(posedge fcnvt_ex2_pipe_clk)
begin
if(fcnvt_ex2_pipedown)
begin
ex3_expt[3:0] <= ex2_expt[3:0];
ex3_result[31:0] <= ex2_total_result[31:0];
ex3_dest_float <= ex2_dest_float;
ex3_special_vld <= ex2_special_vld;
ex3_fspu_vld <= ex2_fspu_vld;
end
end
assign fcnvt_ex3_result[31:0] = ex3_result[31:0];
assign fcnvt_ex3_expt[4:0] = {ex3_expt[3], 1'b0, ex3_expt[2:0]};
//------------------------------------------------------------------------------
// EX3 float result rename for output:
//------------------------------------------------------------------------------
assign fcnvt_ex3_dp_fflags[4:0] = fcnvt_ex3_expt[4:0];
assign fcnvt_ex3_dp_rst[31:0] = fcnvt_ex3_result[31:0];
assign fcnvt_ex3_dp_wb_vld = ex3_dest_float && ~ex3_special_vld && fcnvt_ex3_sel && falu_ctrl_xx_ex3_vld;
assign fcnvt_ex3_fspu_vld = ex3_fspu_vld;
//------------------------------------------------------------------------------
// EX3 int result rename for output:
//------------------------------------------------------------------------------
assign fcnvt_ex3_rtu_fflags[4:0] = fcnvt_ex3_expt[4:0];
assign fcnvt_ex3_rtu_rst[31:0] = fcnvt_ex3_result[31:0];
assign fcnvt_ex3_rtu_wb_vld = (!ex3_dest_float & ~ex3_special_vld | ex3_special_vld) && fcnvt_ex3_sel && falu_ctrl_xx_ex3_vld;
// &ModuleEnd; @483
endmodule

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opene906/E906_RTL_FACTORY/gen_rtl/falu/rtl/pa_fspu_single.v Normal file
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@ -0,0 +1,234 @@
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_fspu_single(
dp_xx_ex1_id,
dp_xx_ex1_inf,
dp_xx_ex1_norm,
dp_xx_ex1_qnan,
dp_xx_ex1_snan,
dp_xx_ex1_zero,
falu_ctrl_xx_ex1_vld,
fspu_ex1_dp_fflags,
fspu_ex1_dp_special_result,
fspu_ex1_dp_special_sel,
fspu_ex1_dp_special_sign,
fspu_ex1_dp_wb_vld,
fspu_ex1_rtu_rst,
fspu_ex1_rtu_wb_vld,
fspu_ex1_rtu_wb_vld_gate,
fspu_sel,
fspu_sel_dp,
fspu_sel_gate,
idu_fpu_ex1_func,
idu_fpu_ex1_srcf0,
idu_fpu_ex1_srcf1,
idu_fpu_ex1_srci
);
// &Ports; @24
input [2 :0] dp_xx_ex1_id;
input [2 :0] dp_xx_ex1_inf;
input [2 :0] dp_xx_ex1_norm;
input [2 :0] dp_xx_ex1_qnan;
input [2 :0] dp_xx_ex1_snan;
input [2 :0] dp_xx_ex1_zero;
input falu_ctrl_xx_ex1_vld;
input fspu_sel;
input fspu_sel_dp;
input fspu_sel_gate;
input [9 :0] idu_fpu_ex1_func;
input [31:0] idu_fpu_ex1_srcf0;
input [31:0] idu_fpu_ex1_srcf1;
input [31:0] idu_fpu_ex1_srci;
output [4 :0] fspu_ex1_dp_fflags;
output [31:0] fspu_ex1_dp_special_result;
output [7 :0] fspu_ex1_dp_special_sel;
output [2 :0] fspu_ex1_dp_special_sign;
output fspu_ex1_dp_wb_vld;
output [31:0] fspu_ex1_rtu_rst;
output fspu_ex1_rtu_wb_vld;
output fspu_ex1_rtu_wb_vld_gate;
// &Regs; @25
// &Wires; @26
wire [2 :0] dp_xx_ex1_id;
wire [2 :0] dp_xx_ex1_inf;
wire [2 :0] dp_xx_ex1_norm;
wire [2 :0] dp_xx_ex1_qnan;
wire [2 :0] dp_xx_ex1_snan;
wire [2 :0] dp_xx_ex1_zero;
wire [31:0] ex1_class_r;
wire ex1_dest_f;
wire ex1_dest_i;
wire [31:0] ex1_f_rst;
wire [31:0] ex1_fmvwx_r;
wire [31:0] ex1_fmvxw_r;
wire [31:0] ex1_fsgnj_r;
wire [31:0] ex1_fsgnjn_r;
wire [31:0] ex1_fsgnjx_r;
wire [31:0] ex1_i_rst;
wire [31:0] ex1_int_src;
wire [31:0] ex1_op0_single;
wire [31:0] ex1_op1_single;
wire ex1_op_class;
wire ex1_op_fmvwx;
wire ex1_op_fmvxw;
wire ex1_op_fsgnj;
wire ex1_op_fsgnjn;
wire ex1_op_fsgnjx;
wire [31:0] ex1_src0;
wire ex1_src0_dn;
wire ex1_src0_inf;
wire ex1_src0_norm;
wire ex1_src0_qnan;
wire ex1_src0_sign;
wire ex1_src0_snan;
wire ex1_src0_zero;
wire [31:0] ex1_src1;
wire ex1_src1_sign;
wire falu_ctrl_xx_ex1_vld;
wire [4 :0] fspu_ex1_dp_fflags;
wire [31:0] fspu_ex1_dp_special_result;
wire [7 :0] fspu_ex1_dp_special_sel;
wire [2 :0] fspu_ex1_dp_special_sign;
wire fspu_ex1_dp_wb_vld;
wire [31:0] fspu_ex1_rtu_rst;
wire fspu_ex1_rtu_wb_vld;
wire fspu_ex1_rtu_wb_vld_gate;
wire fspu_sel;
wire fspu_sel_dp;
wire fspu_sel_gate;
wire [9 :0] idu_fpu_ex1_func;
wire [31:0] idu_fpu_ex1_srcf0;
wire [31:0] idu_fpu_ex1_srcf1;
wire [31:0] idu_fpu_ex1_srci;
// &Force("bus", "dp_xx_ex1_snan", 2, 0); @28
// &Force("bus", "dp_xx_ex1_qnan", 2, 0); @29
// &Force("bus", "dp_xx_ex1_norm", 2, 0); @30
// &Force("bus", "dp_xx_ex1_zero", 2, 0); @31
// &Force("bus", "dp_xx_ex1_inf", 2, 0); @32
// &Force("bus", "dp_xx_ex1_id", 2, 0); @33
// &Force("bus", "idu_fpu_ex1_func", 9, 0); @34
//------------------------------------------------------------------------------
// Interface with idu and fpu:
//------------------------------------------------------------------------------
assign ex1_src0[31:0] = {32{fspu_sel_dp}} & idu_fpu_ex1_srcf0[31:0];
assign ex1_src1[31:0] = {32{fspu_sel_dp}} & idu_fpu_ex1_srcf1[31:0];
assign ex1_int_src[31:0] = idu_fpu_ex1_srci[31:0];
//assign fspu_sel = ctrl_falu_ex1_sel && idu_fpu_ex1_func[2];
//assign fspu_ex1_sel = fspu_sel;
assign ex1_op_fsgnjx = idu_fpu_ex1_func[6] && idu_fpu_ex1_func[4];
assign ex1_op_fsgnjn = idu_fpu_ex1_func[6] && !idu_fpu_ex1_func[3] && !idu_fpu_ex1_func[4];
assign ex1_op_fsgnj = idu_fpu_ex1_func[6] && idu_fpu_ex1_func[3];
assign ex1_op_fmvwx = idu_fpu_ex1_func[7] && idu_fpu_ex1_func[3];
assign ex1_op_fmvxw = idu_fpu_ex1_func[5] && idu_fpu_ex1_func[3];
assign ex1_op_class = idu_fpu_ex1_func[5] && idu_fpu_ex1_func[4];
assign ex1_dest_f = idu_fpu_ex1_func[6] || idu_fpu_ex1_func[7] && !idu_fpu_ex1_func[4];
assign ex1_dest_i = idu_fpu_ex1_func[5] || idu_fpu_ex1_func[7] && idu_fpu_ex1_func[4];
assign ex1_src0_snan = dp_xx_ex1_snan[0];
assign ex1_src0_qnan = dp_xx_ex1_qnan[0];
assign ex1_src0_norm = dp_xx_ex1_norm[0];
assign ex1_src0_zero = dp_xx_ex1_zero[0];
assign ex1_src0_inf = dp_xx_ex1_inf[0];
assign ex1_src0_dn = dp_xx_ex1_id[0];
assign ex1_src0_sign = ex1_op0_single[31];
assign ex1_src1_sign = ex1_op1_single[31];
assign ex1_op0_single[31:0] = ex1_src0[31:0];
assign ex1_op1_single[31:0] = ex1_src1[31:0];
//------------------------------------------------------------------------------
// FCLASS Instruction:
//------------------------------------------------------------------------------
//class: r[9:0] = {qnan, snan, +inf, +nm, +dn, +0, -0, -dn, -nm, -inf}
assign ex1_class_r[31:0] = {
22'b0,
ex1_src0_qnan,
ex1_src0_snan,
!ex1_src0_sign && ex1_src0_inf,
!ex1_src0_sign && ex1_src0_norm && !ex1_src0_dn,
!ex1_src0_sign && ex1_src0_dn,
!ex1_src0_sign && ex1_src0_zero,
ex1_src0_sign && ex1_src0_zero,
ex1_src0_sign && ex1_src0_dn,
ex1_src0_sign && ex1_src0_norm && !ex1_src0_dn,
ex1_src0_sign && ex1_src0_inf};
//------------------------------------------------------------------------------
// FSGNJ Instruction:
//------------------------------------------------------------------------------
//fsgnjx : r_s = s0_s ^ s1_s
//fsgnjn : r_s = ~s1_s
//fsgnj : r_s = s1_s
assign ex1_fsgnjx_r[31:0] = {ex1_src0_sign ^ ex1_src1_sign, ex1_op0_single[30:0]};
assign ex1_fsgnjn_r[31:0] = {~ex1_src1_sign, ex1_op0_single[30:0]};
assign ex1_fsgnj_r[31:0] = {ex1_src1_sign, ex1_op0_single[30:0]};
//------------------------------------------------------------------------------
// FMV Instruction:
//------------------------------------------------------------------------------
//fmv.x.w : mov low 32bits float to int regsiter
//fmv.w.x : mov from int register to low 32bit float regsiter
assign ex1_fmvwx_r[31:0] = ex1_int_src[31:0];
assign ex1_fmvxw_r[31:0] = ex1_src0[31:0];
//------------------------------------------------------------------------------
// Merge float and int result:
//------------------------------------------------------------------------------
assign ex1_f_rst[31:0] = {32{ex1_op_fsgnjx}} & ex1_fsgnjx_r[31:0] |
{32{ex1_op_fsgnjn}} & ex1_fsgnjn_r[31:0] |
{32{ex1_op_fsgnj}} & ex1_fsgnj_r[31:0] |
{32{ex1_op_fmvwx}} & ex1_fmvwx_r[31:0];
assign ex1_i_rst[31:0] = {32{ex1_op_fmvxw}} & ex1_fmvxw_r[31:0] |
{32{ex1_op_class}} & ex1_class_r[31:0];
//------------------------------------------------------------------------------
// Float result rename for output:
//------------------------------------------------------------------------------
assign fspu_ex1_dp_wb_vld = fspu_sel && ex1_dest_f && falu_ctrl_xx_ex1_vld;
assign fspu_ex1_dp_special_sel[7:0] = {1'b1, 7'b0};
assign fspu_ex1_dp_fflags[4:0] = 5'b0;
//------------------------------------------------------------------------------
// Int result rename for output:
//------------------------------------------------------------------------------
assign fspu_ex1_rtu_wb_vld = fspu_sel && ex1_dest_i && falu_ctrl_xx_ex1_vld;
assign fspu_ex1_rtu_wb_vld_gate = fspu_sel_gate && ex1_dest_i && falu_ctrl_xx_ex1_vld;
assign fspu_ex1_rtu_rst[31:0] = ex1_i_rst[31:0];
//assign fspu_ex1_rtu_fflags[4:0] = 5'b0;
assign fspu_ex1_dp_special_sign[2:0] = 3'b0;
assign fspu_ex1_dp_special_result[31:0] = ex1_f_rst[31:0];
// &ModuleEnd; @137
endmodule

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opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_ctrl.v Normal file
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_fdsu_ctrl(
cp0_fpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
ctrl_fdsu_ex1_sel,
ctrl_xx_ex1_cmplt_dp,
ctrl_xx_ex1_inst_vld,
ctrl_xx_ex1_stall,
ctrl_xx_ex1_warm_up,
ctrl_xx_ex2_warm_up,
ctrl_xx_ex3_warm_up,
ex1_div,
ex1_expnt_adder_op0,
ex1_of_result_lfn,
ex1_op0_id,
ex1_op0_norm,
ex1_op1_id_vld,
ex1_op1_norm,
ex1_op1_sel,
ex1_oper_id_expnt,
ex1_oper_id_expnt_f,
ex1_pipedown,
ex1_pipedown_gate,
ex1_result_sign,
ex1_rm,
ex1_save_op0,
ex1_save_op0_gate,
ex1_sqrt,
ex1_srt_skip,
ex2_expnt_adder_op0,
ex2_of,
ex2_pipe_clk,
ex2_pipedown,
ex2_potnt_of,
ex2_potnt_uf,
ex2_result_inf,
ex2_result_lfn,
ex2_rslt_denorm,
ex2_srt_expnt_rst,
ex2_srt_first_round,
ex2_uf,
ex2_uf_srt_skip,
ex3_expnt_adjust_result,
ex3_pipedown,
ex3_rslt_denorm,
fdsu_ex1_sel,
fdsu_fpu_debug_info,
fdsu_fpu_ex1_cmplt,
fdsu_fpu_ex1_cmplt_dp,
fdsu_fpu_ex1_stall,
fdsu_fpu_no_op,
fdsu_frbus_wb_vld,
fdsu_yy_div,
fdsu_yy_expnt_rst,
fdsu_yy_of,
fdsu_yy_of_rm_lfn,
fdsu_yy_op0_norm,
fdsu_yy_op1_norm,
fdsu_yy_potnt_of,
fdsu_yy_potnt_uf,
fdsu_yy_result_inf,
fdsu_yy_result_lfn,
fdsu_yy_result_sign,
fdsu_yy_rm,
fdsu_yy_rslt_denorm,
fdsu_yy_sqrt,
fdsu_yy_uf,
fdsu_yy_wb_freg,
forever_cpuclk,
frbus_fdsu_wb_grant,
idu_fpu_ex1_dst_freg,
idu_fpu_ex1_eu_sel,
pad_yy_icg_scan_en,
rtu_xx_ex1_cancel,
rtu_xx_ex2_cancel,
rtu_yy_xx_async_flush,
rtu_yy_xx_flush,
srt_remainder_zero,
srt_sm_on
);
// &Ports; @24
input cp0_fpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input ctrl_fdsu_ex1_sel;
input ctrl_xx_ex1_cmplt_dp;
input ctrl_xx_ex1_inst_vld;
input ctrl_xx_ex1_stall;
input ctrl_xx_ex1_warm_up;
input ctrl_xx_ex2_warm_up;
input ctrl_xx_ex3_warm_up;
input ex1_div;
input [12:0] ex1_expnt_adder_op0;
input ex1_of_result_lfn;
input ex1_op0_id;
input ex1_op0_norm;
input ex1_op1_id_vld;
input ex1_op1_norm;
input [12:0] ex1_oper_id_expnt;
input ex1_result_sign;
input [2 :0] ex1_rm;
input ex1_sqrt;
input ex1_srt_skip;
input ex2_of;
input ex2_potnt_of;
input ex2_potnt_uf;
input ex2_result_inf;
input ex2_result_lfn;
input ex2_rslt_denorm;
input [9 :0] ex2_srt_expnt_rst;
input ex2_uf;
input ex2_uf_srt_skip;
input [9 :0] ex3_expnt_adjust_result;
input ex3_rslt_denorm;
input forever_cpuclk;
input frbus_fdsu_wb_grant;
input [4 :0] idu_fpu_ex1_dst_freg;
input [2 :0] idu_fpu_ex1_eu_sel;
input pad_yy_icg_scan_en;
input rtu_xx_ex1_cancel;
input rtu_xx_ex2_cancel;
input rtu_yy_xx_async_flush;
input rtu_yy_xx_flush;
input srt_remainder_zero;
output ex1_op1_sel;
output [12:0] ex1_oper_id_expnt_f;
output ex1_pipedown;
output ex1_pipedown_gate;
output ex1_save_op0;
output ex1_save_op0_gate;
output [9 :0] ex2_expnt_adder_op0;
output ex2_pipe_clk;
output ex2_pipedown;
output ex2_srt_first_round;
output ex3_pipedown;
output fdsu_ex1_sel;
output [4 :0] fdsu_fpu_debug_info;
output fdsu_fpu_ex1_cmplt;
output fdsu_fpu_ex1_cmplt_dp;
output fdsu_fpu_ex1_stall;
output fdsu_fpu_no_op;
output fdsu_frbus_wb_vld;
output fdsu_yy_div;
output [9 :0] fdsu_yy_expnt_rst;
output fdsu_yy_of;
output fdsu_yy_of_rm_lfn;
output fdsu_yy_op0_norm;
output fdsu_yy_op1_norm;
output fdsu_yy_potnt_of;
output fdsu_yy_potnt_uf;
output fdsu_yy_result_inf;
output fdsu_yy_result_lfn;
output fdsu_yy_result_sign;
output [2 :0] fdsu_yy_rm;
output fdsu_yy_rslt_denorm;
output fdsu_yy_sqrt;
output fdsu_yy_uf;
output [4 :0] fdsu_yy_wb_freg;
output srt_sm_on;
// &Regs; @25
reg ex2_srt_first_round;
reg [2 :0] fdsu_cur_state;
reg fdsu_div;
reg [9 :0] fdsu_expnt_rst;
reg [2 :0] fdsu_next_state;
reg fdsu_of;
reg fdsu_of_rm_lfn;
reg fdsu_potnt_of;
reg fdsu_potnt_uf;
reg fdsu_result_inf;
reg fdsu_result_lfn;
reg fdsu_result_sign;
reg [2 :0] fdsu_rm;
reg fdsu_sqrt;
reg fdsu_uf;
reg [4 :0] fdsu_wb_freg;
reg fdsu_yy_rslt_denorm;
reg [4 :0] srt_cnt;
reg [1 :0] wb_cur_state;
reg [1 :0] wb_nxt_state;
// &Wires; @26
wire cp0_fpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire ctrl_fdsu_ex1_sel;
wire ctrl_fdsu_ex1_stall;
wire ctrl_fdsu_wb_vld;
wire ctrl_iter_start;
wire ctrl_iter_start_gate;
wire ctrl_pack;
wire ctrl_result_vld;
wire ctrl_round;
wire ctrl_sm_cmplt;
wire ctrl_sm_ex1;
wire ctrl_sm_idle;
wire ctrl_sm_start;
wire ctrl_sm_start_gate;
wire ctrl_srt_idle;
wire ctrl_srt_itering;
wire ctrl_wb_idle;
wire ctrl_wb_sm_cmplt;
wire ctrl_wb_sm_ex2;
wire ctrl_wb_sm_idle;
wire ctrl_wfi2;
wire ctrl_wfwb;
wire ctrl_xx_ex1_cmplt_dp;
wire ctrl_xx_ex1_inst_vld;
wire ctrl_xx_ex1_stall;
wire ctrl_xx_ex1_warm_up;
wire ctrl_xx_ex2_warm_up;
wire ctrl_xx_ex3_warm_up;
wire ex1_div;
wire [12:0] ex1_expnt_adder_op0;
wire ex1_of_result_lfn;
wire ex1_op0_id;
wire ex1_op1_id_vld;
wire ex1_op1_sel;
wire [12:0] ex1_oper_id_expnt;
wire [12:0] ex1_oper_id_expnt_f;
wire ex1_pipe_clk;
wire ex1_pipe_clk_en;
wire ex1_pipedown;
wire ex1_pipedown_gate;
wire ex1_result_sign;
wire [2 :0] ex1_rm;
wire ex1_save_op0;
wire ex1_save_op0_gate;
wire ex1_sqrt;
wire ex1_srt_skip;
wire [4 :0] ex1_wb_freg;
wire [9 :0] ex2_expnt_adder_op0;
wire ex2_of;
wire ex2_pipe_clk;
wire ex2_pipe_clk_en;
wire ex2_pipedown;
wire ex2_potnt_of;
wire ex2_potnt_uf;
wire ex2_result_inf;
wire ex2_result_lfn;
wire ex2_rslt_denorm;
wire [9 :0] ex2_srt_expnt_rst;
wire ex2_uf;
wire ex2_uf_srt_skip;
wire [9 :0] ex3_expnt_adjust_result;
wire ex3_pipedown;
wire ex3_rslt_denorm;
wire expnt_rst_clk;
wire expnt_rst_clk_en;
wire fdsu_busy;
wire fdsu_clk;
wire fdsu_clk_en;
wire fdsu_dn_stall;
wire fdsu_ex1_inst_vld;
wire fdsu_ex1_res_vld;
wire fdsu_ex1_sel;
wire fdsu_flush;
wire [4 :0] fdsu_fpu_debug_info;
wire fdsu_fpu_ex1_cmplt;
wire fdsu_fpu_ex1_cmplt_dp;
wire fdsu_fpu_ex1_stall;
wire fdsu_fpu_no_op;
wire fdsu_frbus_wb_vld;
wire fdsu_op0_norm;
wire fdsu_op1_norm;
wire fdsu_wb_grant;
wire fdsu_yy_div;
wire [9 :0] fdsu_yy_expnt_rst;
wire fdsu_yy_of;
wire fdsu_yy_of_rm_lfn;
wire fdsu_yy_op0_norm;
wire fdsu_yy_op1_norm;
wire fdsu_yy_potnt_of;
wire fdsu_yy_potnt_uf;
wire fdsu_yy_result_inf;
wire fdsu_yy_result_lfn;
wire fdsu_yy_result_sign;
wire [2 :0] fdsu_yy_rm;
wire fdsu_yy_sqrt;
wire fdsu_yy_uf;
wire [4 :0] fdsu_yy_wb_freg;
wire forever_cpuclk;
wire frbus_fdsu_wb_grant;
wire [4 :0] idu_fpu_ex1_dst_freg;
wire [2 :0] idu_fpu_ex1_eu_sel;
wire pad_yy_icg_scan_en;
wire rtu_xx_ex1_cancel;
wire rtu_xx_ex2_cancel;
wire rtu_yy_xx_async_flush;
wire rtu_yy_xx_flush;
wire [4 :0] srt_cnt_ini;
wire srt_cnt_zero;
wire srt_last_round;
wire srt_remainder_zero;
wire srt_skip;
wire srt_sm_on;
//==========================================================
// Input Signal
//==========================================================
assign ex1_wb_freg[4:0] = idu_fpu_ex1_dst_freg[4:0];
assign fdsu_ex1_inst_vld = ctrl_xx_ex1_inst_vld && ctrl_fdsu_ex1_sel;
assign fdsu_ex1_sel = idu_fpu_ex1_eu_sel[2];
// &Force("input", "idu_fpu_ex1_eu_sel"); &Force("bus", "idu_fpu_ex1_eu_sel", 2, 0); @34
//==========================================================
// FDSU Main State Machine
//==========================================================
assign fdsu_ex1_res_vld = fdsu_ex1_inst_vld && ex1_srt_skip;
assign fdsu_wb_grant = frbus_fdsu_wb_grant;
assign ctrl_iter_start = ctrl_sm_start && !fdsu_dn_stall
|| ctrl_wfi2;
assign ctrl_iter_start_gate = ctrl_sm_start_gate && !fdsu_dn_stall
|| ctrl_wfi2;
assign ctrl_sm_start = fdsu_ex1_inst_vld && ctrl_srt_idle
&& !ex1_srt_skip;
assign ctrl_sm_start_gate = fdsu_ex1_inst_vld && ctrl_srt_idle;
assign srt_last_round = (srt_skip ||
srt_remainder_zero ||
srt_cnt_zero) &&
ctrl_srt_itering;
assign srt_skip = ex2_of ||
ex2_uf_srt_skip;
assign srt_cnt_zero = ~|srt_cnt[4:0];
assign fdsu_dn_stall = ctrl_sm_start && ex1_op1_id_vld;
parameter IDLE = 3'b000;
parameter WFI2 = 3'b001;
parameter ITER = 3'b010;
parameter RND = 3'b011;
parameter PACK = 3'b100;
parameter WFWB = 3'b101;
always @ (posedge fdsu_clk or negedge cpurst_b)
begin
if (!cpurst_b)
fdsu_cur_state[2:0] <= IDLE;
else if (fdsu_flush)
fdsu_cur_state[2:0] <= IDLE;
else
fdsu_cur_state[2:0] <= fdsu_next_state[2:0];
end
// &CombBeg; @76
always @( ctrl_sm_start
or fdsu_dn_stall
or srt_last_round
or fdsu_cur_state[2:0]
or fdsu_wb_grant)
begin
case (fdsu_cur_state[2:0])
IDLE:
begin
if (ctrl_sm_start)
if (fdsu_dn_stall)
fdsu_next_state[2:0] = WFI2;
else
fdsu_next_state[2:0] = ITER;
else
fdsu_next_state[2:0] = IDLE;
end
WFI2:
fdsu_next_state[2:0] = ITER;
ITER:
begin
if (srt_last_round)
fdsu_next_state[2:0] = RND;
else
fdsu_next_state[2:0] = ITER;
end
RND:
fdsu_next_state[2:0] = PACK;
PACK:
begin
if (fdsu_wb_grant)
if (ctrl_sm_start)
if (fdsu_dn_stall)
fdsu_next_state[2:0] = WFI2;
else
fdsu_next_state[2:0] = ITER;
else
fdsu_next_state[2:0] = IDLE;
else
fdsu_next_state[2:0] = WFWB;
end
WFWB:
begin
if (fdsu_wb_grant)
if (ctrl_sm_start)
if (fdsu_dn_stall)
fdsu_next_state[2:0] = WFI2;
else
fdsu_next_state[2:0] = ITER;
else
fdsu_next_state[2:0] = IDLE;
else
fdsu_next_state[2:0] = WFWB;
end
default:
fdsu_next_state[2:0] = IDLE;
endcase
// &CombEnd; @128
end
assign ctrl_sm_idle = fdsu_cur_state[2:0] == IDLE;
assign ctrl_wfi2 = fdsu_cur_state[2:0] == WFI2;
assign ctrl_srt_itering = fdsu_cur_state[2:0] == ITER;
assign ctrl_round = fdsu_cur_state[2:0] == RND;
assign ctrl_pack = fdsu_cur_state[2:0] == PACK;
assign ctrl_wfwb = fdsu_cur_state[2:0] == WFWB;
assign ctrl_sm_cmplt = ctrl_pack || ctrl_wfwb;
assign ctrl_srt_idle = ctrl_sm_idle
|| fdsu_wb_grant;
assign ctrl_sm_ex1 = ctrl_srt_idle || ctrl_wfi2;
//==========================================================
// Iteration Counter
//==========================================================
always @ (posedge fdsu_clk)
begin
if (fdsu_flush)
srt_cnt[4:0] <= 5'b0;
else if (ctrl_iter_start)
srt_cnt[4:0] <= srt_cnt_ini[4:0];
else if (ctrl_srt_itering)
srt_cnt[4:0] <= srt_cnt[4:0] - 5'b1;
else
srt_cnt[4:0] <= srt_cnt[4:0];
end
//srt_cnt_ini[4:0]
//For Double, initial is 5'b11100('d28), calculate 29 round
//For Single, initial is 5'b01110('d14), calculate 15 round
assign srt_cnt_ini[4:0] = 5'b01110;
//fdsu srt first round signal
//For srt calculate special use
always @(posedge fdsu_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ex2_srt_first_round <= 1'b0;
else if(fdsu_flush)
ex2_srt_first_round <= 1'b0;
else if(ex1_pipedown)
ex2_srt_first_round <= 1'b1;
else
ex2_srt_first_round <= 1'b0;
end
//==========================================================
// Write Back State Machine
//==========================================================
parameter WB_IDLE = 2'b00,
WB_EX2 = 2'b10,
WB_CMPLT = 2'b01;
always @ (posedge fdsu_clk or negedge cpurst_b)
begin
if (!cpurst_b)
wb_cur_state[1:0] <= WB_IDLE;
else if (fdsu_flush)
wb_cur_state[1:0] <= WB_IDLE;
else
wb_cur_state[1:0] <= wb_nxt_state[1:0];
end
// &CombBeg; @215
always @( ctrl_fdsu_wb_vld
or fdsu_dn_stall
or ctrl_xx_ex1_stall
or fdsu_ex1_inst_vld
or ctrl_iter_start
or fdsu_ex1_res_vld
or wb_cur_state[1:0])
begin
case(wb_cur_state[1:0])
WB_IDLE:
if (fdsu_ex1_inst_vld)
if (ctrl_xx_ex1_stall || fdsu_ex1_res_vld || fdsu_dn_stall)
wb_nxt_state[1:0] = WB_IDLE;
else
wb_nxt_state[1:0] = WB_EX2;
else
wb_nxt_state[1:0] = WB_IDLE;
WB_EX2:
// if (ctrl_xx_ex2_stall)
// wb_nxt_state[1:0] = WB_EX2;
// else
if (ctrl_fdsu_wb_vld)
if (ctrl_iter_start && !ctrl_xx_ex1_stall)
wb_nxt_state[1:0] = WB_EX2;
else
wb_nxt_state[1:0] = WB_IDLE;
else
wb_nxt_state[1:0] = WB_CMPLT;
WB_CMPLT:
if (ctrl_fdsu_wb_vld)
if (ctrl_iter_start && !ctrl_xx_ex1_stall)
wb_nxt_state[1:0] = WB_EX2;
else
wb_nxt_state[1:0] = WB_IDLE;
else
wb_nxt_state[1:0] = WB_CMPLT;
default:
wb_nxt_state[1:0] = WB_IDLE;
endcase
// &CombEnd; @247
end
assign ctrl_wb_idle = wb_cur_state[1:0] == WB_IDLE
|| wb_cur_state[1:0] == WB_CMPLT && ctrl_fdsu_wb_vld;
assign ctrl_wb_sm_idle = wb_cur_state[1:0] == WB_IDLE;
assign ctrl_wb_sm_ex2 = wb_cur_state[1:0] == WB_EX2;
assign ctrl_wb_sm_cmplt = wb_cur_state[1:0] == WB_EX2
|| wb_cur_state[1:0] == WB_CMPLT;
assign ctrl_result_vld = ctrl_sm_cmplt && ctrl_wb_sm_cmplt;
assign ctrl_fdsu_wb_vld = ctrl_result_vld && frbus_fdsu_wb_grant;
assign ctrl_fdsu_ex1_stall = fdsu_ex1_inst_vld && !ctrl_sm_ex1 && !ctrl_wb_idle
|| fdsu_ex1_inst_vld && fdsu_dn_stall;
//==========================================================
// Flops
//==========================================================
always @(posedge ex1_pipe_clk)
begin
if(ex1_pipedown)
begin
fdsu_wb_freg[4:0] <= ex1_wb_freg[4:0];
fdsu_result_sign <= ex1_result_sign;
fdsu_of_rm_lfn <= ex1_of_result_lfn;
fdsu_div <= ex1_div;
fdsu_sqrt <= ex1_sqrt;
fdsu_rm[2:0] <= ex1_rm[2:0];
end
else
begin
fdsu_wb_freg[4:0] <= fdsu_wb_freg[4:0];
fdsu_result_sign <= fdsu_result_sign;
fdsu_of_rm_lfn <= fdsu_of_rm_lfn;
fdsu_div <= fdsu_div;
fdsu_sqrt <= fdsu_sqrt;
fdsu_rm[2:0] <= fdsu_rm[2:0];
end
end
// In 906 FDSU, if one op0/1 is not norm, it will not enter EX2.
assign fdsu_op0_norm = 1'b1;
assign fdsu_op1_norm = 1'b1;
// &Force("input", "ex1_op0_norm"); @337
// &Force("input", "ex1_op1_norm"); @338
// fdsu_expnt_rst is used to save:
// 1. op0 denormal expnt;
// 2. op0 expnt;
// 3. result expnt.
// &Force("bus", "ex1_oper_id_expnt", 12, 0); @378
// &Force("bus", "ex1_expnt_adder_op0", 12, 0); @379
always @ (posedge expnt_rst_clk)
begin
if (ex1_save_op0)
fdsu_expnt_rst[9:0] <= ex1_oper_id_expnt[9:0];
else if (ex1_pipedown)
fdsu_expnt_rst[9:0] <= ex1_expnt_adder_op0[9:0];
else if (ex2_pipedown)
fdsu_expnt_rst[9:0] <= ex2_srt_expnt_rst[9:0];
else if (ex3_pipedown)
fdsu_expnt_rst[9:0] <= ex3_expnt_adjust_result[9:0];
else
fdsu_expnt_rst[9:0] <= fdsu_expnt_rst[9:0];
end
assign ex1_oper_id_expnt_f[12:0] = {3'b1, fdsu_expnt_rst[9:0]};
always @ (posedge expnt_rst_clk)
begin
if (ex2_pipedown)
fdsu_yy_rslt_denorm <= ex2_rslt_denorm;
else if (ex3_pipedown)
fdsu_yy_rslt_denorm <= ex3_rslt_denorm;
else
fdsu_yy_rslt_denorm <= fdsu_yy_rslt_denorm;
end
// &Force("output", "fdsu_yy_rslt_denorm"); @440
// EX2 signal used in EX3 & EX4
always @ (posedge ex2_pipe_clk)
begin
if (ex2_pipedown)
begin
fdsu_result_inf <= ex2_result_inf;
fdsu_result_lfn <= ex2_result_lfn;
fdsu_of <= ex2_of;
fdsu_uf <= ex2_uf;
fdsu_potnt_of <= ex2_potnt_of;
fdsu_potnt_uf <= ex2_potnt_uf;
end
else
begin
fdsu_result_inf <= fdsu_result_inf;
fdsu_result_lfn <= fdsu_result_lfn;
fdsu_of <= fdsu_of;
fdsu_uf <= fdsu_uf;
fdsu_potnt_of <= fdsu_potnt_of;
fdsu_potnt_uf <= fdsu_potnt_uf;
end
end
//==========================================================
// Flush
//==========================================================
assign fdsu_flush = rtu_xx_ex1_cancel && ctrl_wb_idle
|| rtu_xx_ex2_cancel && ctrl_wb_sm_ex2
|| ctrl_xx_ex1_warm_up
|| rtu_yy_xx_async_flush;
//==========================================================
// ICG
//==========================================================
assign fdsu_busy = fdsu_ex1_inst_vld
|| !ctrl_sm_idle
|| !ctrl_wb_sm_idle;
assign fdsu_clk_en = fdsu_busy
|| !ctrl_sm_idle
|| rtu_yy_xx_flush;
// &Instance("gated_clk_cell", "x_fdsu_clk"); @514
gated_clk_cell x_fdsu_clk (
.clk_in (forever_cpuclk ),
.clk_out (fdsu_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (fdsu_clk_en ),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @515
// .external_en (1'b0), @516
// .global_en (cp0_yy_clk_en), @517
// .module_en (cp0_fpu_icg_en), @518
// .local_en (fdsu_clk_en), @519
// .clk_out (fdsu_clk)); @520
assign ex1_pipe_clk_en = ex1_pipedown_gate;
// &Instance("gated_clk_cell","x_ex1_pipe_clk"); @523
gated_clk_cell x_ex1_pipe_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex1_pipe_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex1_pipe_clk_en ),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @524
// .clk_out (ex1_pipe_clk),//Out Clock @525
// .external_en (1'b0), @526
// .global_en (cp0_yy_clk_en), @527
// .local_en (ex1_pipe_clk_en),//Local Condition @528
// .module_en (cp0_fpu_icg_en) @529
// ); @530
assign ex2_pipe_clk_en = ex2_pipedown;
// &Instance("gated_clk_cell","x_ex2_pipe_clk"); @533
gated_clk_cell x_ex2_pipe_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex2_pipe_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex2_pipe_clk_en ),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @534
// .clk_out (ex2_pipe_clk),//Out Clock @535
// .external_en (1'b0), @536
// .global_en (cp0_yy_clk_en), @537
// .local_en (ex2_pipe_clk_en),//Local Condition @538
// .module_en (cp0_fpu_icg_en) @539
// ); @540
// &Force("output", "ex2_pipe_clk"); @541
assign expnt_rst_clk_en = ex1_save_op0_gate
|| ex1_pipedown_gate
|| ex2_pipedown
|| ex3_pipedown;
// &Instance("gated_clk_cell", "x_expnt_rst_clk"); @547
gated_clk_cell x_expnt_rst_clk (
.clk_in (forever_cpuclk ),
.clk_out (expnt_rst_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (expnt_rst_clk_en ),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @548
// .external_en (1'b0), @549
// .global_en (cp0_yy_clk_en), @550
// .module_en (cp0_fpu_icg_en), @551
// .local_en (expnt_rst_clk_en), @552
// .clk_out (expnt_rst_clk)); @553
//==========================================================
// Output Signal
//==========================================================
assign fdsu_yy_wb_freg[4:0] = fdsu_wb_freg[4:0];
assign fdsu_yy_result_sign = fdsu_result_sign;
assign fdsu_yy_op0_norm = fdsu_op0_norm;
assign fdsu_yy_op1_norm = fdsu_op1_norm;
assign fdsu_yy_of_rm_lfn = fdsu_of_rm_lfn;
assign fdsu_yy_div = fdsu_div;
assign fdsu_yy_sqrt = fdsu_sqrt;
assign fdsu_yy_rm[2:0] = fdsu_rm[2:0];
assign fdsu_yy_expnt_rst[9:0] = fdsu_expnt_rst[9:0];
assign ex2_expnt_adder_op0[9:0] = fdsu_expnt_rst[9:0];
assign fdsu_yy_result_inf = fdsu_result_inf;
assign fdsu_yy_result_lfn = fdsu_result_lfn;
assign fdsu_yy_of = fdsu_of;
assign fdsu_yy_uf = fdsu_uf;
assign fdsu_yy_potnt_of = fdsu_potnt_of;
assign fdsu_yy_potnt_uf = fdsu_potnt_uf;
assign ex1_pipedown = ctrl_iter_start || ctrl_xx_ex1_warm_up;
assign ex1_pipedown_gate = ctrl_iter_start_gate || ctrl_xx_ex1_warm_up;
assign ex2_pipedown = ctrl_srt_itering && srt_last_round || ctrl_xx_ex2_warm_up;
assign ex3_pipedown = ctrl_round || ctrl_xx_ex3_warm_up;
// &Force("output", "ex1_pipedown"); @589
// &Force("output", "ex1_pipedown_gate"); @590
// &Force("output", "ex2_pipedown"); @591
// &Force("output", "ex3_pipedown"); @592
assign srt_sm_on = ctrl_srt_itering;
assign fdsu_fpu_ex1_cmplt = fdsu_ex1_inst_vld;
assign fdsu_fpu_ex1_cmplt_dp = ctrl_xx_ex1_cmplt_dp && idu_fpu_ex1_eu_sel[2];
assign fdsu_fpu_ex1_stall = ctrl_fdsu_ex1_stall;
assign fdsu_frbus_wb_vld = ctrl_result_vld;
// &Force("bus","idu_fpu_ex1_eu_sel",2,0); @600
assign fdsu_fpu_no_op = !fdsu_busy;
assign ex1_op1_sel = ctrl_wfi2;
assign ex1_save_op0 = ctrl_sm_start && ex1_op0_id && ex1_op1_id_vld;
assign ex1_save_op0_gate = ctrl_sm_start_gate && ex1_op0_id && ex1_op1_id_vld;
// &Force("output", "ex1_save_op0"); @605
// &Force("output", "ex1_save_op0_gate"); @606
assign fdsu_fpu_debug_info[4:0] = {wb_cur_state[1:0], fdsu_cur_state[2:0]};
// &ModuleEnd; @610
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_fdsu_ff1(
fanc_shift_num,
frac_bin_val,
frac_num
);
// &Ports; @24
input [51:0] frac_num;
output [51:0] fanc_shift_num;
output [12:0] frac_bin_val;
// &Regs; @25
reg [51:0] fanc_shift_num;
reg [12:0] frac_bin_val;
// &Wires; @26
wire [51:0] frac_num;
// &CombBeg; @28
always @( frac_num[51:0])
begin
casez(frac_num[51:0])
52'b1???????????????????????????????????????????????????: frac_bin_val[12:0] = 13'h0;
52'b01??????????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1fff;
52'b001?????????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ffe;
52'b0001????????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ffd;
52'b00001???????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ffc;
52'b000001??????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ffb;
52'b0000001?????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ffa;
52'b00000001????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff9;
52'b000000001???????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff8;
52'b0000000001??????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff7;
52'b00000000001?????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff6;
52'b000000000001????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff5;
52'b0000000000001???????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff4;
52'b00000000000001??????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff3;
52'b000000000000001?????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff2;
52'b0000000000000001????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff1;
52'b00000000000000001???????????????????????????????????: frac_bin_val[12:0] = 13'h1ff0;
52'b000000000000000001??????????????????????????????????: frac_bin_val[12:0] = 13'h1fef;
52'b0000000000000000001?????????????????????????????????: frac_bin_val[12:0] = 13'h1fee;
52'b00000000000000000001????????????????????????????????: frac_bin_val[12:0] = 13'h1fed;
52'b000000000000000000001???????????????????????????????: frac_bin_val[12:0] = 13'h1fec;
52'b0000000000000000000001??????????????????????????????: frac_bin_val[12:0] = 13'h1feb;
52'b00000000000000000000001?????????????????????????????: frac_bin_val[12:0] = 13'h1fea;
52'b000000000000000000000001????????????????????????????: frac_bin_val[12:0] = 13'h1fe9;
52'b0000000000000000000000001???????????????????????????: frac_bin_val[12:0] = 13'h1fe8;
52'b00000000000000000000000001??????????????????????????: frac_bin_val[12:0] = 13'h1fe7;
52'b000000000000000000000000001?????????????????????????: frac_bin_val[12:0] = 13'h1fe6;
52'b0000000000000000000000000001????????????????????????: frac_bin_val[12:0] = 13'h1fe5;
52'b00000000000000000000000000001???????????????????????: frac_bin_val[12:0] = 13'h1fe4;
52'b000000000000000000000000000001??????????????????????: frac_bin_val[12:0] = 13'h1fe3;
52'b0000000000000000000000000000001?????????????????????: frac_bin_val[12:0] = 13'h1fe2;
52'b00000000000000000000000000000001????????????????????: frac_bin_val[12:0] = 13'h1fe1;
52'b000000000000000000000000000000001???????????????????: frac_bin_val[12:0] = 13'h1fe0;
52'b0000000000000000000000000000000001??????????????????: frac_bin_val[12:0] = 13'h1fdf;
52'b00000000000000000000000000000000001?????????????????: frac_bin_val[12:0] = 13'h1fde;
52'b000000000000000000000000000000000001????????????????: frac_bin_val[12:0] = 13'h1fdd;
52'b0000000000000000000000000000000000001???????????????: frac_bin_val[12:0] = 13'h1fdc;
52'b00000000000000000000000000000000000001??????????????: frac_bin_val[12:0] = 13'h1fdb;
52'b000000000000000000000000000000000000001?????????????: frac_bin_val[12:0] = 13'h1fda;
52'b0000000000000000000000000000000000000001????????????: frac_bin_val[12:0] = 13'h1fd9;
52'b00000000000000000000000000000000000000001???????????: frac_bin_val[12:0] = 13'h1fd8;
52'b000000000000000000000000000000000000000001??????????: frac_bin_val[12:0] = 13'h1fd7;
52'b0000000000000000000000000000000000000000001?????????: frac_bin_val[12:0] = 13'h1fd6;
52'b00000000000000000000000000000000000000000001????????: frac_bin_val[12:0] = 13'h1fd5;
52'b000000000000000000000000000000000000000000001???????: frac_bin_val[12:0] = 13'h1fd4;
52'b0000000000000000000000000000000000000000000001??????: frac_bin_val[12:0] = 13'h1fd3;
52'b00000000000000000000000000000000000000000000001?????: frac_bin_val[12:0] = 13'h1fd2;
52'b000000000000000000000000000000000000000000000001????: frac_bin_val[12:0] = 13'h1fd1;
52'b0000000000000000000000000000000000000000000000001???: frac_bin_val[12:0] = 13'h1fd0;
52'b00000000000000000000000000000000000000000000000001??: frac_bin_val[12:0] = 13'h1fcf;
52'b000000000000000000000000000000000000000000000000001?: frac_bin_val[12:0] = 13'h1fce;
52'b0000000000000000000000000000000000000000000000000001: frac_bin_val[12:0] = 13'h1fcd;
52'b0000000000000000000000000000000000000000000000000000: frac_bin_val[12:0] = 13'h1fcc;
default : frac_bin_val[12:0] = 13'h000;
endcase
// &CombEnd; @85
end
// &CombBeg; @87
always @( frac_num[51:0])
begin
casez(frac_num[51:0])
52'b1???????????????????????????????????????????????????: fanc_shift_num[51:0] = frac_num[51:0];
52'b01??????????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[50:0],1'b0};
52'b001?????????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[49:0],2'b0};
52'b0001????????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[48:0],3'b0};
52'b00001???????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[47:0],4'b0};
52'b000001??????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[46:0],5'b0};
52'b0000001?????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[45:0],6'b0};
52'b00000001????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[44:0],7'b0};
52'b000000001???????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[43:0],8'b0};
52'b0000000001??????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[42:0],9'b0};
52'b00000000001?????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[41:0],10'b0};
52'b000000000001????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[40:0],11'b0};
52'b0000000000001???????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[39:0],12'b0};
52'b00000000000001??????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[38:0],13'b0};
52'b000000000000001?????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[37:0],14'b0};
52'b0000000000000001????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[36:0],15'b0};
52'b00000000000000001???????????????????????????????????: fanc_shift_num[51:0] = {frac_num[35:0],16'b0};
52'b000000000000000001??????????????????????????????????: fanc_shift_num[51:0] = {frac_num[34:0],17'b0};
52'b0000000000000000001?????????????????????????????????: fanc_shift_num[51:0] = {frac_num[33:0],18'b0};
52'b00000000000000000001????????????????????????????????: fanc_shift_num[51:0] = {frac_num[32:0],19'b0};
52'b000000000000000000001???????????????????????????????: fanc_shift_num[51:0] = {frac_num[31:0],20'b0};
52'b0000000000000000000001??????????????????????????????: fanc_shift_num[51:0] = {frac_num[30:0],21'b0};
52'b00000000000000000000001?????????????????????????????: fanc_shift_num[51:0] = {frac_num[29:0],22'b0};
52'b000000000000000000000001????????????????????????????: fanc_shift_num[51:0] = {frac_num[28:0],23'b0};
52'b0000000000000000000000001???????????????????????????: fanc_shift_num[51:0] = {frac_num[27:0],24'b0};
52'b00000000000000000000000001??????????????????????????: fanc_shift_num[51:0] = {frac_num[26:0],25'b0};
52'b000000000000000000000000001?????????????????????????: fanc_shift_num[51:0] = {frac_num[25:0],26'b0};
52'b0000000000000000000000000001????????????????????????: fanc_shift_num[51:0] = {frac_num[24:0],27'b0};
52'b00000000000000000000000000001???????????????????????: fanc_shift_num[51:0] = {frac_num[23:0],28'b0};
52'b000000000000000000000000000001??????????????????????: fanc_shift_num[51:0] = {frac_num[22:0],29'b0};
52'b0000000000000000000000000000001?????????????????????: fanc_shift_num[51:0] = {frac_num[21:0],30'b0};
52'b00000000000000000000000000000001????????????????????: fanc_shift_num[51:0] = {frac_num[20:0],31'b0};
52'b000000000000000000000000000000001???????????????????: fanc_shift_num[51:0] = {frac_num[19:0],32'b0};
52'b0000000000000000000000000000000001??????????????????: fanc_shift_num[51:0] = {frac_num[18:0],33'b0};
52'b00000000000000000000000000000000001?????????????????: fanc_shift_num[51:0] = {frac_num[17:0],34'b0};
52'b000000000000000000000000000000000001????????????????: fanc_shift_num[51:0] = {frac_num[16:0],35'b0};
52'b0000000000000000000000000000000000001???????????????: fanc_shift_num[51:0] = {frac_num[15:0],36'b0};
52'b00000000000000000000000000000000000001??????????????: fanc_shift_num[51:0] = {frac_num[14:0],37'b0};
52'b000000000000000000000000000000000000001?????????????: fanc_shift_num[51:0] = {frac_num[13:0],38'b0};
52'b0000000000000000000000000000000000000001????????????: fanc_shift_num[51:0] = {frac_num[12:0],39'b0};
52'b00000000000000000000000000000000000000001???????????: fanc_shift_num[51:0] = {frac_num[11:0],40'b0};
52'b000000000000000000000000000000000000000001??????????: fanc_shift_num[51:0] = {frac_num[10:0],41'b0};
52'b0000000000000000000000000000000000000000001?????????: fanc_shift_num[51:0] = {frac_num[9:0],42'b0};
52'b00000000000000000000000000000000000000000001????????: fanc_shift_num[51:0] = {frac_num[8:0],43'b0};
52'b000000000000000000000000000000000000000000001???????: fanc_shift_num[51:0] = {frac_num[7:0],44'b0};
52'b0000000000000000000000000000000000000000000001??????: fanc_shift_num[51:0] = {frac_num[6:0],45'b0};
52'b00000000000000000000000000000000000000000000001?????: fanc_shift_num[51:0] = {frac_num[5:0],46'b0};
52'b000000000000000000000000000000000000000000000001????: fanc_shift_num[51:0] = {frac_num[4:0],47'b0};
52'b0000000000000000000000000000000000000000000000001???: fanc_shift_num[51:0] = {frac_num[3:0],48'b0};
52'b00000000000000000000000000000000000000000000000001??: fanc_shift_num[51:0] = {frac_num[2:0],49'b0};
52'b000000000000000000000000000000000000000000000000001?: fanc_shift_num[51:0] = {frac_num[1:0],50'b0};
52'b0000000000000000000000000000000000000000000000000001: fanc_shift_num[51:0] = {frac_num[0:0],51'b0};
52'b0000000000000000000000000000000000000000000000000000: fanc_shift_num[51:0] = {52'b0};
default : fanc_shift_num[51:0] = {52'b0};
endcase
// &CombEnd; @144
end
// &ModuleEnd; @146
endmodule

275
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_fdsu_pack_single(
fdsu_ex4_denorm_to_tiny_frac,
fdsu_ex4_frac,
fdsu_ex4_nx,
fdsu_ex4_potnt_norm,
fdsu_ex4_result_nor,
fdsu_frbus_data,
fdsu_frbus_fflags,
fdsu_frbus_freg,
fdsu_yy_expnt_rst,
fdsu_yy_of,
fdsu_yy_of_rm_lfn,
fdsu_yy_potnt_of,
fdsu_yy_potnt_uf,
fdsu_yy_result_inf,
fdsu_yy_result_lfn,
fdsu_yy_result_sign,
fdsu_yy_rslt_denorm,
fdsu_yy_uf,
fdsu_yy_wb_freg
);
// &Ports; @24
input fdsu_ex4_denorm_to_tiny_frac;
input [25:0] fdsu_ex4_frac;
input fdsu_ex4_nx;
input [1 :0] fdsu_ex4_potnt_norm;
input fdsu_ex4_result_nor;
input [9 :0] fdsu_yy_expnt_rst;
input fdsu_yy_of;
input fdsu_yy_of_rm_lfn;
input fdsu_yy_potnt_of;
input fdsu_yy_potnt_uf;
input fdsu_yy_result_inf;
input fdsu_yy_result_lfn;
input fdsu_yy_result_sign;
input fdsu_yy_rslt_denorm;
input fdsu_yy_uf;
input [4 :0] fdsu_yy_wb_freg;
output [31:0] fdsu_frbus_data;
output [4 :0] fdsu_frbus_fflags;
output [4 :0] fdsu_frbus_freg;
// &Regs; @25
reg [22:0] ex4_frac_23;
reg [31:0] ex4_result;
reg [22:0] ex4_single_denorm_frac;
reg [9 :0] expnt_add_op1;
// &Wires; @26
wire ex4_cor_nx;
wire ex4_cor_uf;
wire ex4_denorm_potnt_norm;
wire [31:0] ex4_denorm_result;
wire [9 :0] ex4_expnt_rst;
wire [4 :0] ex4_expt;
wire ex4_final_rst_norm;
wire [25:0] ex4_frac;
wire ex4_of_plus;
wire ex4_result_inf;
wire ex4_result_lfn;
wire ex4_rslt_denorm;
wire [31:0] ex4_rst_inf;
wire [31:0] ex4_rst_lfn;
wire ex4_rst_nor;
wire [31:0] ex4_rst_norm;
wire ex4_uf_plus;
wire fdsu_ex4_denorm_to_tiny_frac;
wire fdsu_ex4_dz;
wire [9 :0] fdsu_ex4_expnt_rst;
wire [25:0] fdsu_ex4_frac;
wire fdsu_ex4_nv;
wire fdsu_ex4_nx;
wire fdsu_ex4_of;
wire fdsu_ex4_of_rst_lfn;
wire [1 :0] fdsu_ex4_potnt_norm;
wire fdsu_ex4_potnt_of;
wire fdsu_ex4_potnt_uf;
wire fdsu_ex4_result_inf;
wire fdsu_ex4_result_lfn;
wire fdsu_ex4_result_nor;
wire fdsu_ex4_result_sign;
wire fdsu_ex4_rslt_denorm;
wire fdsu_ex4_uf;
wire [31:0] fdsu_frbus_data;
wire [4 :0] fdsu_frbus_fflags;
wire [4 :0] fdsu_frbus_freg;
wire [9 :0] fdsu_yy_expnt_rst;
wire fdsu_yy_of;
wire fdsu_yy_of_rm_lfn;
wire fdsu_yy_potnt_of;
wire fdsu_yy_potnt_uf;
wire fdsu_yy_result_inf;
wire fdsu_yy_result_lfn;
wire fdsu_yy_result_sign;
wire fdsu_yy_rslt_denorm;
wire fdsu_yy_uf;
wire [4 :0] fdsu_yy_wb_freg;
assign fdsu_ex4_result_sign = fdsu_yy_result_sign;
assign fdsu_ex4_of_rst_lfn = fdsu_yy_of_rm_lfn;
assign fdsu_ex4_result_inf = fdsu_yy_result_inf;
assign fdsu_ex4_result_lfn = fdsu_yy_result_lfn;
assign fdsu_ex4_of = fdsu_yy_of;
assign fdsu_ex4_uf = fdsu_yy_uf;
assign fdsu_ex4_potnt_of = fdsu_yy_potnt_of;
assign fdsu_ex4_potnt_uf = fdsu_yy_potnt_uf;
assign fdsu_ex4_nv = 1'b0;
assign fdsu_ex4_dz = 1'b0;
assign fdsu_ex4_expnt_rst[9:0] = fdsu_yy_expnt_rst[9:0];
assign fdsu_ex4_rslt_denorm = fdsu_yy_rslt_denorm;
//============================EX4 STAGE=====================
assign ex4_frac[25:0] = fdsu_ex4_frac[25:0];
//exponent adder
// &CombBeg; @43
always @( ex4_frac[25:24])
begin
casez(ex4_frac[25:24])
2'b00 : expnt_add_op1[9:0] = 10'h1ff; //the expnt sub 1
2'b01 : expnt_add_op1[9:0] = 10'h0; //the expnt stay the origi
2'b1? : expnt_add_op1[9:0] = 10'h1; // the exptn add 1
default : expnt_add_op1[9:0] = 10'b0;
endcase
// &CombEnd; @50
end
assign ex4_expnt_rst[9:0] = fdsu_ex4_expnt_rst[9:0] +
expnt_add_op1[9:0];
//==========================Result Pack=====================
// result denormal pack
// shift to the denormal number
// &CombBeg; @58
always @( fdsu_ex4_expnt_rst[9:0]
or fdsu_ex4_denorm_to_tiny_frac
or ex4_frac[25:1])
begin
case(fdsu_ex4_expnt_rst[9:0])
10'h1: ex4_single_denorm_frac[22:0] = { ex4_frac[23:1]}; //-1022 1
10'h0: ex4_single_denorm_frac[22:0] = { ex4_frac[24:2]}; //-1023 0
10'h3ff:ex4_single_denorm_frac[22:0] = { ex4_frac[25:3]}; //-1024 -1
10'h3fe:ex4_single_denorm_frac[22:0] = {1'b0, ex4_frac[25:4]}; //-1025 -2
10'h3fd:ex4_single_denorm_frac[22:0] = {2'b0, ex4_frac[25:5]}; //-1026 -3
10'h3fc:ex4_single_denorm_frac[22:0] = {3'b0, ex4_frac[25:6]}; //-1027 -4
10'h3fb:ex4_single_denorm_frac[22:0] = {4'b0, ex4_frac[25:7]}; //-1028 -5
10'h3fa:ex4_single_denorm_frac[22:0] = {5'b0, ex4_frac[25:8]}; //-1029 -6
10'h3f9:ex4_single_denorm_frac[22:0] = {6'b0, ex4_frac[25:9]}; //-1030 -7
10'h3f8:ex4_single_denorm_frac[22:0] = {7'b0, ex4_frac[25:10]}; //-1031 -8
10'h3f7:ex4_single_denorm_frac[22:0] = {8'b0, ex4_frac[25:11]}; //-1032 -9
10'h3f6:ex4_single_denorm_frac[22:0] = {9'b0, ex4_frac[25:12]}; //-1033 -10
10'h3f5:ex4_single_denorm_frac[22:0] = {10'b0,ex4_frac[25:13]}; //-1034 -11
10'h3f4:ex4_single_denorm_frac[22:0] = {11'b0,ex4_frac[25:14]}; //-1035 -12
10'h3f3:ex4_single_denorm_frac[22:0] = {12'b0,ex4_frac[25:15]}; //-1036 -13
10'h3f2:ex4_single_denorm_frac[22:0] = {13'b0,ex4_frac[25:16]}; // -1037
10'h3f1:ex4_single_denorm_frac[22:0] = {14'b0,ex4_frac[25:17]}; //-1038
10'h3f0:ex4_single_denorm_frac[22:0] = {15'b0,ex4_frac[25:18]}; //-1039
10'h3ef:ex4_single_denorm_frac[22:0] = {16'b0,ex4_frac[25:19]}; //-1040
10'h3ee:ex4_single_denorm_frac[22:0] = {17'b0,ex4_frac[25:20]}; //-1041
10'h3ed:ex4_single_denorm_frac[22:0] = {18'b0,ex4_frac[25:21]}; //-1042
10'h3ec:ex4_single_denorm_frac[22:0] = {19'b0,ex4_frac[25:22]}; //-1043
10'h3eb:ex4_single_denorm_frac[22:0] = {20'b0,ex4_frac[25:23]}; //-1044
10'h3ea:ex4_single_denorm_frac[22:0] = {21'b0,ex4_frac[25:24]}; //-1044
default :ex4_single_denorm_frac[22:0] = fdsu_ex4_denorm_to_tiny_frac ? 23'b1 : 23'b0; //-1045
endcase
// &CombEnd; @86
end
//here when denormal number round to add1, it will become normal number
assign ex4_denorm_potnt_norm = (fdsu_ex4_potnt_norm[1] && ex4_frac[24]) ||
(fdsu_ex4_potnt_norm[0] && ex4_frac[25]) ;
assign ex4_rslt_denorm = fdsu_ex4_rslt_denorm && !ex4_denorm_potnt_norm;
assign ex4_denorm_result[31:0] = {fdsu_ex4_result_sign,
8'h0,ex4_single_denorm_frac[22:0]};
//ex4 overflow/underflow plus
assign ex4_rst_nor = fdsu_ex4_result_nor;
assign ex4_of_plus = fdsu_ex4_potnt_of &&
(|ex4_frac[25:24]) &&
ex4_rst_nor;
assign ex4_uf_plus = fdsu_ex4_potnt_uf &&
(~|ex4_frac[25:24]) &&
ex4_rst_nor;
//ex4 overflow round result
assign ex4_result_lfn = (ex4_of_plus && fdsu_ex4_of_rst_lfn) ||
fdsu_ex4_result_lfn;
assign ex4_result_inf = (ex4_of_plus && !fdsu_ex4_of_rst_lfn) ||
fdsu_ex4_result_inf;
//Special Result Form
// result largest finity number
assign ex4_rst_lfn[31:0] = {fdsu_ex4_result_sign,8'hfe,{23{1'b1}}};
//result infinity
assign ex4_rst_inf[31:0] = {fdsu_ex4_result_sign,8'hff,23'b0};
//result normal
// &CombBeg; @114
always @( ex4_frac[25:0])
begin
casez(ex4_frac[25:24])
2'b00 : ex4_frac_23[22:0] = ex4_frac[22:0];
2'b01 : ex4_frac_23[22:0] = ex4_frac[23:1];
2'b1? : ex4_frac_23[22:0] = ex4_frac[24:2];
default : ex4_frac_23[22:0] = 23'b0;
endcase
// &CombEnd; @121
end
assign ex4_rst_norm[31:0] = {fdsu_ex4_result_sign,
ex4_expnt_rst[7:0],
ex4_frac_23[22:0]};
assign ex4_cor_uf = (fdsu_ex4_uf && !ex4_denorm_potnt_norm || ex4_uf_plus)
&& fdsu_ex4_nx;
assign ex4_cor_nx = fdsu_ex4_nx
|| fdsu_ex4_of
|| ex4_of_plus;
assign ex4_expt[4:0] = {
fdsu_ex4_nv,
fdsu_ex4_dz,
fdsu_ex4_of | ex4_of_plus,
ex4_cor_uf,
ex4_cor_nx};
assign ex4_final_rst_norm = !ex4_result_inf &&
!ex4_result_lfn &&
!ex4_rslt_denorm;
// &CombBeg; @141
always @( ex4_denorm_result[31:0]
or ex4_result_lfn
or ex4_result_inf
or ex4_final_rst_norm
or ex4_rst_norm[31:0]
or ex4_rst_lfn[31:0]
or ex4_rst_inf[31:0]
or ex4_rslt_denorm)
begin
case({ex4_rslt_denorm,
ex4_result_inf,
ex4_result_lfn,
ex4_final_rst_norm})
4'b1000 : ex4_result[31:0] = ex4_denorm_result[31:0];
4'b0100 : ex4_result[31:0] = ex4_rst_inf[31:0];
4'b0010 : ex4_result[31:0] = ex4_rst_lfn[31:0];
4'b0001 : ex4_result[31:0] = ex4_rst_norm[31:0];
default : ex4_result[31:0] = 32'b0;
endcase
// &CombEnd; @152
end
//==========================================================
// Result Generate
//==========================================================
assign fdsu_frbus_freg[4:0] = fdsu_yy_wb_freg[4:0];
assign fdsu_frbus_data[31:0] = ex4_result[31:0];
assign fdsu_frbus_fflags[4:0] = ex4_expt[4:0];
// &ModuleEnd; @161
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_fdsu_prepare(
dp_xx_ex1_rm,
ex1_div,
ex1_divisor,
ex1_expnt_adder_op0,
ex1_expnt_adder_op1,
ex1_of_result_lfn,
ex1_op0_id,
ex1_op0_sign,
ex1_op1_id,
ex1_op1_id_vld,
ex1_op1_sel,
ex1_oper_id_expnt,
ex1_oper_id_expnt_f,
ex1_oper_id_frac,
ex1_oper_id_frac_f,
ex1_remainder,
ex1_result_sign,
ex1_rm,
ex1_sqrt,
fdsu_ex1_sel,
idu_fpu_ex1_func,
idu_fpu_ex1_srcf0,
idu_fpu_ex1_srcf1
);
// &Ports; @24
input [2 :0] dp_xx_ex1_rm;
input ex1_op0_id;
input ex1_op1_id;
input ex1_op1_sel;
input [12:0] ex1_oper_id_expnt_f;
input [51:0] ex1_oper_id_frac_f;
input fdsu_ex1_sel;
input [9 :0] idu_fpu_ex1_func;
input [31:0] idu_fpu_ex1_srcf0;
input [31:0] idu_fpu_ex1_srcf1;
output ex1_div;
output [23:0] ex1_divisor;
output [12:0] ex1_expnt_adder_op0;
output [12:0] ex1_expnt_adder_op1;
output ex1_of_result_lfn;
output ex1_op0_sign;
output ex1_op1_id_vld;
output [12:0] ex1_oper_id_expnt;
output [51:0] ex1_oper_id_frac;
output [31:0] ex1_remainder;
output ex1_result_sign;
output [2 :0] ex1_rm;
output ex1_sqrt;
// &Regs; @25
reg [12:0] ex1_expnt_adder_op1;
reg ex1_of_result_lfn;
// &Wires; @26
wire div_sign;
wire [2 :0] dp_xx_ex1_rm;
wire ex1_div;
wire [52:0] ex1_div_noid_nor_srt_op0;
wire [52:0] ex1_div_noid_nor_srt_op1;
wire [52:0] ex1_div_nor_srt_op0;
wire [52:0] ex1_div_nor_srt_op1;
wire [12:0] ex1_div_op0_expnt;
wire [12:0] ex1_div_op1_expnt;
wire [52:0] ex1_div_srt_op0;
wire [52:0] ex1_div_srt_op1;
wire [23:0] ex1_divisor;
wire ex1_double;
wire [12:0] ex1_expnt_adder_op0;
wire ex1_op0_id;
wire ex1_op0_id_nor;
wire ex1_op0_sign;
wire ex1_op1_id;
wire ex1_op1_id_nor;
wire ex1_op1_id_vld;
wire ex1_op1_sel;
wire ex1_op1_sign;
wire [63:0] ex1_oper0;
wire [51:0] ex1_oper0_frac;
wire [12:0] ex1_oper0_id_expnt;
wire [51:0] ex1_oper0_id_frac;
wire [63:0] ex1_oper1;
wire [51:0] ex1_oper1_frac;
wire [12:0] ex1_oper1_id_expnt;
wire [51:0] ex1_oper1_id_frac;
wire [51:0] ex1_oper_frac;
wire [12:0] ex1_oper_id_expnt;
wire [12:0] ex1_oper_id_expnt_f;
wire [51:0] ex1_oper_id_frac;
wire [51:0] ex1_oper_id_frac_f;
wire [31:0] ex1_remainder;
wire ex1_result_sign;
wire [2 :0] ex1_rm;
wire ex1_single;
wire ex1_sqrt;
wire ex1_sqrt_expnt_odd;
wire ex1_sqrt_op0_expnt_0;
wire [12:0] ex1_sqrt_op1_expnt;
wire [52:0] ex1_sqrt_srt_op0;
wire fdsu_ex1_sel;
wire [9 :0] idu_fpu_ex1_func;
wire [31:0] idu_fpu_ex1_srcf0;
wire [31:0] idu_fpu_ex1_srcf1;
wire [59:0] sqrt_remainder;
wire sqrt_sign;
parameter FLEN = `FLEN;
assign ex1_sqrt = idu_fpu_ex1_func[0];
assign ex1_div = idu_fpu_ex1_func[1];
assign ex1_oper0[63:0] = {32'b0, idu_fpu_ex1_srcf0[FLEN-1:0] & {32{fdsu_ex1_sel}}};
assign ex1_oper1[63:0] = {32'b0, idu_fpu_ex1_srcf1[FLEN-1:0] & {32{fdsu_ex1_sel}}};
assign ex1_double = 1'b0;
assign ex1_single = 1'b1;
// &Force("bus", "idu_fpu_ex1_func", 9, 0); @43
assign ex1_op0_id_nor = ex1_op0_id;
assign ex1_op1_id_nor = ex1_op1_id;
//Sign bit prepare
assign ex1_op0_sign = ex1_double && ex1_oper0[63]
|| ex1_single && ex1_oper0[31];
assign ex1_op1_sign = ex1_double && ex1_oper1[63]
|| ex1_single && ex1_oper1[31];
assign div_sign = ex1_op0_sign ^ ex1_op1_sign;
assign sqrt_sign = ex1_op0_sign;
assign ex1_result_sign = (ex1_div)
? div_sign
: sqrt_sign;
//=====================find first one=======================
// this is for the denormal number
assign ex1_oper_frac[51:0] = ex1_op1_sel ? ex1_oper1_frac[51:0]
: ex1_oper0_frac[51:0];
// &Instance("pa_fdsu_ff1", "x_frac_expnt"); @63
pa_fdsu_ff1 x_frac_expnt (
.fanc_shift_num (ex1_oper_id_frac[51:0] ),
.frac_bin_val (ex1_oper_id_expnt[12:0]),
.frac_num (ex1_oper_frac[51:0] )
);
// &Connect(.frac_num(ex1_oper_frac[51:0])); @64
// &Connect(.frac_bin_val(ex1_oper_id_expnt[12:0])); @65
// &Connect(.fanc_shift_num(ex1_oper_id_frac[51:0])); @66
// &Force("output", "ex1_oper_id_expnt"); &Force("bus", "ex1_oper_id_expnt", 12, 0); @67
// &Force("output", "ex1_oper_id_frac"); &Force("bus", "ex1_oper_id_frac", 51, 0); @68
assign ex1_oper0_id_expnt[12:0] = ex1_op1_sel ? ex1_oper_id_expnt_f[12:0]
: ex1_oper_id_expnt[12:0];
assign ex1_oper0_id_frac[51:0] = ex1_op1_sel ? ex1_oper_id_frac_f[51:0]
: ex1_oper_id_frac[51:0];
assign ex1_oper1_id_expnt[12:0] = ex1_oper_id_expnt[12:0];
assign ex1_oper1_id_frac[51:0] = ex1_oper_id_frac[51:0];
assign ex1_oper0_frac[51:0] = {52{ex1_double}} & ex1_oper0[51:0]
| {52{ex1_single}} & {ex1_oper0[22:0],29'b0};
assign ex1_oper1_frac[51:0] = {52{ex1_double}} & ex1_oper1[51:0]
| {52{ex1_single}} & {ex1_oper1[22:0],29'b0};
//=====================exponent add=========================
//exponent number 0
assign ex1_div_op0_expnt[12:0] = {13{ex1_double}} & {2'b0,ex1_oper0[62:52]}
| {13{ex1_single}} & {5'b0,ex1_oper0[30:23]};
assign ex1_expnt_adder_op0[12:0] = ex1_op0_id_nor ? ex1_oper0_id_expnt[12:0]
: ex1_div_op0_expnt[12:0];
//exponent number 1
assign ex1_div_op1_expnt[12:0] = {13{ex1_double}} & {2'b0,ex1_oper1[62:52]}
| {13{ex1_single}} & {5'b0,ex1_oper1[30:23]};
assign ex1_sqrt_op1_expnt[12:0] = {13{ex1_double}} & {3'b0,{10{1'b1}}} //'d1023
| {13{ex1_single}} & {6'b0,{7{1'b1}}}; //'d127
// &CombBeg; @93
always @( ex1_oper1_id_expnt[12:0]
or ex1_div
or ex1_op1_id_nor
or ex1_sqrt_op1_expnt[12:0]
or ex1_sqrt
or ex1_div_op1_expnt[12:0])
begin
case({ex1_div,ex1_sqrt})
2'b10: ex1_expnt_adder_op1[12:0] = ex1_op1_id_nor ? ex1_oper1_id_expnt[12:0]
: ex1_div_op1_expnt[12:0];
2'b01: ex1_expnt_adder_op1[12:0] = ex1_sqrt_op1_expnt[12:0];
default: ex1_expnt_adder_op1[12:0] = 13'b0;
endcase
// &CombEnd; @100
end
//ex1_sqrt_expnt_odd
//fraction will shift left by 1
// adder_op0/1 timing is bad.
// assign ex1_sqrt_expnt_odd = ex1_expnt_adder_op0[0] ^ ex1_expnt_adder_op1[0];
// sqrt_odd is only used when is sqrt.
assign ex1_sqrt_op0_expnt_0 = ex1_op0_id_nor ? ex1_oper_id_expnt[0]
: ex1_div_op0_expnt[0];
// ex1_expnt_adder_op1 is always 1'b1, so adder_op0[0] should be 0.
assign ex1_sqrt_expnt_odd = !ex1_sqrt_op0_expnt_0;
assign ex1_rm[2:0] = dp_xx_ex1_rm[2:0];
//RNE : Always inc 1 because round to nearest of 1.111...11
//RTZ : Always not inc 1
//RUP : Always not inc 1 when posetive
//RDN : Always not inc 1 when negative
//RMM : Always inc 1 because round to max magnitude
// &CombBeg; @119
always @( ex1_rm[2:0]
or ex1_result_sign)
begin
case(ex1_rm[2:0])
3'b000 : ex1_of_result_lfn = 1'b0;
3'b001 : ex1_of_result_lfn = 1'b1;
3'b010 : ex1_of_result_lfn = !ex1_result_sign;
3'b011 : ex1_of_result_lfn = ex1_result_sign;
3'b100 : ex1_of_result_lfn = 1'b0;
default: ex1_of_result_lfn = 1'b0;
endcase
// &CombEnd; @128
end
//EX1 Remainder
//div : 1/8 <= x < 1/4
//sqrt : 1/16 <= x < 1/4
assign ex1_remainder[31:0] = {32{ex1_div }} & {5'b0,ex1_div_srt_op0[52:28],2'b0} |
{32{ex1_sqrt}} & sqrt_remainder[59:28];
//EX1 Divisor
//1/2 <= y < 1
assign ex1_divisor[23:0] = ex1_div_srt_op1[52:29];
//ex1_div_srt_op0
assign ex1_div_srt_op0[52:0] = ex1_div_nor_srt_op0[52:0];
//ex1_div_srt_op1
assign ex1_div_srt_op1[52:0] = ex1_div_nor_srt_op1[52:0];
//ex1_div_nor_srt_op0
assign ex1_div_noid_nor_srt_op0[52:0] = {53{ex1_double}} & {1'b1,ex1_oper0[51:0]}
| {53{ex1_single}} & {1'b1,ex1_oper0[22:0],29'b0};
assign ex1_div_nor_srt_op0[52:0] = ex1_op0_id_nor ? {ex1_oper0_id_frac[51:0],1'b0}
: ex1_div_noid_nor_srt_op0[52:0];
//ex1_div_nor_srt_op1
assign ex1_div_noid_nor_srt_op1[52:0] = {53{ex1_double}} & {1'b1,ex1_oper1[51:0]}
| {53{ex1_single}} & {1'b1,ex1_oper1[22:0],29'b0};
assign ex1_div_nor_srt_op1[52:0] = ex1_op1_id_nor ? {ex1_oper1_id_frac[51:0],1'b0}
: ex1_div_noid_nor_srt_op1[52:0];
//sqrt_remainder
assign sqrt_remainder[59:0] = (ex1_sqrt_expnt_odd)
? {5'b0,ex1_sqrt_srt_op0[52:0],2'b0}
: {6'b0,ex1_sqrt_srt_op0[52:0],1'b0};
//ex1_sqrt_srt_op0
assign ex1_sqrt_srt_op0[52:0] = ex1_div_srt_op0[52:0];
//========================Pipe to EX2=======================
//exponent register cal result
// &Force("output", "ex1_expnt_adder_op0"); &Force("bus", "ex1_expnt_adder_op0", 12, 0); @173
// &Force("output", "ex1_expnt_adder_op1"); &Force("bus", "ex1_expnt_adder_op1", 12, 0); @174
// &Force("output", "ex1_double"); @175
// &Force("output", "ex1_expnt_adder_op0"); &Force("bus", "ex1_expnt_adder_op0", 12, 0); @177
// &Force("output", "ex1_expnt_adder_op1"); &Force("bus", "ex1_expnt_adder_op1", 12, 0); @178
// &Force("output", "ex1_result_sign"); @180
// &Force("output", "ex1_div"); @181
// &Force("output", "ex1_sqrt"); @182
// &Force("output", "ex1_rm"); &Force("bus", "ex1_rm", 2, 0); @183
// &Force("output", "ex1_op0_sign"); @184
assign ex1_op1_id_vld = ex1_op1_id_nor && ex1_div;
// &ModuleEnd; @188
endmodule

540
opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_round_single.v Normal file
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@ -0,0 +1,540 @@
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_fdsu_round_single(
cp0_fpu_icg_en,
cp0_yy_clk_en,
ex3_expnt_adjust_result,
ex3_frac_final_rst,
ex3_pipedown,
ex3_rslt_denorm,
fdsu_ex3_id_srt_skip,
fdsu_ex3_rem_sign,
fdsu_ex3_rem_zero,
fdsu_ex3_result_denorm_round_add_num,
fdsu_ex4_denorm_to_tiny_frac,
fdsu_ex4_nx,
fdsu_ex4_potnt_norm,
fdsu_ex4_result_nor,
fdsu_yy_expnt_rst,
fdsu_yy_result_inf,
fdsu_yy_result_lfn,
fdsu_yy_result_sign,
fdsu_yy_rm,
fdsu_yy_rslt_denorm,
forever_cpuclk,
pad_yy_icg_scan_en,
total_qt_rt_30
);
// &Ports; @24
input cp0_fpu_icg_en;
input cp0_yy_clk_en;
input ex3_pipedown;
input fdsu_ex3_id_srt_skip;
input fdsu_ex3_rem_sign;
input fdsu_ex3_rem_zero;
input [23:0] fdsu_ex3_result_denorm_round_add_num;
input [9 :0] fdsu_yy_expnt_rst;
input fdsu_yy_result_inf;
input fdsu_yy_result_lfn;
input fdsu_yy_result_sign;
input [2 :0] fdsu_yy_rm;
input fdsu_yy_rslt_denorm;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input [29:0] total_qt_rt_30;
output [9 :0] ex3_expnt_adjust_result;
output [25:0] ex3_frac_final_rst;
output ex3_rslt_denorm;
output fdsu_ex4_denorm_to_tiny_frac;
output fdsu_ex4_nx;
output [1 :0] fdsu_ex4_potnt_norm;
output fdsu_ex4_result_nor;
// &Regs; @25
reg denorm_to_tiny_frac;
reg fdsu_ex4_denorm_to_tiny_frac;
reg fdsu_ex4_nx;
reg [1 :0] fdsu_ex4_potnt_norm;
reg fdsu_ex4_result_nor;
reg [25:0] frac_add1_op1;
reg frac_add_1;
reg frac_orig;
reg [25:0] frac_sub1_op1;
reg frac_sub_1;
reg [27:0] qt_result_single_denorm_for_round;
reg single_denorm_lst_frac;
// &Wires; @26
wire cp0_fpu_icg_en;
wire cp0_yy_clk_en;
wire ex3_denorm_eq;
wire ex3_denorm_gr;
wire ex3_denorm_lst_frac;
wire ex3_denorm_nx;
wire ex3_denorm_plus;
wire ex3_denorm_potnt_norm;
wire ex3_denorm_zero;
wire [9 :0] ex3_expnt_adjst;
wire [9 :0] ex3_expnt_adjust_result;
wire [25:0] ex3_frac_final_rst;
wire ex3_nx;
wire ex3_pipe_clk;
wire ex3_pipe_clk_en;
wire ex3_pipedown;
wire [1 :0] ex3_potnt_norm;
wire ex3_qt_eq;
wire ex3_qt_gr;
wire ex3_qt_sing_lo3_not0;
wire ex3_qt_sing_lo4_not0;
wire ex3_qt_zero;
wire ex3_rslt_denorm;
wire ex3_rst_eq_1;
wire ex3_rst_nor;
wire ex3_single_denorm_eq;
wire ex3_single_denorm_gr;
wire ex3_single_denorm_zero;
wire ex3_single_low_not_zero;
wire [9 :0] fdsu_ex3_expnt_rst;
wire fdsu_ex3_id_srt_skip;
wire fdsu_ex3_rem_sign;
wire fdsu_ex3_rem_zero;
wire [23:0] fdsu_ex3_result_denorm_round_add_num;
wire fdsu_ex3_result_inf;
wire fdsu_ex3_result_lfn;
wire fdsu_ex3_result_sign;
wire [2 :0] fdsu_ex3_rm;
wire fdsu_ex3_rslt_denorm;
wire [9 :0] fdsu_yy_expnt_rst;
wire fdsu_yy_result_inf;
wire fdsu_yy_result_lfn;
wire fdsu_yy_result_sign;
wire [2 :0] fdsu_yy_rm;
wire fdsu_yy_rslt_denorm;
wire forever_cpuclk;
wire [25:0] frac_add1_op1_with_denorm;
wire [25:0] frac_add1_rst;
wire frac_denorm_rdn_add_1;
wire frac_denorm_rdn_sub_1;
wire frac_denorm_rmm_add_1;
wire frac_denorm_rne_add_1;
wire frac_denorm_rtz_sub_1;
wire frac_denorm_rup_add_1;
wire frac_denorm_rup_sub_1;
wire [25:0] frac_final_rst;
wire frac_rdn_add_1;
wire frac_rdn_sub_1;
wire frac_rmm_add_1;
wire frac_rne_add_1;
wire frac_rtz_sub_1;
wire frac_rup_add_1;
wire frac_rup_sub_1;
wire [25:0] frac_sub1_op1_with_denorm;
wire [25:0] frac_sub1_rst;
wire pad_yy_icg_scan_en;
wire [29:0] total_qt_rt_30;
assign fdsu_ex3_result_sign = fdsu_yy_result_sign;
assign fdsu_ex3_expnt_rst[9:0] = fdsu_yy_expnt_rst[9:0];
assign fdsu_ex3_result_inf = fdsu_yy_result_inf;
assign fdsu_ex3_result_lfn = fdsu_yy_result_lfn;
assign fdsu_ex3_rm[2:0] = fdsu_yy_rm[2:0];
assign fdsu_ex3_rslt_denorm = fdsu_yy_rslt_denorm;
//=======================Round Rule=========================
//1/8 <= x < 1/4, 1/2 <= y < 1, => 1/8 < z < 1/2
//q[29:0] represent the fraction part result of quotient, q[29] for 1/2
//Thus the first "1" in 30 bit quotient will be in q[28] or q[27]
//For Single Float
//15 round to get 30 bit quotient, 23+1 bit as valid result, other for round
//if q[28] is 1, q[28:5] as 1.xxxx valid result, [4:0] for round
//if q[28] is 0, q[27:4] as 1.xxxx valid result, [3:0] for round
// &Force("bus","total_qt_rt_30",29,0); @42
assign ex3_qt_sing_lo4_not0 = |total_qt_rt_30[3:0];
assign ex3_qt_sing_lo3_not0 = |total_qt_rt_30[2:0];
//the quotient round bits great than "10000"(ronnd bits 10..0)
assign ex3_qt_gr = (total_qt_rt_30[28])
? total_qt_rt_30[4] && ex3_qt_sing_lo4_not0
: total_qt_rt_30[3] && ex3_qt_sing_lo3_not0;
//the quotient round bits is equal to "10000"(ronnd bits 10..0)
assign ex3_qt_eq = (total_qt_rt_30[28])
? total_qt_rt_30[4] && !ex3_qt_sing_lo4_not0
: total_qt_rt_30[3] && !ex3_qt_sing_lo3_not0;
//the quotient round bits is zero
assign ex3_qt_zero = (total_qt_rt_30[28])
? ~|total_qt_rt_30[4:0]
: ~|total_qt_rt_30[3:0];
//quotient is 1.00000..00 need special dealt with in the following
assign ex3_rst_eq_1 = total_qt_rt_30[28] && ~|total_qt_rt_30[27:5];
// for denormal result, first select the quotation num for rounding
// specially for the result e=-126 and e=-1022,the denorm depends on the
// MSB of the quotient
assign ex3_denorm_plus = !total_qt_rt_30[28] && (fdsu_ex3_expnt_rst[9:0] == 10'h382);
assign ex3_denorm_potnt_norm = total_qt_rt_30[28] && (fdsu_ex3_expnt_rst[9:0] == 10'h381);
assign ex3_rslt_denorm = ex3_denorm_plus || fdsu_ex3_rslt_denorm;
// &Force("output", "ex3_rslt_denorm"); @66
//denomal result, check for rounding further optimization can be done in
//future
// &CombBeg; @70
always @( total_qt_rt_30[28:0]
or fdsu_ex3_expnt_rst[9:0])
begin
case(fdsu_ex3_expnt_rst[9:0])
10'h382:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[4:0],23'b0}; //-126 1
single_denorm_lst_frac = total_qt_rt_30[5];
end//-1022 1
10'h381:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[5:0],22'b0}; //-127 0
single_denorm_lst_frac = total_qt_rt_30[6];
end//-1022 1
10'h380:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[6:0],21'b0}; //-128 -1
single_denorm_lst_frac = total_qt_rt_30[7];
end//-1022 1
10'h37f:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[7:0],20'b0}; //-129 -2
single_denorm_lst_frac = total_qt_rt_30[8];
end//-1022 1
10'h37e:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[8:0],19'b0}; //-130 -3
single_denorm_lst_frac = total_qt_rt_30[9];
end//-1022 1
10'h37d:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[9:0],18'b0}; //-131 -4
single_denorm_lst_frac = total_qt_rt_30[10];
end//-1022 1
10'h37c:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[10:0],17'b0}; //-132 -5
single_denorm_lst_frac = total_qt_rt_30[11];
end//-1022 1
10'h37b:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[11:0],16'b0}; //-133 -6
single_denorm_lst_frac = total_qt_rt_30[12];
end//-1022 1
10'h37a:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[12:0],15'b0}; //-134 -7
single_denorm_lst_frac = total_qt_rt_30[13];
end//-1022 1
10'h379:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[13:0],14'b0}; //-135 -8
single_denorm_lst_frac = total_qt_rt_30[14];
end//-1022 1
10'h378:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[14:0],13'b0}; //-136 -9
single_denorm_lst_frac = total_qt_rt_30[15];
end//-1022 1
10'h377:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[15:0],12'b0}; //-137 -10
single_denorm_lst_frac = total_qt_rt_30[16];
end//-1022 1
10'h376:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[16:0],11'b0}; //-138 -11
single_denorm_lst_frac = total_qt_rt_30[17];
end//-1022 1
10'h375:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[17:0],10'b0}; //-139 -12
single_denorm_lst_frac = total_qt_rt_30[18];
end//-1022 1
10'h374:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[18:0],9'b0}; //-140 -13
single_denorm_lst_frac = total_qt_rt_30[19];
end//-1022 1
10'h373:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[19:0],8'b0}; // -141
single_denorm_lst_frac = total_qt_rt_30[20];
end//-1022 1
10'h372:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[20:0],7'b0};//-142
single_denorm_lst_frac = total_qt_rt_30[21];
end//-1022 1
10'h371:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[21:0],6'b0};//-143
single_denorm_lst_frac = total_qt_rt_30[22];
end//-1022 1
10'h370:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[22:0],5'b0}; //-144
single_denorm_lst_frac = total_qt_rt_30[23];
end//-1022 1
10'h36f:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[23:0],4'b0}; //-145
single_denorm_lst_frac = total_qt_rt_30[24];
end//-1022 1
10'h36e:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[24:0],3'b0}; //-146
single_denorm_lst_frac = total_qt_rt_30[25];
end//-1022 1
10'h36d:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[25:0],2'b0}; //-147
single_denorm_lst_frac = total_qt_rt_30[26];
end//-1022 1
10'h36c:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[26:0],1'b0}; //-148
single_denorm_lst_frac = total_qt_rt_30[27];
end//-1022 1
10'h36b: begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[27:0]};
single_denorm_lst_frac = total_qt_rt_30[28] ;
end//-1022 1
default: begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[28:1]};
single_denorm_lst_frac = 1'b0;
end//-1022 1
endcase
// &CombEnd; @148
end
//rounding evaluation for single denormalize number
assign ex3_single_denorm_eq = qt_result_single_denorm_for_round[27]
&& !ex3_single_low_not_zero;
assign ex3_single_low_not_zero = |qt_result_single_denorm_for_round[26:0];
assign ex3_single_denorm_gr = qt_result_single_denorm_for_round[27]
&& ex3_single_low_not_zero;
assign ex3_single_denorm_zero = !qt_result_single_denorm_for_round[27]
&& !ex3_single_low_not_zero;
//rounding check fo denormalize result
assign ex3_denorm_eq = ex3_single_denorm_eq;
assign ex3_denorm_gr = ex3_single_denorm_gr;
assign ex3_denorm_zero = ex3_single_denorm_zero;
assign ex3_denorm_lst_frac = single_denorm_lst_frac;
//Different Round Mode with different rounding rule
//Here we call rounding bit as "rb", remainder as "rem"
//RNE :
// 1.+1 : rb>10000 || rb==10000 && rem>0
// 2. 0 : Rest Condition
// 3.-1 : Never occur
//RTZ :
// 1.+1 : Never occur
// 2. 0 : Rest Condition
// 3.-1 : rb=10000 && rem<0
//RDN :
// 1.+1 : Q>0 Never occur ; Q<0 Rest condition
// 2. 0 : Q>0 Rest condition; Q<0 Rem<0 && rb=0
// 3.-1 : Q>0 Rem<0 && rb=0 ; Q<0 Never occur
//RUP :
// 1.+1 : Q>0 Rest Condition; Q<0 Never occur
// 2. 0 : Q>0 Rem<0 && rb=0 ; Q<0 Rest condition
// 3.-1 : Q>0 Never occur ; Q<0 Rem<0 && rb=0
//RMM :
// 1.+1 : rb>10000 || rb==10000 && rem>0
// 2. 0 : Rest Condition
// 3.-1 : Never occur
assign frac_rne_add_1 = ex3_qt_gr ||
(ex3_qt_eq && !fdsu_ex3_rem_sign);
assign frac_rtz_sub_1 = ex3_qt_zero && fdsu_ex3_rem_sign;
assign frac_rup_add_1 = !fdsu_ex3_result_sign &&
(!ex3_qt_zero ||
(!fdsu_ex3_rem_sign && !fdsu_ex3_rem_zero));
assign frac_rup_sub_1 = fdsu_ex3_result_sign &&
(ex3_qt_zero && fdsu_ex3_rem_sign);
assign frac_rdn_add_1 = fdsu_ex3_result_sign &&
(!ex3_qt_zero ||
(!fdsu_ex3_rem_sign && !fdsu_ex3_rem_zero));
assign frac_rdn_sub_1 = !fdsu_ex3_result_sign &&
(ex3_qt_zero && fdsu_ex3_rem_sign);
assign frac_rmm_add_1 = ex3_qt_gr ||
(ex3_qt_eq && !fdsu_ex3_rem_sign);
//denormal result
assign frac_denorm_rne_add_1 = ex3_denorm_gr ||
(ex3_denorm_eq &&
((fdsu_ex3_rem_zero &&
ex3_denorm_lst_frac) ||
(!fdsu_ex3_rem_zero &&
!fdsu_ex3_rem_sign)));
assign frac_denorm_rtz_sub_1 = ex3_denorm_zero && fdsu_ex3_rem_sign;
assign frac_denorm_rup_add_1 = !fdsu_ex3_result_sign &&
(!ex3_denorm_zero ||
(!fdsu_ex3_rem_sign && !fdsu_ex3_rem_zero));
assign frac_denorm_rup_sub_1 = fdsu_ex3_result_sign &&
(ex3_denorm_zero && fdsu_ex3_rem_sign);
assign frac_denorm_rdn_add_1 = fdsu_ex3_result_sign &&
(!ex3_denorm_zero ||
(!fdsu_ex3_rem_sign && !fdsu_ex3_rem_zero));
assign frac_denorm_rdn_sub_1 = !fdsu_ex3_result_sign &&
(ex3_denorm_zero && fdsu_ex3_rem_sign);
assign frac_denorm_rmm_add_1 = ex3_denorm_gr ||
(ex3_denorm_eq && !fdsu_ex3_rem_sign);
//RM select
// &CombBeg; @222
always @( fdsu_ex3_rm[2:0]
or frac_denorm_rdn_add_1
or frac_rne_add_1
or frac_denorm_rdn_sub_1
or fdsu_ex3_result_sign
or frac_rup_add_1
or frac_denorm_rup_sub_1
or frac_rdn_sub_1
or frac_rtz_sub_1
or frac_rdn_add_1
or fdsu_ex3_id_srt_skip
or frac_denorm_rtz_sub_1
or ex3_rslt_denorm
or frac_rup_sub_1
or frac_denorm_rmm_add_1
or frac_denorm_rup_add_1
or frac_denorm_rne_add_1
or frac_rmm_add_1)
begin
case(fdsu_ex3_rm[2:0])
3'b000://round to nearst,ties to even
begin
frac_add_1 = ex3_rslt_denorm ? frac_denorm_rne_add_1 : frac_rne_add_1;
frac_sub_1 = 1'b0;
frac_orig = ex3_rslt_denorm ? !frac_denorm_rne_add_1 : !frac_rne_add_1;
denorm_to_tiny_frac = fdsu_ex3_id_srt_skip ? 1'b0 : frac_denorm_rne_add_1;
end
3'b001:// round to 0
begin
frac_add_1 = 1'b0;
frac_sub_1 = ex3_rslt_denorm ? frac_denorm_rtz_sub_1 : frac_rtz_sub_1;
frac_orig = ex3_rslt_denorm ? !frac_denorm_rtz_sub_1 : !frac_rtz_sub_1;
denorm_to_tiny_frac = 1'b0;
end
3'b010://round to -inf
begin
frac_add_1 = ex3_rslt_denorm ? frac_denorm_rdn_add_1 : frac_rdn_add_1;
frac_sub_1 = ex3_rslt_denorm ? frac_denorm_rdn_sub_1 : frac_rdn_sub_1;
frac_orig = ex3_rslt_denorm ? !frac_denorm_rdn_add_1 && !frac_denorm_rdn_sub_1
: !frac_rdn_add_1 && !frac_rdn_sub_1;
denorm_to_tiny_frac = fdsu_ex3_id_srt_skip ? fdsu_ex3_result_sign
: frac_denorm_rdn_add_1;
end
3'b011://round to +inf
begin
frac_add_1 = ex3_rslt_denorm ? frac_denorm_rup_add_1 : frac_rup_add_1;
frac_sub_1 = ex3_rslt_denorm ? frac_denorm_rup_sub_1 : frac_rup_sub_1;
frac_orig = ex3_rslt_denorm ? !frac_denorm_rup_add_1 && !frac_denorm_rup_sub_1
: !frac_rup_add_1 && !frac_rup_sub_1;
denorm_to_tiny_frac = fdsu_ex3_id_srt_skip ? !fdsu_ex3_result_sign
: frac_denorm_rup_add_1;
end
3'b100://round to nearest,ties to max magnitude
begin
frac_add_1 = ex3_rslt_denorm ? frac_denorm_rmm_add_1 : frac_rmm_add_1;
frac_sub_1 = 1'b0;
frac_orig = ex3_rslt_denorm ? !frac_denorm_rmm_add_1 : !frac_rmm_add_1;
denorm_to_tiny_frac = fdsu_ex3_id_srt_skip ? 1'b0 : frac_denorm_rmm_add_1;
end
default:
begin
frac_add_1 = 1'b0;
frac_sub_1 = 1'b0;
frac_orig = 1'b0;
denorm_to_tiny_frac = 1'b0;
end
endcase
// &CombEnd; @271
end
//Add 1 or Sub 1 constant
// &CombBeg; @273
always @( total_qt_rt_30[28])
begin
case(total_qt_rt_30[28])
1'b0:
begin
frac_add1_op1[25:0] = {2'b0,24'b1};
frac_sub1_op1[25:0] = {2'b11,{24{1'b1}}};
end
1'b1:
begin
frac_add1_op1[25:0] = {25'b1,1'b0};
frac_sub1_op1[25:0] = {{25{1'b1}},1'b0};
end
default:
begin
frac_add1_op1[25:0] = 26'b0;
frac_sub1_op1[25:0] = 26'b0;
end
endcase
// &CombEnd; @291
end
//Add 1 or Sub1 final result
//Conner case when quotient is 0.010000...00 and remainder is negative,
//The real quotient is actually 0.00fff..ff,
//The final result will need to sub 1 when
//RN : Never occur
//RP : sign of quotient is -
//RM : sign of quotient is +
assign frac_add1_rst[25:0] = {1'b0,total_qt_rt_30[28:4]} +
frac_add1_op1_with_denorm[25:0];
assign frac_add1_op1_with_denorm[25:0] = ex3_rslt_denorm ?
{1'b0,fdsu_ex3_result_denorm_round_add_num[23:0],1'b0} :
frac_add1_op1[25:0];
assign frac_sub1_rst[25:0] = (ex3_rst_eq_1)
? {3'b0,{23{1'b1}}}
: {1'b0,total_qt_rt_30[28:4]} +
frac_sub1_op1_with_denorm[25:0] + {25'b0, ex3_rslt_denorm};
assign frac_sub1_op1_with_denorm[25:0] = ex3_rslt_denorm ?
~{1'b0,fdsu_ex3_result_denorm_round_add_num[23:0],1'b0} :
frac_sub1_op1[25:0];
assign frac_final_rst[25:0] = (frac_add1_rst[25:0] & {26{frac_add_1}}) |
(frac_sub1_rst[25:0] & {26{frac_sub_1}}) |
({1'b0,total_qt_rt_30[28:4]} & {26{frac_orig}});
//===============Pipe down signal prepare===================
// assign ex3_rst_nor = !fdsu_ex3_result_zero &&
// !fdsu_ex3_result_qnan &&
// !fdsu_ex3_result_inf &&
// !fdsu_ex3_result_lfn;
assign ex3_rst_nor = !fdsu_ex3_result_inf &&
!fdsu_ex3_result_lfn;
assign ex3_nx = ex3_rst_nor &&
(!ex3_qt_zero || !fdsu_ex3_rem_zero || ex3_denorm_nx);
assign ex3_denorm_nx = ex3_rslt_denorm && (!ex3_denorm_zero || !fdsu_ex3_rem_zero);
//Adjust expnt
//Div:Actural expnt should plus 1 when op0 is id, sub 1 when op1 id
assign ex3_expnt_adjst[9:0] = 10'h7f;
assign ex3_expnt_adjust_result[9:0] = fdsu_ex3_expnt_rst[9:0] +
ex3_expnt_adjst[9:0];
//this information is for the packing, which determin the result is normal
//numer or not;
assign ex3_potnt_norm[1:0] = {ex3_denorm_plus,ex3_denorm_potnt_norm};
//=======================Pipe to EX4========================
//gate clk
// &Instance("gated_clk_cell","x_ex3_pipe_clk"); @337
gated_clk_cell x_ex3_pipe_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex3_pipe_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex3_pipe_clk_en ),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @338
// .clk_out (ex3_pipe_clk),//Out Clock @339
// .external_en (1'b0), @340
// .global_en (cp0_yy_clk_en), @341
// .local_en (ex3_pipe_clk_en),//Local Condition @342
// .module_en (cp0_fpu_icg_en) @343
// ); @344
assign ex3_pipe_clk_en = ex3_pipedown;
always @(posedge ex3_pipe_clk)
begin
if(ex3_pipedown)
begin
fdsu_ex4_result_nor <= ex3_rst_nor;
fdsu_ex4_nx <= ex3_nx;
fdsu_ex4_denorm_to_tiny_frac
<= denorm_to_tiny_frac;
fdsu_ex4_potnt_norm[1:0] <= ex3_potnt_norm[1:0];
end
else
begin
fdsu_ex4_result_nor <= fdsu_ex4_result_nor;
fdsu_ex4_nx <= fdsu_ex4_nx;
fdsu_ex4_denorm_to_tiny_frac
<= fdsu_ex4_denorm_to_tiny_frac;
fdsu_ex4_potnt_norm[1:0] <= fdsu_ex4_potnt_norm[1:0];
end
end
// ex3_frac Pipedown to ex4 use srt_divisor.
assign ex3_frac_final_rst[25:0] = frac_final_rst[25:0];
// &Force("output","fdsu_ex4_result_nor"); @397
// &Force("output","fdsu_ex4_nx"); @398
// &Force("output","fdsu_ex4_denorm_to_tiny_frac"); @399
// &Force("output","fdsu_ex4_potnt_norm"); @400
// &ModuleEnd; @403
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_fdsu_special(
cp0_fpu_xx_dqnan,
dp_xx_ex1_cnan,
dp_xx_ex1_id,
dp_xx_ex1_inf,
dp_xx_ex1_qnan,
dp_xx_ex1_snan,
dp_xx_ex1_zero,
ex1_div,
ex1_op0_id,
ex1_op0_norm,
ex1_op0_sign,
ex1_op1_id,
ex1_op1_norm,
ex1_result_sign,
ex1_sqrt,
ex1_srt_skip,
fdsu_fpu_ex1_fflags,
fdsu_fpu_ex1_special_sel,
fdsu_fpu_ex1_special_sign
);
// &Ports; @24
input cp0_fpu_xx_dqnan;
input [2:0] dp_xx_ex1_cnan;
input [2:0] dp_xx_ex1_id;
input [2:0] dp_xx_ex1_inf;
input [2:0] dp_xx_ex1_qnan;
input [2:0] dp_xx_ex1_snan;
input [2:0] dp_xx_ex1_zero;
input ex1_div;
input ex1_op0_sign;
input ex1_result_sign;
input ex1_sqrt;
output ex1_op0_id;
output ex1_op0_norm;
output ex1_op1_id;
output ex1_op1_norm;
output ex1_srt_skip;
output [4:0] fdsu_fpu_ex1_fflags;
output [7:0] fdsu_fpu_ex1_special_sel;
output [3:0] fdsu_fpu_ex1_special_sign;
// &Regs; @25
reg ex1_result_cnan;
reg ex1_result_qnan_op0;
reg ex1_result_qnan_op1;
// &Wires; @26
wire cp0_fpu_xx_dqnan;
wire [2:0] dp_xx_ex1_cnan;
wire [2:0] dp_xx_ex1_id;
wire [2:0] dp_xx_ex1_inf;
wire [2:0] dp_xx_ex1_qnan;
wire [2:0] dp_xx_ex1_snan;
wire [2:0] dp_xx_ex1_zero;
wire ex1_div;
wire ex1_div_dz;
wire ex1_div_nv;
wire ex1_div_rst_inf;
wire ex1_div_rst_qnan;
wire ex1_div_rst_zero;
wire ex1_dz;
wire [4:0] ex1_fflags;
wire ex1_nv;
wire ex1_op0_cnan;
wire ex1_op0_id;
wire ex1_op0_inf;
wire ex1_op0_is_qnan;
wire ex1_op0_is_snan;
wire ex1_op0_norm;
wire ex1_op0_qnan;
wire ex1_op0_sign;
wire ex1_op0_snan;
wire ex1_op0_tt_zero;
wire ex1_op0_zero;
wire ex1_op1_cnan;
wire ex1_op1_id;
wire ex1_op1_inf;
wire ex1_op1_is_qnan;
wire ex1_op1_is_snan;
wire ex1_op1_norm;
wire ex1_op1_qnan;
wire ex1_op1_snan;
wire ex1_op1_tt_zero;
wire ex1_op1_zero;
wire ex1_result_inf;
wire ex1_result_lfn;
wire ex1_result_qnan;
wire ex1_result_sign;
wire ex1_result_zero;
wire ex1_rst_default_qnan;
wire [7:0] ex1_special_sel;
wire [3:0] ex1_special_sign;
wire ex1_sqrt;
wire ex1_sqrt_nv;
wire ex1_sqrt_rst_inf;
wire ex1_sqrt_rst_qnan;
wire ex1_sqrt_rst_zero;
wire ex1_srt_skip;
wire [4:0] fdsu_fpu_ex1_fflags;
wire [7:0] fdsu_fpu_ex1_special_sel;
wire [3:0] fdsu_fpu_ex1_special_sign;
//infinity number
// &Force("bus", "dp_xx_ex1_inf", 2, 0); @29
assign ex1_op0_inf = dp_xx_ex1_inf[0];
assign ex1_op1_inf = dp_xx_ex1_inf[1];
//zero
// &Force("bus", "dp_xx_ex1_zero", 2, 0); @34
assign ex1_op0_zero = dp_xx_ex1_zero[0];
assign ex1_op1_zero = dp_xx_ex1_zero[1];
//denormalize number
// &Force("bus", "dp_xx_ex1_id", 2, 0); @39
assign ex1_op0_id = dp_xx_ex1_id[0];
assign ex1_op1_id = dp_xx_ex1_id[1];
//cNaN
// &Force("bus", "dp_xx_ex1_cnan", 2, 0); @44
assign ex1_op0_cnan = dp_xx_ex1_cnan[0];
assign ex1_op1_cnan = dp_xx_ex1_cnan[1];
//sNaN
// &Force("bus", "dp_xx_ex1_snan", 2, 0); @49
assign ex1_op0_snan = dp_xx_ex1_snan[0];
assign ex1_op1_snan = dp_xx_ex1_snan[1];
//qNaN
// &Force("bus", "dp_xx_ex1_qnan", 2, 0); @54
assign ex1_op0_qnan = dp_xx_ex1_qnan[0];
assign ex1_op1_qnan = dp_xx_ex1_qnan[1];
//======================EX1 expt detect=====================
//ex1_id_detect
//any opration is zero
// no input denormalize exception anymore
//
//ex1_nv_detect
//div_nv
// 1.any operation is sNaN
// 2.0/0(include DN flush to zero)
// 3.inf/inf
//sqrt_nv
// 1.any operation is sNaN
// 2.operation sign is 1 && operation is not zero/qNaN
assign ex1_nv = ex1_div && ex1_div_nv ||
ex1_sqrt && ex1_sqrt_nv;
//ex1_div_nv
assign ex1_div_nv = ex1_op0_snan ||
ex1_op1_snan ||
(ex1_op0_tt_zero && ex1_op1_tt_zero)||
(ex1_op0_inf && ex1_op1_inf);
assign ex1_op0_tt_zero = ex1_op0_zero;
assign ex1_op1_tt_zero = ex1_op1_zero;
//ex1_sqrt_nv
assign ex1_sqrt_nv = ex1_op0_snan ||
ex1_op0_sign &&
(ex1_op0_norm ||
ex1_op0_inf );
// This 'norm' also include denorm.
assign ex1_op0_norm = !ex1_op0_inf && !ex1_op0_zero && !ex1_op0_snan && !ex1_op0_qnan && !ex1_op0_cnan;
assign ex1_op1_norm = !ex1_op1_inf && !ex1_op1_zero && !ex1_op1_snan && !ex1_op1_qnan && !ex1_op1_cnan;
//ex1_of_detect
//div_of
// 1.only detect id overflow case
//assign ex1_of = ex1_div && ex1_div_of;
//assign ex1_div_of = ex1_op1_id_fm1 &&
// ex1_op0_norm &&
// ex1_div_id_of;
//
////ex1_uf_detect
////div_uf
//// 1.only detect id underflow case
//assign ex1_uf = ex1_div && ex1_div_uf;
//assign ex1_div_uf = ex1_op0_id &&
// ex1_op1_norm &&
// ex1_div_id_uf;
//ex1_dz_detect
//div_dz
// 1.op0 is normal && op1 zero
assign ex1_dz = ex1_div && ex1_div_dz;
assign ex1_div_dz = ex1_op1_tt_zero && ex1_op0_norm;
//===================special cal result=====================
//ex1 result is zero
//div_zero
// 1.op0 is zero && op1 is normal
// 2.op0 is zero/normal && op1 is inf
//sqrt_zero
// 1.op0 is zero
assign ex1_result_zero = ex1_div_rst_zero && ex1_div ||
ex1_sqrt_rst_zero && ex1_sqrt;
assign ex1_div_rst_zero = (ex1_op0_tt_zero && ex1_op1_norm ) ||
// (!ex1_expnt0_max && !ex1_op0_cnan && ex1_op1_inf);
(!ex1_op0_inf && !ex1_op0_qnan && !ex1_op0_snan && !ex1_op0_cnan && ex1_op1_inf);
assign ex1_sqrt_rst_zero = ex1_op0_tt_zero;
//ex1 result is qNaN
//ex1_nv
//div_qnan
// 1.op0 is qnan || op1 is qnan
//sqrt_qnan
// 1.op0 is qnan
assign ex1_result_qnan = ex1_div_rst_qnan && ex1_div ||
ex1_sqrt_rst_qnan && ex1_sqrt ||
ex1_nv;
assign ex1_div_rst_qnan = ex1_op0_qnan ||
ex1_op1_qnan;
assign ex1_sqrt_rst_qnan = ex1_op0_qnan;
//ex1_rst_default_qnan
//0/0, inf/inf, sqrt negative should get default qNaN
assign ex1_rst_default_qnan = (ex1_div && ex1_op0_zero && ex1_op1_zero) ||
(ex1_div && ex1_op0_inf && ex1_op1_inf) ||
(ex1_sqrt&& ex1_op0_sign && (ex1_op0_norm || ex1_op0_inf));
//ex1 result is inf
//ex1_dz
//
//div_inf
// 1.op0 is inf && op1 is normal/zero
//sqrt_inf
// 1.op0 is inf
assign ex1_result_inf = ex1_div_rst_inf && ex1_div ||
ex1_sqrt_rst_inf && ex1_sqrt ||
ex1_dz ;
// assign ex1_div_rst_inf = ex1_op0_inf && !ex1_expnt1_max && !ex1_op1_cnan;
assign ex1_div_rst_inf = ex1_op0_inf && !ex1_op1_inf && !ex1_op1_qnan && !ex1_op1_snan && !ex1_op1_cnan;
assign ex1_sqrt_rst_inf = ex1_op0_inf && !ex1_op0_sign;
//ex1 result is lfn
//ex1_of && round result toward not inc 1
assign ex1_result_lfn = 1'b0;
//Default_qnan/Standard_qnan Select
assign ex1_op0_is_snan = ex1_op0_snan;
assign ex1_op1_is_snan = ex1_op1_snan && ex1_div;
assign ex1_op0_is_qnan = ex1_op0_qnan;
assign ex1_op1_is_qnan = ex1_op1_qnan && ex1_div;
// &CombBeg; @169
always @( ex1_op0_is_snan
or ex1_op0_cnan
or ex1_result_qnan
or ex1_op0_is_qnan
or ex1_rst_default_qnan
or cp0_fpu_xx_dqnan
or ex1_op1_cnan
or ex1_op1_is_qnan
or ex1_op1_is_snan)
begin
if(ex1_rst_default_qnan)
begin
ex1_result_qnan_op0 = 1'b0;
ex1_result_qnan_op1 = 1'b0;
ex1_result_cnan = ex1_result_qnan;
end
else if(ex1_op0_is_snan && cp0_fpu_xx_dqnan)
begin
ex1_result_qnan_op0 = ex1_result_qnan;
ex1_result_qnan_op1 = 1'b0;
ex1_result_cnan = 1'b0;
end
else if(ex1_op1_is_snan && cp0_fpu_xx_dqnan)
begin
ex1_result_qnan_op0 = 1'b0;
ex1_result_qnan_op1 = ex1_result_qnan;
ex1_result_cnan = 1'b0;
end
else if(ex1_op0_is_qnan && cp0_fpu_xx_dqnan)
begin
ex1_result_qnan_op0 = ex1_result_qnan && !ex1_op0_cnan;
ex1_result_qnan_op1 = 1'b0;
ex1_result_cnan = ex1_result_qnan && ex1_op0_cnan;
end
else if(ex1_op1_is_qnan && cp0_fpu_xx_dqnan)
begin
ex1_result_qnan_op0 = 1'b0;
ex1_result_qnan_op1 = ex1_result_qnan && !ex1_op1_cnan;
ex1_result_cnan = ex1_result_qnan && ex1_op1_cnan;
end
else
begin
ex1_result_qnan_op0 = 1'b0;
ex1_result_qnan_op1 = 1'b0;
ex1_result_cnan = ex1_result_qnan;
end
// &CombEnd; @206
end
//Special result should skip SRT logic
assign ex1_srt_skip = ex1_result_zero ||
ex1_result_qnan ||
ex1_result_lfn ||
ex1_result_inf;
// fflags:
// NV, DZ, OF, UF, NX
assign ex1_fflags[4:0] = {ex1_nv, ex1_dz, 3'b0};
// Special Sel[7:0]:
// qnan_src2, qnan_src1, qnan_src0, cnan, lfn, inf, zero, src2
assign ex1_special_sel[7:0] = {1'b0, ex1_result_qnan_op1, ex1_result_qnan_op0,
ex1_result_cnan, ex1_result_lfn, ex1_result_inf,
ex1_result_zero, 1'b0};
// Special Sign[3:0]
// lfn, inf, zero, src2
assign ex1_special_sign[3:0] = {ex1_result_sign, ex1_result_sign, ex1_result_sign, 1'b0};
//==========================================================
// Output Signal
//==========================================================
assign fdsu_fpu_ex1_fflags[4:0] = ex1_fflags[4:0];
assign fdsu_fpu_ex1_special_sel[7:0] = ex1_special_sel[7:0];
assign fdsu_fpu_ex1_special_sign[3:0] = ex1_special_sign[3:0];
// &Force("output", "ex1_op0_norm"); @233
// &Force("output", "ex1_op1_norm"); @234
// &ModuleEnd; @236
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_fdsu_srt_single(
cp0_fpu_icg_en,
cp0_yy_clk_en,
ex1_divisor,
ex1_expnt_adder_op1,
ex1_oper_id_frac,
ex1_oper_id_frac_f,
ex1_pipedown,
ex1_pipedown_gate,
ex1_remainder,
ex1_save_op0,
ex1_save_op0_gate,
ex2_expnt_adder_op0,
ex2_of,
ex2_pipe_clk,
ex2_pipedown,
ex2_potnt_of,
ex2_potnt_uf,
ex2_result_inf,
ex2_result_lfn,
ex2_rslt_denorm,
ex2_srt_expnt_rst,
ex2_srt_first_round,
ex2_uf,
ex2_uf_srt_skip,
ex3_frac_final_rst,
ex3_pipedown,
fdsu_ex3_id_srt_skip,
fdsu_ex3_rem_sign,
fdsu_ex3_rem_zero,
fdsu_ex3_result_denorm_round_add_num,
fdsu_ex4_frac,
fdsu_yy_div,
fdsu_yy_of_rm_lfn,
fdsu_yy_op0_norm,
fdsu_yy_op1_norm,
fdsu_yy_sqrt,
forever_cpuclk,
pad_yy_icg_scan_en,
srt_remainder_zero,
srt_sm_on,
total_qt_rt_30
);
// &Ports; @24
input cp0_fpu_icg_en;
input cp0_yy_clk_en;
input [23:0] ex1_divisor;
input [12:0] ex1_expnt_adder_op1;
input [51:0] ex1_oper_id_frac;
input ex1_pipedown;
input ex1_pipedown_gate;
input [31:0] ex1_remainder;
input ex1_save_op0;
input ex1_save_op0_gate;
input [9 :0] ex2_expnt_adder_op0;
input ex2_pipe_clk;
input ex2_pipedown;
input ex2_srt_first_round;
input [25:0] ex3_frac_final_rst;
input ex3_pipedown;
input fdsu_yy_div;
input fdsu_yy_of_rm_lfn;
input fdsu_yy_op0_norm;
input fdsu_yy_op1_norm;
input fdsu_yy_sqrt;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input srt_sm_on;
output [51:0] ex1_oper_id_frac_f;
output ex2_of;
output ex2_potnt_of;
output ex2_potnt_uf;
output ex2_result_inf;
output ex2_result_lfn;
output ex2_rslt_denorm;
output [9 :0] ex2_srt_expnt_rst;
output ex2_uf;
output ex2_uf_srt_skip;
output fdsu_ex3_id_srt_skip;
output fdsu_ex3_rem_sign;
output fdsu_ex3_rem_zero;
output [23:0] fdsu_ex3_result_denorm_round_add_num;
output [25:0] fdsu_ex4_frac;
output srt_remainder_zero;
output [29:0] total_qt_rt_30;
// &Regs; @25
reg [31:0] cur_rem;
reg [7 :0] digit_bound_1;
reg [7 :0] digit_bound_2;
reg [23:0] ex2_result_denorm_round_add_num;
reg fdsu_ex3_id_srt_skip;
reg fdsu_ex3_rem_sign;
reg fdsu_ex3_rem_zero;
reg [23:0] fdsu_ex3_result_denorm_round_add_num;
reg [29:0] qt_rt_const_shift_std;
reg [7 :0] qtrt_sel_rem;
reg [31:0] rem_add1_op1;
reg [31:0] rem_add2_op1;
reg [25:0] srt_divisor;
reg [31:0] srt_remainder;
reg [29:0] total_qt_rt_30;
reg [29:0] total_qt_rt_30_next;
reg [29:0] total_qt_rt_minus_30;
reg [29:0] total_qt_rt_minus_30_next;
// &Wires; @26
wire [7 :0] bound1_cmp_result;
wire bound1_cmp_sign;
wire [7 :0] bound2_cmp_result;
wire bound2_cmp_sign;
wire [3 :0] bound_sel;
wire cp0_fpu_icg_en;
wire cp0_yy_clk_en;
wire [31:0] cur_doub_rem_1;
wire [31:0] cur_doub_rem_2;
wire [31:0] cur_rem_1;
wire [31:0] cur_rem_2;
wire [31:0] div_qt_1_rem_add_op1;
wire [31:0] div_qt_2_rem_add_op1;
wire [31:0] div_qt_r1_rem_add_op1;
wire [31:0] div_qt_r2_rem_add_op1;
wire [23:0] ex1_divisor;
wire ex1_ex2_pipe_clk;
wire ex1_ex2_pipe_clk_en;
wire [12:0] ex1_expnt_adder_op1;
wire [51:0] ex1_oper_id_frac;
wire [51:0] ex1_oper_id_frac_f;
wire ex1_pipedown;
wire ex1_pipedown_gate;
wire [31:0] ex1_remainder;
wire ex1_save_op0;
wire ex1_save_op0_gate;
wire ex2_div_of;
wire ex2_div_uf;
wire [9 :0] ex2_expnt_adder_op0;
wire [9 :0] ex2_expnt_adder_op1;
wire ex2_expnt_of;
wire [9 :0] ex2_expnt_result;
wire ex2_expnt_uf;
wire ex2_id_nor_srt_skip;
wire ex2_of;
wire ex2_of_plus;
wire ex2_pipe_clk;
wire ex2_pipedown;
wire ex2_potnt_of;
wire ex2_potnt_of_pre;
wire ex2_potnt_uf;
wire ex2_potnt_uf_pre;
wire ex2_result_inf;
wire ex2_result_lfn;
wire ex2_rslt_denorm;
wire [9 :0] ex2_sqrt_expnt_result;
wire [9 :0] ex2_srt_expnt_rst;
wire ex2_srt_first_round;
wire ex2_uf;
wire ex2_uf_plus;
wire ex2_uf_srt_skip;
wire [25:0] ex3_frac_final_rst;
wire ex3_pipedown;
wire fdsu_ex2_div;
wire [9 :0] fdsu_ex2_expnt_rst;
wire fdsu_ex2_of_rm_lfn;
wire fdsu_ex2_op0_norm;
wire fdsu_ex2_op1_norm;
wire fdsu_ex2_result_lfn;
wire fdsu_ex2_sqrt;
wire [25:0] fdsu_ex4_frac;
wire fdsu_yy_div;
wire fdsu_yy_of_rm_lfn;
wire fdsu_yy_op0_norm;
wire fdsu_yy_op1_norm;
wire fdsu_yy_sqrt;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
wire qt_clk;
wire qt_clk_en;
wire [29:0] qt_rt_const_pre_sel_q1;
wire [29:0] qt_rt_const_pre_sel_q2;
wire [29:0] qt_rt_const_q1;
wire [29:0] qt_rt_const_q2;
wire [29:0] qt_rt_const_q3;
wire [29:0] qt_rt_const_shift_std_next;
wire [29:0] qt_rt_mins_const_pre_sel_q1;
wire [29:0] qt_rt_mins_const_pre_sel_q2;
wire rem_sign;
wire [31:0] sqrt_qt_1_rem_add_op1;
wire [31:0] sqrt_qt_2_rem_add_op1;
wire [31:0] sqrt_qt_r1_rem_add_op1;
wire [31:0] sqrt_qt_r2_rem_add_op1;
wire srt_div_clk;
wire srt_div_clk_en;
wire [31:0] srt_remainder_nxt;
wire [31:0] srt_remainder_shift;
wire srt_remainder_sign;
wire srt_remainder_zero;
wire srt_sm_on;
wire [29:0] total_qt_rt_pre_sel;
assign fdsu_ex2_div = fdsu_yy_div;
assign fdsu_ex2_sqrt = fdsu_yy_sqrt;
assign fdsu_ex2_op0_norm = fdsu_yy_op0_norm;
assign fdsu_ex2_op1_norm = fdsu_yy_op1_norm;
assign fdsu_ex2_of_rm_lfn = fdsu_yy_of_rm_lfn;
assign fdsu_ex2_result_lfn = 1'b0;
//==========================================================
// EX2 Expnt Generate
//==========================================================
//expnt0 sub expnt1
assign ex2_expnt_result[9:0] = ex2_expnt_adder_op0[9:0] -
ex2_expnt_adder_op1[9:0];
//===================sqrt exponent prepare==================
//sqrt exponent prepare
//afert E sub, div E by 2
assign ex2_sqrt_expnt_result[9:0] = {ex2_expnt_result[9],
ex2_expnt_result[9:1]};
assign ex2_srt_expnt_rst[9:0] = (fdsu_ex2_sqrt)
? ex2_sqrt_expnt_result[9:0]
: ex2_expnt_result[9:0];
// &Force("output", "ex2_srt_expnt_rst"); &Force("bus", "ex2_srt_expnt_rst", 9, 0); @51
assign fdsu_ex2_expnt_rst[9:0] = ex2_srt_expnt_rst[9:0];
//====================EX2 Expt info=========================
//EX1 only detect of/uf under id condition
//EX2 will deal with other condition
//When input is normal, overflow when E1-E2 > 128/1024
assign ex2_expnt_of = ~fdsu_ex2_expnt_rst[9] && (fdsu_ex2_expnt_rst[8]
|| (fdsu_ex2_expnt_rst[7] &&
|fdsu_ex2_expnt_rst[6:0]));
//potential overflow when E1-E2 = 128/1024
assign ex2_potnt_of_pre = ~fdsu_ex2_expnt_rst[9] &&
~fdsu_ex2_expnt_rst[8] &&
fdsu_ex2_expnt_rst[7] &&
~|fdsu_ex2_expnt_rst[6:0];
assign ex2_potnt_of = ex2_potnt_of_pre &&
fdsu_ex2_op0_norm &&
fdsu_ex2_op1_norm &&
fdsu_ex2_div;
//When input is normal, underflow when E1-E2 <= -127/-1023
assign ex2_expnt_uf = fdsu_ex2_expnt_rst[9] &&(fdsu_ex2_expnt_rst[8:0] <= 9'h181);
//potential underflow when E1-E2 = -126/-1022
assign ex2_potnt_uf_pre = &fdsu_ex2_expnt_rst[9:7] &&
~|fdsu_ex2_expnt_rst[6:2] &&
fdsu_ex2_expnt_rst[1] &&
!fdsu_ex2_expnt_rst[0];
assign ex2_potnt_uf = (ex2_potnt_uf_pre &&
fdsu_ex2_op0_norm &&
fdsu_ex2_op1_norm &&
fdsu_ex2_div) ||
(ex2_potnt_uf_pre &&
fdsu_ex2_op0_norm);
//========================EX2 Overflow======================
//ex2 overflow when
// 1.op0 & op1 both norm && expnt overflow
// 2.ex1_id_of
// &Force("output","ex2_of"); @91
assign ex2_of = ex2_of_plus;
assign ex2_of_plus = ex2_div_of && fdsu_ex2_div;
assign ex2_div_of = fdsu_ex2_op0_norm &&
fdsu_ex2_op1_norm &&
ex2_expnt_of;
//=======================EX2 Underflow======================
//ex2 underflow when
// 1.op0 & op1 both norm && expnt underflow
// 2.ex1_id_uf
// and detect when to skip the srt, here, we have further optmization
assign ex2_uf = ex2_uf_plus;
assign ex2_uf_plus = ex2_div_uf && fdsu_ex2_div;
assign ex2_div_uf = fdsu_ex2_op0_norm &&
fdsu_ex2_op1_norm &&
ex2_expnt_uf;
assign ex2_id_nor_srt_skip = fdsu_ex2_expnt_rst[9]
&& (fdsu_ex2_expnt_rst[8:0]<9'h16a);
assign ex2_uf_srt_skip = ex2_id_nor_srt_skip;
assign ex2_rslt_denorm = ex2_uf;
//===============ex2 round prepare for denormal round======
// &CombBeg; @113
always @( fdsu_ex2_expnt_rst[9:0])
begin
case(fdsu_ex2_expnt_rst[9:0])
10'h382:ex2_result_denorm_round_add_num[23:0] = 24'h1; //-126 1
10'h381:ex2_result_denorm_round_add_num[23:0] = 24'h2; //-127 0
10'h380:ex2_result_denorm_round_add_num[23:0] = 24'h4; //-128 -1
10'h37f:ex2_result_denorm_round_add_num[23:0] = 24'h8; //-129 -2
10'h37e:ex2_result_denorm_round_add_num[23:0] = 24'h10; //-130 -3
10'h37d:ex2_result_denorm_round_add_num[23:0] = 24'h20; //-131 -4
10'h37c:ex2_result_denorm_round_add_num[23:0] = 24'h40; //-132 -5
10'h37b:ex2_result_denorm_round_add_num[23:0] = 24'h80; //-133 -6
10'h37a:ex2_result_denorm_round_add_num[23:0] = 24'h100; //-134 -7
10'h379:ex2_result_denorm_round_add_num[23:0] = 24'h200; //-135 -8
10'h378:ex2_result_denorm_round_add_num[23:0] = 24'h400; //-136 -9
10'h377:ex2_result_denorm_round_add_num[23:0] = 24'h800; //-137 -10
10'h376:ex2_result_denorm_round_add_num[23:0] = 24'h1000; //-138 -11
10'h375:ex2_result_denorm_round_add_num[23:0] = 24'h2000; //-139 -12
10'h374:ex2_result_denorm_round_add_num[23:0] = 24'h4000; //-140 -13
10'h373:ex2_result_denorm_round_add_num[23:0] = 24'h8000; // -141 -14
10'h372:ex2_result_denorm_round_add_num[23:0] = 24'h10000;//-142 -15
10'h371:ex2_result_denorm_round_add_num[23:0] = 24'h20000;//-143 -16
10'h370:ex2_result_denorm_round_add_num[23:0] = 24'h40000; //-144 -17
10'h36f:ex2_result_denorm_round_add_num[23:0] = 24'h80000; //-145 -18
10'h36e:ex2_result_denorm_round_add_num[23:0] = 24'h100000; //-146 -19
10'h36d:ex2_result_denorm_round_add_num[23:0] = 24'h200000; //-147 -20
10'h36c:ex2_result_denorm_round_add_num[23:0] = 24'h400000; //-148 -21
10'h36b:ex2_result_denorm_round_add_num[23:0] = 24'h800000; //-148 -22
default: ex2_result_denorm_round_add_num[23:0] = 24'h0; // -23
endcase
// &CombEnd; @141
end
//===================special result========================
assign ex2_result_inf = ex2_of_plus && !fdsu_ex2_of_rm_lfn;
assign ex2_result_lfn = fdsu_ex2_result_lfn ||
ex2_of_plus && fdsu_ex2_of_rm_lfn;
//====================Pipe to EX3===========================
always @(posedge ex1_ex2_pipe_clk)
begin
if(ex1_pipedown)
begin
fdsu_ex3_result_denorm_round_add_num[23:0]
<= {14'b0, ex1_expnt_adder_op1[9:0]};
end
else if(ex2_pipedown)
begin
fdsu_ex3_result_denorm_round_add_num[23:0]
<= ex2_result_denorm_round_add_num[23:0];
end
else
begin
fdsu_ex3_result_denorm_round_add_num[23:0]
<= fdsu_ex3_result_denorm_round_add_num[23:0];
end
end
assign ex2_expnt_adder_op1 = fdsu_ex3_result_denorm_round_add_num[9:0];
// &Force("bus", "ex1_expnt_adder_op1", 12, 0); @193
assign ex1_ex2_pipe_clk_en = ex1_pipedown_gate || ex2_pipedown;
// &Instance("gated_clk_cell", "x_ex1_ex2_pipe_clk"); @196
gated_clk_cell x_ex1_ex2_pipe_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex1_ex2_pipe_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex1_ex2_pipe_clk_en),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk), @197
// .external_en (1'b0), @198
// .global_en (cp0_yy_clk_en), @199
// .module_en (cp0_fpu_icg_en), @200
// .local_en (ex1_ex2_pipe_clk_en), @201
// .clk_out (ex1_ex2_pipe_clk)); @202
always @(posedge ex2_pipe_clk)
begin
if(ex2_pipedown)
begin
fdsu_ex3_rem_sign <= srt_remainder_sign;
fdsu_ex3_rem_zero <= srt_remainder_zero;
fdsu_ex3_id_srt_skip <= ex2_id_nor_srt_skip;
end
else
begin
fdsu_ex3_rem_sign <= fdsu_ex3_rem_sign;
fdsu_ex3_rem_zero <= fdsu_ex3_rem_zero;
fdsu_ex3_id_srt_skip <= fdsu_ex3_id_srt_skip;
end
end
// &Force("output","fdsu_ex3_rem_sign"); @243
// &Force("output","fdsu_ex3_rem_zero"); @244
// &Force("output","fdsu_ex3_result_denorm_round_add_num"); @245
// &Force("output","fdsu_ex3_id_srt_skip"); @246
//==========================================================
// SRT Remainder & Divisor for Quotient/Root Generate
//==========================================================
//===================Remainder Generate=====================
//gate clk
// &Instance("gated_clk_cell","x_srt_rem_clk");
// // &Connect( .clk_in (forever_cpuclk), @255
// // .clk_out (srt_rem_clk),//Out Clock @256
// // .external_en (1'b0), @257
// // .global_en (cp0_yy_clk_en), @258
// // .local_en (srt_rem_clk_en),//Local Condition @259
// // .module_en (cp0_fpu_icg_en) @260
// // ); @261
// assign srt_rem_clk_en = ex1_pipedown ||
// srt_sm_on;
always @(posedge qt_clk)
begin
if (ex1_pipedown)
srt_remainder[31:0] <= ex1_remainder[31:0];
else if (srt_sm_on)
srt_remainder[31:0] <= srt_remainder_nxt[31:0];
else
srt_remainder[31:0] <= srt_remainder[31:0];
end
//=====================Divisor Generate=====================
//gate clk
// &Instance("gated_clk_cell","x_srt_div_clk"); @291
gated_clk_cell x_srt_div_clk (
.clk_in (forever_cpuclk ),
.clk_out (srt_div_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (srt_div_clk_en ),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @292
// .clk_out (srt_div_clk),//Out Clock @293
// .external_en (1'b0), @294
// .global_en (cp0_yy_clk_en), @295
// .local_en (srt_div_clk_en),//Local Condition @296
// .module_en (cp0_fpu_icg_en) @297
// ); @298
assign srt_div_clk_en = ex1_pipedown_gate
|| ex1_save_op0_gate
|| ex3_pipedown;
// final_rst saved in srt_divisor.
// srt_divisor is 26 bits, final_rst is 24 bits.
always @(posedge srt_div_clk)
begin
if (ex1_save_op0)
srt_divisor[25:0] <= {3'b0, {ex1_oper_id_frac[51:29]}};
else if (ex1_pipedown)
srt_divisor[25:0] <= {2'b0, ex1_divisor[23:0]};
else if (ex3_pipedown)
srt_divisor[25:0] <= ex3_frac_final_rst[25:0];
else
srt_divisor[25:0] <= srt_divisor[25:0];
end
assign ex1_oper_id_frac_f[51:0] = {srt_divisor[22:0], 29'b0};
// &Force("bus", "ex1_oper_id_frac", 51, 0); @332
assign fdsu_ex4_frac[25:0] = srt_divisor[25:0];
//=======================Bound Select=======================
//---------------------------------------+
// K | 8 | 9 | 10| 11| 12| 13| 14|15,16|
//---------------------------------------+
//32S1 | 7 | 7 | 8 | 9 | 9 | 10| 11| 12 |
//---------------------------------------+
//32S2 | 25| 28| 31| 33| 36| 39| 41| 47 |
//---------------------------------------+
//bound_sel[3:0]
//For div, use divisor high four bit as K
//For sqrt, use 2qi high four bit as K next round and
// use 1010 as K first round
assign bound_sel[3:0] = (fdsu_ex2_div)
? srt_divisor[23:20]
: (ex2_srt_first_round)
? 4'b1010
: total_qt_rt_30[28:25];
//Select bound as look up table
// K = bound_sel[3:0]
//32S1 = digit_bound_1[7:0]
//32s2 = digit_bound_2[7:0]
// &CombBeg; @357
always @( bound_sel[3:0])
begin
case(bound_sel[3:0])
4'b0000: //when first interation get "10", choose k=16
begin
digit_bound_1[7:0] = 8'b11110100;//-12
digit_bound_2[7:0] = 8'b11010001;//-47
end
4'b1000:
begin
digit_bound_1[7:0] = 8'b11111001;//-7
digit_bound_2[7:0] = 8'b11100111;//-25
end
4'b1001:
begin
digit_bound_1[7:0] = 8'b11111001;//-7
digit_bound_2[7:0] = 8'b11100100;//-28
end
4'b1010:
begin
digit_bound_1[7:0] = 8'b11111000;//-8
digit_bound_2[7:0] = 8'b11100001;//-31
end
4'b1011:
begin
digit_bound_1[7:0] = 8'b11110111;//-9
digit_bound_2[7:0] = 8'b11011111;//-33
end
4'b1100:
begin
digit_bound_1[7:0] = 8'b11110111;//-9
digit_bound_2[7:0] = 8'b11011100;//-36
end
4'b1101:
begin
digit_bound_1[7:0] = 8'b11110110;//-10
digit_bound_2[7:0] = 8'b11011001;//-39
end
4'b1110:
begin
digit_bound_1[7:0] = 8'b11110101;//-11
digit_bound_2[7:0] = 8'b11010111;//-41
end
4'b1111:
begin
digit_bound_1[7:0] = 8'b11110100;//-12
digit_bound_2[7:0] = 8'b11010001;//-47
end
default:
begin
digit_bound_1[7:0] = 8'b11111001;//-7
digit_bound_2[7:0] = 8'b11100111;//-25
end
endcase
// &CombEnd; @410
end
//==============Prepare for quotient generate===============
assign bound1_cmp_result[7:0] = qtrt_sel_rem[7:0] + digit_bound_1[7:0];
assign bound2_cmp_result[7:0] = qtrt_sel_rem[7:0] + digit_bound_2[7:0];
assign bound1_cmp_sign = bound1_cmp_result[7];
assign bound2_cmp_sign = bound2_cmp_result[7];
assign rem_sign = srt_remainder[29];
//qtrt_sel_rem is use to select quotient
//Only when sqrt first round use 8R0 select quotient(special rule)
//4R0 is used to select quotient on other condition
//For negative remaider, we use ~rem not (~rem + 1)
//Because bound1 <= rem < bound2, when positive rem
// -bound2 <= rem < -bound1, when negative rem
//Thus bound1 < -rem <= bound2, when negative rem
//Thus bound1 <= -rem-1 < bound2, when negative rem
//Thus bound1 <= ~rem < bound2, when negative rem
//srt_remainder[29] used as sign bit
// &CombBeg; @429
always @( ex2_srt_first_round
or fdsu_ex2_sqrt
or srt_remainder[29:21])
begin
if(ex2_srt_first_round && fdsu_ex2_sqrt)
qtrt_sel_rem[7:0] = {srt_remainder[29], srt_remainder[27:21]};
else
qtrt_sel_rem[7:0] = srt_remainder[29] ? ~srt_remainder[29:22]
: srt_remainder[29:22];
// &CombEnd; @435
end
//==========================================================
// on fly round method to generate total quotient
//==========================================================
//gate clk
// &Instance("gated_clk_cell","x_qt_clk"); @441
gated_clk_cell x_qt_clk (
.clk_in (forever_cpuclk ),
.clk_out (qt_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (qt_clk_en ),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @442
// .clk_out (qt_clk),//Out Clock @443
// .external_en (1'b0), @444
// .global_en (cp0_yy_clk_en), @445
// .local_en (qt_clk_en),//Local Condition @446
// .module_en (cp0_fpu_icg_en) @447
// ); @448
assign qt_clk_en = srt_sm_on ||
ex1_pipedown_gate;
//qt_rt_const_shift_std[29:0] is const data for on fly round
// which is used to record the times of round
//
//total_qt_rt[29:0] is total quotient
//total_qt_rt_minus[29:0] is total quotient minus
// which is used to generate quotient rapidly
always @(posedge qt_clk)
begin
if(ex1_pipedown)
begin
qt_rt_const_shift_std[29:0] <= {1'b0,1'b1,28'b0};
total_qt_rt_30[29:0] <= 30'b0;
total_qt_rt_minus_30[29:0] <= 30'b0;
end
else if(srt_sm_on)
begin
qt_rt_const_shift_std[29:0] <= qt_rt_const_shift_std_next[29:0];
total_qt_rt_30[29:0] <= total_qt_rt_30_next[29:0];
total_qt_rt_minus_30[29:0] <= total_qt_rt_minus_30_next[29:0];
end
else
begin
qt_rt_const_shift_std[29:0] <= qt_rt_const_shift_std[29:0];
total_qt_rt_30[29:0] <= total_qt_rt_30[29:0];
total_qt_rt_minus_30[29:0] <= total_qt_rt_minus_30[29:0];
end
end
// &Force("output","total_qt_rt_30"); @508
//qt_rt_const_q1/q2/q3 for shift 1/2/3 in
assign qt_rt_const_q1[29:0] = qt_rt_const_shift_std[29:0];
assign qt_rt_const_q2[29:0] = {qt_rt_const_shift_std[28:0],1'b0};
assign qt_rt_const_q3[29:0] = qt_rt_const_q1[29:0] |
qt_rt_const_q2[29:0];
//qt_rt_const update value
assign qt_rt_const_shift_std_next[29:0] = {2'b0, qt_rt_const_shift_std[29:2]};
//========total_qt_rt & total_qt_rt_minus update value======
//q(i+1) is the total quotient/root after the (i+1) digit
//is calculated
// q(i+1) qm(i+1)
//d(i+1)=-2 qm(i)+2*shift qm(i)+1*shift
//d(i+1)=-1 qm(i)+3*shift qm(i)+2*shift
//d(i+1)=0 q(i) qm(i)+3*shift
//d(i+1)=1 q(i)+1*shift q(i)
//d(i+1)=2 q(i)+2*shift q(i)+1*shift
//Note:
//shift = 4^(-i-1), qm(i+1)=q(i+1)-shift
//pre select for quotient
assign total_qt_rt_pre_sel[29:0] = (rem_sign) ?
total_qt_rt_minus_30[29:0] :
total_qt_rt_30[29:0];
//when the quotient is 2 or -2
assign qt_rt_const_pre_sel_q2[29:0] = qt_rt_const_q2[29:0];
assign qt_rt_mins_const_pre_sel_q2[29:0] = qt_rt_const_q1[29:0];
//when the quotient is 1 or -1
assign qt_rt_const_pre_sel_q1[29:0] = (rem_sign) ?
qt_rt_const_q3[29:0] ://-1
qt_rt_const_q1[29:0]; //1
assign qt_rt_mins_const_pre_sel_q1[29:0] = (rem_sign) ?
qt_rt_const_q2[29:0] : //-1
30'b0;
//After bound compare, the final selection
// &CombBeg; @546
always @( qt_rt_const_q3[29:0]
or qt_rt_mins_const_pre_sel_q1[29:0]
or bound1_cmp_sign
or total_qt_rt_30[29:0]
or qt_rt_mins_const_pre_sel_q2[29:0]
or total_qt_rt_minus_30[29:0]
or bound2_cmp_sign
or qt_rt_const_pre_sel_q2[29:0]
or qt_rt_const_pre_sel_q1[29:0]
or total_qt_rt_pre_sel[29:0])
begin
casez({bound1_cmp_sign,bound2_cmp_sign})
2'b00:// the quotient is -2 or 2
begin
total_qt_rt_30_next[29:0] = total_qt_rt_pre_sel[29:0] |
qt_rt_const_pre_sel_q2[29:0];
total_qt_rt_minus_30_next[29:0] = total_qt_rt_pre_sel[29:0] |
qt_rt_mins_const_pre_sel_q2[29:0];
end
2'b01:// quotient is -1 or 1
begin
total_qt_rt_30_next[29:0] = total_qt_rt_pre_sel[29:0] |
qt_rt_const_pre_sel_q1[29:0];
total_qt_rt_minus_30_next[29:0] = total_qt_rt_pre_sel[29:0] |
qt_rt_mins_const_pre_sel_q1[29:0];
end
2'b1?: // quotient is 0
begin
total_qt_rt_30_next[29:0] = total_qt_rt_30[29:0];
total_qt_rt_minus_30_next[29:0] = total_qt_rt_minus_30[29:0] |
qt_rt_const_q3[29:0];
end
default:
begin
total_qt_rt_30_next[29:0] = 30'b0;
total_qt_rt_minus_30_next[29:0] = 30'b0;
end
endcase
// &CombEnd; @574
end
//==========================================================
// on fly round method to generate cur remainder
//==========================================================
//Division emainder add value
//Quoit 1
assign div_qt_1_rem_add_op1[31:0] = ~{3'b0,srt_divisor[23:0],5'b0};
//Quoit 2
assign div_qt_2_rem_add_op1[31:0] = ~{2'b0,srt_divisor[23:0],6'b0};
//Quoit -1
assign div_qt_r1_rem_add_op1[31:0] = {3'b0,srt_divisor[23:0],5'b0};
//Quoit -2
assign div_qt_r2_rem_add_op1[31:0] = {2'b0,srt_divisor[23:0],6'b0};
//Sqrt remainder add value op1
//Quoit 1
assign sqrt_qt_1_rem_add_op1[31:0] = ~({2'b0,total_qt_rt_30[29:0]} |
{3'b0,qt_rt_const_q1[29:1]});
//Quoit 2
assign sqrt_qt_2_rem_add_op1[31:0] = ~({1'b0,total_qt_rt_30[29:0],1'b0} |
{1'b0,qt_rt_const_q1[29:0],1'b0});
//Quoit -1
assign sqrt_qt_r1_rem_add_op1[31:0] = {2'b0,total_qt_rt_minus_30[29:0]} |
{1'b0,qt_rt_const_q1[29:0],1'b0} |
{2'b0,qt_rt_const_q1[29:0]} |
{3'b0,qt_rt_const_q1[29:1]};
//Quoit -2
assign sqrt_qt_r2_rem_add_op1[31:0] = {1'b0,
total_qt_rt_minus_30[29:0],1'b0} |
{qt_rt_const_q1[29:0],2'b0} |
{1'b0,qt_rt_const_q1[29:0],1'b0};
//Remainder Adder select logic
// &CombBeg; @607
always @( div_qt_2_rem_add_op1[31:0]
or sqrt_qt_r2_rem_add_op1[31:0]
or sqrt_qt_r1_rem_add_op1[31:0]
or rem_sign
or div_qt_r2_rem_add_op1[31:0]
or div_qt_1_rem_add_op1[31:0]
or sqrt_qt_2_rem_add_op1[31:0]
or fdsu_ex2_sqrt
or div_qt_r1_rem_add_op1[31:0]
or sqrt_qt_1_rem_add_op1[31:0])
begin
case({rem_sign,fdsu_ex2_sqrt})
2'b01:
begin
rem_add1_op1[31:0] = sqrt_qt_1_rem_add_op1[31:0];
rem_add2_op1[31:0] = sqrt_qt_2_rem_add_op1[31:0];
end
2'b00:
begin
rem_add1_op1[31:0] = div_qt_1_rem_add_op1[31:0];
rem_add2_op1[31:0] = div_qt_2_rem_add_op1[31:0];
end
2'b11:
begin
rem_add1_op1[31:0] = sqrt_qt_r1_rem_add_op1[31:0];
rem_add2_op1[31:0] = sqrt_qt_r2_rem_add_op1[31:0];
end
2'b10:
begin
rem_add1_op1[31:0] = div_qt_r1_rem_add_op1[31:0];
rem_add2_op1[31:0] = div_qt_r2_rem_add_op1[31:0];
end
default :
begin
rem_add1_op1[31:0] = 32'b0;
rem_add2_op1[31:0] = 32'b0;
end
endcase
// &CombEnd; @635
end
assign srt_remainder_shift[31:0] = {srt_remainder[31],
srt_remainder[28:0],2'b0};
//Remainder add
assign cur_doub_rem_1[31:0] = srt_remainder_shift[31:0] +
rem_add1_op1[31:0] +
{31'b0, ~rem_sign};
assign cur_doub_rem_2[31:0] = srt_remainder_shift[31:0] +
rem_add2_op1[31:0] +
{31'b0, ~rem_sign};
assign cur_rem_1[31:0] = cur_doub_rem_1[31:0];
assign cur_rem_2[31:0] = cur_doub_rem_2[31:0];
//Generate srt remainder update value
// &CombBeg; @648
always @( cur_rem_2[31:0]
or bound1_cmp_sign
or srt_remainder_shift[31:0]
or bound2_cmp_sign
or cur_rem_1[31:0])
begin
case({bound1_cmp_sign,bound2_cmp_sign})
2'b00: cur_rem[31:0] = cur_rem_2[31:0]; //+-2
2'b01: cur_rem[31:0] = cur_rem_1[31:0]; //+-1
default: cur_rem[31:0] = srt_remainder_shift[31:0]; //0
endcase
// &CombEnd; @654
end
assign srt_remainder_nxt[31:0] = cur_rem[31:0];
//Remainder is zero signal in EX3
assign srt_remainder_zero = ~|srt_remainder[31:0];
// &Force("output","srt_remainder_zero"); @659
assign srt_remainder_sign = srt_remainder[31];
// &Force("output", "ex2_uf"); @662
// &ModuleEnd; @663
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_fdsu_top(
cp0_fpu_icg_en,
cp0_fpu_xx_dqnan,
cp0_yy_clk_en,
cpurst_b,
ctrl_fdsu_ex1_sel,
ctrl_xx_ex1_cmplt_dp,
ctrl_xx_ex1_inst_vld,
ctrl_xx_ex1_stall,
ctrl_xx_ex1_warm_up,
ctrl_xx_ex2_warm_up,
ctrl_xx_ex3_warm_up,
dp_xx_ex1_cnan,
dp_xx_ex1_id,
dp_xx_ex1_inf,
dp_xx_ex1_qnan,
dp_xx_ex1_rm,
dp_xx_ex1_snan,
dp_xx_ex1_zero,
fdsu_fpu_debug_info,
fdsu_fpu_ex1_cmplt,
fdsu_fpu_ex1_cmplt_dp,
fdsu_fpu_ex1_fflags,
fdsu_fpu_ex1_special_sel,
fdsu_fpu_ex1_special_sign,
fdsu_fpu_ex1_stall,
fdsu_fpu_no_op,
fdsu_frbus_data,
fdsu_frbus_fflags,
fdsu_frbus_freg,
fdsu_frbus_wb_vld,
forever_cpuclk,
frbus_fdsu_wb_grant,
idu_fpu_ex1_dst_freg,
idu_fpu_ex1_eu_sel,
idu_fpu_ex1_func,
idu_fpu_ex1_srcf0,
idu_fpu_ex1_srcf1,
pad_yy_icg_scan_en,
rtu_xx_ex1_cancel,
rtu_xx_ex2_cancel,
rtu_yy_xx_async_flush,
rtu_yy_xx_flush
);
// &Ports; @24
input cp0_fpu_icg_en;
input cp0_fpu_xx_dqnan;
input cp0_yy_clk_en;
input cpurst_b;
input ctrl_fdsu_ex1_sel;
input ctrl_xx_ex1_cmplt_dp;
input ctrl_xx_ex1_inst_vld;
input ctrl_xx_ex1_stall;
input ctrl_xx_ex1_warm_up;
input ctrl_xx_ex2_warm_up;
input ctrl_xx_ex3_warm_up;
input [2 :0] dp_xx_ex1_cnan;
input [2 :0] dp_xx_ex1_id;
input [2 :0] dp_xx_ex1_inf;
input [2 :0] dp_xx_ex1_qnan;
input [2 :0] dp_xx_ex1_rm;
input [2 :0] dp_xx_ex1_snan;
input [2 :0] dp_xx_ex1_zero;
input forever_cpuclk;
input frbus_fdsu_wb_grant;
input [4 :0] idu_fpu_ex1_dst_freg;
input [2 :0] idu_fpu_ex1_eu_sel;
input [9 :0] idu_fpu_ex1_func;
input [31:0] idu_fpu_ex1_srcf0;
input [31:0] idu_fpu_ex1_srcf1;
input pad_yy_icg_scan_en;
input rtu_xx_ex1_cancel;
input rtu_xx_ex2_cancel;
input rtu_yy_xx_async_flush;
input rtu_yy_xx_flush;
output [4 :0] fdsu_fpu_debug_info;
output fdsu_fpu_ex1_cmplt;
output fdsu_fpu_ex1_cmplt_dp;
output [4 :0] fdsu_fpu_ex1_fflags;
output [7 :0] fdsu_fpu_ex1_special_sel;
output [3 :0] fdsu_fpu_ex1_special_sign;
output fdsu_fpu_ex1_stall;
output fdsu_fpu_no_op;
output [31:0] fdsu_frbus_data;
output [4 :0] fdsu_frbus_fflags;
output [4 :0] fdsu_frbus_freg;
output fdsu_frbus_wb_vld;
// &Regs; @25
// &Wires; @26
wire cp0_fpu_icg_en;
wire cp0_fpu_xx_dqnan;
wire cp0_yy_clk_en;
wire cpurst_b;
wire ctrl_fdsu_ex1_sel;
wire ctrl_xx_ex1_cmplt_dp;
wire ctrl_xx_ex1_inst_vld;
wire ctrl_xx_ex1_stall;
wire ctrl_xx_ex1_warm_up;
wire ctrl_xx_ex2_warm_up;
wire ctrl_xx_ex3_warm_up;
wire [2 :0] dp_xx_ex1_cnan;
wire [2 :0] dp_xx_ex1_id;
wire [2 :0] dp_xx_ex1_inf;
wire [2 :0] dp_xx_ex1_qnan;
wire [2 :0] dp_xx_ex1_rm;
wire [2 :0] dp_xx_ex1_snan;
wire [2 :0] dp_xx_ex1_zero;
wire ex1_div;
wire [23:0] ex1_divisor;
wire [12:0] ex1_expnt_adder_op0;
wire [12:0] ex1_expnt_adder_op1;
wire ex1_of_result_lfn;
wire ex1_op0_id;
wire ex1_op0_norm;
wire ex1_op0_sign;
wire ex1_op1_id;
wire ex1_op1_id_vld;
wire ex1_op1_norm;
wire ex1_op1_sel;
wire [12:0] ex1_oper_id_expnt;
wire [12:0] ex1_oper_id_expnt_f;
wire [51:0] ex1_oper_id_frac;
wire [51:0] ex1_oper_id_frac_f;
wire ex1_pipedown;
wire ex1_pipedown_gate;
wire [31:0] ex1_remainder;
wire ex1_result_sign;
wire [2 :0] ex1_rm;
wire ex1_save_op0;
wire ex1_save_op0_gate;
wire ex1_sqrt;
wire ex1_srt_skip;
wire [9 :0] ex2_expnt_adder_op0;
wire ex2_of;
wire ex2_pipe_clk;
wire ex2_pipedown;
wire ex2_potnt_of;
wire ex2_potnt_uf;
wire ex2_result_inf;
wire ex2_result_lfn;
wire ex2_rslt_denorm;
wire [9 :0] ex2_srt_expnt_rst;
wire ex2_srt_first_round;
wire ex2_uf;
wire ex2_uf_srt_skip;
wire [9 :0] ex3_expnt_adjust_result;
wire [25:0] ex3_frac_final_rst;
wire ex3_pipedown;
wire ex3_rslt_denorm;
wire fdsu_ex1_sel;
wire fdsu_ex3_id_srt_skip;
wire fdsu_ex3_rem_sign;
wire fdsu_ex3_rem_zero;
wire [23:0] fdsu_ex3_result_denorm_round_add_num;
wire fdsu_ex4_denorm_to_tiny_frac;
wire [25:0] fdsu_ex4_frac;
wire fdsu_ex4_nx;
wire [1 :0] fdsu_ex4_potnt_norm;
wire fdsu_ex4_result_nor;
wire [4 :0] fdsu_fpu_debug_info;
wire fdsu_fpu_ex1_cmplt;
wire fdsu_fpu_ex1_cmplt_dp;
wire [4 :0] fdsu_fpu_ex1_fflags;
wire [7 :0] fdsu_fpu_ex1_special_sel;
wire [3 :0] fdsu_fpu_ex1_special_sign;
wire fdsu_fpu_ex1_stall;
wire fdsu_fpu_no_op;
wire [31:0] fdsu_frbus_data;
wire [4 :0] fdsu_frbus_fflags;
wire [4 :0] fdsu_frbus_freg;
wire fdsu_frbus_wb_vld;
wire fdsu_yy_div;
wire [9 :0] fdsu_yy_expnt_rst;
wire fdsu_yy_of;
wire fdsu_yy_of_rm_lfn;
wire fdsu_yy_op0_norm;
wire fdsu_yy_op1_norm;
wire fdsu_yy_potnt_of;
wire fdsu_yy_potnt_uf;
wire fdsu_yy_result_inf;
wire fdsu_yy_result_lfn;
wire fdsu_yy_result_sign;
wire [2 :0] fdsu_yy_rm;
wire fdsu_yy_rslt_denorm;
wire fdsu_yy_sqrt;
wire fdsu_yy_uf;
wire [4 :0] fdsu_yy_wb_freg;
wire forever_cpuclk;
wire frbus_fdsu_wb_grant;
wire [4 :0] idu_fpu_ex1_dst_freg;
wire [2 :0] idu_fpu_ex1_eu_sel;
wire [9 :0] idu_fpu_ex1_func;
wire [31:0] idu_fpu_ex1_srcf0;
wire [31:0] idu_fpu_ex1_srcf1;
wire pad_yy_icg_scan_en;
wire rtu_xx_ex1_cancel;
wire rtu_xx_ex2_cancel;
wire rtu_yy_xx_async_flush;
wire rtu_yy_xx_flush;
wire srt_remainder_zero;
wire srt_sm_on;
wire [29:0] total_qt_rt_30;
// &Instance("pa_fdsu_special"); @29
pa_fdsu_special x_pa_fdsu_special (
.cp0_fpu_xx_dqnan (cp0_fpu_xx_dqnan ),
.dp_xx_ex1_cnan (dp_xx_ex1_cnan ),
.dp_xx_ex1_id (dp_xx_ex1_id ),
.dp_xx_ex1_inf (dp_xx_ex1_inf ),
.dp_xx_ex1_qnan (dp_xx_ex1_qnan ),
.dp_xx_ex1_snan (dp_xx_ex1_snan ),
.dp_xx_ex1_zero (dp_xx_ex1_zero ),
.ex1_div (ex1_div ),
.ex1_op0_id (ex1_op0_id ),
.ex1_op0_norm (ex1_op0_norm ),
.ex1_op0_sign (ex1_op0_sign ),
.ex1_op1_id (ex1_op1_id ),
.ex1_op1_norm (ex1_op1_norm ),
.ex1_result_sign (ex1_result_sign ),
.ex1_sqrt (ex1_sqrt ),
.ex1_srt_skip (ex1_srt_skip ),
.fdsu_fpu_ex1_fflags (fdsu_fpu_ex1_fflags ),
.fdsu_fpu_ex1_special_sel (fdsu_fpu_ex1_special_sel ),
.fdsu_fpu_ex1_special_sign (fdsu_fpu_ex1_special_sign)
);
// &Instance("pa_fdsu_prepare"); @30
pa_fdsu_prepare x_pa_fdsu_prepare (
.dp_xx_ex1_rm (dp_xx_ex1_rm ),
.ex1_div (ex1_div ),
.ex1_divisor (ex1_divisor ),
.ex1_expnt_adder_op0 (ex1_expnt_adder_op0),
.ex1_expnt_adder_op1 (ex1_expnt_adder_op1),
.ex1_of_result_lfn (ex1_of_result_lfn ),
.ex1_op0_id (ex1_op0_id ),
.ex1_op0_sign (ex1_op0_sign ),
.ex1_op1_id (ex1_op1_id ),
.ex1_op1_id_vld (ex1_op1_id_vld ),
.ex1_op1_sel (ex1_op1_sel ),
.ex1_oper_id_expnt (ex1_oper_id_expnt ),
.ex1_oper_id_expnt_f (ex1_oper_id_expnt_f),
.ex1_oper_id_frac (ex1_oper_id_frac ),
.ex1_oper_id_frac_f (ex1_oper_id_frac_f ),
.ex1_remainder (ex1_remainder ),
.ex1_result_sign (ex1_result_sign ),
.ex1_rm (ex1_rm ),
.ex1_sqrt (ex1_sqrt ),
.fdsu_ex1_sel (fdsu_ex1_sel ),
.idu_fpu_ex1_func (idu_fpu_ex1_func ),
.idu_fpu_ex1_srcf0 (idu_fpu_ex1_srcf0 ),
.idu_fpu_ex1_srcf1 (idu_fpu_ex1_srcf1 )
);
// &Instance("pa_fdsu_srt"); @32
// &Instance("pa_fdsu_round"); @33
// &Instance("pa_fdsu_pack"); @34
// &Instance("pa_fdsu_srt_single", "x_pa_fdsu_srt"); @36
pa_fdsu_srt_single x_pa_fdsu_srt (
.cp0_fpu_icg_en (cp0_fpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.ex1_divisor (ex1_divisor ),
.ex1_expnt_adder_op1 (ex1_expnt_adder_op1 ),
.ex1_oper_id_frac (ex1_oper_id_frac ),
.ex1_oper_id_frac_f (ex1_oper_id_frac_f ),
.ex1_pipedown (ex1_pipedown ),
.ex1_pipedown_gate (ex1_pipedown_gate ),
.ex1_remainder (ex1_remainder ),
.ex1_save_op0 (ex1_save_op0 ),
.ex1_save_op0_gate (ex1_save_op0_gate ),
.ex2_expnt_adder_op0 (ex2_expnt_adder_op0 ),
.ex2_of (ex2_of ),
.ex2_pipe_clk (ex2_pipe_clk ),
.ex2_pipedown (ex2_pipedown ),
.ex2_potnt_of (ex2_potnt_of ),
.ex2_potnt_uf (ex2_potnt_uf ),
.ex2_result_inf (ex2_result_inf ),
.ex2_result_lfn (ex2_result_lfn ),
.ex2_rslt_denorm (ex2_rslt_denorm ),
.ex2_srt_expnt_rst (ex2_srt_expnt_rst ),
.ex2_srt_first_round (ex2_srt_first_round ),
.ex2_uf (ex2_uf ),
.ex2_uf_srt_skip (ex2_uf_srt_skip ),
.ex3_frac_final_rst (ex3_frac_final_rst ),
.ex3_pipedown (ex3_pipedown ),
.fdsu_ex3_id_srt_skip (fdsu_ex3_id_srt_skip ),
.fdsu_ex3_rem_sign (fdsu_ex3_rem_sign ),
.fdsu_ex3_rem_zero (fdsu_ex3_rem_zero ),
.fdsu_ex3_result_denorm_round_add_num (fdsu_ex3_result_denorm_round_add_num),
.fdsu_ex4_frac (fdsu_ex4_frac ),
.fdsu_yy_div (fdsu_yy_div ),
.fdsu_yy_of_rm_lfn (fdsu_yy_of_rm_lfn ),
.fdsu_yy_op0_norm (fdsu_yy_op0_norm ),
.fdsu_yy_op1_norm (fdsu_yy_op1_norm ),
.fdsu_yy_sqrt (fdsu_yy_sqrt ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.srt_remainder_zero (srt_remainder_zero ),
.srt_sm_on (srt_sm_on ),
.total_qt_rt_30 (total_qt_rt_30 )
);
// &Instance("pa_fdsu_round_single", "x_pa_fdsu_round"); @37
pa_fdsu_round_single x_pa_fdsu_round (
.cp0_fpu_icg_en (cp0_fpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.ex3_expnt_adjust_result (ex3_expnt_adjust_result ),
.ex3_frac_final_rst (ex3_frac_final_rst ),
.ex3_pipedown (ex3_pipedown ),
.ex3_rslt_denorm (ex3_rslt_denorm ),
.fdsu_ex3_id_srt_skip (fdsu_ex3_id_srt_skip ),
.fdsu_ex3_rem_sign (fdsu_ex3_rem_sign ),
.fdsu_ex3_rem_zero (fdsu_ex3_rem_zero ),
.fdsu_ex3_result_denorm_round_add_num (fdsu_ex3_result_denorm_round_add_num),
.fdsu_ex4_denorm_to_tiny_frac (fdsu_ex4_denorm_to_tiny_frac ),
.fdsu_ex4_nx (fdsu_ex4_nx ),
.fdsu_ex4_potnt_norm (fdsu_ex4_potnt_norm ),
.fdsu_ex4_result_nor (fdsu_ex4_result_nor ),
.fdsu_yy_expnt_rst (fdsu_yy_expnt_rst ),
.fdsu_yy_result_inf (fdsu_yy_result_inf ),
.fdsu_yy_result_lfn (fdsu_yy_result_lfn ),
.fdsu_yy_result_sign (fdsu_yy_result_sign ),
.fdsu_yy_rm (fdsu_yy_rm ),
.fdsu_yy_rslt_denorm (fdsu_yy_rslt_denorm ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.total_qt_rt_30 (total_qt_rt_30 )
);
// &Instance("pa_fdsu_pack_single", "x_pa_fdsu_pack"); @38
pa_fdsu_pack_single x_pa_fdsu_pack (
.fdsu_ex4_denorm_to_tiny_frac (fdsu_ex4_denorm_to_tiny_frac),
.fdsu_ex4_frac (fdsu_ex4_frac ),
.fdsu_ex4_nx (fdsu_ex4_nx ),
.fdsu_ex4_potnt_norm (fdsu_ex4_potnt_norm ),
.fdsu_ex4_result_nor (fdsu_ex4_result_nor ),
.fdsu_frbus_data (fdsu_frbus_data ),
.fdsu_frbus_fflags (fdsu_frbus_fflags ),
.fdsu_frbus_freg (fdsu_frbus_freg ),
.fdsu_yy_expnt_rst (fdsu_yy_expnt_rst ),
.fdsu_yy_of (fdsu_yy_of ),
.fdsu_yy_of_rm_lfn (fdsu_yy_of_rm_lfn ),
.fdsu_yy_potnt_of (fdsu_yy_potnt_of ),
.fdsu_yy_potnt_uf (fdsu_yy_potnt_uf ),
.fdsu_yy_result_inf (fdsu_yy_result_inf ),
.fdsu_yy_result_lfn (fdsu_yy_result_lfn ),
.fdsu_yy_result_sign (fdsu_yy_result_sign ),
.fdsu_yy_rslt_denorm (fdsu_yy_rslt_denorm ),
.fdsu_yy_uf (fdsu_yy_uf ),
.fdsu_yy_wb_freg (fdsu_yy_wb_freg )
);
// &Instance("pa_fdsu_ctrl"); @41
pa_fdsu_ctrl x_pa_fdsu_ctrl (
.cp0_fpu_icg_en (cp0_fpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ctrl_fdsu_ex1_sel (ctrl_fdsu_ex1_sel ),
.ctrl_xx_ex1_cmplt_dp (ctrl_xx_ex1_cmplt_dp ),
.ctrl_xx_ex1_inst_vld (ctrl_xx_ex1_inst_vld ),
.ctrl_xx_ex1_stall (ctrl_xx_ex1_stall ),
.ctrl_xx_ex1_warm_up (ctrl_xx_ex1_warm_up ),
.ctrl_xx_ex2_warm_up (ctrl_xx_ex2_warm_up ),
.ctrl_xx_ex3_warm_up (ctrl_xx_ex3_warm_up ),
.ex1_div (ex1_div ),
.ex1_expnt_adder_op0 (ex1_expnt_adder_op0 ),
.ex1_of_result_lfn (ex1_of_result_lfn ),
.ex1_op0_id (ex1_op0_id ),
.ex1_op0_norm (ex1_op0_norm ),
.ex1_op1_id_vld (ex1_op1_id_vld ),
.ex1_op1_norm (ex1_op1_norm ),
.ex1_op1_sel (ex1_op1_sel ),
.ex1_oper_id_expnt (ex1_oper_id_expnt ),
.ex1_oper_id_expnt_f (ex1_oper_id_expnt_f ),
.ex1_pipedown (ex1_pipedown ),
.ex1_pipedown_gate (ex1_pipedown_gate ),
.ex1_result_sign (ex1_result_sign ),
.ex1_rm (ex1_rm ),
.ex1_save_op0 (ex1_save_op0 ),
.ex1_save_op0_gate (ex1_save_op0_gate ),
.ex1_sqrt (ex1_sqrt ),
.ex1_srt_skip (ex1_srt_skip ),
.ex2_expnt_adder_op0 (ex2_expnt_adder_op0 ),
.ex2_of (ex2_of ),
.ex2_pipe_clk (ex2_pipe_clk ),
.ex2_pipedown (ex2_pipedown ),
.ex2_potnt_of (ex2_potnt_of ),
.ex2_potnt_uf (ex2_potnt_uf ),
.ex2_result_inf (ex2_result_inf ),
.ex2_result_lfn (ex2_result_lfn ),
.ex2_rslt_denorm (ex2_rslt_denorm ),
.ex2_srt_expnt_rst (ex2_srt_expnt_rst ),
.ex2_srt_first_round (ex2_srt_first_round ),
.ex2_uf (ex2_uf ),
.ex2_uf_srt_skip (ex2_uf_srt_skip ),
.ex3_expnt_adjust_result (ex3_expnt_adjust_result),
.ex3_pipedown (ex3_pipedown ),
.ex3_rslt_denorm (ex3_rslt_denorm ),
.fdsu_ex1_sel (fdsu_ex1_sel ),
.fdsu_fpu_debug_info (fdsu_fpu_debug_info ),
.fdsu_fpu_ex1_cmplt (fdsu_fpu_ex1_cmplt ),
.fdsu_fpu_ex1_cmplt_dp (fdsu_fpu_ex1_cmplt_dp ),
.fdsu_fpu_ex1_stall (fdsu_fpu_ex1_stall ),
.fdsu_fpu_no_op (fdsu_fpu_no_op ),
.fdsu_frbus_wb_vld (fdsu_frbus_wb_vld ),
.fdsu_yy_div (fdsu_yy_div ),
.fdsu_yy_expnt_rst (fdsu_yy_expnt_rst ),
.fdsu_yy_of (fdsu_yy_of ),
.fdsu_yy_of_rm_lfn (fdsu_yy_of_rm_lfn ),
.fdsu_yy_op0_norm (fdsu_yy_op0_norm ),
.fdsu_yy_op1_norm (fdsu_yy_op1_norm ),
.fdsu_yy_potnt_of (fdsu_yy_potnt_of ),
.fdsu_yy_potnt_uf (fdsu_yy_potnt_uf ),
.fdsu_yy_result_inf (fdsu_yy_result_inf ),
.fdsu_yy_result_lfn (fdsu_yy_result_lfn ),
.fdsu_yy_result_sign (fdsu_yy_result_sign ),
.fdsu_yy_rm (fdsu_yy_rm ),
.fdsu_yy_rslt_denorm (fdsu_yy_rslt_denorm ),
.fdsu_yy_sqrt (fdsu_yy_sqrt ),
.fdsu_yy_uf (fdsu_yy_uf ),
.fdsu_yy_wb_freg (fdsu_yy_wb_freg ),
.forever_cpuclk (forever_cpuclk ),
.frbus_fdsu_wb_grant (frbus_fdsu_wb_grant ),
.idu_fpu_ex1_dst_freg (idu_fpu_ex1_dst_freg ),
.idu_fpu_ex1_eu_sel (idu_fpu_ex1_eu_sel ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_xx_ex1_cancel (rtu_xx_ex1_cancel ),
.rtu_xx_ex2_cancel (rtu_xx_ex2_cancel ),
.rtu_yy_xx_async_flush (rtu_yy_xx_async_flush ),
.rtu_yy_xx_flush (rtu_yy_xx_flush ),
.srt_remainder_zero (srt_remainder_zero ),
.srt_sm_on (srt_sm_on )
);
// &ModuleEnd; @44
endmodule

243
opene906/E906_RTL_FACTORY/gen_rtl/filelists/E906_asic_rtl.fl Normal file
View File

@ -0,0 +1,243 @@
${CODE_BASE_PATH}/gen_rtl/cpu/rtl/cpu_cfig.h
${CODE_BASE_PATH}/gen_rtl/dtu/rtl/pa_dtu_cfig.h
${CODE_BASE_PATH}/gen_rtl/idu/rtl/pa_idu_cfig.h
${CODE_BASE_PATH}/gen_rtl/tdt/rtl/top/tdt_define.h
${CODE_BASE_PATH}/gen_rtl/sysmap/rtl/sysmap.h
${CODE_BASE_PATH}/gen_rtl/common/rtl/BUFGCE.v
${CODE_BASE_PATH}/gen_rtl/fmau/rtl/booth_code_25_bit.v
${CODE_BASE_PATH}/gen_rtl/iu/rtl/booth_code_33_bit.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/fpga_ram.v
${CODE_BASE_PATH}/gen_rtl/clk/rtl/gated_clk_cell.v
${CODE_BASE_PATH}/gen_rtl/iu/rtl/multiplier_33x33_partial.v
${CODE_BASE_PATH}/gen_rtl/biu/rtl/pa_ahbl_if.v
${CODE_BASE_PATH}/gen_rtl/biu/rtl/pa_ahbl_if_fo.v
${CODE_BASE_PATH}/gen_rtl/bmu/rtl/pa_bmu_bus_if.v
${CODE_BASE_PATH}/gen_rtl/bmu/rtl/pa_bmu_dbus_if.v
${CODE_BASE_PATH}/gen_rtl/bmu/rtl/pa_bmu_top.v
${CODE_BASE_PATH}/gen_rtl/clic/rtl/pa_clic_arb.v
${CODE_BASE_PATH}/gen_rtl/clic/rtl/pa_clic_arb_32to1_kernel.v
${CODE_BASE_PATH}/gen_rtl/clic/rtl/pa_clic_arb_kernel.v
${CODE_BASE_PATH}/gen_rtl/clic/rtl/pa_clic_busif.v
${CODE_BASE_PATH}/gen_rtl/clic/rtl/pa_clic_cpuif_2cycle.v
${CODE_BASE_PATH}/gen_rtl/clic/rtl/pa_clic_ctrl.v
${CODE_BASE_PATH}/gen_rtl/clic/rtl/pa_clic_expand.v
${CODE_BASE_PATH}/gen_rtl/clic/rtl/pa_clic_ff1_onehot.v
${CODE_BASE_PATH}/gen_rtl/clic/rtl/pa_clic_kid.v
${CODE_BASE_PATH}/gen_rtl/clic/rtl/pa_clic_kid_dummy.v
${CODE_BASE_PATH}/gen_rtl/clic/rtl/pa_clic_sel.v
${CODE_BASE_PATH}/gen_rtl/clic/rtl/pa_clic_top.v
${CODE_BASE_PATH}/gen_rtl/clint/rtl/pa_clint_busif.v
${CODE_BASE_PATH}/gen_rtl/clint/rtl/pa_clint_regs.v
${CODE_BASE_PATH}/gen_rtl/clint/rtl/pa_clint_top.v
${CODE_BASE_PATH}/gen_rtl/clk/rtl/pa_clk_top.v
${CODE_BASE_PATH}/gen_rtl/clk/rtl/pa_clkrst_top.v
${CODE_BASE_PATH}/gen_rtl/cpu/rtl/pa_core.v
${CODE_BASE_PATH}/gen_rtl/cpu/rtl/pa_core_top.v
${CODE_BASE_PATH}/gen_rtl/cp0/rtl/pa_cp0_ext_csr.v
${CODE_BASE_PATH}/gen_rtl/cp0/rtl/pa_cp0_ext_inst.v
${CODE_BASE_PATH}/gen_rtl/cp0/rtl/pa_cp0_float_csr.v
${CODE_BASE_PATH}/gen_rtl/cp0/rtl/pa_cp0_info_csr.v
${CODE_BASE_PATH}/gen_rtl/cp0/rtl/pa_cp0_iui.v
${CODE_BASE_PATH}/gen_rtl/cp0/rtl/pa_cp0_regs.v
${CODE_BASE_PATH}/gen_rtl/cp0/rtl/pa_cp0_special.v
${CODE_BASE_PATH}/gen_rtl/cp0/rtl/pa_cp0_srst.v
${CODE_BASE_PATH}/gen_rtl/cp0/rtl/pa_cp0_top.v
${CODE_BASE_PATH}/gen_rtl/cp0/rtl/pa_cp0_trap_csr.v
${CODE_BASE_PATH}/gen_rtl/cpu/rtl/openE906.v
${CODE_BASE_PATH}/gen_rtl/cpu/rtl/pa_cpu_top_golden_port.v
${CODE_BASE_PATH}/gen_rtl/biu/rtl/pa_dahbl_top.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_dcache_data_array.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_dcache_dirty_array.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_dcache_tag_array.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_dcache_top.v
${CODE_BASE_PATH}/gen_rtl/dtu/rtl/pa_dtu_cdc.v
${CODE_BASE_PATH}/gen_rtl/dtu/rtl/pa_dtu_cdc_lvl.v
${CODE_BASE_PATH}/gen_rtl/dtu/rtl/pa_dtu_cdc_pulse.v
${CODE_BASE_PATH}/gen_rtl/dtu/rtl/pa_dtu_ctrl.v
${CODE_BASE_PATH}/gen_rtl/dtu/rtl/pa_dtu_dbginfo.v
${CODE_BASE_PATH}/gen_rtl/dtu/rtl/pa_dtu_m_iie_all.v
${CODE_BASE_PATH}/gen_rtl/dtu/rtl/pa_dtu_mcontrol_0.v
${CODE_BASE_PATH}/gen_rtl/dtu/rtl/pa_dtu_mcontrol_1.v
${CODE_BASE_PATH}/gen_rtl/dtu/rtl/pa_dtu_mcontrol_2.v
${CODE_BASE_PATH}/gen_rtl/dtu/rtl/pa_dtu_mcontrol_output_select.v
${CODE_BASE_PATH}/gen_rtl/dtu/rtl/pa_dtu_pcfifo.v
${CODE_BASE_PATH}/gen_rtl/dtu/rtl/pa_dtu_top.v
${CODE_BASE_PATH}/gen_rtl/dtu/rtl/pa_dtu_trigger_module.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_1024x32.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_1024x36.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_1024x37.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_1024x4.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_128x32.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_128x4.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_128x42.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_128x43.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_2048x32.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_256x32.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_256x4.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_256x40.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_256x41.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_32x4.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_32x46.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_32x47.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_4096x32.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_512x16.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_512x32.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_512x38.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_512x39.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_512x4.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_64x4.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_64x44.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_64x45.v
${CODE_BASE_PATH}/gen_rtl/fpga/rtl/pa_f_spsram_8192x32.v
${CODE_BASE_PATH}/gen_rtl/falu/rtl/pa_fadd_lop_s1_s.v
${CODE_BASE_PATH}/gen_rtl/falu/rtl/pa_fadd_nm_shift_single.v
${CODE_BASE_PATH}/gen_rtl/falu/rtl/pa_fadd_shift_sub_single.v
${CODE_BASE_PATH}/gen_rtl/falu/rtl/pa_fadd_single.v
${CODE_BASE_PATH}/gen_rtl/falu/rtl/pa_falu_ctrl.v
${CODE_BASE_PATH}/gen_rtl/falu/rtl/pa_falu_top.v
${CODE_BASE_PATH}/gen_rtl/falu/rtl/pa_fcnvt_ftoi_s.v
${CODE_BASE_PATH}/gen_rtl/falu/rtl/pa_fcnvt_itof_s.v
${CODE_BASE_PATH}/gen_rtl/falu/rtl/pa_fcnvt_single.v
${CODE_BASE_PATH}/gen_rtl/fdsu/rtl/pa_fdsu_ctrl.v
${CODE_BASE_PATH}/gen_rtl/fdsu/rtl/pa_fdsu_ff1.v
${CODE_BASE_PATH}/gen_rtl/fdsu/rtl/pa_fdsu_pack_single.v
${CODE_BASE_PATH}/gen_rtl/fdsu/rtl/pa_fdsu_prepare.v
${CODE_BASE_PATH}/gen_rtl/fdsu/rtl/pa_fdsu_round_single.v
${CODE_BASE_PATH}/gen_rtl/fdsu/rtl/pa_fdsu_special.v
${CODE_BASE_PATH}/gen_rtl/fdsu/rtl/pa_fdsu_srt_single.v
${CODE_BASE_PATH}/gen_rtl/fdsu/rtl/pa_fdsu_top.v
${CODE_BASE_PATH}/gen_rtl/fmau/rtl/pa_fmau_ctrl.v
${CODE_BASE_PATH}/gen_rtl/fmau/rtl/pa_fmau_dp.v
${CODE_BASE_PATH}/gen_rtl/fmau/rtl/pa_fmau_ex1_special_judge.v
${CODE_BASE_PATH}/gen_rtl/fmau/rtl/pa_fmau_frac_add.v
${CODE_BASE_PATH}/gen_rtl/fmau/rtl/pa_fmau_frac_mult.v
${CODE_BASE_PATH}/gen_rtl/fmau/rtl/pa_fmau_frac_shift.v
${CODE_BASE_PATH}/gen_rtl/fmau/rtl/pa_fmau_lza_single.v
${CODE_BASE_PATH}/gen_rtl/fmau/rtl/pa_fmau_multiplier_24x24_partial.v
${CODE_BASE_PATH}/gen_rtl/fmau/rtl/pa_fmau_src2_shifter_single.v
${CODE_BASE_PATH}/gen_rtl/fmau/rtl/pa_fmau_top.v
${CODE_BASE_PATH}/gen_rtl/fpu/rtl/pa_fpu_ctrl.v
${CODE_BASE_PATH}/gen_rtl/fpu/rtl/pa_fpu_dp.v
${CODE_BASE_PATH}/gen_rtl/fpu/rtl/pa_fpu_frbus.v
${CODE_BASE_PATH}/gen_rtl/fpu/rtl/pa_fpu_src_type.v
${CODE_BASE_PATH}/gen_rtl/fpu/rtl/pa_fpu_top.v
${CODE_BASE_PATH}/gen_rtl/falu/rtl/pa_fspu_single.v
${CODE_BASE_PATH}/gen_rtl/pmu/rtl/pa_hpcp_cnt.v
${CODE_BASE_PATH}/gen_rtl/pmu/rtl/pa_hpcp_event.v
${CODE_BASE_PATH}/gen_rtl/pmu/rtl/pa_hpcp_top.v
${CODE_BASE_PATH}/gen_rtl/biu/rtl/pa_iahbl_top.v
${CODE_BASE_PATH}/gen_rtl/idu/rtl/pa_idu_ctrl.v
${CODE_BASE_PATH}/gen_rtl/idu/rtl/pa_idu_decd_dsp.v
${CODE_BASE_PATH}/gen_rtl/idu/rtl/pa_idu_decd_fp.v
${CODE_BASE_PATH}/gen_rtl/idu/rtl/pa_idu_decd_rv32c.v
${CODE_BASE_PATH}/gen_rtl/idu/rtl/pa_idu_decd_rv32fd.v
${CODE_BASE_PATH}/gen_rtl/idu/rtl/pa_idu_decd_rv32im.v
${CODE_BASE_PATH}/gen_rtl/idu/rtl/pa_idu_decd_rv32x.v
${CODE_BASE_PATH}/gen_rtl/idu/rtl/pa_idu_dp.v
${CODE_BASE_PATH}/gen_rtl/idu/rtl/pa_idu_fpr.v
${CODE_BASE_PATH}/gen_rtl/idu/rtl/pa_idu_gpr.v
${CODE_BASE_PATH}/gen_rtl/idu/rtl/pa_idu_hs.v
${CODE_BASE_PATH}/gen_rtl/idu/rtl/pa_idu_id_fp.v
${CODE_BASE_PATH}/gen_rtl/idu/rtl/pa_idu_reg.v
${CODE_BASE_PATH}/gen_rtl/idu/rtl/pa_idu_reg32.v
${CODE_BASE_PATH}/gen_rtl/idu/rtl/pa_idu_reg32_high.v
${CODE_BASE_PATH}/gen_rtl/idu/rtl/pa_idu_reg_sp.v
${CODE_BASE_PATH}/gen_rtl/idu/rtl/pa_idu_split.v
${CODE_BASE_PATH}/gen_rtl/idu/rtl/pa_idu_top.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_ifu_bht.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_ifu_bht_array.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_ifu_btb.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_ifu_btb_entry.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_ifu_ctrl.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_ifu_ibuf.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_ifu_ibuf_entry.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_ifu_ibuf_pop_entry.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_ifu_icache.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_ifu_icache_data_array.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_ifu_icache_tag_array.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_ifu_id_pred.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_ifu_ifetch.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_ifu_ipack.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_ifu_ipack_entry.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_ifu_pcgen.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_ifu_pre_decd.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_ifu_ras.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_ifu_ras_entry.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_ifu_top.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_ifu_vec.v
${CODE_BASE_PATH}/gen_rtl/iu/rtl/pa_iu_addr_gen.v
${CODE_BASE_PATH}/gen_rtl/iu/rtl/pa_iu_alu.v
${CODE_BASE_PATH}/gen_rtl/iu/rtl/pa_iu_bju.v
${CODE_BASE_PATH}/gen_rtl/iu/rtl/pa_iu_ctrl.v
${CODE_BASE_PATH}/gen_rtl/iu/rtl/pa_iu_div.v
${CODE_BASE_PATH}/gen_rtl/iu/rtl/pa_iu_div_shift2_kernel.v
${CODE_BASE_PATH}/gen_rtl/iu/rtl/pa_iu_mul.v
${CODE_BASE_PATH}/gen_rtl/iu/rtl/pa_iu_top.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_lsu_ag.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_lsu_arb.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_lsu_dahbif.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_lsu_dc.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_lsu_dtif.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_lsu_icc.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_lsu_lfb.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_lsu_lm.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_lsu_ncb.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_lsu_rdl.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_lsu_stb.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_lsu_stb_entry.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_lsu_top.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_lsu_vb.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_lsu_vb_entry.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_lsu_wb_entry.v
${CODE_BASE_PATH}/gen_rtl/pmp/rtl/pa_pmp_acc_arb.v
${CODE_BASE_PATH}/gen_rtl/pmp/rtl/pa_pmp_comp_hit.v
${CODE_BASE_PATH}/gen_rtl/pmp/rtl/pa_pmp_enc.v
${CODE_BASE_PATH}/gen_rtl/pmp/rtl/pa_pmp_regs.v
${CODE_BASE_PATH}/gen_rtl/pmp/rtl/pa_pmp_top.v
${CODE_BASE_PATH}/gen_rtl/rst/rtl/pa_rst_top.v
${CODE_BASE_PATH}/gen_rtl/rtu/rtl/pa_rtu_cbus.v
${CODE_BASE_PATH}/gen_rtl/rtu/rtl/pa_rtu_int.v
${CODE_BASE_PATH}/gen_rtl/rtu/rtl/pa_rtu_lockup.v
${CODE_BASE_PATH}/gen_rtl/rtu/rtl/pa_rtu_rbus.v
${CODE_BASE_PATH}/gen_rtl/rtu/rtl/pa_rtu_retire.v
${CODE_BASE_PATH}/gen_rtl/rtu/rtl/pa_rtu_top.v
${CODE_BASE_PATH}/gen_rtl/biu/rtl/pa_sahbl_top.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_spsram_1024x32.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_spsram_1024x36.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_spsram_1024x37.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_spsram_1024x4.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_spsram_128x32.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_spsram_128x4.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_spsram_128x42.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_spsram_128x43.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_spsram_2048x32.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_spsram_256x32.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_spsram_256x4.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_spsram_256x40.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_spsram_256x41.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_spsram_32x4.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_spsram_32x46.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_spsram_32x47.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_spsram_4096x32.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_spsram_512x16.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_spsram_512x32.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_spsram_512x38.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_spsram_512x39.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_spsram_512x4.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_spsram_64x4.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_spsram_64x44.v
${CODE_BASE_PATH}/gen_rtl/ifu/rtl/pa_spsram_64x45.v
${CODE_BASE_PATH}/gen_rtl/lsu/rtl/pa_spsram_8192x32.v
${CODE_BASE_PATH}/gen_rtl/cpu/rtl/pa_sys_io.v
${CODE_BASE_PATH}/gen_rtl/sysmap/rtl/pa_sysmap_access.v
${CODE_BASE_PATH}/gen_rtl/sysmap/rtl/pa_sysmap_busif.v
${CODE_BASE_PATH}/gen_rtl/sysmap/rtl/pa_sysmap_hit.v
${CODE_BASE_PATH}/gen_rtl/sysmap/rtl/pa_sysmap_reg.v
${CODE_BASE_PATH}/gen_rtl/sysmap/rtl/pa_sysmap_top.v
${CODE_BASE_PATH}/gen_rtl/tcipif/rtl/pa_tcipif_behavior_bus.v
${CODE_BASE_PATH}/gen_rtl/tcipif/rtl/pa_tcipif_dummy_bus.v
${CODE_BASE_PATH}/gen_rtl/tcipif/rtl/pa_tcipif_top.v
${CODE_BASE_PATH}/gen_rtl/tdt/rtl/debug/tdt_dm.v
${CODE_BASE_PATH}/gen_rtl/tdt/rtl/top/tdt_dm_top.v
${CODE_BASE_PATH}/gen_rtl/tdt/rtl/top/tdt_top.v

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${CODE_BASE_PATH}/gen_rtl/tdt/rtl/top/tdt_dmi_define.h
${CODE_BASE_PATH}/gen_rtl/tdt/rtl/debug/tdt_apb_master.v
${CODE_BASE_PATH}/gen_rtl/tdt/rtl/top/tdt_dmi.v
${CODE_BASE_PATH}/gen_rtl/tdt/rtl/debug/tdt_dmi_pulse_sync.v
${CODE_BASE_PATH}/gen_rtl/tdt/rtl/top/tdt_dmi_rst_top.v
${CODE_BASE_PATH}/gen_rtl/tdt/rtl/debug/tdt_dmi_sync_dff.v
${CODE_BASE_PATH}/gen_rtl/tdt/rtl/top/tdt_dmi_top.v
${CODE_BASE_PATH}/gen_rtl/tdt/rtl/debug/tdt_dtm_chain.v
${CODE_BASE_PATH}/gen_rtl/tdt/rtl/debug/tdt_dtm_ctrl.v
${CODE_BASE_PATH}/gen_rtl/tdt/rtl/debug/tdt_dtm_idr.v
${CODE_BASE_PATH}/gen_rtl/tdt/rtl/debug/tdt_dtm_io.v
${CODE_BASE_PATH}/gen_rtl/tdt/rtl/debug/tdt_dtm_top.v
${CODE_BASE_PATH}/gen_rtl/tdt/rtl/common/tdt_gated_clk_cell.v

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @21
module booth_code_25_bit(
A,
code,
h,
product,
sn
);
// &Ports; @22
input [24:0] A;
input [2 :0] code;
output [1 :0] h;
output [24:0] product;
output sn;
// &Regs; @23
reg [1 :0] h;
reg [24:0] product;
reg sn;
// &Wires; @24
wire [24:0] A;
wire [2 :0] code;
parameter SRC_WIDTH = 25;
// &CombBeg; @28
always @( code[2:0]
or A[24:0])
begin
case(code[2:0])
3'b000 : product[SRC_WIDTH-1:0] = {SRC_WIDTH{1'b0}};
3'b001 : product[SRC_WIDTH-1:0] = {A[SRC_WIDTH-1:0]};
3'b010 : product[SRC_WIDTH-1:0] = {A[SRC_WIDTH-1:0]};
3'b011 : product[SRC_WIDTH-1:0] = {A[SRC_WIDTH-2:0],1'b0};
3'b100 : product[SRC_WIDTH-1:0] = {~A[SRC_WIDTH-2:0],1'b0};
3'b101 : product[SRC_WIDTH-1:0] = {~A[SRC_WIDTH-1:0]};
3'b110 : product[SRC_WIDTH-1:0] = {~A[SRC_WIDTH-1:0]};
3'b111 : product[SRC_WIDTH-1:0] = {SRC_WIDTH{1'b0}};
default: product[SRC_WIDTH-1:0] = {SRC_WIDTH{1'bx}};
endcase
// &CombEnd; @40
end
// &CombBeg; @42
always @( A[24]
or code[2:0])
begin
case(code[2:0])
3'b000 : sn = 1'b1;
3'b001 : sn = ~A[SRC_WIDTH-1];
3'b010 : sn = ~A[SRC_WIDTH-1];
3'b011 : sn = ~A[SRC_WIDTH-1];
3'b100 : sn = A[SRC_WIDTH-1];
3'b101 : sn = A[SRC_WIDTH-1];
3'b110 : sn = A[SRC_WIDTH-1];
3'b111 : sn = 1'b1;
default: sn = 1'bx;
endcase
// &CombEnd; @54
end
// &CombBeg; @56
always @( code[2:0])
begin
case(code[2:0])
3'b000 : h[1:0] = 2'b00;
3'b001 : h[1:0] = 2'b00;
3'b010 : h[1:0] = 2'b00;
3'b011 : h[1:0] = 2'b00;
3'b100 : h[1:0] = 2'b10;
3'b101 : h[1:0] = 2'b01;
3'b110 : h[1:0] = 2'b01;
3'b111 : h[1:0] = 2'b00;
default: h[1:0] = {2{1'bx}};
endcase
// &CombEnd; @68
end
// &ModuleEnd; @70
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @24
module pa_fmau_ctrl(
cp0_fpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
ctrl_dp_ex1_inst_pipe_down,
ctrl_dp_ex1_inst_vld,
ctrl_dp_ex2_inst_pipe_down,
ctrl_dp_ex2_inst_vld,
ctrl_dp_ex3_inst_pipe_down,
ctrl_dp_ex3_inst_vld,
ctrl_fmau_ex1_sel,
ctrl_fmau_ex1_sel_gate,
ctrl_xx_ex1_cmplt_dp,
ctrl_xx_ex1_stall,
ctrl_xx_ex2_cancel,
ctrl_xx_ex2_stall,
ctrl_xx_ex3_stall,
ctrl_xx_ex4_stall,
dp_ctrl_ex3_mac,
dp_xx_ex1_id,
ex1_id_reg,
ex2_special_cmplt,
fmau_fpu_ex1_cmplt,
fmau_fpu_ex1_cmplt_dp,
fmau_fpu_ex1_denorm_stall,
fmau_fpu_ex3_result_vld,
fmau_fpu_id_reg_set,
forever_cpuclk,
idu_fpu_ex1_eu_sel,
pad_yy_icg_scan_en,
rtu_xx_ex1_cancel
);
// &Ports; @25
input cp0_fpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input ctrl_fmau_ex1_sel;
input ctrl_fmau_ex1_sel_gate;
input ctrl_xx_ex1_cmplt_dp;
input ctrl_xx_ex1_stall;
input ctrl_xx_ex2_cancel;
input ctrl_xx_ex2_stall;
input ctrl_xx_ex3_stall;
input ctrl_xx_ex4_stall;
input dp_ctrl_ex3_mac;
input [2:0] dp_xx_ex1_id;
input ex2_special_cmplt;
input forever_cpuclk;
input [2:0] idu_fpu_ex1_eu_sel;
input pad_yy_icg_scan_en;
input rtu_xx_ex1_cancel;
output ctrl_dp_ex1_inst_pipe_down;
output ctrl_dp_ex1_inst_vld;
output ctrl_dp_ex2_inst_pipe_down;
output ctrl_dp_ex2_inst_vld;
output ctrl_dp_ex3_inst_pipe_down;
output ctrl_dp_ex3_inst_vld;
output [1:0] ex1_id_reg;
output fmau_fpu_ex1_cmplt;
output fmau_fpu_ex1_cmplt_dp;
output fmau_fpu_ex1_denorm_stall;
output fmau_fpu_ex3_result_vld;
output fmau_fpu_id_reg_set;
// &Regs; @26
reg [1:0] ex1_id_reg;
reg ex2_inst_vld;
reg ex3_inst_vld;
reg ex4_inst_vld;
// &Wires; @27
wire cp0_fpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire ctrl_dp_ex1_inst_pipe_down;
wire ctrl_dp_ex1_inst_vld;
wire ctrl_dp_ex2_inst_pipe_down;
wire ctrl_dp_ex2_inst_vld;
wire ctrl_dp_ex3_inst_pipe_down;
wire ctrl_dp_ex3_inst_vld;
wire ctrl_fmau_ex1_sel;
wire ctrl_fmau_ex1_sel_gate;
wire ctrl_xx_ex1_cmplt_dp;
wire ctrl_xx_ex1_stall;
wire ctrl_xx_ex2_cancel;
wire ctrl_xx_ex2_stall;
wire ctrl_xx_ex3_stall;
wire ctrl_xx_ex4_stall;
wire dp_ctrl_ex3_mac;
wire [2:0] dp_xx_ex1_id;
wire ex1_denormal_clk;
wire ex1_denormal_clk_en;
wire ex1_denormal_stall;
wire ex1_inst_vld;
wire ex2_ctrl_clk;
wire ex2_ctrl_clk_en;
wire ex2_special_cmplt;
wire ex3_ctrl_clk;
wire ex3_ctrl_clk_en;
wire ex4_ctrl_clk;
wire ex4_ctrl_clk_en;
wire fmau_fpu_ex1_cmplt;
wire fmau_fpu_ex1_cmplt_dp;
wire fmau_fpu_ex1_denorm_stall;
wire fmau_fpu_ex3_result_vld;
wire fmau_fpu_id_reg_set;
wire forever_cpuclk;
wire [2:0] idu_fpu_ex1_eu_sel;
wire pad_yy_icg_scan_en;
wire rtu_xx_ex1_cancel;
// &Depend("cpu_cfig.h"); @29
parameter DOUBLE_WIDTH = 64;
parameter DOUBLE_FRAC = 52;
parameter DOUBLE_EXPN = 11;
parameter SINGLE_WIDTH = 32;
parameter SINGLE_FRAC = 23;
parameter SINGLE_EXPN = 8;
parameter FUNC_WIDTH = 10;
//==========================================================
// EX1 Interface
//==========================================================
assign ex1_inst_vld = ctrl_fmau_ex1_sel;
//==========================================================
// EX1 denormal judge
//==========================================================
// &Force("bus","dp_xx_ex1_id",2,0); @49
assign ex1_denormal_clk_en = ctrl_fmau_ex1_sel_gate && |dp_xx_ex1_id[1:0]
|| |ex1_id_reg[1:0];
assign ex1_denormal_stall = ex1_inst_vld && (ex1_id_reg[1:0]==2'b00) && |dp_xx_ex1_id[1:0];
assign fmau_fpu_ex1_denorm_stall = ex1_denormal_stall;
assign fmau_fpu_ex1_cmplt = ex1_inst_vld && ((dp_xx_ex1_id[1:0]==2'b00) || |ex1_id_reg[1:0]);
assign fmau_fpu_ex1_cmplt_dp = ctrl_xx_ex1_cmplt_dp && idu_fpu_ex1_eu_sel[1] && ((dp_xx_ex1_id[1:0]==2'b00) || |ex1_id_reg[1:0]);
// &Force("bus","idu_fpu_ex1_eu_sel",2,0); @60
// &Instance("gated_clk_cell", "x_ctrl_ex1_denormal_gated_clk"); @61
gated_clk_cell x_ctrl_ex1_denormal_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex1_denormal_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex1_denormal_clk_en),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk ), @62
// .external_en (1'b0 ), @63
// .global_en (cp0_yy_clk_en ), @64
// .module_en (cp0_fpu_icg_en ), @65
// .local_en (ex1_denormal_clk_en ), @66
// .clk_out (ex1_denormal_clk )); @67
always@(posedge ex1_denormal_clk or negedge cpurst_b)
begin
if (!cpurst_b)
ex1_id_reg[1:0] <= {2{1'b0}};
else if(ex1_denormal_stall)
ex1_id_reg[1:0] <= dp_xx_ex1_id[1:0];
else
ex1_id_reg[1:0] <= {2{1'b0}};
end
assign fmau_fpu_id_reg_set = | ex1_id_reg[1:0];
// &Force("output","ex1_id_reg"); @81
//==========================================================
// EX2 inst vld ctrl
//==========================================================
assign ctrl_dp_ex1_inst_vld = ex1_inst_vld;
assign ctrl_dp_ex1_inst_pipe_down = ex1_inst_vld && !ctrl_xx_ex2_stall;
assign ex2_ctrl_clk_en = ctrl_fmau_ex1_sel_gate || ex2_inst_vld;
// &Instance("gated_clk_cell", "x_ctrl_ex2_gated_clk"); @90
gated_clk_cell x_ctrl_ex2_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex2_ctrl_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex2_ctrl_clk_en ),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @91
// .external_en (1'b0 ), @92
// .global_en (cp0_yy_clk_en ), @93
// .module_en (cp0_fpu_icg_en ), @94
// .local_en (ex2_ctrl_clk_en ), @95
// .clk_out (ex2_ctrl_clk )); @96
always@(posedge ex2_ctrl_clk or negedge cpurst_b)
begin
if (!cpurst_b)
ex2_inst_vld <= 1'b0;
else if(ctrl_xx_ex2_cancel)
ex2_inst_vld <= 1'b0;
else if(!ctrl_xx_ex2_stall)
ex2_inst_vld <= ex1_inst_vld && !rtu_xx_ex1_cancel && !ctrl_xx_ex1_stall;
else
ex2_inst_vld <= ex2_inst_vld;
end
//==========================================================
// EX3 inst vld ctrl
//==========================================================
assign ctrl_dp_ex2_inst_vld = ex2_inst_vld;
assign ctrl_dp_ex2_inst_pipe_down = ex2_inst_vld && !ctrl_xx_ex3_stall && !ex2_special_cmplt;
assign ex3_ctrl_clk_en = ex2_inst_vld || ex3_inst_vld;
// &Instance("gated_clk_cell", "x_ctrl_ex3_gated_clk"); @119
gated_clk_cell x_ctrl_ex3_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex3_ctrl_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex3_ctrl_clk_en ),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @120
// .external_en (1'b0 ), @121
// .global_en (cp0_yy_clk_en ), @122
// .module_en (cp0_fpu_icg_en ), @123
// .local_en (ex3_ctrl_clk_en ), @124
// .clk_out (ex3_ctrl_clk )); @125
always@(posedge ex3_ctrl_clk or negedge cpurst_b)
begin
if (!cpurst_b)
ex3_inst_vld <= 1'b0;
else if(!ctrl_xx_ex3_stall)
ex3_inst_vld <= ex2_inst_vld &&!ctrl_xx_ex2_cancel && !ex2_special_cmplt && !ctrl_xx_ex2_stall;
else
ex3_inst_vld <= ex3_inst_vld;
end
assign fmau_fpu_ex3_result_vld = ex3_inst_vld && !dp_ctrl_ex3_mac;
//==========================================================
// EX4 inst vld ctrl
//==========================================================
assign ctrl_dp_ex3_inst_vld = ex3_inst_vld && dp_ctrl_ex3_mac;
assign ctrl_dp_ex3_inst_pipe_down = ex3_inst_vld && dp_ctrl_ex3_mac && !ctrl_xx_ex4_stall;
assign ex4_ctrl_clk_en = ex3_inst_vld || ex4_inst_vld;
// &Instance("gated_clk_cell", "x_ctrl_ex4_gated_clk"); @147
gated_clk_cell x_ctrl_ex4_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex4_ctrl_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex4_ctrl_clk_en ),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @148
// .external_en (1'b0 ), @149
// .global_en (cp0_yy_clk_en ), @150
// .module_en (cp0_fpu_icg_en ), @151
// .local_en (ex4_ctrl_clk_en ), @152
// .clk_out (ex4_ctrl_clk )); @153
always@(posedge ex4_ctrl_clk or negedge cpurst_b)
begin
if (!cpurst_b)
ex4_inst_vld <= 1'b0;
else if(!ctrl_xx_ex4_stall)
ex4_inst_vld <= ex3_inst_vld && dp_ctrl_ex3_mac && !ctrl_xx_ex3_stall;
else
ex4_inst_vld <= ex4_inst_vld;
end
//assign fmau_fpu_ex4_result_vld = ex4_inst_vld;
// &ModuleEnd; @167
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @24
module pa_fmau_dp(
cp0_fpu_icg_en,
cp0_fpu_xx_dqnan,
cp0_yy_clk_en,
ctrl_dp_ex1_inst_pipe_down,
ctrl_dp_ex1_inst_vld,
ctrl_dp_ex2_inst_pipe_down,
ctrl_dp_ex2_inst_vld,
ctrl_dp_ex3_inst_pipe_down,
ctrl_dp_ex3_inst_vld,
ctrl_xx_ex1_warm_up,
ctrl_xx_ex2_warm_up,
ctrl_xx_ex3_warm_up,
dp_ctrl_ex3_mac,
dp_xx_ex1_cnan,
dp_xx_ex1_inf,
dp_xx_ex1_norm,
dp_xx_ex1_qnan,
dp_xx_ex1_rm,
dp_xx_ex1_snan,
dp_xx_ex1_srcf2,
dp_xx_ex1_zero,
dp_xx_ex2_srcf2,
dp_xx_ex3_rm,
dp_xx_ex4_rm,
ex1_id_reg,
ex2_special_cmplt,
fmau_fpu_ex1_fflags,
fmau_fpu_ex1_special_sel,
fmau_fpu_ex1_special_sign,
fmau_fpu_ex3_fflags,
fmau_fpu_ex3_result,
fmau_fpu_ex4_fflags,
fmau_fpu_ex4_result,
forever_cpuclk,
idu_fpu_ex1_eu_sel,
idu_fpu_ex1_func,
idu_fpu_ex1_srcf0,
idu_fpu_ex1_srcf1,
pad_yy_icg_scan_en
);
// &Ports; @25
input cp0_fpu_icg_en;
input cp0_fpu_xx_dqnan;
input cp0_yy_clk_en;
input ctrl_dp_ex1_inst_pipe_down;
input ctrl_dp_ex1_inst_vld;
input ctrl_dp_ex2_inst_pipe_down;
input ctrl_dp_ex2_inst_vld;
input ctrl_dp_ex3_inst_pipe_down;
input ctrl_dp_ex3_inst_vld;
input ctrl_xx_ex1_warm_up;
input ctrl_xx_ex2_warm_up;
input ctrl_xx_ex3_warm_up;
input [2 :0] dp_xx_ex1_cnan;
input [2 :0] dp_xx_ex1_inf;
input [2 :0] dp_xx_ex1_norm;
input [2 :0] dp_xx_ex1_qnan;
input [2 :0] dp_xx_ex1_rm;
input [2 :0] dp_xx_ex1_snan;
input [31:0] dp_xx_ex1_srcf2;
input [2 :0] dp_xx_ex1_zero;
input [31:0] dp_xx_ex2_srcf2;
input [2 :0] dp_xx_ex3_rm;
input [2 :0] dp_xx_ex4_rm;
input [1 :0] ex1_id_reg;
input forever_cpuclk;
input [2 :0] idu_fpu_ex1_eu_sel;
input [9 :0] idu_fpu_ex1_func;
input [31:0] idu_fpu_ex1_srcf0;
input [31:0] idu_fpu_ex1_srcf1;
input pad_yy_icg_scan_en;
output dp_ctrl_ex3_mac;
output ex2_special_cmplt;
output [4 :0] fmau_fpu_ex1_fflags;
output [7 :0] fmau_fpu_ex1_special_sel;
output [3 :0] fmau_fpu_ex1_special_sign;
output [4 :0] fmau_fpu_ex3_fflags;
output [31:0] fmau_fpu_ex3_result;
output [4 :0] fmau_fpu_ex4_fflags;
output [31:0] fmau_fpu_ex4_result;
// &Regs; @26
reg [9 :0] ex2_expnt_2;
reg ex2_mac;
reg [9 :0] ex2_mult_expnt;
reg ex2_mult_sign;
reg ex2_special_cmplt;
reg ex2_src2_expnt_not_zero;
reg ex2_src2_sign;
reg ex3_mac;
reg [9 :0] ex3_mac_expnt;
reg [9 :0] ex3_mult_expnt;
reg ex3_mult_sign;
reg ex3_sub_vld;
// &Wires; @27
wire cp0_fpu_icg_en;
wire cp0_fpu_xx_dqnan;
wire cp0_yy_clk_en;
wire ctrl_dp_ex1_inst_pipe_down;
wire ctrl_dp_ex1_inst_vld;
wire ctrl_dp_ex2_inst_pipe_down;
wire ctrl_dp_ex2_inst_vld;
wire ctrl_dp_ex3_inst_pipe_down;
wire ctrl_dp_ex3_inst_vld;
wire ctrl_xx_ex1_warm_up;
wire ctrl_xx_ex2_warm_up;
wire ctrl_xx_ex3_warm_up;
wire dp_ctrl_ex3_mac;
wire [2 :0] dp_xx_ex1_cnan;
wire [2 :0] dp_xx_ex1_inf;
wire [2 :0] dp_xx_ex1_norm;
wire [2 :0] dp_xx_ex1_qnan;
wire [2 :0] dp_xx_ex1_rm;
wire [2 :0] dp_xx_ex1_snan;
wire [31:0] dp_xx_ex1_srcf2;
wire [2 :0] dp_xx_ex1_zero;
wire [31:0] dp_xx_ex2_srcf2;
wire [2 :0] dp_xx_ex3_rm;
wire [2 :0] dp_xx_ex4_rm;
wire [2 :0] ex1_eu_sel;
wire [9 :0] ex1_expnt_0;
wire [9 :0] ex1_expnt_1;
wire [9 :0] ex1_expnt_2;
wire [9 :0] ex1_expnt_bias;
wire ex1_expnt_near_of;
wire ex1_expnt_near_uf;
wire [23:0] ex1_frac_0;
wire [23:0] ex1_frac_1;
wire [9 :0] ex1_func;
wire [1 :0] ex1_id_reg;
wire [2 :0] ex1_inst_rm;
wire ex1_mac;
wire ex1_mac_update;
wire [9 :0] ex1_mult_expnt;
wire ex1_mult_sign;
wire ex1_neg;
wire ex1_special_cmplt;
wire ex1_src2_expnt_not_zero;
wire ex1_src2_sign;
wire [31:0] ex1_srcf0;
wire [31:0] ex1_srcf1;
wire [31:0] ex1_srcf2;
wire ex1_sub;
wire ex1_sub_vld;
wire ex2_adder_0_sel_h;
wire [23:0] ex2_frac_2;
wire [9 :0] ex2_mac_expnt;
wire [47:0] ex2_mult_data;
wire [52:0] ex2_shift_data;
wire [31:0] ex2_srcf2;
wire ex2_sub_vld;
wire [2 :0] ex3_inst_rm;
wire [2 :0] ex4_inst_rm;
wire fmau_ex2_data_clk;
wire fmau_ex2_data_clk_en;
wire fmau_ex3_data_clk;
wire fmau_ex3_data_clk_en;
wire fmau_ex4_data_clk;
wire fmau_ex4_data_clk_en;
wire [4 :0] fmau_fpu_ex1_fflags;
wire [7 :0] fmau_fpu_ex1_special_sel;
wire [3 :0] fmau_fpu_ex1_special_sign;
wire [4 :0] fmau_fpu_ex3_fflags;
wire [31:0] fmau_fpu_ex3_result;
wire [4 :0] fmau_fpu_ex4_fflags;
wire [31:0] fmau_fpu_ex4_result;
wire forever_cpuclk;
wire [2 :0] idu_fpu_ex1_eu_sel;
wire [9 :0] idu_fpu_ex1_func;
wire [31:0] idu_fpu_ex1_srcf0;
wire [31:0] idu_fpu_ex1_srcf1;
wire pad_yy_icg_scan_en;
// &Depend("cpu_cfig.h"); @29
parameter DOUBLE_WIDTH = 64;
parameter DOUBLE_FRAC = 52;
parameter DOUBLE_EXPN = 11;
parameter SINGLE_WIDTH = 32;
parameter SINGLE_FRAC = 23;
parameter SINGLE_EXPN = 8;
parameter FUNC_WIDTH = 10;
//==========================================================
// EX1 Interface
//==========================================================
assign ex1_func[FUNC_WIDTH-1:0] = idu_fpu_ex1_func[FUNC_WIDTH-1:0];
assign ex1_inst_rm[2:0] = dp_xx_ex1_rm[2:0];
//assign ex2_inst_rm[2:0] = dp_xx_ex2_rm[2:0];
assign ex3_inst_rm[2:0] = dp_xx_ex3_rm[2:0];
assign ex4_inst_rm[2:0] = dp_xx_ex4_rm[2:0];
assign ex1_srcf0[SINGLE_WIDTH-1:0] = idu_fpu_ex1_srcf0[SINGLE_WIDTH-1:0];
assign ex1_srcf1[SINGLE_WIDTH-1:0] = idu_fpu_ex1_srcf1[SINGLE_WIDTH-1:0];
assign ex1_srcf2[SINGLE_WIDTH-1:0] = dp_xx_ex1_srcf2[SINGLE_WIDTH-1:0];
assign ex2_srcf2[SINGLE_WIDTH-1:0] = dp_xx_ex2_srcf2[SINGLE_WIDTH-1:0];
assign ex1_mac = ex1_func[0];
assign ex1_sub = ex1_func[1];
assign ex1_neg = ex1_func[2];
// &Instance("pa_fmau_ex1_special_judge","x_pa_fmau_ex1_special_judge"); @70
pa_fmau_ex1_special_judge x_pa_fmau_ex1_special_judge (
.cp0_fpu_xx_dqnan (cp0_fpu_xx_dqnan ),
.dp_xx_ex1_cnan (dp_xx_ex1_cnan ),
.dp_xx_ex1_inf (dp_xx_ex1_inf ),
.dp_xx_ex1_norm (dp_xx_ex1_norm ),
.dp_xx_ex1_qnan (dp_xx_ex1_qnan ),
.dp_xx_ex1_snan (dp_xx_ex1_snan ),
.dp_xx_ex1_zero (dp_xx_ex1_zero ),
.ex1_inst_rm (ex1_inst_rm ),
.ex1_mac (ex1_mac ),
.ex1_mult_expnt (ex1_mult_expnt ),
.ex1_mult_sign (ex1_mult_sign ),
.ex1_special_cmplt (ex1_special_cmplt ),
.ex1_src2_sign (ex1_src2_sign ),
.ex1_sub_vld (ex1_sub_vld ),
.fmau_fpu_ex1_fflags (fmau_fpu_ex1_fflags ),
.fmau_fpu_ex1_special_sel (fmau_fpu_ex1_special_sel ),
.fmau_fpu_ex1_special_sign (fmau_fpu_ex1_special_sign)
);
//==========================================================
// EX1 Fraction data path
//==========================================================
assign ex1_mac_update = ex1_mac || |ex1_id_reg[1:0] || ex1_expnt_near_uf || ex1_expnt_near_of;
assign ex1_eu_sel[2:0] = idu_fpu_ex1_eu_sel[2:0];
assign ex1_frac_0[SINGLE_FRAC:0] = {!ex1_id_reg[0],ex1_srcf0[SINGLE_FRAC-1:0]} & {(SINGLE_FRAC+1){ex1_eu_sel[1]}};
assign ex1_frac_1[SINGLE_FRAC:0] = {!ex1_id_reg[1],ex1_srcf1[SINGLE_FRAC-1:0]} & {(SINGLE_FRAC+1){ex1_eu_sel[1]}};
// &Instance("pa_fmau_frac_mult","x_pa_fmau_frac_mult"); @88
pa_fmau_frac_mult x_pa_fmau_frac_mult (
.ctrl_dp_ex1_inst_pipe_down (ctrl_dp_ex1_inst_pipe_down),
.ctrl_xx_ex1_warm_up (ctrl_xx_ex1_warm_up ),
.ex1_frac_0 (ex1_frac_0 ),
.ex1_frac_1 (ex1_frac_1 ),
.ex2_mult_data (ex2_mult_data ),
.fmau_ex2_data_clk (fmau_ex2_data_clk )
);
//==========================================================
// EX1 Exponent data path
//==========================================================
assign ex1_expnt_0[SINGLE_EXPN+1:0] = {2'b00,ex1_srcf0[SINGLE_FRAC+SINGLE_EXPN-1:SINGLE_FRAC]};
assign ex1_expnt_1[SINGLE_EXPN+1:0] = {2'b00,ex1_srcf1[SINGLE_FRAC+SINGLE_EXPN-1:SINGLE_FRAC]};
assign ex1_expnt_2[SINGLE_EXPN+1:0] = ex1_src2_expnt_not_zero ? {2'b00,ex1_srcf2[SINGLE_FRAC+SINGLE_EXPN-1:SINGLE_FRAC]}:10'b00_0000_0001;
assign ex1_src2_expnt_not_zero = |ex1_srcf2[SINGLE_FRAC+SINGLE_EXPN-1:SINGLE_FRAC];
assign ex1_expnt_bias[SINGLE_EXPN+1:0] = 10'b11_1000_0001; //single= -127
assign ex1_mult_expnt[SINGLE_EXPN+1:0] = {ex1_expnt_0[SINGLE_EXPN+1:0]} +
{ex1_expnt_1[SINGLE_EXPN+1:0]} +
{1'b0,{SINGLE_EXPN{1'b0}},ex1_id_reg[0]} +
{1'b0,{SINGLE_EXPN{1'b0}},ex1_id_reg[1]} +
ex1_expnt_bias[SINGLE_EXPN+1:0];
assign ex1_expnt_near_uf = ex1_mult_expnt[SINGLE_EXPN+1] || //<-127
!(|ex1_mult_expnt[SINGLE_EXPN+1:0]); //=-127
assign ex1_expnt_near_of =(ex1_mult_expnt[SINGLE_EXPN+1:0]==10'b00_1111_1110); //127
assign ex1_mult_sign = (ex1_srcf0[SINGLE_WIDTH-1]^ex1_srcf1[SINGLE_WIDTH-1]^ex1_neg);
assign ex1_src2_sign = (ex1_srcf2[SINGLE_WIDTH-1]^ex1_neg^ex1_sub);
assign ex1_sub_vld = (ex1_mult_sign ^ ex1_src2_sign) && ex1_mac;
// &Instance("pa_fmau_frac_shift","x_pa_fmau_frac_shift"); @156
pa_fmau_frac_shift x_pa_fmau_frac_shift (
.ctrl_dp_ex1_inst_pipe_down (ctrl_dp_ex1_inst_pipe_down),
.ctrl_xx_ex1_warm_up (ctrl_xx_ex1_warm_up ),
.ex1_expnt_2 (ex1_expnt_2 ),
.ex1_mult_expnt (ex1_mult_expnt ),
.ex2_adder_0_sel_h (ex2_adder_0_sel_h ),
.ex2_expnt_2 (ex2_expnt_2 ),
.ex2_frac_2 (ex2_frac_2 ),
.ex2_mac (ex2_mac ),
.ex2_mac_expnt (ex2_mac_expnt ),
.ex2_mult_expnt (ex2_mult_expnt ),
.ex2_shift_data (ex2_shift_data ),
.fmau_ex2_data_clk (fmau_ex2_data_clk )
);
// &Instance("pa_fmau_frac_add","x_pa_fmau_frac_add"); @158
pa_fmau_frac_add x_pa_fmau_frac_add (
.ctrl_dp_ex2_inst_pipe_down (ctrl_dp_ex2_inst_pipe_down),
.ctrl_dp_ex3_inst_pipe_down (ctrl_dp_ex3_inst_pipe_down),
.ctrl_xx_ex2_warm_up (ctrl_xx_ex2_warm_up ),
.ctrl_xx_ex3_warm_up (ctrl_xx_ex3_warm_up ),
.ex2_adder_0_sel_h (ex2_adder_0_sel_h ),
.ex2_mac (ex2_mac ),
.ex2_mac_expnt (ex2_mac_expnt ),
.ex2_mult_data (ex2_mult_data ),
.ex2_shift_data (ex2_shift_data ),
.ex2_sub_vld (ex2_sub_vld ),
.ex3_inst_rm (ex3_inst_rm ),
.ex3_mac_expnt (ex3_mac_expnt ),
.ex3_mult_expnt (ex3_mult_expnt ),
.ex3_mult_sign (ex3_mult_sign ),
.ex3_sub_vld (ex3_sub_vld ),
.ex4_inst_rm (ex4_inst_rm ),
.fmau_ex3_data_clk (fmau_ex3_data_clk ),
.fmau_ex4_data_clk (fmau_ex4_data_clk ),
.fmau_fpu_ex3_fflags (fmau_fpu_ex3_fflags ),
.fmau_fpu_ex3_result (fmau_fpu_ex3_result ),
.fmau_fpu_ex4_fflags (fmau_fpu_ex4_fflags ),
.fmau_fpu_ex4_result (fmau_fpu_ex4_result )
);
//==========================================================
// EX2 Stage
//==========================================================
//----------------------------------------------------------
// Instance of Gated Cell
//----------------------------------------------------------
assign fmau_ex2_data_clk_en = ctrl_dp_ex1_inst_vld || ctrl_xx_ex1_warm_up;
// &Instance("gated_clk_cell", "x_fmau_ex2_data_gated_clk"); @167
gated_clk_cell x_fmau_ex2_data_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (fmau_ex2_data_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (fmau_ex2_data_clk_en),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk ), @168
// .external_en (1'b0 ), @169
// .global_en (cp0_yy_clk_en ), @170
// .module_en (cp0_fpu_icg_en ), @171
// .local_en (fmau_ex2_data_clk_en), @172
// .clk_out (fmau_ex2_data_clk )); @173
always @(posedge fmau_ex2_data_clk)
begin
if(ctrl_dp_ex1_inst_pipe_down || ctrl_xx_ex1_warm_up)
begin
ex2_special_cmplt <= ex1_special_cmplt;
ex2_mac <= ex1_mac_update;
ex2_mult_sign <= ex1_mult_sign;
ex2_src2_sign <= ex1_src2_sign;
ex2_src2_expnt_not_zero <= ex1_src2_expnt_not_zero;
end
end
always @(posedge fmau_ex2_data_clk)
begin
if(ctrl_dp_ex1_inst_pipe_down || ctrl_xx_ex1_warm_up)
begin
ex2_mult_expnt[SINGLE_EXPN+1:0] <= ex1_mult_expnt[SINGLE_EXPN+1:0];
ex2_expnt_2[SINGLE_EXPN+1:0] <= ex1_expnt_2[SINGLE_EXPN+1:0];
end
end
assign ex2_sub_vld = (ex2_mult_sign ^ ex2_src2_sign) && ex2_mac;
// &CombBeg; @274
// &CombEnd; @280
assign ex2_frac_2[SINGLE_FRAC:0] = {ex2_src2_expnt_not_zero,ex2_srcf2[SINGLE_FRAC-1:0]};
//==========================================================
// EX3 Stage
//==========================================================
assign fmau_ex3_data_clk_en = ctrl_dp_ex2_inst_vld || ctrl_xx_ex2_warm_up;
// &Instance("gated_clk_cell", "x_fmau_ex3_data_gated_clk"); @291
gated_clk_cell x_fmau_ex3_data_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (fmau_ex3_data_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (fmau_ex3_data_clk_en),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk ), @292
// .external_en (1'b0 ), @293
// .global_en (cp0_yy_clk_en ), @294
// .module_en (cp0_fpu_icg_en ), @295
// .local_en (fmau_ex3_data_clk_en), @296
// .clk_out (fmau_ex3_data_clk )); @297
always @(posedge fmau_ex3_data_clk)
begin
if(ctrl_dp_ex2_inst_pipe_down || ctrl_xx_ex2_warm_up)
begin
ex3_sub_vld <= ex2_sub_vld;
ex3_mac <= ex2_mac;
ex3_mult_sign <= ex2_mult_sign;
end
end
assign dp_ctrl_ex3_mac = ex3_mac;
always @(posedge fmau_ex3_data_clk)
begin
if(ctrl_dp_ex2_inst_pipe_down || ctrl_xx_ex2_warm_up)
begin
ex3_mult_expnt[SINGLE_EXPN+1:0] <= ex2_mult_expnt[SINGLE_EXPN+1:0];
ex3_mac_expnt[SINGLE_EXPN+1:0] <= ex2_mac_expnt[SINGLE_EXPN+1:0];
end
end
//==========================================================
// EX4 Stage
//==========================================================
assign fmau_ex4_data_clk_en = ctrl_dp_ex3_inst_vld || ctrl_xx_ex3_warm_up;
// &Instance("gated_clk_cell", "x_fmau_ex4_data_gated_clk"); @397
gated_clk_cell x_fmau_ex4_data_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (fmau_ex4_data_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (fmau_ex4_data_clk_en),
.module_en (cp0_fpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk ), @398
// .external_en (1'b0 ), @399
// .global_en (cp0_yy_clk_en ), @400
// .module_en (cp0_fpu_icg_en ), @401
// .local_en (fmau_ex4_data_clk_en), @402
// .clk_out (fmau_ex4_data_clk )); @403
// &ModuleEnd; @432
endmodule

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opene906/E906_RTL_FACTORY/gen_rtl/fmau/rtl/pa_fmau_ex1_special_judge.v Normal file
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @24
module pa_fmau_ex1_special_judge(
cp0_fpu_xx_dqnan,
dp_xx_ex1_cnan,
dp_xx_ex1_inf,
dp_xx_ex1_norm,
dp_xx_ex1_qnan,
dp_xx_ex1_snan,
dp_xx_ex1_zero,
ex1_inst_rm,
ex1_mac,
ex1_mult_expnt,
ex1_mult_sign,
ex1_special_cmplt,
ex1_src2_sign,
ex1_sub_vld,
fmau_fpu_ex1_fflags,
fmau_fpu_ex1_special_sel,
fmau_fpu_ex1_special_sign
);
// &Ports; @25
input cp0_fpu_xx_dqnan;
input [2:0] dp_xx_ex1_cnan;
input [2:0] dp_xx_ex1_inf;
input [2:0] dp_xx_ex1_norm;
input [2:0] dp_xx_ex1_qnan;
input [2:0] dp_xx_ex1_snan;
input [2:0] dp_xx_ex1_zero;
input [2:0] ex1_inst_rm;
input ex1_mac;
input [9:0] ex1_mult_expnt;
input ex1_mult_sign;
input ex1_src2_sign;
input ex1_sub_vld;
output ex1_special_cmplt;
output [4:0] fmau_fpu_ex1_fflags;
output [7:0] fmau_fpu_ex1_special_sel;
output [3:0] fmau_fpu_ex1_special_sign;
// &Regs; @26
// &Wires; @27
wire cp0_fpu_xx_dqnan;
wire [2:0] dp_xx_ex1_cnan;
wire [2:0] dp_xx_ex1_inf;
wire [2:0] dp_xx_ex1_norm;
wire [2:0] dp_xx_ex1_qnan;
wire [2:0] dp_xx_ex1_snan;
wire [2:0] dp_xx_ex1_zero;
wire ex1_fmau_inf_sign;
wire ex1_fmau_lfn_sign;
wire ex1_fmau_nv;
wire ex1_fmau_of;
wire ex1_fmau_result_cnan;
wire ex1_fmau_result_inf;
wire ex1_fmau_result_lfn;
wire [2:0] ex1_fmau_result_qnan;
wire ex1_fmau_result_src2;
wire ex1_fmau_result_zero;
wire ex1_fmau_src2_sign;
wire ex1_fmau_zero_sign;
wire [2:0] ex1_inst_rm;
wire ex1_mac;
wire [9:0] ex1_mult_expnt;
wire ex1_mult_sign;
wire [2:0] ex1_nv;
wire [2:0] ex1_result_qnan;
wire ex1_result_zero;
wire ex1_special_cmplt;
wire ex1_src2_sign;
wire ex1_sub_vld;
wire [4:0] fmau_fpu_ex1_fflags;
wire [7:0] fmau_fpu_ex1_special_sel;
wire [3:0] fmau_fpu_ex1_special_sign;
// &Depend("cpu_cfig.h"); @29
parameter FPU_WIDTH = 64;
parameter SINGLE_FRAC = 23;
parameter DOUBLE_FRAC = 52;
parameter SINGLE_EXPN = 8;
parameter DOUBLE_EXPN = 11;
parameter FUNC_WIDTH = 10;
//==========================================================
// EX1 exception judge
//==========================================================
assign ex1_nv[0] = |dp_xx_ex1_snan[2:0]; //sNan
assign ex1_nv[1] = (dp_xx_ex1_zero[0] && dp_xx_ex1_inf[1]) //0*inf
|| (dp_xx_ex1_zero[1] && dp_xx_ex1_inf[0]);//inf*0
assign ex1_nv[2] = (dp_xx_ex1_inf[0] && dp_xx_ex1_norm[1] && dp_xx_ex1_inf[2] && ex1_sub_vld) //inf*F -inf
|| (dp_xx_ex1_inf[1] && dp_xx_ex1_norm[0] && dp_xx_ex1_inf[2] && ex1_sub_vld) //inf*F -inf
|| (dp_xx_ex1_inf[0] && dp_xx_ex1_inf[1] && dp_xx_ex1_inf[2] && ex1_sub_vld); //inf*inf -inf
assign ex1_fmau_nv = |ex1_nv[2:0];
assign ex1_fmau_of = (ex1_mult_expnt[9 : 8] == 2'b01) && &dp_xx_ex1_norm[1:0] && (dp_xx_ex1_norm[2] || dp_xx_ex1_zero[2]) //single expt >128
|| (ex1_mult_expnt[9 : 0] == 10'b00_1111_1111) && &dp_xx_ex1_norm[1:0] && !ex1_mac; //single expt>127
//==========================================================
// EX1 special result judge
//==========================================================
assign ex1_result_qnan[0] = dp_xx_ex1_snan[0]
|| dp_xx_ex1_qnan[0] && !dp_xx_ex1_snan[1] && !dp_xx_ex1_snan[2];
assign ex1_result_qnan[1] = !dp_xx_ex1_snan[0] && dp_xx_ex1_snan[1]
|| !dp_xx_ex1_snan[0] &&!dp_xx_ex1_qnan[0] && dp_xx_ex1_qnan[1] && !dp_xx_ex1_snan[2];
assign ex1_result_qnan[2] = !dp_xx_ex1_snan[0] && !dp_xx_ex1_snan[1] && dp_xx_ex1_snan[2]
|| !dp_xx_ex1_snan[0] && !dp_xx_ex1_snan[1] && !dp_xx_ex1_qnan[0] && !dp_xx_ex1_qnan[1] && dp_xx_ex1_qnan[2];
assign ex1_fmau_result_cnan = ex1_result_qnan[0] && (dp_xx_ex1_cnan[0] || !cp0_fpu_xx_dqnan)
||ex1_result_qnan[1] && (dp_xx_ex1_cnan[1] || !cp0_fpu_xx_dqnan)
||ex1_result_qnan[2] && (dp_xx_ex1_cnan[2] || !cp0_fpu_xx_dqnan)
||ex1_nv[1] && !ex1_result_qnan[2]
||ex1_nv[2];
assign ex1_fmau_result_qnan[2:0] = ex1_result_qnan[2:0] &(~dp_xx_ex1_cnan[2:0]) & {3{cp0_fpu_xx_dqnan}};
assign ex1_result_zero = dp_xx_ex1_zero[0] && dp_xx_ex1_norm[1] && dp_xx_ex1_zero[2]
|| dp_xx_ex1_zero[1] && dp_xx_ex1_norm[0] && dp_xx_ex1_zero[2]
|| dp_xx_ex1_zero[0] && dp_xx_ex1_zero[1] && dp_xx_ex1_zero[2];
assign ex1_fmau_result_zero = ex1_result_zero;
assign ex1_fmau_zero_sign = ex1_sub_vld ? (ex1_inst_rm[2:0]==3'b010) : ex1_mult_sign;
assign ex1_fmau_result_inf = (|dp_xx_ex1_inf[2:0]) && !(|ex1_result_qnan[2:0]) && !ex1_nv[1] && !ex1_nv[2]
||ex1_fmau_of &&
((ex1_inst_rm[1:0]==2'b00)
|| ex1_mult_sign && (ex1_inst_rm[2:0]==3'b010)
||!ex1_mult_sign && (ex1_inst_rm[2:0]==3'b011));
assign ex1_fmau_inf_sign = (|dp_xx_ex1_inf[1:0] || ex1_fmau_of) ? ex1_mult_sign : ex1_src2_sign;
assign ex1_fmau_result_lfn = ex1_fmau_of &&
((ex1_inst_rm[2:0]==3'b001)
||!ex1_mult_sign && (ex1_inst_rm[2:0]==3'b010)
|| ex1_mult_sign && (ex1_inst_rm[2:0]==3'b011));
assign ex1_fmau_lfn_sign = ex1_mult_sign;
assign ex1_fmau_result_src2 = dp_xx_ex1_zero[0] && dp_xx_ex1_norm[1] && dp_xx_ex1_norm[2] //zero * normal
|| dp_xx_ex1_zero[1] && dp_xx_ex1_norm[0] && dp_xx_ex1_norm[2]
|| dp_xx_ex1_zero[0] && dp_xx_ex1_zero[1] && dp_xx_ex1_norm[2];
assign ex1_fmau_src2_sign = ex1_src2_sign;
assign fmau_fpu_ex1_special_sel[7:0] = {ex1_fmau_result_qnan[2:0],
ex1_fmau_result_cnan,
ex1_fmau_result_lfn,
ex1_fmau_result_inf,
ex1_fmau_result_zero,
ex1_fmau_result_src2};
assign fmau_fpu_ex1_special_sign[3:0]= {ex1_fmau_lfn_sign, ex1_fmau_inf_sign, ex1_fmau_zero_sign, ex1_fmau_src2_sign};
assign fmau_fpu_ex1_fflags[4:0] = {ex1_fmau_nv, 1'b0,ex1_fmau_of,1'b0,ex1_fmau_of};
assign ex1_special_cmplt =|({ex1_fmau_result_qnan[2:0],
ex1_fmau_result_cnan,
ex1_fmau_result_lfn,
ex1_fmau_result_inf,
ex1_fmau_result_zero,
ex1_fmau_result_src2});
// &ModuleEnd; @127
endmodule

507
opene906/E906_RTL_FACTORY/gen_rtl/fmau/rtl/pa_fmau_frac_add.v Normal file
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@ -0,0 +1,507 @@
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @24
module pa_fmau_frac_add(
ctrl_dp_ex2_inst_pipe_down,
ctrl_dp_ex3_inst_pipe_down,
ctrl_xx_ex2_warm_up,
ctrl_xx_ex3_warm_up,
ex2_adder_0_sel_h,
ex2_mac,
ex2_mac_expnt,
ex2_mult_data,
ex2_shift_data,
ex2_sub_vld,
ex3_inst_rm,
ex3_mac_expnt,
ex3_mult_expnt,
ex3_mult_sign,
ex3_sub_vld,
ex4_inst_rm,
fmau_ex3_data_clk,
fmau_ex4_data_clk,
fmau_fpu_ex3_fflags,
fmau_fpu_ex3_result,
fmau_fpu_ex4_fflags,
fmau_fpu_ex4_result
);
// &Ports; @25
input ctrl_dp_ex2_inst_pipe_down;
input ctrl_dp_ex3_inst_pipe_down;
input ctrl_xx_ex2_warm_up;
input ctrl_xx_ex3_warm_up;
input ex2_adder_0_sel_h;
input ex2_mac;
input [9 :0] ex2_mac_expnt;
input [47:0] ex2_mult_data;
input [52:0] ex2_shift_data;
input ex2_sub_vld;
input [2 :0] ex3_inst_rm;
input [9 :0] ex3_mac_expnt;
input [9 :0] ex3_mult_expnt;
input ex3_mult_sign;
input ex3_sub_vld;
input [2 :0] ex4_inst_rm;
input fmau_ex3_data_clk;
input fmau_ex4_data_clk;
output [4 :0] fmau_fpu_ex3_fflags;
output [31:0] fmau_fpu_ex3_result;
output [4 :0] fmau_fpu_ex4_fflags;
output [31:0] fmau_fpu_ex4_result;
// &Regs; @26
reg [52:0] ex3_adder_0;
reg [52:0] ex3_adder_1;
reg [52:0] ex3_adder_result;
reg [22:0] ex3_mult_frac_result;
reg ex3_mult_rnd_in;
reg [1 :0] ex3_mult_single_gs_bit;
reg [15:0] ex3_shift_limit_low;
reg [9 :0] ex4_mac_expnt;
reg ex4_mac_expnt_neg_max;
reg [7 :0] ex4_mac_expnt_result;
reg ex4_mac_frac_not_zero;
reg [52:0] ex4_mac_frac_pre;
reg [22:0] ex4_mac_frac_result;
reg ex4_mac_rnd_in;
reg ex4_mac_shift_32_bit;
reg ex4_mac_sign;
// &Wires; @27
wire ctrl_dp_ex2_inst_pipe_down;
wire ctrl_dp_ex3_inst_pipe_down;
wire ctrl_xx_ex2_warm_up;
wire ctrl_xx_ex3_warm_up;
wire [52:0] ex2_adder_0;
wire [52:0] ex2_adder_0_0;
wire [52:0] ex2_adder_0_1;
wire ex2_adder_0_sel_h;
wire [52:0] ex2_adder_1;
wire ex2_adder_1_for_single_rnd_add_1;
wire ex2_adder_1_for_single_rnd_add_2;
wire [52:0] ex2_adder_1_rnd_data;
wire ex2_mac;
wire [9 :0] ex2_mac_expnt;
wire [47:0] ex2_mult_data;
wire [1 :0] ex2_mult_single_gs_bit;
wire [52:0] ex2_shift_data;
wire [15:0] ex2_shift_limit_low;
wire ex2_shift_limit_vld;
wire ex2_sub_vld;
wire [52:0] ex3_adder_0_result;
wire [52:0] ex3_adder_1_result;
wire [2 :0] ex3_adder_result_sel;
wire [2 :0] ex3_inst_rm;
wire [6 :0] ex3_lza_result;
wire [9 :0] ex3_mac_expnt;
wire [9 :0] ex3_mac_expnt_adjust;
wire ex3_mac_expnt_neg_max;
wire ex3_mac_frac_not_zero;
wire [52:0] ex3_mac_result_shift;
wire ex3_mac_sign;
wire [9 :0] ex3_mult_expnt;
wire ex3_mult_expnt_add_in;
wire [9 :0] ex3_mult_expnt_plus_1;
wire [7 :0] ex3_mult_expnt_result;
wire [1 :0] ex3_mult_frac_sel;
wire [22:0] ex3_mult_no_rnd_result;
wire ex3_mult_nx;
wire [24:0] ex3_mult_result;
wire [2 :0] ex3_mult_rnd_bit;
wire [24:0] ex3_mult_rnd_result;
wire ex3_mult_sign;
wire [31:0] ex3_mult_single_result;
wire [52:0] ex3_shift_limit;
wire [63:0] ex3_shift_limit_one_hot;
wire ex3_sub_vld;
wire ex4_early_of;
wire ex4_expnt_rnd_in;
wire [31:0] ex4_fmau_single_result;
wire [2 :0] ex4_inst_rm;
wire ex4_late_of;
wire [24:0] ex4_mac_data_for_rnd;
wire [23:0] ex4_mac_data_no_rnd;
wire ex4_mac_expnt_plus_1;
wire [2 :0] ex4_mac_expnt_sel;
wire [52:0] ex4_mac_frac;
wire [1 :0] ex4_mac_frac_sel;
wire ex4_mac_nx;
wire ex4_mac_of;
wire [24:0] ex4_mac_rnd_result;
wire ex4_mac_sign_result;
wire ex4_mac_uf;
wire ex4_of_frac_bit;
wire ex4_plus_1_of;
wire [2 :0] ex4_rnd_bit;
wire fmau_ex3_data_clk;
wire fmau_ex4_data_clk;
wire [4 :0] fmau_fpu_ex3_fflags;
wire [31:0] fmau_fpu_ex3_result;
wire [4 :0] fmau_fpu_ex4_fflags;
wire [31:0] fmau_fpu_ex4_result;
// &Depend("cpu_cfig.h"); @29
parameter DOUBLE_WIDTH= 64;
parameter DOUBLE_FRAC = 52;
parameter DOUBLE_EXPN = 11;
parameter ADD_D_WIDTH =111;
parameter FUNC_WIDTH = 10;
parameter SINGLE_WIDTH= 32;
parameter SINGLE_FRAC = 23;
parameter SINGLE_EXPN = 8;
parameter ADD_S_WIDTH = 53;
//==================================================================
// EX2 data prepare
//==================================================================
//case 1: E01+2>=E2 MAC
// MULT_RESULT:0|0|X|X|FRAC_H[51:0]|FRAC_L[51:0]|0|0|0
// SRC2 0|x|FRAC[51:0]|000.........000000000000>>shift index
//case 2: E01+2 < E2 MAC
// MULT_RESULT:0|0|00...00000|0|0|X|X|FRAC_H[51:0]|S
// SRC2 0|x|FRAC[51:0]|00....0.....000000000000>>shift index
//case 3:MULT ROUNDING
// MULT_RESULT:00..........000000|0|X|X|FRAC_H[51:0]|S
// SRC2 00..........000000000000|SINGLE...OUBLE|>>shift index
// &CombBeg; @129
// &CombEnd; @136
// &Instance("pa_fmau_lza_double","x_pa_fmau_lza_double"); @156
// &Connect( .summand (ex3_adder_0 ), @157
// .addend (ex3_adder_1 ), @158
// .sub_vld (ex3_sub_vld ), @159
// .upper_limit (ex3_shift_limit), @160
// .lza_result (ex3_lza_result )); @161
// &CombBeg; @266
// &CombEnd; @275
// &CombBeg; @280
// &CombEnd; @286
// &CombBeg; @304
// &CombEnd; @311
// &CombBeg; @354
// &CombEnd; @363
// &CombBeg; @371
// &CombEnd; @377
//==================================================================
// EX2 data prepare
//==================================================================
//case 1: E01+2>=E2 MAC
// MULT_RESULT:0|0|X|X|FRAC_H[22:0]|FRAC_L[22:0]|0|0|0
// SRC2 0|x|FRAC[22:0]|000.........000000000000>>shift index
//case 2: E01+2 < E2 MAC
// MULT_RESULT:0|0|00...00000|0|0|X|X|FRAC_H[22:0]|S
// SRC2 0|x|FRAC[22:0]|00....0.....000000000000>>shift index
//case 3:MULT ROUNDING
// MULT_RESULT:00..........000000|0|X|X|FRAC_H[22:0]|S
// SRC2 00..........000000000000|SINGLE...OUBLE|>>shift index
assign ex2_adder_0_0[ADD_S_WIDTH-1:0] = {2'b00,{SINGLE_FRAC{1'b0}}, 2'b00, ex2_mult_data[2*SINGLE_FRAC+1:SINGLE_FRAC],|ex2_mult_single_gs_bit[1:0]};
assign ex2_adder_0_1[ADD_S_WIDTH-1:0] = {2'b00, ex2_mult_data[2*SINGLE_FRAC+1:0],3'b0};
assign ex2_adder_0[ADD_S_WIDTH-1:0] = ex2_adder_0_sel_h ? ex2_adder_0_0[ADD_S_WIDTH-1:0] : ex2_adder_0_1[ADD_S_WIDTH-1:0];
assign ex2_adder_1_for_single_rnd_add_1 = !ex2_mac && !ex2_mult_data[2*SINGLE_FRAC+1];
assign ex2_adder_1_for_single_rnd_add_2 = !ex2_mac && ex2_mult_data[2*SINGLE_FRAC+1];
assign ex2_adder_1_rnd_data[ADD_S_WIDTH-1:0] = {{51{1'b0}},ex2_adder_1_for_single_rnd_add_1,{1{1'b0}} }
| {{50{1'b0}},ex2_adder_1_for_single_rnd_add_2,{2{1'b0}} };
assign ex2_adder_1[ADD_S_WIDTH-1:0] = ex2_sub_vld
? ~ex2_shift_data[ADD_S_WIDTH-1:0]
: (ex2_shift_data[ADD_S_WIDTH-1:0] |ex2_adder_1_rnd_data[ADD_S_WIDTH-1:0]);
assign ex2_mult_single_gs_bit[1:0] = {ex2_mult_data[22], |ex2_mult_data[21: 0]};
assign ex2_shift_limit_low[15:0] = 16'b1000_0000_0000_0000 >> ex2_mac_expnt[3:0];
assign ex2_shift_limit_vld = (ex2_mac_expnt[9:6]==4'b0000);
//==========================================================
// EX3 data pipe
//==========================================================
always @(posedge fmau_ex3_data_clk)
begin
if(ctrl_dp_ex2_inst_pipe_down || ctrl_xx_ex2_warm_up)
begin
ex3_mult_single_gs_bit[1:0] <= ex2_mult_single_gs_bit[1:0];
ex3_adder_0[ADD_S_WIDTH-1:0] <= ex2_adder_0[ADD_S_WIDTH-1:0];
ex3_adder_1[ADD_S_WIDTH-1:0] <= ex2_adder_1[ADD_S_WIDTH-1:0];
ex3_shift_limit_low[15:0] <= ex2_shift_limit_low[15:0] & {16{ex2_shift_limit_vld}};
end
end
assign ex3_shift_limit_one_hot[63:0] = {ex3_shift_limit_low[15:0],{48{1'b0}} } >> {ex3_mac_expnt[5:4],4'b0};
assign ex3_shift_limit[52:0] = ex3_shift_limit_one_hot[63:11];
//==========================================================
// EX3 adders
//==========================================================
assign ex3_adder_0_result[ADD_S_WIDTH-1:0] = ex3_adder_0[ADD_S_WIDTH-1:0] + ex3_adder_1[ADD_S_WIDTH-1:0];
assign ex3_adder_1_result[ADD_S_WIDTH-1:0] = ex3_adder_0[ADD_S_WIDTH-1:0] + ex3_adder_1[ADD_S_WIDTH-1:0] + 1'b1;
assign ex3_adder_result_sel[0] = !ex3_sub_vld;
assign ex3_adder_result_sel[1] = ex3_sub_vld && ex3_adder_1_result[ADD_S_WIDTH-1];
assign ex3_adder_result_sel[2] = ex3_sub_vld &&!ex3_adder_1_result[ADD_S_WIDTH-1];
// &CombBeg; @484
always @( ex3_adder_0_result[52:0]
or ex3_adder_1_result[52:0]
or ex3_adder_result_sel[2:0])
begin
case(ex3_adder_result_sel[2:0])
3'b001: ex3_adder_result[ADD_S_WIDTH-1:0] = ex3_adder_0_result[ADD_S_WIDTH-1:0];
3'b010: ex3_adder_result[ADD_S_WIDTH-1:0] =~ex3_adder_0_result[ADD_S_WIDTH-1:0];
3'b100: ex3_adder_result[ADD_S_WIDTH-1:0] = ex3_adder_1_result[ADD_S_WIDTH-1:0];
default: ex3_adder_result[ADD_S_WIDTH-1:0] = {ADD_S_WIDTH{1'bx}};
endcase
// &CombEnd; @491
end
assign ex3_mac_sign = ex3_mult_sign ^(ex3_sub_vld && ex3_adder_1_result[ADD_S_WIDTH-1]);
assign ex3_mac_frac_not_zero = |ex3_adder_result[ADD_S_WIDTH-1:0];
//==========================================================
// EX3 early overflow judge
//==========================================================
//assign ex3_single_of = (ex3_mac_expnt[9:0]==10'b01_0000_0001) && |ex3_adder_result[ADD_S_WIDTH-1:ADD_S_WIDTH-4] //expn=130,frac=1x.xxx or 01.xxx or 00.1xxx or 00.01x
// ||(ex3_mac_expnt[9:0]==10'b01_0000_0000) && |ex3_adder_result[ADD_S_WIDTH-1:ADD_S_WIDTH-3] //expn=129,frac=1x.xxx or 01.xxx or 00.1xxx
// ||(ex3_mac_expnt[9:0]==10'b00_1111_1111) && |ex3_adder_result[ADD_S_WIDTH-1:ADD_S_WIDTH-2] //expn=128,frac=1x.xxx or 01.xxx
// ||(ex3_mac_expnt[9:0]==10'b00_1111_1110) && ex3_adder_result[ADD_S_WIDTH-1]; //expn=127, frac=1x.xxx
//======================================================================
// leading zero predict
//======================================================================
// &Instance("pa_fmau_lza_single","x_pa_fmau_lza_single"); @506
pa_fmau_lza_single x_pa_fmau_lza_single (
.addend (ex3_adder_1 ),
.lza_result (ex3_lza_result ),
.sub_vld (ex3_sub_vld ),
.summand (ex3_adder_0 ),
.upper_limit (ex3_shift_limit)
);
// &Connect( .summand (ex3_adder_0 ), @507
// .addend (ex3_adder_1 ), @508
// .sub_vld (ex3_sub_vld ), @509
// .upper_limit (ex3_shift_limit), @510
// .lza_result (ex3_lza_result )); @511
//==========================================================
// EX3 result pipe down
//==========================================================
assign ex3_mac_result_shift[ADD_S_WIDTH-1:0] = ex3_adder_result[ADD_S_WIDTH-1:0]<<{ex3_lza_result[4:0]};
assign ex3_mac_expnt_adjust[SINGLE_EXPN+1:0] = ex3_mac_expnt[SINGLE_EXPN+1:0] -{ {4{1'b0}},ex3_lza_result[5:0]};//plus1
assign ex3_mac_expnt_neg_max =(ex3_mac_expnt[SINGLE_EXPN+1:0] == { {4{1'b0}},ex3_lza_result[5:0]});
always @(posedge fmau_ex4_data_clk)
begin
if(ctrl_dp_ex3_inst_pipe_down || ctrl_xx_ex3_warm_up)
begin
ex4_mac_expnt[SINGLE_EXPN+1:0] <= ex3_mac_expnt_adjust[SINGLE_EXPN+1:0];
ex4_mac_frac_pre[ADD_S_WIDTH-1:0] <= ex3_mac_result_shift[ADD_S_WIDTH-1:0];
ex4_mac_expnt_neg_max <= ex3_mac_expnt_neg_max;
ex4_mac_frac_not_zero <= ex3_mac_frac_not_zero;
ex4_mac_shift_32_bit <= ex3_lza_result[5];
ex4_mac_sign <= ex3_mac_sign;
// ex4_single_of <= ex3_single_of;
end
end
//======================================================================
// EX4 MAC RESULT ROUNDING
//======================================================================
assign ex4_mac_frac[ADD_S_WIDTH-1:0] = ex4_mac_shift_32_bit ? {ex4_mac_frac_pre[ADD_S_WIDTH-33:0], {32{1'b0}} }
: ex4_mac_frac_pre[ADD_S_WIDTH- 1:0];
assign ex4_early_of = (ex4_mac_expnt[9 : 8]==2'b01)||(ex4_mac_expnt[9 : 0]==10'b00_1111_1111);
assign ex4_plus_1_of=(ex4_mac_expnt[9:0] == 10'b00_1111_1110) && ex4_mac_expnt_plus_1;
assign ex4_of_frac_bit = (ex4_inst_rm[2:0]==3'b001)//rnd to zero
||(ex4_inst_rm[2:0]==3'b010) && !ex4_mac_sign //rnd to neg and !sign
||(ex4_inst_rm[2:0]==3'b011) && ex4_mac_sign;//rnd to pos and sign
assign ex4_mac_expnt_plus_1 = ex4_mac_frac[ADD_S_WIDTH-1] || ex4_mac_expnt_neg_max;
assign ex4_mac_data_no_rnd[SINGLE_FRAC:0] =(ex4_mac_frac[ADD_S_WIDTH-1] || ex4_mac_expnt_neg_max)
? ex4_mac_frac[ADD_S_WIDTH-1:ADD_S_WIDTH-SINGLE_FRAC-1]
: ex4_mac_frac[ADD_S_WIDTH-2:ADD_S_WIDTH-SINGLE_FRAC-2];
assign ex4_mac_data_for_rnd[SINGLE_FRAC+1:0] = {1'b0, ex4_mac_data_no_rnd[SINGLE_FRAC:0]};
assign ex4_mac_rnd_result[SINGLE_FRAC+1:0] = ex4_mac_data_for_rnd[SINGLE_FRAC+1:0] +
{ {24{1'b0}},1'b1 };
assign ex4_rnd_bit[2:0] = (ex4_mac_frac[ADD_S_WIDTH-1] || ex4_mac_expnt_neg_max)
? {ex4_mac_frac[29:28],|ex4_mac_frac[27:0]}
: {ex4_mac_frac[28:27],|ex4_mac_frac[26:0]};
// &CombBeg; @587
always @( ex4_inst_rm[2:0]
or ex4_mac_sign
or ex4_rnd_bit[2:0])
begin
case(ex4_inst_rm[2:0])
3'b000: ex4_mac_rnd_in = ex4_rnd_bit[1] && (ex4_rnd_bit[0] || ex4_rnd_bit[2]); //round to nearest even
3'b001: ex4_mac_rnd_in = 1'b0;
3'b010: ex4_mac_rnd_in = ex4_mac_sign && |ex4_rnd_bit[1:0]; //round to negative infinity
3'b011: ex4_mac_rnd_in =!ex4_mac_sign && |ex4_rnd_bit[1:0]; //round to positive infinity
3'b100: ex4_mac_rnd_in = ex4_rnd_bit[1];
default : ex4_mac_rnd_in = 1'b0;
endcase
// &CombEnd; @596
end
assign ex4_mac_frac_sel[0] = ex4_mac_rnd_result[SINGLE_FRAC+1] && ex4_mac_rnd_in && !ex4_early_of && !ex4_plus_1_of; //1x.xxx after rnd,no of
assign ex4_mac_frac_sel[1] =!ex4_mac_rnd_result[SINGLE_FRAC+1] && ex4_mac_rnd_in && !ex4_early_of && !ex4_plus_1_of; //0x.xxx after rnd,no of
// &CombBeg; @601
always @( ex4_mac_rnd_result[23:0]
or ex4_early_of
or ex4_mac_data_no_rnd[22:0]
or ex4_mac_frac_sel[1:0]
or ex4_plus_1_of
or ex4_of_frac_bit)
begin
case(ex4_mac_frac_sel[1:0])
2'b01: ex4_mac_frac_result[SINGLE_FRAC-1:0] = ex4_mac_rnd_result[SINGLE_FRAC:1];
2'b10: ex4_mac_frac_result[SINGLE_FRAC-1:0] = ex4_mac_rnd_result[SINGLE_FRAC-1:0];
default: ex4_mac_frac_result[SINGLE_FRAC-1:0] =(ex4_early_of || ex4_plus_1_of) ? {SINGLE_FRAC{ex4_of_frac_bit}} : ex4_mac_data_no_rnd[SINGLE_FRAC-1:0];
endcase
// &CombEnd; @607
end
assign ex4_expnt_rnd_in = ex4_mac_rnd_in &&
&(ex4_mac_data_for_rnd[SINGLE_FRAC-1:0]);
assign ex4_mac_expnt_sel[2] = ex4_mac_data_no_rnd[SINGLE_FRAC] && ex4_mac_frac_not_zero && !ex4_early_of
&& ex4_expnt_rnd_in && ex4_mac_expnt_plus_1 && !ex4_plus_1_of; //plus 2
assign ex4_mac_expnt_sel[1] = ex4_mac_data_no_rnd[SINGLE_FRAC] && ex4_mac_frac_not_zero && !ex4_early_of
&&(ex4_expnt_rnd_in ^ ex4_mac_expnt_plus_1) && !ex4_plus_1_of //plus 1
||!ex4_mac_data_no_rnd[SINGLE_FRAC] && ex4_mac_frac_not_zero && !ex4_early_of
&& ex4_expnt_rnd_in; //plus 1
assign ex4_mac_expnt_sel[0] = ex4_mac_data_no_rnd[SINGLE_FRAC] && ex4_mac_frac_not_zero && !ex4_early_of
&&!ex4_expnt_rnd_in && !ex4_mac_expnt_plus_1 //plus 0
||!ex4_mac_data_no_rnd[SINGLE_FRAC] && ex4_mac_frac_not_zero && !ex4_early_of
&&!ex4_expnt_rnd_in;
// &CombBeg; @624
always @( ex4_mac_expnt[7:0]
or ex4_mac_expnt_sel[2:0]
or ex4_early_of
or ex4_plus_1_of
or ex4_of_frac_bit)
begin
case(ex4_mac_expnt_sel[2:0])
3'b100: ex4_mac_expnt_result[SINGLE_EXPN-1:0] = ex4_mac_expnt[SINGLE_EXPN-1:0] + 8'b0000_0010;
3'b010: ex4_mac_expnt_result[SINGLE_EXPN-1:0] = ex4_mac_expnt[SINGLE_EXPN-1:0] + 8'b0000_0001;
3'b001: ex4_mac_expnt_result[SINGLE_EXPN-1:0] = ex4_mac_expnt[SINGLE_EXPN-1:0];
default: ex4_mac_expnt_result[SINGLE_EXPN-1:0] =(ex4_early_of || ex4_plus_1_of) ? {{7{1'b1}},!ex4_of_frac_bit}: 8'b0000_0000;
endcase
// &CombEnd; @631
end
assign ex4_mac_sign_result = ex4_mac_frac_not_zero ? ex4_mac_sign : (ex4_inst_rm[2:0]==3'b010);
assign ex4_late_of = (ex4_mac_expnt[7:0]==8'b1111_1101) && ex4_mac_expnt_sel[2]
||(ex4_mac_expnt[7:0]==8'b1111_1110) && ex4_mac_expnt_sel[1];
assign ex4_mac_of = ex4_early_of || ex4_plus_1_of || ex4_late_of;
assign ex4_mac_uf = ex4_mac_expnt_neg_max && |ex4_rnd_bit[1:0] //inexact frac
&& !ex4_expnt_rnd_in && !ex4_mac_data_no_rnd[SINGLE_FRAC];
assign ex4_mac_nx = |ex4_rnd_bit[1:0];
assign fmau_fpu_ex4_fflags[4:0] = {1'b0, 1'b0,ex4_mac_of,ex4_mac_uf,ex4_mac_nx || ex4_mac_of};
assign ex4_fmau_single_result[31:0] = {ex4_mac_sign_result,ex4_mac_expnt_result[7:0],ex4_mac_frac_result[22:0]};
assign fmau_fpu_ex4_result[31:0] = ex4_fmau_single_result[31:0];
//==================================================================================
// EX3 normal mult rounding:expnt= [-126/-1022,126/1022] && no denormal no overflow
//==================================================================================
assign ex3_mult_result[SINGLE_FRAC+1:0] = ex3_adder_0[SINGLE_FRAC+2:1];
assign ex3_mult_rnd_result[SINGLE_FRAC+1:0] = ex3_adder_0_result[SINGLE_FRAC+2:1];
assign ex3_mult_rnd_bit[2:0] = ex3_mult_result[SINGLE_FRAC+1]
?{ex3_mult_result[1:0],|ex3_mult_single_gs_bit[1:0]}
:{ex3_mult_result[0], ex3_mult_single_gs_bit[1:0]};
// &CombBeg; @663
always @( ex3_mult_sign
or ex3_inst_rm[2:0]
or ex3_mult_rnd_bit[2:0])
begin
case(ex3_inst_rm[2:0])
3'b000: ex3_mult_rnd_in = ex3_mult_rnd_bit[1] && (ex3_mult_rnd_bit[0] || ex3_mult_rnd_bit[2]); //round to nearest even
3'b001: ex3_mult_rnd_in = 1'b0;
3'b010: ex3_mult_rnd_in = ex3_mult_sign && |ex3_mult_rnd_bit[1:0]; //round to negative infinity
3'b011: ex3_mult_rnd_in =!ex3_mult_sign && |ex3_mult_rnd_bit[1:0]; //round to positive infinity
3'b100: ex3_mult_rnd_in = ex3_mult_rnd_bit[1];
default : ex3_mult_rnd_in = 1'b0;
endcase
// &CombEnd; @672
end
assign ex3_mult_frac_sel[0] = ex3_mult_rnd_result[SINGLE_FRAC+1] && ex3_mult_rnd_in;
assign ex3_mult_frac_sel[1] =!ex3_mult_rnd_result[SINGLE_FRAC+1] && ex3_mult_rnd_in;
assign ex3_mult_no_rnd_result[SINGLE_FRAC-1:0] = ex3_mult_result[SINGLE_FRAC+1]
? ex3_mult_result[SINGLE_FRAC:1]
: ex3_mult_result[SINGLE_FRAC-1:0];
// &CombBeg; @680
always @( ex3_mult_no_rnd_result[22:0]
or ex3_mult_frac_sel[1:0]
or ex3_mult_rnd_result[23:0])
begin
case(ex3_mult_frac_sel[1:0])
2'b01: ex3_mult_frac_result[SINGLE_FRAC-1:0] = ex3_mult_rnd_result[SINGLE_FRAC:1];
2'b10: ex3_mult_frac_result[SINGLE_FRAC-1:0] = ex3_mult_rnd_result[SINGLE_FRAC-1:0];
default: ex3_mult_frac_result[SINGLE_FRAC-1:0] = ex3_mult_no_rnd_result[SINGLE_FRAC-1:0];
endcase
// &CombEnd; @686
end
assign ex3_mult_expnt_add_in = ex3_mult_result[SINGLE_FRAC+1]
|| &ex3_mult_result[SINGLE_FRAC-1:0] && ex3_mult_rnd_in;
assign ex3_mult_expnt_plus_1[SINGLE_EXPN+1:0] = ex3_mult_expnt[SINGLE_EXPN+1:0] + 1'b1;
assign ex3_mult_expnt_result[SINGLE_EXPN-1:0] = ex3_mult_expnt_add_in
? ex3_mult_expnt_plus_1[SINGLE_EXPN-1:0]
: ex3_mult_expnt[SINGLE_EXPN-1:0];
assign ex3_mult_single_result[SINGLE_WIDTH-1:0] = { ex3_mult_sign,
ex3_mult_expnt_result[SINGLE_EXPN-1:0],
ex3_mult_frac_result[SINGLE_FRAC-1:SINGLE_FRAC-SINGLE_FRAC]};
assign ex3_mult_nx = |ex3_mult_rnd_bit[1:0];
assign fmau_fpu_ex3_result[SINGLE_WIDTH-1:0] = ex3_mult_single_result[SINGLE_WIDTH-1:0];
assign fmau_fpu_ex3_fflags[4:0] = {4'b0,ex3_mult_nx};
// &ModuleEnd; @708
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @24
module pa_fmau_frac_mult(
ctrl_dp_ex1_inst_pipe_down,
ctrl_xx_ex1_warm_up,
ex1_frac_0,
ex1_frac_1,
ex2_mult_data,
fmau_ex2_data_clk
);
// &Ports; @25
input ctrl_dp_ex1_inst_pipe_down;
input ctrl_xx_ex1_warm_up;
input [23:0] ex1_frac_0;
input [23:0] ex1_frac_1;
input fmau_ex2_data_clk;
output [47:0] ex2_mult_data;
// &Regs; @26
reg [47:0] ex2_partial_result_0;
reg [47:0] ex2_partial_result_1;
// &Wires; @27
wire ctrl_dp_ex1_inst_pipe_down;
wire ctrl_xx_ex1_warm_up;
wire [23:0] ex1_frac_0;
wire [23:0] ex1_frac_1;
wire [49:0] ex1_partial_result_0;
wire [49:0] ex1_partial_result_1;
wire [47:0] ex2_mult_data;
wire fmau_ex2_data_clk;
wire [23:0] mult_0_0;
wire [23:0] mult_0_1;
wire [49:0] result_0_0;
wire [49:0] result_0_1;
// &Depend("cpu_cfig.h"); @29
parameter FPU_WIDTH = 64;
parameter SINGLE_FRAC = 23;
parameter DOUBLE_FRAC = 52;
parameter SINGLE_EXPN = 8;
parameter DOUBLE_EXPN = 11;
parameter FUNC_WIDTH = 10;
//==========================================================
// EX1 data path
//==========================================================
// &Instance("pa_fmau_multiplier_53x27_partial","multiplier_53x27"); @52
// &Connect( @53
// .a(mult_0_0), @54
// .b(mult_0_1), @55
// .out0(result_0_0), @56
// .out1(result_0_1) @57
// ); @58
// &Instance("pa_fmau_multiplier_53x27_partial","multiplier_53x26"); @60
// &Connect( @61
// .a(mult_1_0), @62
// .b(mult_1_1), @63
// .out0(result_1_0), @64
// .out1(result_1_1) @65
// ); @66
// &Force("bus","result_0_0",83,0); @68
// &Force("bus","result_0_1",83,0); @69
// &Force("bus","result_1_0",83,0); @70
// &Force("bus","result_1_1",83,0); @71
// &Force("nonport", "mult_0_0"); @79
// &Force("nonport", "mult_0_1"); @80
// &Force("nonport", "result_0_0"); @81
// &Force("nonport", "result_0_1"); @82
// &Force("nonport", "mult_1_0"); @92
// &Force("nonport", "mult_1_1"); @93
// &Force("nonport", "result_1_0"); @94
// &Force("nonport", "result_1_1"); @95
assign mult_0_0[23:0] = ex1_frac_0[23:0];
assign mult_0_1[23:0] = ex1_frac_1[23:0];
// &Instance("pa_fmau_multiplier_24x24_partial","multiplier_24x24"); @164
pa_fmau_multiplier_24x24_partial multiplier_24x24 (
.a (mult_0_0 ),
.b (mult_0_1 ),
.out0 (result_0_0),
.out1 (result_0_1)
);
// &Connect( @165
// .a(mult_0_0), @166
// .b(mult_0_1), @167
// .out0(result_0_0), @168
// .out1(result_0_1) @169
// ); @170
// &Force("nonport", "mult_0_0"); @174
// &Force("nonport", "mult_0_1"); @175
// &Force("nonport", "result_0_0"); @176
// &Force("nonport", "result_0_1"); @177
assign ex1_partial_result_0[49:0] = result_0_0[49:0];
assign ex1_partial_result_1[49:0] = result_0_1[49:0];
always@(posedge fmau_ex2_data_clk)
begin
if(ctrl_dp_ex1_inst_pipe_down || ctrl_xx_ex1_warm_up)
begin
ex2_partial_result_0[47:0] <= ex1_partial_result_0[47:0];
ex2_partial_result_1[47:0] <= ex1_partial_result_1[47:0];
end
end
assign ex2_mult_data[47:0] = ex2_partial_result_0[47:0] + ex2_partial_result_1[47:0];
// &ModuleEnd; @220
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @24
module pa_fmau_frac_shift(
ctrl_dp_ex1_inst_pipe_down,
ctrl_xx_ex1_warm_up,
ex1_expnt_2,
ex1_mult_expnt,
ex2_adder_0_sel_h,
ex2_expnt_2,
ex2_frac_2,
ex2_mac,
ex2_mac_expnt,
ex2_mult_expnt,
ex2_shift_data,
fmau_ex2_data_clk
);
// &Ports; @25
input ctrl_dp_ex1_inst_pipe_down;
input ctrl_xx_ex1_warm_up;
input [9 :0] ex1_expnt_2;
input [9 :0] ex1_mult_expnt;
input [9 :0] ex2_expnt_2;
input [23:0] ex2_frac_2;
input ex2_mac;
input [9 :0] ex2_mult_expnt;
input fmau_ex2_data_clk;
output ex2_adder_0_sel_h;
output [9 :0] ex2_mac_expnt;
output [52:0] ex2_shift_data;
// &Regs; @26
reg [9 :0] ex2_left_max;
reg [9 :0] ex2_mac_expnt_diff;
reg ex2_right_sel;
reg [5 :0] ex2_shift_index;
// &Wires; @27
wire ctrl_dp_ex1_inst_pipe_down;
wire ctrl_xx_ex1_warm_up;
wire [9 :0] ex1_expnt_2;
wire [9 :0] ex1_left_max;
wire [9 :0] ex1_mac_expnt_diff;
wire [9 :0] ex1_mult_expnt;
wire [9 :0] ex1_right_max;
wire ex1_right_sel;
wire ex2_adder_0_sel_h;
wire [23:0] ex2_data_for_shift;
wire [9 :0] ex2_expnt_2;
wire [23:0] ex2_frac_2;
wire ex2_mac;
wire [9 :0] ex2_mac_expnt;
wire [9 :0] ex2_mult_expnt;
wire [9 :0] ex2_right_max;
wire [52:0] ex2_shift_data;
wire [52:0] ex2_shift_data_out;
wire [2 :0] ex2_shift_sel;
wire fmau_ex2_data_clk;
// &Depend("cpu_cfig.h"); @29
parameter DOUBLE_WIDTH= 64;
parameter DOUBLE_FRAC = 52;
parameter DOUBLE_EXPN = 11;
parameter SINGLE_WIDTH= 32;
parameter SINGLE_FRAC = 23;
parameter SINGLE_EXPN = 8;
parameter FUNC_WIDTH = 10;
//==========================================================
// EX1 data path
//==========================================================
// &CombBeg; @88
// &CombEnd; @95
// &Instance("pa_fmau_src2_shifter_double","x_pa_fmau_src2_shifter_double"); @107
assign ex1_mac_expnt_diff[SINGLE_EXPN+1:0] = ex1_mult_expnt[SINGLE_EXPN+1:0] +
{{SINGLE_EXPN{1'b0}},2'b10} -
{ex1_expnt_2[SINGLE_EXPN+1:0]};
assign ex1_right_max[SINGLE_EXPN+1:0] = 10'b00_0011_0011;//51=2*FRAC+5
assign ex1_right_sel = (ex1_mac_expnt_diff[SINGLE_EXPN:0]< ex1_right_max[SINGLE_EXPN:0]);
assign ex1_left_max[SINGLE_EXPN+1:0] = 10'b00_0001_1001 + //FRAC+2 -(-D)
+ ex1_mac_expnt_diff[SINGLE_EXPN+1:0];
always @(posedge fmau_ex2_data_clk)
begin
if(ctrl_dp_ex1_inst_pipe_down || ctrl_xx_ex1_warm_up)
begin
ex2_mac_expnt_diff[SINGLE_EXPN+1:0]<= ex1_mac_expnt_diff[SINGLE_EXPN+1:0];
ex2_left_max[SINGLE_EXPN+1:0] <= ex1_left_max[SINGLE_EXPN+1:0];
ex2_right_sel <= ex1_right_sel;
end
end
assign ex2_shift_sel[0] = !ex2_mac_expnt_diff[SINGLE_EXPN+1] && ex2_right_sel;//right shift diff
assign ex2_shift_sel[1] = !ex2_mac_expnt_diff[SINGLE_EXPN+1] && !ex2_right_sel;//right shift 2*FRAC+5
assign ex2_shift_sel[2] = ex2_mac_expnt_diff[SINGLE_EXPN+1] && !ex2_left_max[SINGLE_EXPN+1]; //left shift FRAC+2-|diff|
assign ex2_right_max[SINGLE_EXPN+1:0] = 10'b00_0011_0011;//51=2*FRAC+5
// &CombBeg; @156
always @( ex2_left_max[5:0]
or ex2_right_max[5:0]
or ex2_mac_expnt_diff[5:0]
or ex2_shift_sel[2:0])
begin
case(ex2_shift_sel[2:0])
3'b001: ex2_shift_index[5:0] = ex2_mac_expnt_diff[5:0];
3'b010: ex2_shift_index[5:0] = ex2_right_max[5:0];
3'b100: ex2_shift_index[5:0] = ex2_left_max[5:0];
default: ex2_shift_index[5:0] = {6{1'b0}};
endcase
// &CombEnd; @163
end
assign ex2_mac_expnt[SINGLE_EXPN+1:0] = ex2_mac_expnt_diff[SINGLE_EXPN+1]
? ex2_expnt_2[SINGLE_EXPN+1:0] + { {4{1'b0}},ex2_shift_index[5:0]}
: ex2_mult_expnt[SINGLE_EXPN+1:0]+{ {SINGLE_EXPN{1'b0}},2'b10};
assign ex2_data_for_shift[SINGLE_FRAC:0] = ex2_frac_2[SINGLE_FRAC:0];
assign ex2_adder_0_sel_h = ex2_mac_expnt_diff[SINGLE_EXPN+1] || !ex2_mac;
//==========================================================
// EX2 data path
//==========================================================
// &Instance("pa_fmau_src2_shifter_single","x_pa_fmau_src2_shifter_single"); @175
pa_fmau_src2_shifter_single x_pa_fmau_src2_shifter_single (
.ex2_data_for_shift (ex2_data_for_shift),
.ex2_shift_data_out (ex2_shift_data_out),
.ex2_shift_index (ex2_shift_index )
);
assign ex2_shift_data[52:0] = ex2_shift_data_out[52:0];
// &ModuleEnd; @180
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_fmau_lza_single(
addend,
lza_result,
sub_vld,
summand,
upper_limit
);
// &Ports; @24
input [52:0] addend;
input sub_vld;
input [52:0] summand;
input [52:0] upper_limit;
output [6 :0] lza_result;
// &Regs; @25
reg [6 :0] lza_result;
// &Wires; @26
wire [52:0] addend;
wire [52:0] carry_d;
wire [52:0] carry_g;
wire [52:0] carry_p;
wire [52:0] data_for_ff1;
wire [52:0] lza_precod;
wire sub_vld;
wire [52:0] summand;
wire [52:0] upper_limit;
parameter DATA_WIDTH = 53;
//==========================================================
// Signal Pre-encode
//==========================================================
//----------------------------------------------------------
// Signal preparation
//----------------------------------------------------------
// carry_p: carry propagete
// carry_g: carry generate
// carry_d: carry delete
assign carry_p[DATA_WIDTH-1:0] = summand[DATA_WIDTH-1:0] ^ addend[DATA_WIDTH-1:0];
assign carry_g[DATA_WIDTH-1:0] = summand[DATA_WIDTH-1:0] & addend[DATA_WIDTH-1:0];
assign carry_d[DATA_WIDTH-1:0] = ~(summand[DATA_WIDTH-1:0] | addend[DATA_WIDTH-1:0]);
//----------------------------------------------------------
// Signal decode
//----------------------------------------------------------
//pre-predecode for leading zero anticipation
assign lza_precod[0] =
carry_p[1] && (carry_g[0] && sub_vld || carry_d[0])
|| !carry_p[1] && (carry_d[0] && sub_vld || carry_g[0]);
assign lza_precod[DATA_WIDTH-1] =
sub_vld && (carry_g[DATA_WIDTH-1] && !carry_d[DATA_WIDTH-2]
|| carry_d[DATA_WIDTH-1] && !carry_g[DATA_WIDTH-2])
|| !sub_vld && (carry_d[DATA_WIDTH-1] && !carry_d[DATA_WIDTH-2]
|| !carry_d[DATA_WIDTH-1]);
assign lza_precod[DATA_WIDTH-2:1] =
carry_p[DATA_WIDTH-1:2] & (carry_g[DATA_WIDTH-2:1] & ~carry_d[DATA_WIDTH-3:0]
| carry_d[DATA_WIDTH-2:1] & ~carry_g[DATA_WIDTH-3:0])
| ~carry_p[DATA_WIDTH-1:2] & (carry_g[DATA_WIDTH-2:1] & ~carry_g[DATA_WIDTH-3:0]
| carry_d[DATA_WIDTH-2:1] & ~carry_d[DATA_WIDTH-3:0]);
//==========================================================
// LZA coding
//==========================================================
assign data_for_ff1[DATA_WIDTH-1:0] = lza_precod[DATA_WIDTH-1:0] | upper_limit[DATA_WIDTH-1:0];
// &CombBeg; @66
always @( data_for_ff1[52:0])
begin
casez(data_for_ff1[DATA_WIDTH-1:0])
53'b1????????????????????????????????????????????????????:lza_result[6:0] = 7'd0;
53'b01???????????????????????????????????????????????????:lza_result[6:0] = 7'd1;
53'b001??????????????????????????????????????????????????:lza_result[6:0] = 7'd2;
53'b0001?????????????????????????????????????????????????:lza_result[6:0] = 7'd3;
53'b00001????????????????????????????????????????????????:lza_result[6:0] = 7'd4;
53'b000001???????????????????????????????????????????????:lza_result[6:0] = 7'd5;
53'b0000001??????????????????????????????????????????????:lza_result[6:0] = 7'd6;
53'b00000001?????????????????????????????????????????????:lza_result[6:0] = 7'd7;
53'b000000001????????????????????????????????????????????:lza_result[6:0] = 7'd8;
53'b0000000001???????????????????????????????????????????:lza_result[6:0] = 7'd9;
53'b00000000001??????????????????????????????????????????:lza_result[6:0] = 7'd10;
53'b000000000001?????????????????????????????????????????:lza_result[6:0] = 7'd11;
53'b0000000000001????????????????????????????????????????:lza_result[6:0] = 7'd12;
53'b00000000000001???????????????????????????????????????:lza_result[6:0] = 7'd13;
53'b000000000000001??????????????????????????????????????:lza_result[6:0] = 7'd14;
53'b0000000000000001?????????????????????????????????????:lza_result[6:0] = 7'd15;
53'b00000000000000001????????????????????????????????????:lza_result[6:0] = 7'd16;
53'b000000000000000001???????????????????????????????????:lza_result[6:0] = 7'd17;
53'b0000000000000000001??????????????????????????????????:lza_result[6:0] = 7'd18;
53'b00000000000000000001?????????????????????????????????:lza_result[6:0] = 7'd19;
53'b000000000000000000001????????????????????????????????:lza_result[6:0] = 7'd20;
53'b0000000000000000000001???????????????????????????????:lza_result[6:0] = 7'd21;
53'b00000000000000000000001??????????????????????????????:lza_result[6:0] = 7'd22;
53'b000000000000000000000001?????????????????????????????:lza_result[6:0] = 7'd23;
53'b0000000000000000000000001????????????????????????????:lza_result[6:0] = 7'd24;
53'b00000000000000000000000001???????????????????????????:lza_result[6:0] = 7'd25;
53'b000000000000000000000000001??????????????????????????:lza_result[6:0] = 7'd26;
53'b0000000000000000000000000001?????????????????????????:lza_result[6:0] = 7'd27;
53'b00000000000000000000000000001????????????????????????:lza_result[6:0] = 7'd28;
53'b000000000000000000000000000001???????????????????????:lza_result[6:0] = 7'd29;
53'b0000000000000000000000000000001??????????????????????:lza_result[6:0] = 7'd30;
53'b00000000000000000000000000000001?????????????????????:lza_result[6:0] = 7'd31;
53'b000000000000000000000000000000001????????????????????:lza_result[6:0] = 7'd32;
53'b0000000000000000000000000000000001???????????????????:lza_result[6:0] = 7'd33;
53'b00000000000000000000000000000000001??????????????????:lza_result[6:0] = 7'd34;
53'b000000000000000000000000000000000001?????????????????:lza_result[6:0] = 7'd35;
53'b0000000000000000000000000000000000001????????????????:lza_result[6:0] = 7'd36;
53'b00000000000000000000000000000000000001???????????????:lza_result[6:0] = 7'd37;
53'b000000000000000000000000000000000000001??????????????:lza_result[6:0] = 7'd38;
53'b0000000000000000000000000000000000000001?????????????:lza_result[6:0] = 7'd39;
53'b00000000000000000000000000000000000000001????????????:lza_result[6:0] = 7'd40;
53'b000000000000000000000000000000000000000001???????????:lza_result[6:0] = 7'd41;
53'b0000000000000000000000000000000000000000001??????????:lza_result[6:0] = 7'd42;
53'b00000000000000000000000000000000000000000001?????????:lza_result[6:0] = 7'd43;
53'b000000000000000000000000000000000000000000001????????:lza_result[6:0] = 7'd44;
53'b0000000000000000000000000000000000000000000001???????:lza_result[6:0] = 7'd45;
53'b00000000000000000000000000000000000000000000001??????:lza_result[6:0] = 7'd46;
53'b000000000000000000000000000000000000000000000001?????:lza_result[6:0] = 7'd47;
53'b0000000000000000000000000000000000000000000000001????:lza_result[6:0] = 7'd48;
53'b00000000000000000000000000000000000000000000000001???:lza_result[6:0] = 7'd49;
53'b000000000000000000000000000000000000000000000000001??:lza_result[6:0] = 7'd50;
53'b0000000000000000000000000000000000000000000000000001?:lza_result[6:0] = 7'd51;
53'b00000000000000000000000000000000000000000000000000001:lza_result[6:0] = 7'd52;
53'b00000000000000000000000000000000000000000000000000000:lza_result[6:0] = 7'd53;
default :lza_result[6:0] = 7'd0;
endcase
// &CombEnd; @124
end
// &ModuleEnd; @126
endmodule

444
opene906/E906_RTL_FACTORY/gen_rtl/fmau/rtl/pa_fmau_multiplier_24x24_partial.v Normal file
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@ -0,0 +1,444 @@
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_fmau_multiplier_24x24_partial(
a,
b,
out0,
out1
);
// &Ports; @21
input [23:0] a;
input [23:0] b;
output [49:0] out0;
output [49:0] out1;
// &Regs; @22
// &Wires; @23
wire [23:0] a;
wire [23:0] b;
wire [26:0] data_for_code;
wire [49:0] ex1_c0_0;
wire [49:0] ex1_c0_1;
wire [49:0] ex1_c0_2;
wire [49:0] ex1_c1_0;
wire [49:0] ex1_c1_1;
wire [50:0] ex1_c2_0;
wire [49:0] ex1_p0_0_0;
wire [49:0] ex1_p0_0_1;
wire [49:0] ex1_p0_0_2;
wire [49:0] ex1_p0_0_3;
wire [49:0] ex1_p0_0_cout;
wire [49:0] ex1_p0_0_xor;
wire [49:0] ex1_p0_1_0;
wire [49:0] ex1_p0_1_1;
wire [49:0] ex1_p0_1_2;
wire [49:0] ex1_p0_1_3;
wire [49:0] ex1_p0_1_cout;
wire [49:0] ex1_p0_1_xor;
wire [49:0] ex1_p0_2_0;
wire [49:0] ex1_p0_2_1;
wire [49:0] ex1_p0_2_2;
wire [49:0] ex1_p0_2_3;
wire [49:0] ex1_p0_2_cout;
wire [49:0] ex1_p0_2_xor;
wire [49:0] ex1_p0_3_0;
wire [49:0] ex1_p0_3_1;
wire [49:0] ex1_p1_0_0;
wire [49:0] ex1_p1_0_1;
wire [49:0] ex1_p1_0_2;
wire [49:0] ex1_p1_0_3;
wire [49:0] ex1_p1_0_cout;
wire [49:0] ex1_p1_0_xor;
wire [49:0] ex1_p1_1_0;
wire [49:0] ex1_p1_1_1;
wire [49:0] ex1_p1_1_2;
wire [49:0] ex1_p1_1_3;
wire [49:0] ex1_p1_1_cout;
wire [49:0] ex1_p1_1_xor;
wire [50:0] ex1_p2_0_0;
wire [50:0] ex1_p2_0_1;
wire [50:0] ex1_p2_0_2;
wire [50:0] ex1_p2_0_3;
wire [50:0] ex1_p2_0_cout;
wire [50:0] ex1_p2_0_xor;
wire [49:0] ex1_s0_0;
wire [49:0] ex1_s0_1;
wire [49:0] ex1_s0_2;
wire [49:0] ex1_s1_0;
wire [49:0] ex1_s1_1;
wire [50:0] ex1_s2_0;
wire [1 :0] h0;
wire [1 :0] h1;
wire [1 :0] h10;
wire [1 :0] h11;
wire [1 :0] h12;
wire [1 :0] h2;
wire [1 :0] h3;
wire [1 :0] h4;
wire [1 :0] h5;
wire [1 :0] h6;
wire [1 :0] h7;
wire [1 :0] h8;
wire [1 :0] h9;
wire [24:0] mult_src;
wire [24:0] multiplicand;
wire [49:0] out0;
wire [49:0] out1;
wire [24:0] part_product0;
wire [24:0] part_product1;
wire [24:0] part_product10;
wire [24:0] part_product11;
wire [24:0] part_product12;
wire [24:0] part_product2;
wire [24:0] part_product3;
wire [24:0] part_product4;
wire [24:0] part_product5;
wire [24:0] part_product6;
wire [24:0] part_product7;
wire [24:0] part_product8;
wire [24:0] part_product9;
wire [12:0] sign_not;
parameter SRC0_WIDTH = 25;
parameter SRC1_WIDTH = 25;
parameter DST_WIDTH = 50;
assign multiplicand[SRC0_WIDTH-1:0] = {1'b0,a[SRC0_WIDTH-2:0]};
assign mult_src[SRC1_WIDTH-1:0] = {1'b0,b[SRC1_WIDTH-2:0]};
assign data_for_code[SRC1_WIDTH+1:0] = {mult_src[SRC1_WIDTH-1],mult_src[SRC1_WIDTH-1:0],1'b0};
// &Instance("booth_code_25_bit", "x_pa_booth_code_25_bit0"); @35
booth_code_25_bit x_pa_booth_code_25_bit0 (
.A (multiplicand[24:0] ),
.code (data_for_code[2:0] ),
.h (h0[1:0] ),
.product (part_product0[24:0]),
.sn (sign_not[0] )
);
// &Connect(.A(multiplicand[SRC0_WIDTH-1:0]), @36
// .code(data_for_code[2:0]), @37
// .product(part_product0[SRC0_WIDTH-1:0]), @38
// .h(h0[1:0]), @39
// .sn(sign_not[0])); @40
// &Instance("booth_code_25_bit", "x_pa_booth_code_25_bit1"); @42
booth_code_25_bit x_pa_booth_code_25_bit1 (
.A (multiplicand[24:0] ),
.code (data_for_code[4:2] ),
.h (h1[1:0] ),
.product (part_product1[24:0]),
.sn (sign_not[1] )
);
// &Connect(.A(multiplicand[SRC0_WIDTH-1:0]), @43
// .code(data_for_code[4:2]), @44
// .product(part_product1[SRC0_WIDTH-1:0]), @45
// .h(h1[1:0]), @46
// .sn(sign_not[1])); @47
// &Instance("booth_code_25_bit", "x_pa_booth_code_25_bit2"); @49
booth_code_25_bit x_pa_booth_code_25_bit2 (
.A (multiplicand[24:0] ),
.code (data_for_code[6:4] ),
.h (h2[1:0] ),
.product (part_product2[24:0]),
.sn (sign_not[2] )
);
// &Connect(.A(multiplicand[SRC0_WIDTH-1:0]), @50
// .code(data_for_code[6:4]), @51
// .product(part_product2[SRC0_WIDTH-1:0]), @52
// .h(h2[1:0]), @53
// .sn(sign_not[2])); @54
// &Instance("booth_code_25_bit", "x_pa_booth_code_25_bit3"); @56
booth_code_25_bit x_pa_booth_code_25_bit3 (
.A (multiplicand[24:0] ),
.code (data_for_code[8:6] ),
.h (h3[1:0] ),
.product (part_product3[24:0]),
.sn (sign_not[3] )
);
// &Connect(.A(multiplicand[SRC0_WIDTH-1:0]), @57
// .code(data_for_code[8:6]), @58
// .product(part_product3[SRC0_WIDTH-1:0]), @59
// .h(h3[1:0]), @60
// .sn(sign_not[3])); @61
// &Instance("booth_code_25_bit", "x_pa_booth_code_25_bit4"); @63
booth_code_25_bit x_pa_booth_code_25_bit4 (
.A (multiplicand[24:0] ),
.code (data_for_code[10:8]),
.h (h4[1:0] ),
.product (part_product4[24:0]),
.sn (sign_not[4] )
);
// &Connect(.A(multiplicand[SRC0_WIDTH-1:0]), @64
// .code(data_for_code[10:8]), @65
// .product(part_product4[SRC0_WIDTH-1:0]), @66
// .h(h4[1:0]), @67
// .sn(sign_not[4])); @68
// &Instance("booth_code_25_bit", "x_pa_booth_code_25_bit5"); @70
booth_code_25_bit x_pa_booth_code_25_bit5 (
.A (multiplicand[24:0] ),
.code (data_for_code[12:10]),
.h (h5[1:0] ),
.product (part_product5[24:0] ),
.sn (sign_not[5] )
);
// &Connect(.A(multiplicand[SRC0_WIDTH-1:0]), @71
// .code(data_for_code[12:10]), @72
// .product(part_product5[SRC0_WIDTH-1:0]), @73
// .h(h5[1:0]), @74
// .sn(sign_not[5])); @75
// &Instance("booth_code_25_bit", "x_pa_booth_code_25_bit6"); @77
booth_code_25_bit x_pa_booth_code_25_bit6 (
.A (multiplicand[24:0] ),
.code (data_for_code[14:12]),
.h (h6[1:0] ),
.product (part_product6[24:0] ),
.sn (sign_not[6] )
);
// &Connect(.A(multiplicand[SRC0_WIDTH-1:0]), @78
// .code(data_for_code[14:12]), @79
// .product(part_product6[SRC0_WIDTH-1:0]), @80
// .h(h6[1:0]), @81
// .sn(sign_not[6])); @82
// &Instance("booth_code_25_bit", "x_pa_booth_code_25_bit7"); @84
booth_code_25_bit x_pa_booth_code_25_bit7 (
.A (multiplicand[24:0] ),
.code (data_for_code[16:14]),
.h (h7[1:0] ),
.product (part_product7[24:0] ),
.sn (sign_not[7] )
);
// &Connect(.A(multiplicand[SRC0_WIDTH-1:0]), @85
// .code(data_for_code[16:14]), @86
// .product(part_product7[SRC0_WIDTH-1:0]), @87
// .h(h7[1:0]), @88
// .sn(sign_not[7])); @89
// &Instance("booth_code_25_bit", "x_pa_booth_code_25_bit8"); @91
booth_code_25_bit x_pa_booth_code_25_bit8 (
.A (multiplicand[24:0] ),
.code (data_for_code[18:16]),
.h (h8[1:0] ),
.product (part_product8[24:0] ),
.sn (sign_not[8] )
);
// &Connect(.A(multiplicand[SRC0_WIDTH-1:0]), @92
// .code(data_for_code[18:16]), @93
// .product(part_product8[SRC0_WIDTH-1:0]), @94
// .h(h8[1:0]), @95
// .sn(sign_not[8])); @96
// &Instance("booth_code_25_bit", "x_pa_booth_code_25_bit9"); @98
booth_code_25_bit x_pa_booth_code_25_bit9 (
.A (multiplicand[24:0] ),
.code (data_for_code[20:18]),
.h (h9[1:0] ),
.product (part_product9[24:0] ),
.sn (sign_not[9] )
);
// &Connect(.A(multiplicand[SRC0_WIDTH-1:0]), @99
// .code(data_for_code[20:18]), @100
// .product(part_product9[SRC0_WIDTH-1:0]), @101
// .h(h9[1:0]), @102
// .sn(sign_not[9])); @103
// &Instance("booth_code_25_bit", "x_pa_booth_code_25_bit10"); @105
booth_code_25_bit x_pa_booth_code_25_bit10 (
.A (multiplicand[24:0] ),
.code (data_for_code[22:20]),
.h (h10[1:0] ),
.product (part_product10[24:0]),
.sn (sign_not[10] )
);
// &Connect(.A(multiplicand[SRC0_WIDTH-1:0]), @106
// .code(data_for_code[22:20]), @107
// .product(part_product10[SRC0_WIDTH-1:0]), @108
// .h(h10[1:0]), @109
// .sn(sign_not[10])); @110
// &Instance("booth_code_25_bit", "x_pa_booth_code_25_bit11"); @112
booth_code_25_bit x_pa_booth_code_25_bit11 (
.A (multiplicand[24:0] ),
.code (data_for_code[24:22]),
.h (h11[1:0] ),
.product (part_product11[24:0]),
.sn (sign_not[11] )
);
// &Connect(.A(multiplicand[SRC0_WIDTH-1:0]), @113
// .code(data_for_code[24:22]), @114
// .product(part_product11[SRC0_WIDTH-1:0]), @115
// .h(h11[1:0]), @116
// .sn(sign_not[11])); @117
// &Instance("booth_code_25_bit", "x_pa_booth_code_25_bit12"); @119
booth_code_25_bit x_pa_booth_code_25_bit12 (
.A (multiplicand[24:0] ),
.code (data_for_code[26:24]),
.h (h12[1:0] ),
.product (part_product12[24:0]),
.sn (sign_not[12] )
);
// &Connect(.A(multiplicand[SRC0_WIDTH-1:0]), @120
// .code(data_for_code[26:24]), @121
// .product(part_product12[SRC0_WIDTH-1:0]), @122
// .h(h12[1:0]), @123
// .sn(sign_not[12])); @124
//=============================================================================
// prepare for the the first compression
//=============================================================================
assign ex1_p0_0_0[DST_WIDTH-1:0] = { {22{1'b0}}, sign_not[0],{2{!sign_not[0]}},part_product0[SRC0_WIDTH-1:0]};
assign ex1_p0_0_1[DST_WIDTH-1:0] = { {21{1'b0}},1'b1, sign_not[1], part_product1[SRC0_WIDTH-1:0], h0[1:0]};
assign ex1_p0_0_2[DST_WIDTH-1:0] = { {19{1'b0}},1'b1, sign_not[2], part_product2[SRC0_WIDTH-1:0], h1[1:0], { 2{1'b0}} };
assign ex1_p0_0_3[DST_WIDTH-1:0] = { {17{1'b0}},1'b1, sign_not[3], part_product3[SRC0_WIDTH-1:0], h2[1:0], { 4{1'b0}} };
assign ex1_p0_1_0[DST_WIDTH-1:0] = { {15{1'b0}},1'b1, sign_not[4], part_product4[SRC0_WIDTH-1:0], h3[1:0], { 6{1'b0}} };
assign ex1_p0_1_1[DST_WIDTH-1:0] = { {13{1'b0}},1'b1, sign_not[5], part_product5[SRC0_WIDTH-1:0], h4[1:0], { 8{1'b0}} };
assign ex1_p0_1_2[DST_WIDTH-1:0] = { {11{1'b0}},1'b1, sign_not[6], part_product6[SRC0_WIDTH-1:0], h5[1:0], {10{1'b0}} };
assign ex1_p0_1_3[DST_WIDTH-1:0] = { { 9{1'b0}},1'b1, sign_not[7], part_product7[SRC0_WIDTH-1:0], h6[1:0], {12{1'b0}} };
assign ex1_p0_2_0[DST_WIDTH-1:0] = { { 7{1'b0}},1'b1, sign_not[8], part_product8[SRC0_WIDTH-1:0], h7[1:0], {14{1'b0}} };
assign ex1_p0_2_1[DST_WIDTH-1:0] = { { 5{1'b0}},1'b1, sign_not[9], part_product9[SRC0_WIDTH-1:0], h8[1:0], {16{1'b0}} };
assign ex1_p0_2_2[DST_WIDTH-1:0] = { { 3{1'b0}},1'b1, sign_not[10], part_product10[SRC0_WIDTH-1:0],h9[1:0], {18{1'b0}} };
assign ex1_p0_2_3[DST_WIDTH-1:0] = { { 1{1'b0}},1'b1, sign_not[11], part_product11[SRC0_WIDTH-1:0],h10[1:0],{20{1'b0}} };
assign ex1_p0_3_0[DST_WIDTH-1:0] = { sign_not[12], part_product12[SRC0_WIDTH-1:0],h11[1:0],{22{1'b0}} };
assign ex1_p0_3_1[DST_WIDTH-1:0] = { {22{1'b0}}, h12[1:0],{26{1'b0}} };
//=========== 14 src to 8 src==========//
assign ex1_p0_0_cout[DST_WIDTH-1:0] = (ex1_p0_0_0[DST_WIDTH-1:0] & ex1_p0_0_1[DST_WIDTH-1:0]) |
(ex1_p0_0_1[DST_WIDTH-1:0] & ex1_p0_0_2[DST_WIDTH-1:0]) |
(ex1_p0_0_0[DST_WIDTH-1:0] & ex1_p0_0_2[DST_WIDTH-1:0]) ;
assign ex1_p0_0_xor[DST_WIDTH-1:0] = (ex1_p0_0_0[DST_WIDTH-1:0] ^ ex1_p0_0_1[DST_WIDTH-1:0]) ^
(ex1_p0_0_2[DST_WIDTH-1:0] ^ ex1_p0_0_3[DST_WIDTH-1:0]);
assign ex1_s0_0[DST_WIDTH-1:0] = ex1_p0_0_xor[DST_WIDTH-1:0]^ {ex1_p0_0_cout[DST_WIDTH-2:0],1'b0};
assign ex1_c0_0[DST_WIDTH-1:0] = ex1_p0_0_xor[DST_WIDTH-1:0]& {ex1_p0_0_cout[DST_WIDTH-2:0],1'b0}|
(~ex1_p0_0_xor[DST_WIDTH-1:0]& ex1_p0_0_3[DST_WIDTH-1:0]);
//----------------------------------------------
assign ex1_p0_1_cout[DST_WIDTH-1:0] = (ex1_p0_1_0[DST_WIDTH-1:0] & ex1_p0_1_1[DST_WIDTH-1:0]) |
(ex1_p0_1_1[DST_WIDTH-1:0] & ex1_p0_1_2[DST_WIDTH-1:0]) |
(ex1_p0_1_0[DST_WIDTH-1:0] & ex1_p0_1_2[DST_WIDTH-1:0]) ;
assign ex1_p0_1_xor[DST_WIDTH-1:0] = (ex1_p0_1_0[DST_WIDTH-1:0] ^ ex1_p0_1_1[DST_WIDTH-1:0]) ^
(ex1_p0_1_2[DST_WIDTH-1:0] ^ ex1_p0_1_3[DST_WIDTH-1:0]);
assign ex1_s0_1[DST_WIDTH-1:0] = ex1_p0_1_xor[DST_WIDTH-1:0]^ {ex1_p0_1_cout[DST_WIDTH-2:0],1'b0};
assign ex1_c0_1[DST_WIDTH-1:0] = ex1_p0_1_xor[DST_WIDTH-1:0]& {ex1_p0_1_cout[DST_WIDTH-2:0],1'b0}|
(~ex1_p0_1_xor[DST_WIDTH-1:0]& ex1_p0_1_3[DST_WIDTH-1:0]);
//----------------------------------------------
assign ex1_p0_2_cout[DST_WIDTH-1:0] = (ex1_p0_2_0[DST_WIDTH-1:0] & ex1_p0_2_1[DST_WIDTH-1:0]) |
(ex1_p0_2_1[DST_WIDTH-1:0] & ex1_p0_2_2[DST_WIDTH-1:0]) |
(ex1_p0_2_0[DST_WIDTH-1:0] & ex1_p0_2_2[DST_WIDTH-1:0]) ;
assign ex1_p0_2_xor[DST_WIDTH-1:0] = (ex1_p0_2_0[DST_WIDTH-1:0] ^ ex1_p0_2_1[DST_WIDTH-1:0]) ^
(ex1_p0_2_2[DST_WIDTH-1:0] ^ ex1_p0_2_3[DST_WIDTH-1:0]);
assign ex1_s0_2[DST_WIDTH-1:0] = ex1_p0_2_xor[DST_WIDTH-1:0]^ {ex1_p0_2_cout[DST_WIDTH-2:0],1'b0};
assign ex1_c0_2[DST_WIDTH-1:0] = ex1_p0_2_xor[DST_WIDTH-1:0]& {ex1_p0_2_cout[DST_WIDTH-2:0],1'b0}|
(~ex1_p0_2_xor[DST_WIDTH-1:0]& ex1_p0_2_3[DST_WIDTH-1:0]);
//=============================================================================
// prepare for the the second compression
//=============================================================================
assign ex1_p1_0_0[DST_WIDTH-1:0] = ex1_s0_0[DST_WIDTH-1:0];
assign ex1_p1_0_1[DST_WIDTH-1:0] ={ex1_c0_0[DST_WIDTH-2:0],1'b0};
assign ex1_p1_0_2[DST_WIDTH-1:0] = ex1_s0_1[DST_WIDTH-1:0];
assign ex1_p1_0_3[DST_WIDTH-1:0] ={ex1_c0_1[DST_WIDTH-2:0],1'b0};
assign ex1_p1_1_0[DST_WIDTH-1:0] = ex1_s0_2[DST_WIDTH-1:0];
assign ex1_p1_1_1[DST_WIDTH-1:0] ={ex1_c0_2[DST_WIDTH-2:0],1'b0};
assign ex1_p1_1_2[DST_WIDTH-1:0] = ex1_p0_3_0[DST_WIDTH-1:0];
assign ex1_p1_1_3[DST_WIDTH-1:0] = ex1_p0_3_1[DST_WIDTH-1:0];
//=========== 8 src to 4 src==========//
assign ex1_p1_0_cout[DST_WIDTH-1:0] = (ex1_p1_0_0[DST_WIDTH-1:0] & ex1_p1_0_1[DST_WIDTH-1:0]) |
(ex1_p1_0_1[DST_WIDTH-1:0] & ex1_p1_0_2[DST_WIDTH-1:0]) |
(ex1_p1_0_0[DST_WIDTH-1:0] & ex1_p1_0_2[DST_WIDTH-1:0]) ;
assign ex1_p1_0_xor[DST_WIDTH-1:0] = (ex1_p1_0_0[DST_WIDTH-1:0] ^ ex1_p1_0_1[DST_WIDTH-1:0]) ^
(ex1_p1_0_2[DST_WIDTH-1:0] ^ ex1_p1_0_3[DST_WIDTH-1:0]);
assign ex1_s1_0[DST_WIDTH-1:0] = ex1_p1_0_xor[DST_WIDTH-1:0]^ {ex1_p1_0_cout[DST_WIDTH-2:0],1'b0};
assign ex1_c1_0[DST_WIDTH-1:0] = ex1_p1_0_xor[DST_WIDTH-1:0]& {ex1_p1_0_cout[DST_WIDTH-2:0],1'b0}|
(~ex1_p1_0_xor[DST_WIDTH-1:0]& ex1_p1_0_3[DST_WIDTH-1:0]);
//----------------------------------------------
assign ex1_p1_1_cout[DST_WIDTH-1:0] = (ex1_p1_1_0[DST_WIDTH-1:0] & ex1_p1_1_1[DST_WIDTH-1:0]) |
(ex1_p1_1_1[DST_WIDTH-1:0] & ex1_p1_1_2[DST_WIDTH-1:0]) |
(ex1_p1_1_0[DST_WIDTH-1:0] & ex1_p1_1_2[DST_WIDTH-1:0]) ;
assign ex1_p1_1_xor[DST_WIDTH-1:0] = (ex1_p1_1_0[DST_WIDTH-1:0] ^ ex1_p1_1_1[DST_WIDTH-1:0]) ^
(ex1_p1_1_2[DST_WIDTH-1:0] ^ ex1_p1_1_3[DST_WIDTH-1:0]);
assign ex1_s1_1[DST_WIDTH-1:0] = ex1_p1_1_xor[DST_WIDTH-1:0]^ {ex1_p1_1_cout[DST_WIDTH-2:0],1'b0};
assign ex1_c1_1[DST_WIDTH-1:0] = ex1_p1_1_xor[DST_WIDTH-1:0]& {ex1_p1_1_cout[DST_WIDTH-2:0],1'b0}|
(~ex1_p1_1_xor[DST_WIDTH-1:0]& ex1_p1_1_3[DST_WIDTH-1:0]);
//=============================================================================
// prepare for the the third compression
//=============================================================================
assign ex1_p2_0_0[DST_WIDTH :0] ={ex1_s1_0[DST_WIDTH-1],ex1_s1_0[DST_WIDTH-1:0]};
assign ex1_p2_0_1[DST_WIDTH :0] ={ex1_c1_0[DST_WIDTH-1:0],1'b0};
assign ex1_p2_0_2[DST_WIDTH :0] ={ex1_s1_1[DST_WIDTH-1],ex1_s1_1[DST_WIDTH-1:0]};
assign ex1_p2_0_3[DST_WIDTH :0] ={ex1_c1_1[DST_WIDTH-1:0],1'b0};
//=========== 4 src to 2 src==========//
assign ex1_p2_0_cout[DST_WIDTH :0] = (ex1_p2_0_0[DST_WIDTH :0] & ex1_p2_0_1[DST_WIDTH :0]) |
(ex1_p2_0_1[DST_WIDTH :0] & ex1_p2_0_2[DST_WIDTH :0]) |
(ex1_p2_0_0[DST_WIDTH :0] & ex1_p2_0_2[DST_WIDTH :0]) ;
assign ex1_p2_0_xor[DST_WIDTH :0] = (ex1_p2_0_0[DST_WIDTH :0] ^ ex1_p2_0_1[DST_WIDTH :0]) ^
(ex1_p2_0_2[DST_WIDTH :0] ^ ex1_p2_0_3[DST_WIDTH :0]);
assign ex1_s2_0[DST_WIDTH :0] = ex1_p2_0_xor[DST_WIDTH :0]^ {ex1_p2_0_cout[DST_WIDTH-1:0],1'b0};
assign ex1_c2_0[DST_WIDTH :0] = ex1_p2_0_xor[DST_WIDTH :0]& {ex1_p2_0_cout[DST_WIDTH-1:0],1'b0}|
(~ex1_p2_0_xor[DST_WIDTH :0]& ex1_p2_0_3[DST_WIDTH :0]);
assign out0[DST_WIDTH-1:0] ={ex1_s2_0[DST_WIDTH-1:0]};
assign out1[DST_WIDTH-1:0] ={ex1_c2_0[DST_WIDTH-2:0],1'b0};
// &ModuleEnd; @244
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @24
module pa_fmau_src2_shifter_single(
ex2_data_for_shift,
ex2_shift_data_out,
ex2_shift_index
);
// &Ports; @25
input [23:0] ex2_data_for_shift;
input [5 :0] ex2_shift_index;
output [52:0] ex2_shift_data_out;
// &Regs; @26
reg [52:0] shift_data;
// &Wires; @27
wire [52:0] data_for_shift;
wire [23:0] ex2_data_for_shift;
wire [52:0] ex2_shift_data_out;
wire [5 :0] ex2_shift_index;
wire [5 :0] shift_index;
parameter DATA_WIDTH = 53;
parameter SINGLE_FRAC = 23;
assign data_for_shift[DATA_WIDTH-1:0] = {1'b0,ex2_data_for_shift[SINGLE_FRAC:0], {SINGLE_FRAC{1'b0}}, 5'b0};
assign shift_index[5:0] = ex2_shift_index[5:0];
// &CombBeg; @36
always @( data_for_shift[52: 17]
or data_for_shift[52: 3]
or data_for_shift[52: 45]
or data_for_shift[52: 8]
or data_for_shift[52: 10]
or data_for_shift[52: 39]
or data_for_shift[52: 35]
or data_for_shift[52: 28]
or data_for_shift[52: 46]
or data_for_shift[52: 7]
or data_for_shift[52: 49]
or data_for_shift[52: 29]
or data_for_shift[52: 2]
or data_for_shift[52: 24]
or data_for_shift[52: 38]
or data_for_shift[52: 43]
or data_for_shift[52: 52]
or data_for_shift[52: 33]
or data_for_shift[52: 48]
or data_for_shift[52: 27]
or data_for_shift[52: 18]
or data_for_shift[52: 14]
or data_for_shift[52: 15]
or shift_index[5:0]
or data_for_shift[52: 13]
or data_for_shift[52: 5]
or data_for_shift[52: 22]
or data_for_shift[52: 23]
or data_for_shift[52: 34]
or data_for_shift[52: 37]
or data_for_shift[52: 12]
or data_for_shift[52: 40]
or data_for_shift[52: 6]
or data_for_shift[52: 25]
or data_for_shift[52: 21]
or data_for_shift[52: 31]
or data_for_shift[52: 47]
or data_for_shift[52: 19]
or data_for_shift[52: 4]
or data_for_shift[52: 32]
or data_for_shift[51:0]
or data_for_shift[52: 1]
or data_for_shift[52: 26]
or data_for_shift[52: 16]
or data_for_shift[52: 42]
or data_for_shift[52: 50]
or data_for_shift[52: 41]
or data_for_shift[52: 36]
or data_for_shift[52: 30]
or data_for_shift[52: 9]
or data_for_shift[52: 51]
or data_for_shift[52: 44]
or data_for_shift[52: 20]
or data_for_shift[52: 11])
begin
case(shift_index[5:0])
6'b00_0000: shift_data[DATA_WIDTH-1:0] = { data_for_shift[DATA_WIDTH-1: 1], data_for_shift[0] };
6'b00_0001: shift_data[DATA_WIDTH-1:0] = {{ 1{1'b0}},data_for_shift[DATA_WIDTH-1: 2],|data_for_shift[1 :0]};
6'b00_0010: shift_data[DATA_WIDTH-1:0] = {{ 2{1'b0}},data_for_shift[DATA_WIDTH-1: 3],|data_for_shift[2 :0]};
6'b00_0011: shift_data[DATA_WIDTH-1:0] = {{ 3{1'b0}},data_for_shift[DATA_WIDTH-1: 4],|data_for_shift[3 :0]};
6'b00_0100: shift_data[DATA_WIDTH-1:0] = {{ 4{1'b0}},data_for_shift[DATA_WIDTH-1: 5],|data_for_shift[4 :0]};
6'b00_0101: shift_data[DATA_WIDTH-1:0] = {{ 5{1'b0}},data_for_shift[DATA_WIDTH-1: 6],|data_for_shift[5 :0]};
6'b00_0110: shift_data[DATA_WIDTH-1:0] = {{ 6{1'b0}},data_for_shift[DATA_WIDTH-1: 7],|data_for_shift[6 :0]};
6'b00_0111: shift_data[DATA_WIDTH-1:0] = {{ 7{1'b0}},data_for_shift[DATA_WIDTH-1: 8],|data_for_shift[7 :0]};
6'b00_1000: shift_data[DATA_WIDTH-1:0] = {{ 8{1'b0}},data_for_shift[DATA_WIDTH-1: 9],|data_for_shift[8 :0]};
6'b00_1001: shift_data[DATA_WIDTH-1:0] = {{ 9{1'b0}},data_for_shift[DATA_WIDTH-1: 10],|data_for_shift[9 :0]};
6'b00_1010: shift_data[DATA_WIDTH-1:0] = {{ 10{1'b0}},data_for_shift[DATA_WIDTH-1: 11],|data_for_shift[10 :0]};
6'b00_1011: shift_data[DATA_WIDTH-1:0] = {{ 11{1'b0}},data_for_shift[DATA_WIDTH-1: 12],|data_for_shift[11 :0]};
6'b00_1100: shift_data[DATA_WIDTH-1:0] = {{ 12{1'b0}},data_for_shift[DATA_WIDTH-1: 13],|data_for_shift[12 :0]};
6'b00_1101: shift_data[DATA_WIDTH-1:0] = {{ 13{1'b0}},data_for_shift[DATA_WIDTH-1: 14],|data_for_shift[13 :0]};
6'b00_1110: shift_data[DATA_WIDTH-1:0] = {{ 14{1'b0}},data_for_shift[DATA_WIDTH-1: 15],|data_for_shift[14 :0]};
6'b00_1111: shift_data[DATA_WIDTH-1:0] = {{ 15{1'b0}},data_for_shift[DATA_WIDTH-1: 16],|data_for_shift[15 :0]};
6'b01_0000: shift_data[DATA_WIDTH-1:0] = {{ 16{1'b0}},data_for_shift[DATA_WIDTH-1: 17],|data_for_shift[16 :0]};
6'b01_0001: shift_data[DATA_WIDTH-1:0] = {{ 17{1'b0}},data_for_shift[DATA_WIDTH-1: 18],|data_for_shift[17 :0]};
6'b01_0010: shift_data[DATA_WIDTH-1:0] = {{ 18{1'b0}},data_for_shift[DATA_WIDTH-1: 19],|data_for_shift[18 :0]};
6'b01_0011: shift_data[DATA_WIDTH-1:0] = {{ 19{1'b0}},data_for_shift[DATA_WIDTH-1: 20],|data_for_shift[19 :0]};
6'b01_0100: shift_data[DATA_WIDTH-1:0] = {{ 20{1'b0}},data_for_shift[DATA_WIDTH-1: 21],|data_for_shift[20 :0]};
6'b01_0101: shift_data[DATA_WIDTH-1:0] = {{ 21{1'b0}},data_for_shift[DATA_WIDTH-1: 22],|data_for_shift[21 :0]};
6'b01_0110: shift_data[DATA_WIDTH-1:0] = {{ 22{1'b0}},data_for_shift[DATA_WIDTH-1: 23],|data_for_shift[22 :0]};
6'b01_0111: shift_data[DATA_WIDTH-1:0] = {{ 23{1'b0}},data_for_shift[DATA_WIDTH-1: 24],|data_for_shift[23 :0]};
6'b01_1000: shift_data[DATA_WIDTH-1:0] = {{ 24{1'b0}},data_for_shift[DATA_WIDTH-1: 25],|data_for_shift[24 :0]};
6'b01_1001: shift_data[DATA_WIDTH-1:0] = {{ 25{1'b0}},data_for_shift[DATA_WIDTH-1: 26],|data_for_shift[25 :0]};
6'b01_1010: shift_data[DATA_WIDTH-1:0] = {{ 26{1'b0}},data_for_shift[DATA_WIDTH-1: 27],|data_for_shift[26 :0]};
6'b01_1011: shift_data[DATA_WIDTH-1:0] = {{ 27{1'b0}},data_for_shift[DATA_WIDTH-1: 28],|data_for_shift[27 :0]};
6'b01_1100: shift_data[DATA_WIDTH-1:0] = {{ 28{1'b0}},data_for_shift[DATA_WIDTH-1: 29],|data_for_shift[28 :0]};
6'b01_1101: shift_data[DATA_WIDTH-1:0] = {{ 29{1'b0}},data_for_shift[DATA_WIDTH-1: 30],|data_for_shift[29 :0]};
6'b01_1110: shift_data[DATA_WIDTH-1:0] = {{ 30{1'b0}},data_for_shift[DATA_WIDTH-1: 31],|data_for_shift[30 :0]};
6'b01_1111: shift_data[DATA_WIDTH-1:0] = {{ 31{1'b0}},data_for_shift[DATA_WIDTH-1: 32],|data_for_shift[31 :0]};
6'b10_0000: shift_data[DATA_WIDTH-1:0] = {{ 32{1'b0}},data_for_shift[DATA_WIDTH-1: 33],|data_for_shift[32 :0]};
6'b10_0001: shift_data[DATA_WIDTH-1:0] = {{ 33{1'b0}},data_for_shift[DATA_WIDTH-1: 34],|data_for_shift[33 :0]};
6'b10_0010: shift_data[DATA_WIDTH-1:0] = {{ 34{1'b0}},data_for_shift[DATA_WIDTH-1: 35],|data_for_shift[34 :0]};
6'b10_0011: shift_data[DATA_WIDTH-1:0] = {{ 35{1'b0}},data_for_shift[DATA_WIDTH-1: 36],|data_for_shift[35 :0]};
6'b10_0100: shift_data[DATA_WIDTH-1:0] = {{ 36{1'b0}},data_for_shift[DATA_WIDTH-1: 37],|data_for_shift[36 :0]};
6'b10_0101: shift_data[DATA_WIDTH-1:0] = {{ 37{1'b0}},data_for_shift[DATA_WIDTH-1: 38],|data_for_shift[37 :0]};
6'b10_0110: shift_data[DATA_WIDTH-1:0] = {{ 38{1'b0}},data_for_shift[DATA_WIDTH-1: 39],|data_for_shift[38 :0]};
6'b10_0111: shift_data[DATA_WIDTH-1:0] = {{ 39{1'b0}},data_for_shift[DATA_WIDTH-1: 40],|data_for_shift[39 :0]};
6'b10_1000: shift_data[DATA_WIDTH-1:0] = {{ 40{1'b0}},data_for_shift[DATA_WIDTH-1: 41],|data_for_shift[40 :0]};
6'b10_1001: shift_data[DATA_WIDTH-1:0] = {{ 41{1'b0}},data_for_shift[DATA_WIDTH-1: 42],|data_for_shift[41 :0]};
6'b10_1010: shift_data[DATA_WIDTH-1:0] = {{ 42{1'b0}},data_for_shift[DATA_WIDTH-1: 43],|data_for_shift[42 :0]};
6'b10_1011: shift_data[DATA_WIDTH-1:0] = {{ 43{1'b0}},data_for_shift[DATA_WIDTH-1: 44],|data_for_shift[43 :0]};
6'b10_1100: shift_data[DATA_WIDTH-1:0] = {{ 44{1'b0}},data_for_shift[DATA_WIDTH-1: 45],|data_for_shift[44 :0]};
6'b10_1101: shift_data[DATA_WIDTH-1:0] = {{ 45{1'b0}},data_for_shift[DATA_WIDTH-1: 46],|data_for_shift[45 :0]};
6'b10_1110: shift_data[DATA_WIDTH-1:0] = {{ 46{1'b0}},data_for_shift[DATA_WIDTH-1: 47],|data_for_shift[46 :0]};
6'b10_1111: shift_data[DATA_WIDTH-1:0] = {{ 47{1'b0}},data_for_shift[DATA_WIDTH-1: 48],|data_for_shift[47 :0]};
6'b11_0000: shift_data[DATA_WIDTH-1:0] = {{ 48{1'b0}},data_for_shift[DATA_WIDTH-1: 49],|data_for_shift[48 :0]};
6'b11_0001: shift_data[DATA_WIDTH-1:0] = {{ 49{1'b0}},data_for_shift[DATA_WIDTH-1: 50],|data_for_shift[49 :0]};
6'b11_0010: shift_data[DATA_WIDTH-1:0] = {{ 50{1'b0}},data_for_shift[DATA_WIDTH-1: 51],|data_for_shift[50 :0]};
6'b11_0011: shift_data[DATA_WIDTH-1:0] = {{ 51{1'b0}},data_for_shift[DATA_WIDTH-1: 52],|data_for_shift[51 :0]};
default: shift_data[DATA_WIDTH-1:0] = {DATA_WIDTH{1'bx}};
endcase
// &CombEnd; @92
end
assign ex2_shift_data_out[DATA_WIDTH-1:0] = shift_data[DATA_WIDTH-1:0];
// &ModuleEnd; @96
endmodule

259
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &ModuleBeg; @23
module pa_fmau_top(
cp0_fpu_icg_en,
cp0_fpu_xx_dqnan,
cp0_yy_clk_en,
cpurst_b,
ctrl_fmau_ex1_sel,
ctrl_fmau_ex1_sel_gate,
ctrl_xx_ex1_cmplt_dp,
ctrl_xx_ex1_stall,
ctrl_xx_ex1_warm_up,
ctrl_xx_ex2_cancel,
ctrl_xx_ex2_stall,
ctrl_xx_ex2_warm_up,
ctrl_xx_ex3_stall,
ctrl_xx_ex3_warm_up,
ctrl_xx_ex4_stall,
dp_xx_ex1_cnan,
dp_xx_ex1_id,
dp_xx_ex1_inf,
dp_xx_ex1_norm,
dp_xx_ex1_qnan,
dp_xx_ex1_rm,
dp_xx_ex1_snan,
dp_xx_ex1_srcf2,
dp_xx_ex1_zero,
dp_xx_ex2_srcf2,
dp_xx_ex3_rm,
dp_xx_ex4_rm,
fmau_fpu_ex1_cmplt,
fmau_fpu_ex1_cmplt_dp,
fmau_fpu_ex1_denorm_stall,
fmau_fpu_ex1_fflags,
fmau_fpu_ex1_special_sel,
fmau_fpu_ex1_special_sign,
fmau_fpu_ex3_fflags,
fmau_fpu_ex3_result,
fmau_fpu_ex3_result_vld,
fmau_fpu_ex4_fflags,
fmau_fpu_ex4_result,
fmau_fpu_id_reg_set,
forever_cpuclk,
idu_fpu_ex1_eu_sel,
idu_fpu_ex1_func,
idu_fpu_ex1_srcf0,
idu_fpu_ex1_srcf1,
pad_yy_icg_scan_en,
rtu_xx_ex1_cancel
);
// &Ports; @24
input cp0_fpu_icg_en;
input cp0_fpu_xx_dqnan;
input cp0_yy_clk_en;
input cpurst_b;
input ctrl_fmau_ex1_sel;
input ctrl_fmau_ex1_sel_gate;
input ctrl_xx_ex1_cmplt_dp;
input ctrl_xx_ex1_stall;
input ctrl_xx_ex1_warm_up;
input ctrl_xx_ex2_cancel;
input ctrl_xx_ex2_stall;
input ctrl_xx_ex2_warm_up;
input ctrl_xx_ex3_stall;
input ctrl_xx_ex3_warm_up;
input ctrl_xx_ex4_stall;
input [2 :0] dp_xx_ex1_cnan;
input [2 :0] dp_xx_ex1_id;
input [2 :0] dp_xx_ex1_inf;
input [2 :0] dp_xx_ex1_norm;
input [2 :0] dp_xx_ex1_qnan;
input [2 :0] dp_xx_ex1_rm;
input [2 :0] dp_xx_ex1_snan;
input [31:0] dp_xx_ex1_srcf2;
input [2 :0] dp_xx_ex1_zero;
input [31:0] dp_xx_ex2_srcf2;
input [2 :0] dp_xx_ex3_rm;
input [2 :0] dp_xx_ex4_rm;
input forever_cpuclk;
input [2 :0] idu_fpu_ex1_eu_sel;
input [9 :0] idu_fpu_ex1_func;
input [31:0] idu_fpu_ex1_srcf0;
input [31:0] idu_fpu_ex1_srcf1;
input pad_yy_icg_scan_en;
input rtu_xx_ex1_cancel;
output fmau_fpu_ex1_cmplt;
output fmau_fpu_ex1_cmplt_dp;
output fmau_fpu_ex1_denorm_stall;
output [4 :0] fmau_fpu_ex1_fflags;
output [7 :0] fmau_fpu_ex1_special_sel;
output [3 :0] fmau_fpu_ex1_special_sign;
output [4 :0] fmau_fpu_ex3_fflags;
output [31:0] fmau_fpu_ex3_result;
output fmau_fpu_ex3_result_vld;
output [4 :0] fmau_fpu_ex4_fflags;
output [31:0] fmau_fpu_ex4_result;
output fmau_fpu_id_reg_set;
// &Regs; @25
// &Wires; @26
wire cp0_fpu_icg_en;
wire cp0_fpu_xx_dqnan;
wire cp0_yy_clk_en;
wire cpurst_b;
wire ctrl_dp_ex1_inst_pipe_down;
wire ctrl_dp_ex1_inst_vld;
wire ctrl_dp_ex2_inst_pipe_down;
wire ctrl_dp_ex2_inst_vld;
wire ctrl_dp_ex3_inst_pipe_down;
wire ctrl_dp_ex3_inst_vld;
wire ctrl_fmau_ex1_sel;
wire ctrl_fmau_ex1_sel_gate;
wire ctrl_xx_ex1_cmplt_dp;
wire ctrl_xx_ex1_stall;
wire ctrl_xx_ex1_warm_up;
wire ctrl_xx_ex2_cancel;
wire ctrl_xx_ex2_stall;
wire ctrl_xx_ex2_warm_up;
wire ctrl_xx_ex3_stall;
wire ctrl_xx_ex3_warm_up;
wire ctrl_xx_ex4_stall;
wire dp_ctrl_ex3_mac;
wire [2 :0] dp_xx_ex1_cnan;
wire [2 :0] dp_xx_ex1_id;
wire [2 :0] dp_xx_ex1_inf;
wire [2 :0] dp_xx_ex1_norm;
wire [2 :0] dp_xx_ex1_qnan;
wire [2 :0] dp_xx_ex1_rm;
wire [2 :0] dp_xx_ex1_snan;
wire [31:0] dp_xx_ex1_srcf2;
wire [2 :0] dp_xx_ex1_zero;
wire [31:0] dp_xx_ex2_srcf2;
wire [2 :0] dp_xx_ex3_rm;
wire [2 :0] dp_xx_ex4_rm;
wire [1 :0] ex1_id_reg;
wire ex2_special_cmplt;
wire fmau_fpu_ex1_cmplt;
wire fmau_fpu_ex1_cmplt_dp;
wire fmau_fpu_ex1_denorm_stall;
wire [4 :0] fmau_fpu_ex1_fflags;
wire [7 :0] fmau_fpu_ex1_special_sel;
wire [3 :0] fmau_fpu_ex1_special_sign;
wire [4 :0] fmau_fpu_ex3_fflags;
wire [31:0] fmau_fpu_ex3_result;
wire fmau_fpu_ex3_result_vld;
wire [4 :0] fmau_fpu_ex4_fflags;
wire [31:0] fmau_fpu_ex4_result;
wire fmau_fpu_id_reg_set;
wire forever_cpuclk;
wire [2 :0] idu_fpu_ex1_eu_sel;
wire [9 :0] idu_fpu_ex1_func;
wire [31:0] idu_fpu_ex1_srcf0;
wire [31:0] idu_fpu_ex1_srcf1;
wire pad_yy_icg_scan_en;
wire rtu_xx_ex1_cancel;
// &Depend("cpu_cfig.h"); @28
// &Instance("pa_fmau_dp","x_pa_fmau_dp"); @30
pa_fmau_dp x_pa_fmau_dp (
.cp0_fpu_icg_en (cp0_fpu_icg_en ),
.cp0_fpu_xx_dqnan (cp0_fpu_xx_dqnan ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.ctrl_dp_ex1_inst_pipe_down (ctrl_dp_ex1_inst_pipe_down),
.ctrl_dp_ex1_inst_vld (ctrl_dp_ex1_inst_vld ),
.ctrl_dp_ex2_inst_pipe_down (ctrl_dp_ex2_inst_pipe_down),
.ctrl_dp_ex2_inst_vld (ctrl_dp_ex2_inst_vld ),
.ctrl_dp_ex3_inst_pipe_down (ctrl_dp_ex3_inst_pipe_down),
.ctrl_dp_ex3_inst_vld (ctrl_dp_ex3_inst_vld ),
.ctrl_xx_ex1_warm_up (ctrl_xx_ex1_warm_up ),
.ctrl_xx_ex2_warm_up (ctrl_xx_ex2_warm_up ),
.ctrl_xx_ex3_warm_up (ctrl_xx_ex3_warm_up ),
.dp_ctrl_ex3_mac (dp_ctrl_ex3_mac ),
.dp_xx_ex1_cnan (dp_xx_ex1_cnan ),
.dp_xx_ex1_inf (dp_xx_ex1_inf ),
.dp_xx_ex1_norm (dp_xx_ex1_norm ),
.dp_xx_ex1_qnan (dp_xx_ex1_qnan ),
.dp_xx_ex1_rm (dp_xx_ex1_rm ),
.dp_xx_ex1_snan (dp_xx_ex1_snan ),
.dp_xx_ex1_srcf2 (dp_xx_ex1_srcf2 ),
.dp_xx_ex1_zero (dp_xx_ex1_zero ),
.dp_xx_ex2_srcf2 (dp_xx_ex2_srcf2 ),
.dp_xx_ex3_rm (dp_xx_ex3_rm ),
.dp_xx_ex4_rm (dp_xx_ex4_rm ),
.ex1_id_reg (ex1_id_reg ),
.ex2_special_cmplt (ex2_special_cmplt ),
.fmau_fpu_ex1_fflags (fmau_fpu_ex1_fflags ),
.fmau_fpu_ex1_special_sel (fmau_fpu_ex1_special_sel ),
.fmau_fpu_ex1_special_sign (fmau_fpu_ex1_special_sign ),
.fmau_fpu_ex3_fflags (fmau_fpu_ex3_fflags ),
.fmau_fpu_ex3_result (fmau_fpu_ex3_result ),
.fmau_fpu_ex4_fflags (fmau_fpu_ex4_fflags ),
.fmau_fpu_ex4_result (fmau_fpu_ex4_result ),
.forever_cpuclk (forever_cpuclk ),
.idu_fpu_ex1_eu_sel (idu_fpu_ex1_eu_sel ),
.idu_fpu_ex1_func (idu_fpu_ex1_func ),
.idu_fpu_ex1_srcf0 (idu_fpu_ex1_srcf0 ),
.idu_fpu_ex1_srcf1 (idu_fpu_ex1_srcf1 ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Instance("pa_fmau_ctrl","x_pa_fmau_ctrl"); @31
pa_fmau_ctrl x_pa_fmau_ctrl (
.cp0_fpu_icg_en (cp0_fpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ctrl_dp_ex1_inst_pipe_down (ctrl_dp_ex1_inst_pipe_down),
.ctrl_dp_ex1_inst_vld (ctrl_dp_ex1_inst_vld ),
.ctrl_dp_ex2_inst_pipe_down (ctrl_dp_ex2_inst_pipe_down),
.ctrl_dp_ex2_inst_vld (ctrl_dp_ex2_inst_vld ),
.ctrl_dp_ex3_inst_pipe_down (ctrl_dp_ex3_inst_pipe_down),
.ctrl_dp_ex3_inst_vld (ctrl_dp_ex3_inst_vld ),
.ctrl_fmau_ex1_sel (ctrl_fmau_ex1_sel ),
.ctrl_fmau_ex1_sel_gate (ctrl_fmau_ex1_sel_gate ),
.ctrl_xx_ex1_cmplt_dp (ctrl_xx_ex1_cmplt_dp ),
.ctrl_xx_ex1_stall (ctrl_xx_ex1_stall ),
.ctrl_xx_ex2_cancel (ctrl_xx_ex2_cancel ),
.ctrl_xx_ex2_stall (ctrl_xx_ex2_stall ),
.ctrl_xx_ex3_stall (ctrl_xx_ex3_stall ),
.ctrl_xx_ex4_stall (ctrl_xx_ex4_stall ),
.dp_ctrl_ex3_mac (dp_ctrl_ex3_mac ),
.dp_xx_ex1_id (dp_xx_ex1_id ),
.ex1_id_reg (ex1_id_reg ),
.ex2_special_cmplt (ex2_special_cmplt ),
.fmau_fpu_ex1_cmplt (fmau_fpu_ex1_cmplt ),
.fmau_fpu_ex1_cmplt_dp (fmau_fpu_ex1_cmplt_dp ),
.fmau_fpu_ex1_denorm_stall (fmau_fpu_ex1_denorm_stall ),
.fmau_fpu_ex3_result_vld (fmau_fpu_ex3_result_vld ),
.fmau_fpu_id_reg_set (fmau_fpu_id_reg_set ),
.forever_cpuclk (forever_cpuclk ),
.idu_fpu_ex1_eu_sel (idu_fpu_ex1_eu_sel ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_xx_ex1_cancel (rtu_xx_ex1_cancel )
);
// &ModuleEnd; @196
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module fpga_ram(
PortAClk,
PortAAddr,
PortADataIn,
PortAWriteEnable,
// PortAChipEnable,
PortADataOut
);
parameter DATAWIDTH = 2;
parameter ADDRWIDTH = 2;
input PortAClk;
input [(ADDRWIDTH-1):0] PortAAddr;
input [(DATAWIDTH-1):0] PortADataIn;
input PortAWriteEnable;
//input PortAChipEnable;
output [(DATAWIDTH-1):0] PortADataOut;
parameter MEMDEPTH = 2**(ADDRWIDTH);
reg [(DATAWIDTH-1):0] mem [(MEMDEPTH-1):0] /* synthesis syn_ramstyle = "no_rw_check" */;
reg [(DATAWIDTH-1):0] PortADataOut;
always @(posedge PortAClk)
begin
if(PortAWriteEnable)
begin
mem[PortAAddr] <= PortADataIn;
PortADataOut <= PortADataIn;
end
else
begin
PortADataOut <= mem[PortAAddr];
end
end
//wire [(DATAWIDTH-1):0] tt;
//assign t = mem[PortAAddr];
//always @(posedge PortAClk)
//begin
// if(PortAWriteEnable)
// begin
// PortADataOut <= PortADataIn;
// end
// else
// begin
// PortADataOut <= mem[PortAAddr];
// end
//end
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_f_spsram_1024x32(
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 10;
parameter DATA_WIDTH = 32;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_WIDTH-1:0] Q;
reg [ADDR_WIDTH-1:0] addr_holding;
wire [ADDR_WIDTH-1:0] A;
wire CEN;
wire CLK;
wire [DATA_WIDTH-1:0] D;
wire GWEN;
wire [DATA_WIDTH-1:0] WEN;
wire [DATA_WIDTH-1:0] Q;
wire [ADDR_WIDTH-1:0] addr;
always@(posedge CLK)
begin
if(!CEN) begin
addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
end
end
assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0]
: A[ADDR_WIDTH-1:0];
wire [DATA_WIDTH-1:0] ram_wen_vec;
genvar i;
generate
for(i=0; i<DATA_WIDTH; i=i+1) begin: RAM_DIN_VEC
assign ram_wen_vec[i] = !CEN & !WEN[i] & !GWEN;
fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram_instance(
.PortAClk (CLK),
.PortAAddr(addr),
.PortADataIn (D[i]),
.PortAWriteEnable(ram_wen_vec[i]),
.PortADataOut(Q[i]));
end
endgenerate
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_f_spsram_1024x36(
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 10;
parameter DATA_WIDTH = 36;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_WIDTH-1:0] Q;
reg [ADDR_WIDTH-1:0] addr_holding;
wire [ADDR_WIDTH-1:0] A;
wire CEN;
wire CLK;
wire [DATA_WIDTH-1:0] D;
wire GWEN;
wire [DATA_WIDTH-1:0] WEN;
wire [DATA_WIDTH-1:0] Q;
wire [ADDR_WIDTH-1:0] addr;
always@(posedge CLK)
begin
if(!CEN) begin
addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
end
end
assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0]
: A[ADDR_WIDTH-1:0];
wire [DATA_WIDTH-1:0] ram_wen_vec;
genvar i;
generate
for(i=0; i<DATA_WIDTH; i=i+1) begin: RAM_DIN_VEC
assign ram_wen_vec[i] = !CEN & !WEN[i] & !GWEN;
fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram_instance(
.PortAClk (CLK),
.PortAAddr(addr),
.PortADataIn (D[i]),
.PortAWriteEnable(ram_wen_vec[i]),
.PortADataOut(Q[i]));
end
endgenerate
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_f_spsram_1024x37(
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 10;
parameter DATA_WIDTH = 37;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_WIDTH-1:0] Q;
reg [ADDR_WIDTH-1:0] addr_holding;
wire [ADDR_WIDTH-1:0] A;
wire CEN;
wire CLK;
wire [DATA_WIDTH-1:0] D;
wire GWEN;
wire [DATA_WIDTH-1:0] WEN;
wire [DATA_WIDTH-1:0] Q;
wire [ADDR_WIDTH-1:0] addr;
always@(posedge CLK)
begin
if(!CEN) begin
addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
end
end
assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0]
: A[ADDR_WIDTH-1:0];
wire [DATA_WIDTH-1:0] ram_wen_vec;
genvar i;
generate
for(i=0; i<DATA_WIDTH; i=i+1) begin: RAM_DIN_VEC
assign ram_wen_vec[i] = !CEN & !WEN[i] & !GWEN;
fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram_instance(
.PortAClk (CLK),
.PortAAddr(addr),
.PortADataIn (D[i]),
.PortAWriteEnable(ram_wen_vec[i]),
.PortADataOut(Q[i]));
end
endgenerate
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &Depend("fpga_ram.v"); @22
// &ModuleBeg; @24
module pa_f_spsram_1024x4(
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @25
input [9:0] A;
input CEN;
input CLK;
input [3:0] D;
input GWEN;
input [3:0] WEN;
output [3:0] Q;
// &Regs; @26
reg [9:0] addr_holding;
// &Wires; @27
wire [9:0] A;
wire CEN;
wire CLK;
wire [3:0] D;
wire GWEN;
wire [3:0] Q;
wire [3:0] WEN;
wire [9:0] addr;
wire [0:0] ram0_din;
wire [0:0] ram0_dout;
wire ram0_wen;
wire [0:0] ram1_din;
wire [0:0] ram1_dout;
wire ram1_wen;
wire [0:0] ram2_din;
wire [0:0] ram2_dout;
wire ram2_wen;
wire [0:0] ram3_din;
wire [0:0] ram3_dout;
wire ram3_wen;
parameter ADDR_WIDTH = 10;
parameter WRAP_SIZE = 1;
//write enable
// &Force("nonport","ram0_wen"); @33
// &Force("nonport","ram1_wen"); @34
// &Force("nonport","ram2_wen"); @35
// &Force("nonport","ram3_wen"); @36
// &Force("bus","WEN",3,0); @37
assign ram0_wen = !CEN && !WEN[0] && !GWEN;
assign ram1_wen = !CEN && !WEN[1] && !GWEN;
assign ram2_wen = !CEN && !WEN[2] && !GWEN;
assign ram3_wen = !CEN && !WEN[3] && !GWEN;
//din
// &Force("nonport","ram0_din"); @44
// &Force("nonport","ram1_din"); @45
// &Force("nonport","ram2_din"); @46
// &Force("nonport","ram3_din"); @47
// &Force("bus","D",4*WRAP_SIZE-1,0); @48
assign ram0_din[WRAP_SIZE-1:0] = D[WRAP_SIZE-1:0];
assign ram1_din[WRAP_SIZE-1:0] = D[2*WRAP_SIZE-1:WRAP_SIZE];
assign ram2_din[WRAP_SIZE-1:0] = D[3*WRAP_SIZE-1:2*WRAP_SIZE];
assign ram3_din[WRAP_SIZE-1:0] = D[4*WRAP_SIZE-1:3*WRAP_SIZE];
//address
// &Force("nonport","addr"); @54
always@(posedge CLK)
begin
if(!CEN) begin
addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
end
end
assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0]
: A[ADDR_WIDTH-1:0];
//dout
// &Force("nonport","ram0_dout"); @65
// &Force("nonport","ram1_dout"); @66
// &Force("nonport","ram2_dout"); @67
// &Force("nonport","ram3_dout"); @68
assign Q[WRAP_SIZE-1:0] = ram0_dout[WRAP_SIZE-1:0];
assign Q[2*WRAP_SIZE-1:WRAP_SIZE] = ram1_dout[WRAP_SIZE-1:0];
assign Q[3*WRAP_SIZE-1:2*WRAP_SIZE] = ram2_dout[WRAP_SIZE-1:0];
assign Q[4*WRAP_SIZE-1:2*WRAP_SIZE] = ram3_dout[WRAP_SIZE-1:0];
fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram0(
.PortAClk (CLK),
.PortAAddr(addr),
.PortADataIn (ram0_din),
.PortAWriteEnable(ram0_wen),
.PortADataOut(ram0_dout));
fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram1(
.PortAClk (CLK),
.PortAAddr(addr),
.PortADataIn (ram1_din),
.PortAWriteEnable(ram1_wen),
.PortADataOut(ram1_dout));
fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram2(
.PortAClk (CLK),
.PortAAddr(addr),
.PortADataIn (ram2_din),
.PortAWriteEnable(ram2_wen),
.PortADataOut(ram2_dout));
fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram3(
.PortAClk (CLK),
.PortAAddr(addr),
.PortADataIn (ram3_din),
.PortAWriteEnable(ram3_wen),
.PortADataOut(ram3_dout));
// &ModuleEnd; @105
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_f_spsram_128x32(
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 7;
parameter DATA_WIDTH = 32;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_WIDTH-1:0] Q;
reg [ADDR_WIDTH-1:0] addr_holding;
wire [ADDR_WIDTH-1:0] A;
wire CEN;
wire CLK;
wire [DATA_WIDTH-1:0] D;
wire GWEN;
wire [DATA_WIDTH-1:0] WEN;
wire [DATA_WIDTH-1:0] Q;
wire [ADDR_WIDTH-1:0] addr;
always@(posedge CLK)
begin
if(!CEN) begin
addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
end
end
assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0]
: A[ADDR_WIDTH-1:0];
wire [DATA_WIDTH-1:0] ram_wen_vec;
genvar i;
generate
for(i=0; i<DATA_WIDTH; i=i+1) begin: RAM_DIN_VEC
assign ram_wen_vec[i] = !CEN & !WEN[i] & !GWEN;
fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram_instance(
.PortAClk (CLK),
.PortAAddr(addr),
.PortADataIn (D[i]),
.PortAWriteEnable(ram_wen_vec[i]),
.PortADataOut(Q[i]));
end
endgenerate
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_f_spsram_128x4(
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 7;
parameter DATA_WIDTH = 4;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_WIDTH-1:0] Q;
reg [ADDR_WIDTH-1:0] addr_holding;
wire [ADDR_WIDTH-1:0] A;
wire CEN;
wire CLK;
wire [DATA_WIDTH-1:0] D;
wire GWEN;
wire [DATA_WIDTH-1:0] WEN;
wire [DATA_WIDTH-1:0] Q;
wire [ADDR_WIDTH-1:0] addr;
always@(posedge CLK)
begin
if(!CEN) begin
addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
end
end
assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0]
: A[ADDR_WIDTH-1:0];
wire [DATA_WIDTH-1:0] ram_wen_vec;
genvar i;
generate
for(i=0; i<DATA_WIDTH; i=i+1) begin: RAM_DIN_VEC
assign ram_wen_vec[i] = !CEN & !WEN[i] & !GWEN;
fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram_instance(
.PortAClk (CLK),
.PortAAddr(addr),
.PortADataIn (D[i]),
.PortAWriteEnable(ram_wen_vec[i]),
.PortADataOut(Q[i]));
end
endgenerate
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &Depend("fpga_ram.v"); @22
// &ModuleBeg; @24
module pa_f_spsram_128x42(
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @25
input [6 :0] A;
input CEN;
input CLK;
input [41:0] D;
input GWEN;
input [41:0] WEN;
output [41:0] Q;
// &Regs; @26
reg [6 :0] addr_holding;
// &Wires; @27
wire [6 :0] A;
wire CEN;
wire CLK;
wire [41:0] D;
wire GWEN;
wire [41:0] Q;
wire [41:0] WEN;
wire [6 :0] addr;
wire [20:0] ram0_din;
wire [20:0] ram0_dout;
wire ram0_wen;
wire [20:0] ram1_din;
wire [20:0] ram1_dout;
wire ram1_wen;
parameter ADDR_WIDTH = 7;
parameter WRAP_SIZE = 21;
//write enable
// &Force("nonport","ram0_wen"); @33
// &Force("nonport","ram1_wen"); @34
// &Force("bus","WEN",41,0); @35
assign ram0_wen = !CEN && !WEN[ 0] && !GWEN;
assign ram1_wen = !CEN && !WEN[21] && !GWEN;
//din
// &Force("nonport","ram0_din"); @40
// &Force("nonport","ram1_din"); @41
// &Force("bus","D",2*WRAP_SIZE-1,0); @42
assign ram0_din[WRAP_SIZE-1:0] = D[WRAP_SIZE-1:0];
assign ram1_din[WRAP_SIZE-1:0] = D[2*WRAP_SIZE-1:WRAP_SIZE];
//address
// &Force("nonport","addr"); @46
always@(posedge CLK)
begin
if(!CEN) begin
addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
end
end
assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0]
: A[ADDR_WIDTH-1:0];
//dout
// &Force("nonport","ram0_dout"); @57
// &Force("nonport","ram1_dout"); @58
assign Q[WRAP_SIZE-1:0] = ram0_dout[WRAP_SIZE-1:0];
assign Q[2*WRAP_SIZE-1:WRAP_SIZE] = ram1_dout[WRAP_SIZE-1:0];
fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram0(
.PortAClk (CLK),
.PortAAddr(addr),
.PortADataIn (ram0_din),
.PortAWriteEnable(ram0_wen),
.PortADataOut(ram0_dout));
fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram1(
.PortAClk (CLK),
.PortAAddr(addr),
.PortADataIn (ram1_din),
.PortAWriteEnable(ram1_wen),
.PortADataOut(ram1_dout));
// &ModuleEnd; @78
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_f_spsram_128x43(
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 7;
parameter DATA_WIDTH = 43;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_WIDTH-1:0] Q;
reg [ADDR_WIDTH-1:0] addr_holding;
wire [ADDR_WIDTH-1:0] A;
wire CEN;
wire CLK;
wire [DATA_WIDTH-1:0] D;
wire GWEN;
wire [DATA_WIDTH-1:0] WEN;
wire [DATA_WIDTH-1:0] Q;
wire [ADDR_WIDTH-1:0] addr;
always@(posedge CLK)
begin
if(!CEN) begin
addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
end
end
assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0]
: A[ADDR_WIDTH-1:0];
wire [DATA_WIDTH-1:0] ram_wen_vec;
genvar i;
generate
for(i=0; i<DATA_WIDTH; i=i+1) begin: RAM_DIN_VEC
assign ram_wen_vec[i] = !CEN & !WEN[i] & !GWEN;
fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram_instance(
.PortAClk (CLK),
.PortAAddr(addr),
.PortADataIn (D[i]),
.PortAWriteEnable(ram_wen_vec[i]),
.PortADataOut(Q[i]));
end
endgenerate
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_f_spsram_2048x32(
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 11;
parameter DATA_WIDTH = 32;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_WIDTH-1:0] Q;
reg [ADDR_WIDTH-1:0] addr_holding;
wire [ADDR_WIDTH-1:0] A;
wire CEN;
wire CLK;
wire [DATA_WIDTH-1:0] D;
wire GWEN;
wire [DATA_WIDTH-1:0] WEN;
wire [DATA_WIDTH-1:0] Q;
wire [ADDR_WIDTH-1:0] addr;
always@(posedge CLK)
begin
if(!CEN) begin
addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
end
end
assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0]
: A[ADDR_WIDTH-1:0];
wire [DATA_WIDTH-1:0] ram_wen_vec;
genvar i;
generate
for(i=0; i<DATA_WIDTH; i=i+1) begin: RAM_DIN_VEC
assign ram_wen_vec[i] = !CEN & !WEN[i] & !GWEN;
fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram_instance(
.PortAClk (CLK),
.PortAAddr(addr),
.PortADataIn (D[i]),
.PortAWriteEnable(ram_wen_vec[i]),
.PortADataOut(Q[i]));
end
endgenerate
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module pa_f_spsram_256x32(
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
parameter ADDR_WIDTH = 8;
parameter DATA_WIDTH = 32;
parameter WRAP_SIZE = 1;
input [ADDR_WIDTH-1:0] A;
input CEN;
input CLK;
input [DATA_WIDTH-1:0] D;
input GWEN;
input [DATA_WIDTH-1:0] WEN;
output [DATA_WIDTH-1:0] Q;
reg [ADDR_WIDTH-1:0] addr_holding;
wire [ADDR_WIDTH-1:0] A;
wire CEN;
wire CLK;
wire [DATA_WIDTH-1:0] D;
wire GWEN;
wire [DATA_WIDTH-1:0] WEN;
wire [DATA_WIDTH-1:0] Q;
wire [ADDR_WIDTH-1:0] addr;
always@(posedge CLK)
begin
if(!CEN) begin
addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
end
end
assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0]
: A[ADDR_WIDTH-1:0];
wire [DATA_WIDTH-1:0] ram_wen_vec;
genvar i;
generate
for(i=0; i<DATA_WIDTH; i=i+1) begin: RAM_DIN_VEC
assign ram_wen_vec[i] = !CEN & !WEN[i] & !GWEN;
fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram_instance(
.PortAClk (CLK),
.PortAAddr(addr),
.PortADataIn (D[i]),
.PortAWriteEnable(ram_wen_vec[i]),
.PortADataOut(Q[i]));
end
endgenerate
endmodule

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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// &Depend("fpga_ram.v"); @22
// &ModuleBeg; @24
module pa_f_spsram_256x4(
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @25
input [7:0] A;
input CEN;
input CLK;
input [3:0] D;
input GWEN;
input [3:0] WEN;
output [3:0] Q;
// &Regs; @26
reg [7:0] addr_holding;
// &Wires; @27
wire [7:0] A;
wire CEN;
wire CLK;
wire [3:0] D;
wire GWEN;
wire [3:0] Q;
wire [3:0] WEN;
wire [7:0] addr;
wire [0:0] ram0_din;
wire [0:0] ram0_dout;
wire ram0_wen;
wire [0:0] ram1_din;
wire [0:0] ram1_dout;
wire ram1_wen;
wire [0:0] ram2_din;
wire [0:0] ram2_dout;
wire ram2_wen;
wire [0:0] ram3_din;
wire [0:0] ram3_dout;
wire ram3_wen;
parameter ADDR_WIDTH = 8;
parameter WRAP_SIZE = 1;
//write enable
// &Force("nonport","ram0_wen"); @33
// &Force("nonport","ram1_wen"); @34
// &Force("nonport","ram2_wen"); @35
// &Force("nonport","ram3_wen"); @36
// &Force("bus","WEN",3,0); @37
assign ram0_wen = !CEN && !WEN[0] && !GWEN;
assign ram1_wen = !CEN && !WEN[1] && !GWEN;
assign ram2_wen = !CEN && !WEN[2] && !GWEN;
assign ram3_wen = !CEN && !WEN[3] && !GWEN;
//din
// &Force("nonport","ram0_din"); @44
// &Force("nonport","ram1_din"); @45
// &Force("nonport","ram2_din"); @46
// &Force("nonport","ram3_din"); @47
// &Force("bus","D",4*WRAP_SIZE-1,0); @48
assign ram0_din[WRAP_SIZE-1:0] = D[WRAP_SIZE-1:0];
assign ram1_din[WRAP_SIZE-1:0] = D[2*WRAP_SIZE-1:WRAP_SIZE];
assign ram2_din[WRAP_SIZE-1:0] = D[3*WRAP_SIZE-1:2*WRAP_SIZE];
assign ram3_din[WRAP_SIZE-1:0] = D[4*WRAP_SIZE-1:3*WRAP_SIZE];
//address
// &Force("nonport","addr"); @54
always@(posedge CLK)
begin
if(!CEN) begin
addr_holding[ADDR_WIDTH-1:0] <= A[ADDR_WIDTH-1:0];
end
end
assign addr[ADDR_WIDTH-1:0] = CEN ? addr_holding[ADDR_WIDTH-1:0]
: A[ADDR_WIDTH-1:0];
//dout
// &Force("nonport","ram0_dout"); @65
// &Force("nonport","ram1_dout"); @66
// &Force("nonport","ram2_dout"); @67
// &Force("nonport","ram3_dout"); @68
assign Q[WRAP_SIZE-1:0] = ram0_dout[WRAP_SIZE-1:0];
assign Q[2*WRAP_SIZE-1:WRAP_SIZE] = ram1_dout[WRAP_SIZE-1:0];
assign Q[3*WRAP_SIZE-1:2*WRAP_SIZE] = ram2_dout[WRAP_SIZE-1:0];
assign Q[4*WRAP_SIZE-1:3*WRAP_SIZE] = ram3_dout[WRAP_SIZE-1:0];
fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram0(
.PortAClk (CLK),
.PortAAddr(addr),
.PortADataIn (ram0_din),
.PortAWriteEnable(ram0_wen),
.PortADataOut(ram0_dout));
fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram1(
.PortAClk (CLK),
.PortAAddr(addr),
.PortADataIn (ram1_din),
.PortAWriteEnable(ram1_wen),
.PortADataOut(ram1_dout));
fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram2(
.PortAClk (CLK),
.PortAAddr(addr),
.PortADataIn (ram2_din),
.PortAWriteEnable(ram2_wen),
.PortADataOut(ram2_dout));
fpga_ram #(WRAP_SIZE,ADDR_WIDTH) ram3(
.PortAClk (CLK),
.PortAAddr(addr),
.PortADataIn (ram3_din),
.PortAWriteEnable(ram3_wen),
.PortADataOut(ram3_dout));
// &ModuleEnd; @105
endmodule

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