Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does
not start an SB write access when sbreadonaddr/dbreadondata is set. Add fpga_optimize option to swerv.config; eliminates over 90% of clock-gating to support faster FPGA simulation.
This commit is contained in:
Joseph Rahmeh
parent
bc367eaf3a
commit
0dacc978da
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@ -148,6 +148,8 @@ Direct options for the following parameters exist:
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-ahb_lite
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build with AHB-lite bus interface
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default is AXI4
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-fpga_optimize = { 0, 1 }
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if 1, minimize clock-gating to facilitate FPGA builds
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";
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@ -170,6 +172,7 @@ my $pic_offset;
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my $pic_size;
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my $pic_total_int;
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my $ahb_lite;
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my $fpga_optimize;
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my $top_align_iccm = 0;
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@ -202,6 +205,7 @@ GetOptions(
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"pic_total_int=s" => \$pic_total_int,
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"icache_size=s" => \$icache_size,
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"ahb_lite" => \$ahb_lite,
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"fpga_optimize" => \$fpga_optimize,
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"set=s@" => \@sets,
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"unset=s@" => \@unsets,
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) || die("$helpusage");
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@ -658,7 +662,8 @@ our %config = (#{{{
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"lsu_stbuf_depth" => "$lsu_stbuf_depth",
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"dma_buf_depth" => "$dma_buf_depth",
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"lsu_num_nbload" => "$lsu_num_nbload",
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"no_secondary_alu" => "$no_secondary_alu",
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"no_secondary_alu" => "$no_secondary_alu",
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"fpga_optimize" => "$fpga_optimize"
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},
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"dccm" => {
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@ -815,6 +820,7 @@ our %config = (#{{{
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"even_odd_trigger_chains" => "true",
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);
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if (($fpga_optimize==0) && !grep(/fpga_optimize/, @sets)) { delete $config{"core"}{"fpga_optimize"}; }
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if (($iccm_enable==0) && !grep(/iccm_enable/, @sets)) { delete $config{"iccm"}{"iccm_enable"}; }
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if (($dccm_enable==0) && !grep(/dccm_enable/, @sets)) { delete $config{"dccm"}{"dccm_enable"}; }
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if (($icache_enable==0) && !grep(/icache_enable/, @sets)) { delete $config{"icache"}{"icache_enable"}; }
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@ -823,6 +829,8 @@ if (($no_secondary_alu==0) && !grep(/no_secondary_alu/, @sets)) { dele
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if (($pic_2cycle==0) && !grep(/pic_2cycle/, @sets)) { delete $config{"pic"}{"pic_2cycle"}; }
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if (($icache_ecc==0) && !grep(/icache_ecc/, @sets)) { delete $config{"icache"}{"icache_ecc"}; }
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# Perform any overrides first before derived values
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map_set_unset();
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gen_define("","", \%config,[]);
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@ -117,7 +117,7 @@ module dbg (
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`include "global.h"
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typedef enum logic [2:0] {IDLE=3'b000, HALTING=3'b001, HALTED=3'b010, CMD_START=3'b011, CMD_WAIT=3'b100, CMD_DONE=3'b101, RESUMING=3'b110} state_t;
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typedef enum logic [3:0] {SBIDLE=4'b0, WAIT=4'b1, CMD_RD=4'b10, CMD_WR=4'b11, CMD_WR_ADDR=4'b100, CMD_WR_DATA=4'b101, RSP_RD=4'b110, RSP_WR=4'b111, DONE=4'b1000} sb_state_t;
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typedef enum logic [3:0] {SBIDLE=4'h0, WAIT_RD=4'h1, WAIT_WR=4'h2, CMD_RD=4'h3, CMD_WR=4'h4, CMD_WR_ADDR=4'h5, CMD_WR_DATA=4'h6, RSP_RD=4'h7, RSP_WR=4'h8, DONE=4'h9} sb_state_t;
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state_t dbg_state;
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state_t dbg_nxtstate;
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@ -233,8 +233,8 @@ module dbg (
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assign sb_free_clken = dmi_reg_en | sb_state_en | (sb_state != SBIDLE) | clk_override;
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assign bus_clken = (sb_axi_awvalid | sb_axi_wvalid | sb_axi_arvalid | sb_axi_bvalid | sb_axi_rvalid | clk_override) & dbg_bus_clk_en;
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rvclkhdr dbg_free_cgc (.en(dbg_free_clken), .l1clk(dbg_free_clk), .*);
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rvclkhdr sb_free_cgc (.en(sb_free_clken), .l1clk(sb_free_clk), .*);
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rvoclkhdr dbg_free_cgc (.en(dbg_free_clken), .l1clk(dbg_free_clk), .*);
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rvoclkhdr sb_free_cgc (.en(sb_free_clken), .l1clk(sb_free_clk), .*);
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rvclkhdr bus_cgc (.en(bus_clken), .l1clk(bus_clk), .*);
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// end clocking section
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@ -494,15 +494,21 @@ module dbg (
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sbaddress0_reg_wren1 = 1'b0;
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case (sb_state)
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SBIDLE: begin
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sb_nxtstate = WAIT;
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sb_nxtstate = sbdata0wr_access ? WAIT_WR : WAIT_RD;
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sb_state_en = sbdata0wr_access | sbreadondata_access | sbreadonaddr_access;
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sbcs_sbbusy_wren = sb_state_en; // set the single read bit if it is a singlread command
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sbcs_sbbusy_din = 1'b1;
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sbcs_sberror_wren = sbcs_wren & (|dmi_reg_wdata[14:12]); // write to clear the error bits
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sbcs_sberror_din[2:0] = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
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end
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WAIT: begin
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sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size) ? DONE : (sbcs_reg[15] | sbcs_reg[20]) ? CMD_RD : CMD_WR;
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WAIT_RD: begin
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sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_RD;
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sb_state_en = dbg_bus_clk_en | sbcs_unaligned | sbcs_illegal_size;
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sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size;
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sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100;
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end
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WAIT_WR: begin
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sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_WR;
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sb_state_en = dbg_bus_clk_en | sbcs_unaligned | sbcs_illegal_size;
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sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size;
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sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100;
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@ -571,7 +577,7 @@ module dbg (
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rvdffs #(.WIDTH(1)) axi_rvalid_ff (.din(sb_axi_rvalid), .dout(sb_axi_rvalid_q), .en(dbg_bus_clk_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk), .*);
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rvdffs #(.WIDTH(1)) axi_rready_ff (.din(sb_axi_rready), .dout(sb_axi_rready_q), .en(dbg_bus_clk_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk), .*);
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rvdff #(.WIDTH(2)) axi_rresp_ff (.din(sb_axi_rresp[1:0]), .dout(sb_axi_rresp_q[1:0]), .rst_l(dbg_dm_rst_l), .clk(bus_clk), .*);
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rvdff #(.WIDTH(64)) axi_rdata_ff (.din(sb_axi_rdata[63:0]), .dout(sb_axi_rdata_q[63:0]), .rst_l(dbg_dm_rst_l), .clk(bus_clk), .*);
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rvdffe #(.WIDTH(64)) axi_rdata_ff (.din(sb_axi_rdata[63:0]), .dout(sb_axi_rdata_q[63:0]), .rst_l(dbg_dm_rst_l), .en(bus_clken), .*);
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// AXI Request signals
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assign sb_axi_awvalid = ((sb_state == CMD_WR) | (sb_state == CMD_WR_ADDR)) & ~(sb_axi_awvalid_q & sb_axi_awready_q);
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@ -391,16 +391,16 @@ module dec_tlu_ctl
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// for CSRs that have inpipe writes only
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logic csr_wr_clk;
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rvclkhdr csrwr_wb_cgc ( .en(dec_csr_wen_wb_mod | clk_override), .l1clk(csr_wr_clk), .* );
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rvoclkhdr csrwr_wb_cgc ( .en(dec_csr_wen_wb_mod | clk_override), .l1clk(csr_wr_clk), .* );
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logic lsu_e3_e4_clk, lsu_e4_e5_clk;
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rvclkhdr lsu_e3_e4_cgc ( .en(lsu_error_pkt_dc3.exc_valid | lsu_error_pkt_dc4.exc_valid | lsu_error_pkt_dc3.single_ecc_error | lsu_error_pkt_dc4.single_ecc_error | clk_override), .l1clk(lsu_e3_e4_clk), .* );
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rvclkhdr lsu_e4_e5_cgc ( .en(lsu_error_pkt_dc4.exc_valid | lsu_exc_valid_wb | clk_override), .l1clk(lsu_e4_e5_clk), .* );
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rvoclkhdr lsu_e3_e4_cgc ( .en(lsu_error_pkt_dc3.exc_valid | lsu_error_pkt_dc4.exc_valid | lsu_error_pkt_dc3.single_ecc_error | lsu_error_pkt_dc4.single_ecc_error | clk_override), .l1clk(lsu_e3_e4_clk), .* );
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rvoclkhdr lsu_e4_e5_cgc ( .en(lsu_error_pkt_dc4.exc_valid | lsu_exc_valid_wb | clk_override), .l1clk(lsu_e4_e5_clk), .* );
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logic e4e5_clk, e4_valid, e5_valid, e4e5_valid, internal_dbg_halt_mode_f;
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assign e4_valid = dec_tlu_i0_valid_e4 | dec_tlu_i1_valid_e4;
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assign e4e5_valid = e4_valid | e5_valid;
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rvclkhdr e4e5_cgc ( .en(e4e5_valid | clk_override), .l1clk(e4e5_clk), .* );
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rvclkhdr e4e5_int_cgc ( .en(e4e5_valid | internal_dbg_halt_mode_f | i_cpu_run_req_d1 | interrupt_valid | interrupt_valid_wb | reset_delayed | pause_expired_e4 | pause_expired_wb | clk_override), .l1clk(e4e5_int_clk), .* );
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rvoclkhdr e4e5_cgc ( .en(e4e5_valid | clk_override), .l1clk(e4e5_clk), .* );
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rvoclkhdr e4e5_int_cgc ( .en(e4e5_valid | internal_dbg_halt_mode_f | i_cpu_run_req_d1 | interrupt_valid | interrupt_valid_wb | reset_delayed | pause_expired_e4 | pause_expired_wb | clk_override), .l1clk(e4e5_int_clk), .* );
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assign lsu_freeze_pulse_e3 = lsu_freeze_dc3 & ~lsu_freeze_e4;
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@ -2091,7 +2091,7 @@ module dec_tlu_ctl
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//--------------------------------------------------------------------------------
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logic usoc_tclk;
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rvclkhdr usoctrace_cgc ( .en(i0_valid_wb | exc_or_int_valid_wb | interrupt_valid_wb | dec_tlu_i0_valid_wb1 |
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rvoclkhdr usoctrace_cgc ( .en(i0_valid_wb | exc_or_int_valid_wb | interrupt_valid_wb | dec_tlu_i0_valid_wb1 |
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dec_tlu_i0_exc_valid_wb1 | dec_tlu_i1_exc_valid_wb1 | dec_tlu_int_valid_wb1 | clk_override), .l1clk(usoc_tclk), .* );
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rvdff #(10) traceff (.*, .clk(usoc_tclk),
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.din ({i0_valid_wb, i1_valid_wb,
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@ -405,8 +405,8 @@ module dma_ctrl (
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assign dma_buffer_c1_clken = (axi_mstr_valid & dma_bus_clk_en) | dbg_cmd_valid | dec_tlu_stall_dma | clk_override;
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assign dma_free_clken = (axi_mstr_valid | axi_mstr_valid_q | axi_slv_valid | axi_slv_sent_q | dbg_cmd_valid | dma_dbg_cmd_done | dma_dbg_cmd_done_q | (|fifo_valid[DEPTH-1:0]) | wrbuf_vld | rdbuf_vld | dec_tlu_stall_dma | clk_override);
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rvclkhdr dma_buffer_c1cgc ( .en(dma_buffer_c1_clken), .l1clk(dma_buffer_c1_clk), .* );
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rvclkhdr dma_free_cgc (.en(dma_free_clken), .l1clk(dma_free_clk), .*);
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rvoclkhdr dma_buffer_c1cgc ( .en(dma_buffer_c1_clken), .l1clk(dma_buffer_c1_clk), .* );
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rvoclkhdr dma_free_cgc (.en(dma_free_clken), .l1clk(dma_free_clk), .*);
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rvclkhdr dma_bus_cgc (.en(dma_bus_clk_en), .l1clk(dma_bus_clk), .*);
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// Write channel buffer
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@ -1,65 +1,65 @@
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//------------------------------------------------------------------------------------
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// This module Synchronizes the signals between JTAG (TCK) and
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// processor (clk)
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//
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//-------------------------------------------------------------------------------------
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module dmi_jtag_to_core_sync (
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// JTAG signals
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input rd_en, // 1 bit Read Enable
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input wr_en, // 1 bit Write enable
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// Processor Signals
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input rst_n, // Core clock
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input clk, // Core reset
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output reg_en, // 1 bit Write interface bit to Processor
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output reg_wr_en // 1 bit Write enable to Processor
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);
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wire c_rd_en;
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wire c_wr_en;
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//Assign statements
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assign reg_en = c_wr_en | c_rd_en;
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assign reg_wr_en = c_wr_en;
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reg [2:0] rden, wren;
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// synchronizers
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always @ ( posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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rden <= '0;
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wren <= '0;
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end
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else begin
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rden <= {rden[1:0], rd_en};
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wren <= {wren[1:0], wr_en};
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end
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end
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assign c_rd_en = rden[1] & ~rden[2];
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assign c_wr_en = wren[1] & ~wren[2];
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endmodule
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//------------------------------------------------------------------------------------
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// This module Synchronizes the signals between JTAG (TCK) and
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// processor (clk)
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//
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//-------------------------------------------------------------------------------------
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module dmi_jtag_to_core_sync (
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// JTAG signals
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input rd_en, // 1 bit Read Enable
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input wr_en, // 1 bit Write enable
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// Processor Signals
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input rst_n, // Core clock
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input clk, // Core reset
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output reg_en, // 1 bit Write interface bit to Processor
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output reg_wr_en // 1 bit Write enable to Processor
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);
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wire c_rd_en;
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wire c_wr_en;
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//Assign statements
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assign reg_en = c_wr_en | c_rd_en;
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assign reg_wr_en = c_wr_en;
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reg [2:0] rden, wren;
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// synchronizers
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always @ ( posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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rden <= '0;
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wren <= '0;
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end
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else begin
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rden <= {rden[1:0], rd_en};
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wren <= {wren[1:0], wr_en};
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end
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end
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assign c_rd_en = rden[1] & ~rden[2];
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assign c_wr_en = wren[1] & ~wren[2];
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endmodule
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@ -1,91 +1,91 @@
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//------------------------------------------------------------------------------------
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//
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// Copyright Western Digital, 2019
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// Owner : Anusha Narayanamoorthy
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// Description:
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// Wrapper module for JTAG_TAP and DMI synchronizer
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//
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//-------------------------------------------------------------------------------------
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module dmi_wrapper(
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input scan_mode, // scan mode
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// JTAG signals
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input trst_n, // JTAG reset
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input tck, // JTAG clock
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input tms, // Test mode select
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input tdi, // Test Data Input
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output tdo, // Test Data Output
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output tdoEnable, // Test Data Output enable
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// Processor Signals
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input core_rst_n, // Core reset
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input core_clk, // Core clock
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input [31:1] jtag_id, // JTAG ID
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input [31:0] rd_data, // 32 bit Read data from Processor
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output [31:0] reg_wr_data, // 32 bit Write data to Processor
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output [6:0] reg_wr_addr, // 7 bit reg address to Processor
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output reg_en, // 1 bit Read enable to Processor
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output reg_wr_en, // 1 bit Write enable to Processor
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output dmi_hard_reset
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);
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//Wire Declaration
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wire rd_en;
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wire wr_en;
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wire dmireset;
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//jtag_tap instantiation
|
||||
rvjtag_tap i_jtag_tap(
|
||||
.trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
|
||||
.tck(tck), // dedicated JTAG TCK pad signal
|
||||
.tms(tms), // dedicated JTAG TMS pad signal
|
||||
.tdi(tdi), // dedicated JTAG TDI pad signal
|
||||
.tdo(tdo), // dedicated JTAG TDO pad signal
|
||||
.tdoEnable(tdoEnable), // enable for TDO pad
|
||||
.wr_data(reg_wr_data), // 32 bit Write data
|
||||
.wr_addr(reg_wr_addr), // 7 bit Write address
|
||||
.rd_en(rd_en), // 1 bit read enable
|
||||
.wr_en(wr_en), // 1 bit Write enable
|
||||
.rd_data(rd_data), // 32 bit Read data
|
||||
.rd_status(2'b0),
|
||||
.idle(3'h0), // no need to wait to sample data
|
||||
.dmi_stat(2'b0), // no need to wait or error possible
|
||||
.version(4'h1), // debug spec 0.13 compliant
|
||||
.jtag_id(jtag_id),
|
||||
.dmi_hard_reset(dmi_hard_reset),
|
||||
.dmi_reset(dmireset)
|
||||
);
|
||||
|
||||
|
||||
// dmi_jtag_to_core_sync instantiation
|
||||
dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync(
|
||||
.wr_en(wr_en), // 1 bit Write enable
|
||||
.rd_en(rd_en), // 1 bit Read enable
|
||||
|
||||
.rst_n(core_rst_n),
|
||||
.clk(core_clk),
|
||||
.reg_en(reg_en), // 1 bit Write interface bit
|
||||
.reg_wr_en(reg_wr_en) // 1 bit Write enable
|
||||
);
|
||||
|
||||
endmodule
|
||||
// SPDX-License-Identifier: Apache-2.0
|
||||
// Copyright 2019 Western Digital Corporation or its affiliates.
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//------------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright Western Digital, 2019
|
||||
// Owner : Anusha Narayanamoorthy
|
||||
// Description:
|
||||
// Wrapper module for JTAG_TAP and DMI synchronizer
|
||||
//
|
||||
//-------------------------------------------------------------------------------------
|
||||
|
||||
module dmi_wrapper(
|
||||
input scan_mode, // scan mode
|
||||
|
||||
// JTAG signals
|
||||
input trst_n, // JTAG reset
|
||||
input tck, // JTAG clock
|
||||
input tms, // Test mode select
|
||||
input tdi, // Test Data Input
|
||||
output tdo, // Test Data Output
|
||||
output tdoEnable, // Test Data Output enable
|
||||
|
||||
// Processor Signals
|
||||
input core_rst_n, // Core reset
|
||||
input core_clk, // Core clock
|
||||
input [31:1] jtag_id, // JTAG ID
|
||||
input [31:0] rd_data, // 32 bit Read data from Processor
|
||||
output [31:0] reg_wr_data, // 32 bit Write data to Processor
|
||||
output [6:0] reg_wr_addr, // 7 bit reg address to Processor
|
||||
output reg_en, // 1 bit Read enable to Processor
|
||||
output reg_wr_en, // 1 bit Write enable to Processor
|
||||
output dmi_hard_reset
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//Wire Declaration
|
||||
wire rd_en;
|
||||
wire wr_en;
|
||||
wire dmireset;
|
||||
|
||||
|
||||
//jtag_tap instantiation
|
||||
rvjtag_tap i_jtag_tap(
|
||||
.trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
|
||||
.tck(tck), // dedicated JTAG TCK pad signal
|
||||
.tms(tms), // dedicated JTAG TMS pad signal
|
||||
.tdi(tdi), // dedicated JTAG TDI pad signal
|
||||
.tdo(tdo), // dedicated JTAG TDO pad signal
|
||||
.tdoEnable(tdoEnable), // enable for TDO pad
|
||||
.wr_data(reg_wr_data), // 32 bit Write data
|
||||
.wr_addr(reg_wr_addr), // 7 bit Write address
|
||||
.rd_en(rd_en), // 1 bit read enable
|
||||
.wr_en(wr_en), // 1 bit Write enable
|
||||
.rd_data(rd_data), // 32 bit Read data
|
||||
.rd_status(2'b0),
|
||||
.idle(3'h0), // no need to wait to sample data
|
||||
.dmi_stat(2'b0), // no need to wait or error possible
|
||||
.version(4'h1), // debug spec 0.13 compliant
|
||||
.jtag_id(jtag_id),
|
||||
.dmi_hard_reset(dmi_hard_reset),
|
||||
.dmi_reset(dmireset)
|
||||
);
|
||||
|
||||
|
||||
// dmi_jtag_to_core_sync instantiation
|
||||
dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync(
|
||||
.wr_en(wr_en), // 1 bit Write enable
|
||||
.rd_en(rd_en), // 1 bit Read enable
|
||||
|
||||
.rst_n(core_rst_n),
|
||||
.clk(core_clk),
|
||||
.reg_en(reg_en), // 1 bit Write interface bit
|
||||
.reg_wr_en(reg_wr_en) // 1 bit Write enable
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -74,8 +74,8 @@ module exu_mul_ctl
|
|||
rvdff #(1) ld_rs1_byp_e1_ff (.*, .din(mp.load_mul_rs1_bypass_e1), .dout(load_mul_rs1_bypass_e1), .clk(exu_mul_c1_e1_clk));
|
||||
rvdff #(1) ld_rs2_byp_e1_ff (.*, .din(mp.load_mul_rs2_bypass_e1), .dout(load_mul_rs2_bypass_e1), .clk(exu_mul_c1_e1_clk));
|
||||
|
||||
rvdff #(32) a_e1_ff (.*, .din(a[31:0]), .dout(a_ff_e1[31:0]), .clk(exu_mul_c1_e1_clk));
|
||||
rvdff #(32) b_e1_ff (.*, .din(b[31:0]), .dout(b_ff_e1[31:0]), .clk(exu_mul_c1_e1_clk));
|
||||
rvdffe #(32) a_e1_ff (.*, .din(a[31:0]), .dout(a_ff_e1[31:0]), .en(mul_c1_e1_clken));
|
||||
rvdffe #(32) b_e1_ff (.*, .din(b[31:0]), .dout(b_ff_e1[31:0]), .en(mul_c1_e1_clken));
|
||||
|
||||
|
||||
|
||||
|
|
@ -91,8 +91,8 @@ module exu_mul_ctl
|
|||
rvdffs #(1) valid_e2_ff (.*, .din(valid_e1), .dout(valid_e2), .clk(active_clk), .en(~freeze));
|
||||
rvdff #(1) low_e2_ff (.*, .din(low_e1), .dout(low_e2), .clk(exu_mul_c1_e2_clk));
|
||||
|
||||
rvdff #(33) a_e2_ff (.*, .din({rs1_neg_e1, a_e1[31:0]}), .dout(a_ff_e2[32:0]), .clk(exu_mul_c1_e2_clk));
|
||||
rvdff #(33) b_e2_ff (.*, .din({rs2_neg_e1, b_e1[31:0]}), .dout(b_ff_e2[32:0]), .clk(exu_mul_c1_e2_clk));
|
||||
rvdffe #(33) a_e2_ff (.*, .din({rs1_neg_e1, a_e1[31:0]}), .dout(a_ff_e2[32:0]), .en(mul_c1_e2_clken));
|
||||
rvdffe #(33) b_e2_ff (.*, .din({rs2_neg_e1, b_e1[31:0]}), .dout(b_ff_e2[32:0]), .en(mul_c1_e2_clken));
|
||||
|
||||
|
||||
|
||||
|
|
@ -105,7 +105,7 @@ module exu_mul_ctl
|
|||
|
||||
|
||||
rvdff #(1) low_e3_ff (.*, .din(low_e2), .dout(low_e3), .clk(exu_mul_c1_e3_clk));
|
||||
rvdff #(64) prod_e3_ff (.*, .din(prod_e2[63:0]), .dout(prod_e3[63:0]), .clk(exu_mul_c1_e3_clk));
|
||||
rvdffe #(64) prod_e3_ff (.*, .din(prod_e2[63:0]), .dout(prod_e3[63:0]), .en(mul_c1_e3_clken));
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
//********************************************************************************
|
||||
// SPDX-License-Identifier: Apache-2.0
|
||||
// Copyright 2019 Western Digital Corporation or its affiliates.
|
||||
// Copyright 2019 Western Digital Corporation or it's affiliates.
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
|
|
@ -225,7 +225,7 @@ localparam NUM_SUBBANKS=4 ;
|
|||
|
||||
for (genvar i=0; i<NUM_WAYS; i++) begin: WAYS
|
||||
|
||||
rvclkhdr bank_way_c1_cgc ( .en(ic_bank_way_clken[i]), .l1clk(ic_bank_way_clk[i]), .* );
|
||||
rvoclkhdr bank_way_c1_cgc ( .en(ic_bank_way_clken[i]), .l1clk(ic_bank_way_clk[i]), .* );
|
||||
|
||||
for (genvar k=0; k<NUM_SUBBANKS; k++) begin: SUBBANKS // 16B subbank
|
||||
|
||||
|
|
|
|||
|
|
@ -82,10 +82,10 @@ module ifu_iccm_mem
|
|||
assign iccm_lo0_clken[i] = wren_bank_lo0[i] | (rden_bank[i] | clk_override); // Do not override the writes
|
||||
assign iccm_lo1_clken[i] = wren_bank_lo1[i] | (rden_bank[i] | clk_override); // Do not override the writes
|
||||
|
||||
rvclkhdr iccm_hi0_c1_cgc ( .en(iccm_hi0_clken[i]), .l1clk(iccm_hi0_clk[i]), .* );
|
||||
rvclkhdr iccm_hi1_c1_cgc ( .en(iccm_hi1_clken[i]), .l1clk(iccm_hi1_clk[i]), .* );
|
||||
rvclkhdr iccm_lo0_c1_cgc ( .en(iccm_lo0_clken[i]), .l1clk(iccm_lo0_clk[i]), .* );
|
||||
rvclkhdr iccm_lo1_c1_cgc ( .en(iccm_lo1_clken[i]), .l1clk(iccm_lo1_clk[i]), .* );
|
||||
rvoclkhdr iccm_hi0_c1_cgc ( .en(iccm_hi0_clken[i]), .l1clk(iccm_hi0_clk[i]), .* );
|
||||
rvoclkhdr iccm_hi1_c1_cgc ( .en(iccm_hi1_clken[i]), .l1clk(iccm_hi1_clk[i]), .* );
|
||||
rvoclkhdr iccm_lo0_c1_cgc ( .en(iccm_lo0_clken[i]), .l1clk(iccm_lo0_clk[i]), .* );
|
||||
rvoclkhdr iccm_lo1_c1_cgc ( .en(iccm_lo1_clken[i]), .l1clk(iccm_lo1_clk[i]), .* );
|
||||
|
||||
|
||||
assign addr_bank[i][ICCM_INDEX_BITS-1:0] = iccm_rw_addr[ICCM_BITS-1:(ICCM_BANK_BITS+2)];
|
||||
|
|
|
|||
|
|
@ -98,7 +98,7 @@ module ifu_ifc_ctl
|
|||
logic ifc_fetch_req_f2_raw;
|
||||
|
||||
logic ifc_f2_clk;
|
||||
rvclkhdr ifu_fa2_cgc ( .en(ifc_fetch_req_f1 | clk_override), .l1clk(ifc_f2_clk), .* );
|
||||
rvoclkhdr ifu_fa2_cgc ( .en(ifc_fetch_req_f1 | clk_override), .l1clk(ifc_f2_clk), .* );
|
||||
|
||||
// FSM assignment
|
||||
typedef enum logic [1:0] { IDLE=2'b00, FETCH=2'b01, STALL=2'b10, WFM=2'b11} state_t;
|
||||
|
|
|
|||
|
|
@ -488,15 +488,15 @@ module ifu_mem_ctl
|
|||
|
||||
|
||||
|
||||
rvdff #(31) ifu_fetch_addr_f2_ff (.*,
|
||||
.clk (fetch_f1_f2_c1_clk),
|
||||
rvdffe #(31) ifu_fetch_addr_f2_ff (.*,
|
||||
.en (fetch_f1_f2_c1_clken),
|
||||
.din ({fetch_addr_f1[31:1]}),
|
||||
.dout({ifu_fetch_addr_int_f2[31:1]}));
|
||||
|
||||
assign vaddr_f2[3:1] = ifu_fetch_addr_int_f2[3:1] ;
|
||||
|
||||
rvdff #(1) unc_miss_ff (.*, .clk(fetch_f1_f2_c1_clk), .din (uncacheable_miss_in), .dout(uncacheable_miss_ff));
|
||||
rvdff #(31) imb_f2_ff (.*, .clk(fetch_f1_f2_c1_clk), .din ({imb_in[31:1]}), .dout({imb_ff[31:1]}));
|
||||
rvdffe #(31) imb_f2_ff (.*, .en(fetch_f1_f2_c1_clken), .din ({imb_in[31:1]}), .dout({imb_ff[31:1]}));
|
||||
rvdff #(3) mb_rep_wayf2_ff (.*, .clk(fetch_f1_f2_c1_clk), .din ({way_status_mb_in[2:0]}), .dout({way_status_mb_ff[2:0]}));
|
||||
|
||||
rvdff #(4) mb_tagv_ff (.*, .clk(fetch_f1_f2_c1_clk), .din ({tagv_mb_in[3:0]}), .dout({tagv_mb_ff[3:0]}));
|
||||
|
|
@ -732,8 +732,8 @@ assign ic_fetch_val_f2[0] = fetch_req_f2_qual ;
|
|||
assign write_byp_second_data = axi_ifu_wr_en_new & ({byp_tag_ff[IFU_BUS_TAG-1:1],1'b1} == ifu_axi_rid_ff[IFU_BUS_TAG-1:0]);
|
||||
|
||||
// First Half flops
|
||||
rvdff #(64) byp_data_first_half (.*,
|
||||
.clk(byp_data_first_c1_clk),
|
||||
rvdffe #(64) byp_data_first_half (.*,
|
||||
.en(byp_data_first_c1_clken),
|
||||
.din (ifu_wr_data_new[63:0]),
|
||||
.dout(ifu_byp_data_first_half[63:0]));
|
||||
|
||||
|
|
@ -752,8 +752,8 @@ assign ic_fetch_val_f2[0] = fetch_req_f2_qual ;
|
|||
|
||||
|
||||
// Second Half flops
|
||||
rvdff #(64) byp_data_second_half (.*,
|
||||
.clk(byp_data_second_c1_clk),
|
||||
rvdffe #(64) byp_data_second_half (.*,
|
||||
.en(byp_data_second_c1_clken),
|
||||
.din (ifu_wr_data_new[63:0]),
|
||||
.dout(ifu_byp_data_second_half[63:0]));
|
||||
|
||||
|
|
@ -1410,7 +1410,7 @@ assign ic_debug_ic_array_sel_word2_in = (ic_debug_addr[3:2] == 2'b10) & ic_debug
|
|||
assign ic_debug_ic_array_sel_word3_in = (ic_debug_addr[3:2] == 2'b11) & ic_debug_rd_en & ~ic_debug_tag_array ;
|
||||
assign ic_debug_ict_array_sel_in = ic_debug_rd_en & ic_debug_tag_array ;
|
||||
|
||||
rvdff #(09) ifu_debug_sel_ff (.*, .clk (debug_c1_clk),
|
||||
rvdffe #(09) ifu_debug_sel_ff (.*, .en (debug_c1_clken),
|
||||
.din ({ic_debug_ic_array_sel_word0_in,
|
||||
ic_debug_ic_array_sel_word1_in,
|
||||
ic_debug_ic_array_sel_word2_in,
|
||||
|
|
@ -1444,7 +1444,7 @@ assign ifu_ic_debug_rd_data_in[41:0] = ( {42{ic_debug_ict_array_sel_ff }} & {
|
|||
( {42{ic_debug_ic_array_sel_word2 }} & {ic_rd_data [125:84]}) |
|
||||
( {42{ic_debug_ic_array_sel_word3 }} & {ic_rd_data [167:126]}) ;
|
||||
|
||||
rvdff #(42) ifu_debug_data_ff (.*, .clk (debug_data_clk),
|
||||
rvdffe #(42) ifu_debug_data_ff (.*, .en (debug_data_clken),
|
||||
.din ({
|
||||
ifu_ic_debug_rd_data_in[41:0]
|
||||
}),
|
||||
|
|
@ -1460,7 +1460,7 @@ assign ifu_ic_debug_rd_data_in[33:0] = ( {34{ic_debug_ict_array_sel_ff }} & {
|
|||
( {34{ic_debug_ic_array_sel_word2 }} & {ic_rd_data [101:68]}) |
|
||||
( {34{ic_debug_ic_array_sel_word3 }} & {ic_rd_data [135:102]}) ;
|
||||
|
||||
rvdff #(34) ifu_debug_data_ff (.*, .clk (debug_data_clk),
|
||||
rvdffe #(34) ifu_debug_data_ff (.*, .en (debug_data_clken),
|
||||
.din ({
|
||||
ifu_ic_debug_rd_data_in[33:0]
|
||||
}),
|
||||
|
|
|
|||
|
|
@ -112,6 +112,25 @@ module rvclkhdr
|
|||
|
||||
endmodule
|
||||
|
||||
module rvoclkhdr
|
||||
(
|
||||
input logic en,
|
||||
input logic clk,
|
||||
input logic scan_mode,
|
||||
output logic l1clk
|
||||
);
|
||||
|
||||
logic TE;
|
||||
assign TE = scan_mode;
|
||||
|
||||
`ifdef RV_FPGA_OPTIMIZE
|
||||
assign l1clk = clk;
|
||||
`else
|
||||
`TEC_RV_ICG rvclkhdr ( .*, .E(en), .CP(clk), .Q(l1clk));
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
||||
module rvdffe #( parameter WIDTH=1 )
|
||||
(
|
||||
input logic [WIDTH-1:0] din,
|
||||
|
|
@ -124,6 +143,12 @@ module rvdffe #( parameter WIDTH=1 )
|
|||
|
||||
logic l1clk;
|
||||
|
||||
`ifdef RV_FPGA_OPTIMIZE
|
||||
begin: genblock
|
||||
rvdffs #(WIDTH) dff ( .* );
|
||||
end
|
||||
`else
|
||||
|
||||
`ifndef PHYSICAL
|
||||
if (WIDTH >= 8) begin: genblock
|
||||
`endif
|
||||
|
|
@ -134,6 +159,8 @@ module rvdffe #( parameter WIDTH=1 )
|
|||
else
|
||||
$error("%m: rvdffe width must be >= 8");
|
||||
`endif
|
||||
|
||||
`endif
|
||||
|
||||
endmodule // rvdffe
|
||||
|
||||
|
|
|
|||
|
|
@ -256,13 +256,14 @@ module lsu
|
|||
// Clocks
|
||||
logic lsu_c1_dc3_clk, lsu_c1_dc4_clk, lsu_c1_dc5_clk;
|
||||
logic lsu_c2_dc3_clk, lsu_c2_dc4_clk, lsu_c2_dc5_clk;
|
||||
logic lsu_freeze_c1_dc1_clk, lsu_freeze_c1_dc2_clk, lsu_freeze_c1_dc3_clk;
|
||||
logic lsu_store_c1_dc1_clk, lsu_store_c1_dc2_clk, lsu_store_c1_dc3_clk, lsu_store_c1_dc4_clk, lsu_store_c1_dc5_clk;
|
||||
logic lsu_freeze_c1_dc2_clk, lsu_freeze_c1_dc3_clk;
|
||||
logic lsu_freeze_c1_dc1_clken, lsu_freeze_c1_dc2_clken, lsu_freeze_c1_dc3_clken;
|
||||
logic lsu_store_c1_dc1_clken, lsu_store_c1_dc2_clken, lsu_store_c1_dc3_clken, lsu_store_c1_dc4_clk, lsu_store_c1_dc5_clk;
|
||||
|
||||
logic lsu_freeze_c2_dc1_clk, lsu_freeze_c2_dc2_clk, lsu_freeze_c2_dc3_clk, lsu_freeze_c2_dc4_clk;
|
||||
logic lsu_stbuf_c1_clk;
|
||||
logic lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk;
|
||||
logic lsu_dccm_c1_dc3_clk, lsu_pic_c1_dc3_clk;
|
||||
logic lsu_dccm_c1_dc3_clk, lsu_pic_c1_dc3_clken;
|
||||
logic lsu_busm_clk;
|
||||
logic lsu_free_c2_clk;
|
||||
|
||||
|
|
|
|||
|
|
@ -66,13 +66,16 @@ module lsu_clkdomain
|
|||
output logic lsu_c2_dc4_clk, // dc4 pipe double pulse clock
|
||||
output logic lsu_c2_dc5_clk, // dc5 pipe double pulse clock
|
||||
|
||||
output logic lsu_store_c1_dc1_clk, // store in dc1
|
||||
output logic lsu_store_c1_dc2_clk, // store in dc2
|
||||
output logic lsu_store_c1_dc3_clk, // store in dc3
|
||||
output logic lsu_store_c1_dc1_clken, // store in dc1
|
||||
output logic lsu_store_c1_dc2_clken, // store in dc2
|
||||
output logic lsu_store_c1_dc3_clken, // store in dc3
|
||||
output logic lsu_store_c1_dc4_clk, // store in dc4
|
||||
output logic lsu_store_c1_dc5_clk, // store in dc5
|
||||
|
||||
output logic lsu_freeze_c1_dc1_clk, // freeze
|
||||
output logic lsu_freeze_c1_dc1_clken, // freeze
|
||||
output logic lsu_freeze_c1_dc2_clken, // freeze
|
||||
output logic lsu_freeze_c1_dc3_clken, // freeze
|
||||
|
||||
output logic lsu_freeze_c1_dc2_clk, // freeze
|
||||
output logic lsu_freeze_c1_dc3_clk, // freeze
|
||||
|
||||
|
|
@ -82,7 +85,7 @@ module lsu_clkdomain
|
|||
output logic lsu_freeze_c2_dc4_clk,
|
||||
|
||||
output logic lsu_dccm_c1_dc3_clk, // dccm clock
|
||||
output logic lsu_pic_c1_dc3_clk, // pic clock
|
||||
output logic lsu_pic_c1_dc3_clken, // pic clock enable
|
||||
|
||||
output logic lsu_stbuf_c1_clk,
|
||||
output logic lsu_bus_obuf_c1_clk, // ibuf clock
|
||||
|
|
@ -98,16 +101,16 @@ module lsu_clkdomain
|
|||
logic lsu_c1_dc1_clken, lsu_c1_dc2_clken, lsu_c1_dc3_clken, lsu_c1_dc4_clken, lsu_c1_dc5_clken;
|
||||
logic lsu_c2_dc3_clken, lsu_c2_dc4_clken, lsu_c2_dc5_clken;
|
||||
logic lsu_c1_dc1_clken_q, lsu_c1_dc2_clken_q, lsu_c1_dc3_clken_q, lsu_c1_dc4_clken_q, lsu_c1_dc5_clken_q;
|
||||
logic lsu_store_c1_dc1_clken, lsu_store_c1_dc2_clken, lsu_store_c1_dc3_clken, lsu_store_c1_dc4_clken, lsu_store_c1_dc5_clken;
|
||||
logic lsu_store_c1_dc4_clken, lsu_store_c1_dc5_clken;
|
||||
|
||||
logic lsu_freeze_c1_dc1_clken, lsu_freeze_c1_dc2_clken, lsu_freeze_c1_dc3_clken, lsu_freeze_c1_dc4_clken;
|
||||
logic lsu_freeze_c1_dc4_clken;
|
||||
logic lsu_freeze_c2_dc1_clken, lsu_freeze_c2_dc2_clken, lsu_freeze_c2_dc3_clken, lsu_freeze_c2_dc4_clken;
|
||||
logic lsu_freeze_c1_dc1_clken_q, lsu_freeze_c1_dc2_clken_q, lsu_freeze_c1_dc3_clken_q, lsu_freeze_c1_dc4_clken_q;
|
||||
|
||||
logic lsu_stbuf_c1_clken;
|
||||
logic lsu_bus_ibuf_c1_clken, lsu_bus_obuf_c1_clken, lsu_bus_buf_c1_clken;
|
||||
|
||||
logic lsu_dccm_c1_dc3_clken, lsu_pic_c1_dc3_clken;
|
||||
logic lsu_dccm_c1_dc3_clken;
|
||||
|
||||
logic lsu_free_c1_clken, lsu_free_c1_clken_q, lsu_free_c2_clken;
|
||||
logic lsu_bus_valid_clken;
|
||||
|
|
@ -171,21 +174,21 @@ module lsu_clkdomain
|
|||
rvdff #(1) lsu_freeze_c1_dc4_clkenff (.din(lsu_freeze_c1_dc4_clken), .dout(lsu_freeze_c1_dc4_clken_q), .clk(lsu_freeze_c2_dc4_clk), .*);
|
||||
|
||||
// Clock Headers
|
||||
rvclkhdr lsu_c1dc3_cgc ( .en(lsu_c1_dc3_clken), .l1clk(lsu_c1_dc3_clk), .* );
|
||||
rvclkhdr lsu_c1dc4_cgc ( .en(lsu_c1_dc4_clken), .l1clk(lsu_c1_dc4_clk), .* );
|
||||
rvclkhdr lsu_c1dc5_cgc ( .en(lsu_c1_dc5_clken), .l1clk(lsu_c1_dc5_clk), .* );
|
||||
rvoclkhdr lsu_c1dc3_cgc ( .en(lsu_c1_dc3_clken), .l1clk(lsu_c1_dc3_clk), .* );
|
||||
rvoclkhdr lsu_c1dc4_cgc ( .en(lsu_c1_dc4_clken), .l1clk(lsu_c1_dc4_clk), .* );
|
||||
rvoclkhdr lsu_c1dc5_cgc ( .en(lsu_c1_dc5_clken), .l1clk(lsu_c1_dc5_clk), .* );
|
||||
|
||||
rvclkhdr lsu_c2dc3_cgc ( .en(lsu_c2_dc3_clken), .l1clk(lsu_c2_dc3_clk), .* );
|
||||
rvclkhdr lsu_c2dc4_cgc ( .en(lsu_c2_dc4_clken), .l1clk(lsu_c2_dc4_clk), .* );
|
||||
rvclkhdr lsu_c2dc5_cgc ( .en(lsu_c2_dc5_clken), .l1clk(lsu_c2_dc5_clk), .* );
|
||||
rvoclkhdr lsu_c2dc3_cgc ( .en(lsu_c2_dc3_clken), .l1clk(lsu_c2_dc3_clk), .* );
|
||||
rvoclkhdr lsu_c2dc4_cgc ( .en(lsu_c2_dc4_clken), .l1clk(lsu_c2_dc4_clk), .* );
|
||||
rvoclkhdr lsu_c2dc5_cgc ( .en(lsu_c2_dc5_clken), .l1clk(lsu_c2_dc5_clk), .* );
|
||||
|
||||
rvclkhdr lsu_store_c1dc1_cgc (.en(lsu_store_c1_dc1_clken), .l1clk(lsu_store_c1_dc1_clk), .*);
|
||||
rvclkhdr lsu_store_c1dc2_cgc (.en(lsu_store_c1_dc2_clken), .l1clk(lsu_store_c1_dc2_clk), .*);
|
||||
rvclkhdr lsu_store_c1dc3_cgc (.en(lsu_store_c1_dc3_clken), .l1clk(lsu_store_c1_dc3_clk), .*);
|
||||
rvclkhdr lsu_store_c1dc4_cgc (.en(lsu_store_c1_dc4_clken), .l1clk(lsu_store_c1_dc4_clk), .*);
|
||||
rvclkhdr lsu_store_c1dc5_cgc (.en(lsu_store_c1_dc5_clken), .l1clk(lsu_store_c1_dc5_clk), .*);
|
||||
// rvclkhdr lsu_store_c1dc1_cgc (.en(lsu_store_c1_dc1_clken), .l1clk(lsu_store_c1_dc1_clk), .*);
|
||||
// rvclkhdr lsu_store_c1dc2_cgc (.en(lsu_store_c1_dc2_clken), .l1clk(lsu_store_c1_dc2_clk), .*);
|
||||
// rvclkhdr lsu_store_c1dc3_cgc (.en(lsu_store_c1_dc3_clken), .l1clk(lsu_store_c1_dc3_clk), .*);
|
||||
rvoclkhdr lsu_store_c1dc4_cgc (.en(lsu_store_c1_dc4_clken), .l1clk(lsu_store_c1_dc4_clk), .*);
|
||||
rvoclkhdr lsu_store_c1dc5_cgc (.en(lsu_store_c1_dc5_clken), .l1clk(lsu_store_c1_dc5_clk), .*);
|
||||
|
||||
rvclkhdr lsu_freeze_c1dc1_cgc ( .en(lsu_freeze_c1_dc1_clken), .l1clk(lsu_freeze_c1_dc1_clk), .* );
|
||||
// rvclkhdr lsu_freeze_c1dc1_cgc ( .en(lsu_freeze_c1_dc1_clken), .l1clk(lsu_freeze_c1_dc1_clk), .* );
|
||||
rvclkhdr lsu_freeze_c1dc2_cgc ( .en(lsu_freeze_c1_dc2_clken), .l1clk(lsu_freeze_c1_dc2_clk), .* );
|
||||
rvclkhdr lsu_freeze_c1dc3_cgc ( .en(lsu_freeze_c1_dc3_clken), .l1clk(lsu_freeze_c1_dc3_clk), .* );
|
||||
|
||||
|
|
@ -194,15 +197,15 @@ module lsu_clkdomain
|
|||
rvclkhdr lsu_freeze_c2dc3_cgc ( .en(lsu_freeze_c2_dc3_clken), .l1clk(lsu_freeze_c2_dc3_clk), .* );
|
||||
rvclkhdr lsu_freeze_c2dc4_cgc ( .en(lsu_freeze_c2_dc4_clken), .l1clk(lsu_freeze_c2_dc4_clk), .* );
|
||||
|
||||
rvclkhdr lsu_stbuf_c1_cgc ( .en(lsu_stbuf_c1_clken), .l1clk(lsu_stbuf_c1_clk), .* );
|
||||
rvclkhdr lsu_bus_ibuf_c1_cgc ( .en(lsu_bus_ibuf_c1_clken), .l1clk(lsu_bus_ibuf_c1_clk), .* );
|
||||
rvclkhdr lsu_bus_obuf_c1_cgc ( .en(lsu_bus_obuf_c1_clken), .l1clk(lsu_bus_obuf_c1_clk), .* );
|
||||
rvclkhdr lsu_bus_buf_c1_cgc ( .en(lsu_bus_buf_c1_clken), .l1clk(lsu_bus_buf_c1_clk), .* );
|
||||
rvoclkhdr lsu_stbuf_c1_cgc ( .en(lsu_stbuf_c1_clken), .l1clk(lsu_stbuf_c1_clk), .* );
|
||||
rvoclkhdr lsu_bus_ibuf_c1_cgc ( .en(lsu_bus_ibuf_c1_clken), .l1clk(lsu_bus_ibuf_c1_clk), .* );
|
||||
rvoclkhdr lsu_bus_obuf_c1_cgc ( .en(lsu_bus_obuf_c1_clken), .l1clk(lsu_bus_obuf_c1_clk), .* );
|
||||
rvoclkhdr lsu_bus_buf_c1_cgc ( .en(lsu_bus_buf_c1_clken), .l1clk(lsu_bus_buf_c1_clk), .* );
|
||||
|
||||
rvclkhdr lsu_busm_cgc (.en(lsu_bus_clk_en), .l1clk(lsu_busm_clk), .*);
|
||||
|
||||
rvclkhdr lsu_dccm_c1dc3_cgc (.en(lsu_dccm_c1_dc3_clken), .l1clk(lsu_dccm_c1_dc3_clk), .*);
|
||||
rvclkhdr lsu_pic_c1dc3_cgc (.en(lsu_pic_c1_dc3_clken), .l1clk(lsu_pic_c1_dc3_clk), .*);
|
||||
// rvclkhdr lsu_pic_c1dc3_cgc (.en(lsu_pic_c1_dc3_clken), .l1clk(lsu_pic_c1_dc3_clk), .*);
|
||||
|
||||
rvclkhdr lsu_free_cgc (.en(lsu_free_c2_clken), .l1clk(lsu_free_c2_clk), .*);
|
||||
|
||||
|
|
|
|||
|
|
@ -32,9 +32,10 @@ module lsu_dccm_ctl
|
|||
input logic lsu_freeze_c2_dc2_clk, // clocks
|
||||
input logic lsu_freeze_c2_dc3_clk,
|
||||
input logic lsu_dccm_c1_dc3_clk,
|
||||
input logic lsu_pic_c1_dc3_clk,
|
||||
input logic lsu_pic_c1_dc3_clken,
|
||||
|
||||
input logic rst_l,
|
||||
input logic clk,
|
||||
input logic lsu_freeze_dc3, // freze
|
||||
|
||||
input lsu_pkt_t lsu_pkt_dc3, // lsu packets
|
||||
|
|
@ -175,7 +176,7 @@ module lsu_dccm_ctl
|
|||
// Flops
|
||||
assign picm_mask_data_dc3[31:0] = picm_rd_data_lo_dc3[31:0];
|
||||
assign picm_rd_data_dc3[63:0] = {picm_rd_data_lo_dc3[31:0], picm_rd_data_lo_dc3[31:0]} ;
|
||||
rvdff #(32) picm_data_ff (.*, .din(picm_rd_data[31:0]), .dout(picm_rd_data_lo_dc3[31:0]), .clk(lsu_pic_c1_dc3_clk));
|
||||
rvdffe #(32) picm_data_ff (.*, .din(picm_rd_data[31:0]), .dout(picm_rd_data_lo_dc3[31:0]), .en(lsu_pic_c1_dc3_clken));
|
||||
if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
|
||||
rvdff #(1) dccm_rden_dc2ff (.*, .din(lsu_dccm_rden_dc1), .dout(lsu_dccm_rden_dc2), .clk(lsu_freeze_c2_dc2_clk));
|
||||
rvdff #(1) dccm_rden_dc3ff (.*, .din(lsu_dccm_rden_dc2), .dout(lsu_dccm_rden_dc3), .clk(lsu_freeze_c2_dc3_clk));
|
||||
|
|
|
|||
|
|
@ -29,22 +29,26 @@ module lsu_lsc_ctl
|
|||
import swerv_types::*;
|
||||
(
|
||||
input logic rst_l,
|
||||
input logic clk,
|
||||
|
||||
// clocks per pipe
|
||||
input logic lsu_c1_dc4_clk,
|
||||
input logic lsu_c1_dc5_clk,
|
||||
input logic lsu_c2_dc4_clk,
|
||||
input logic lsu_c2_dc5_clk,
|
||||
// freez clocks per pipe
|
||||
input logic lsu_freeze_c1_dc1_clk,
|
||||
input logic lsu_freeze_c1_dc1_clken,
|
||||
input logic lsu_freeze_c1_dc2_clken,
|
||||
input logic lsu_freeze_c1_dc2_clk,
|
||||
input logic lsu_freeze_c1_dc3_clk,
|
||||
input logic lsu_freeze_c1_dc3_clken,
|
||||
input logic lsu_freeze_c1_dc3_clk,
|
||||
input logic lsu_freeze_c2_dc1_clk,
|
||||
input logic lsu_freeze_c2_dc2_clk,
|
||||
input logic lsu_freeze_c2_dc3_clk,
|
||||
|
||||
input logic lsu_store_c1_dc1_clk,
|
||||
input logic lsu_store_c1_dc2_clk,
|
||||
input logic lsu_store_c1_dc3_clk,
|
||||
input logic lsu_store_c1_dc1_clken,
|
||||
input logic lsu_store_c1_dc2_clken,
|
||||
input logic lsu_store_c1_dc3_clken,
|
||||
input logic lsu_store_c1_dc4_clk,
|
||||
input logic lsu_store_c1_dc5_clk,
|
||||
|
||||
|
|
@ -167,8 +171,8 @@ module lsu_lsc_ctl
|
|||
assign lsu_rs1_d[31:0] = dma_dccm_req ? dma_mem_addr[31:0] : exu_lsu_rs1_d[31:0];
|
||||
assign lsu_offset_d[11:0] = dec_lsu_offset_d[11:0] & ~{12{dma_dccm_req}};
|
||||
|
||||
rvdff #(32) rs1ff (.*, .din(lsu_rs1_d[31:0]), .dout(rs1_dc1_raw[31:0]), .clk(lsu_freeze_c1_dc1_clk));
|
||||
rvdff #(12) offsetff (.*, .din(lsu_offset_d[11:0]), .dout(offset_dc1[11:0]), .clk(lsu_freeze_c1_dc1_clk));
|
||||
rvdffe #(32) rs1ff (.*, .din(lsu_rs1_d[31:0]), .dout(rs1_dc1_raw[31:0]), .en(lsu_freeze_c1_dc1_clken));
|
||||
rvdffe #(12) offsetff (.*, .din(lsu_offset_d[11:0]), .dout(offset_dc1[11:0]), .en(lsu_freeze_c1_dc1_clken));
|
||||
|
||||
assign rs1_dc1[31:0] = (lsu_pkt_dc1.load_ldst_bypass_c1) ? lsu_result_dc3[31:0] : rs1_dc1_raw[31:0];
|
||||
|
||||
|
|
@ -245,9 +249,9 @@ module lsu_lsc_ctl
|
|||
rvdff #(1) lsu_pkt_vlddc4ff (.*, .din(lsu_pkt_dc4_in.valid), .dout(lsu_pkt_dc4.valid), .clk(lsu_c2_dc4_clk));
|
||||
rvdff #(1) lsu_pkt_vlddc5ff (.*, .din(lsu_pkt_dc5_in.valid), .dout(lsu_pkt_dc5.valid), .clk(lsu_c2_dc5_clk));
|
||||
|
||||
rvdff #($bits(lsu_pkt_t)-1) lsu_pkt_dc1ff (.*, .din(lsu_pkt_dc1_in[$bits(lsu_pkt_t)-1:1]), .dout(lsu_pkt_dc1[$bits(lsu_pkt_t)-1:1]), .clk(lsu_freeze_c1_dc1_clk));
|
||||
rvdff #($bits(lsu_pkt_t)-1) lsu_pkt_dc2ff (.*, .din(lsu_pkt_dc2_in[$bits(lsu_pkt_t)-1:1]), .dout(lsu_pkt_dc2[$bits(lsu_pkt_t)-1:1]), .clk(lsu_freeze_c1_dc2_clk));
|
||||
rvdff #($bits(lsu_pkt_t)-1) lsu_pkt_dc3ff (.*, .din(lsu_pkt_dc3_in[$bits(lsu_pkt_t)-1:1]), .dout(lsu_pkt_dc3[$bits(lsu_pkt_t)-1:1]), .clk(lsu_freeze_c1_dc3_clk));
|
||||
rvdffe #($bits(lsu_pkt_t)-1) lsu_pkt_dc1ff (.*, .din(lsu_pkt_dc1_in[$bits(lsu_pkt_t)-1:1]), .dout(lsu_pkt_dc1[$bits(lsu_pkt_t)-1:1]), .en(lsu_freeze_c1_dc1_clken));
|
||||
rvdffe #($bits(lsu_pkt_t)-1) lsu_pkt_dc2ff (.*, .din(lsu_pkt_dc2_in[$bits(lsu_pkt_t)-1:1]), .dout(lsu_pkt_dc2[$bits(lsu_pkt_t)-1:1]), .en(lsu_freeze_c1_dc2_clken));
|
||||
rvdffe #($bits(lsu_pkt_t)-1) lsu_pkt_dc3ff (.*, .din(lsu_pkt_dc3_in[$bits(lsu_pkt_t)-1:1]), .dout(lsu_pkt_dc3[$bits(lsu_pkt_t)-1:1]), .en(lsu_freeze_c1_dc3_clken));
|
||||
rvdff #($bits(lsu_pkt_t)-1) lsu_pkt_dc4ff (.*, .din(lsu_pkt_dc4_in[$bits(lsu_pkt_t)-1:1]), .dout(lsu_pkt_dc4[$bits(lsu_pkt_t)-1:1]), .clk(lsu_c1_dc4_clk));
|
||||
rvdff #($bits(lsu_pkt_t)-1) lsu_pkt_dc5ff (.*, .din(lsu_pkt_dc5_in[$bits(lsu_pkt_t)-1:1]), .dout(lsu_pkt_dc5[$bits(lsu_pkt_t)-1:1]), .clk(lsu_c1_dc5_clk));
|
||||
|
||||
|
|
@ -295,19 +299,20 @@ module lsu_lsc_ctl
|
|||
|
||||
rvdff #(32) lsu_result_corr_dc4ff (.*, .din(lsu_result_corr_dc3[31:0]), .dout(lsu_result_corr_dc4[31:0]), .clk(lsu_c1_dc4_clk));
|
||||
|
||||
rvdff #(64) sddc1ff (.*, .din(store_data_d[63:0]), .dout(store_data_dc1[63:0]), .clk(lsu_store_c1_dc1_clk));
|
||||
rvdff #(64) sddc2ff (.*, .din(store_data_dc2_in[63:0]), .dout(store_data_pre_dc2[63:0]), .clk(lsu_store_c1_dc2_clk));
|
||||
rvdffs #(64) sddc3ff (.*, .din(store_data_dc2[63:0]), .dout(store_data_pre_dc3[63:0]), .en(~lsu_freeze_dc3), .clk(lsu_store_c1_dc3_clk));
|
||||
rvdffe #(64) sddc1ff (.*, .din(store_data_d[63:0]), .dout(store_data_dc1[63:0]), .en(lsu_store_c1_dc1_clken));
|
||||
rvdffe #(64) sddc2ff (.*, .din(store_data_dc2_in[63:0]), .dout(store_data_pre_dc2[63:0]), .en(lsu_store_c1_dc2_clken));
|
||||
rvdffe #(64) sddc3ff (.*, .din(store_data_dc2[63:0]), .dout(store_data_pre_dc3[63:0]), .en(~lsu_freeze_dc3 & lsu_store_c1_dc3_clken) );
|
||||
|
||||
rvdff #(32) sddc4ff (.*, .din(store_data_dc3[31:0]), .dout(store_data_dc4[31:0]), .clk(lsu_store_c1_dc4_clk));
|
||||
rvdff #(32) sddc5ff (.*, .din(store_data_dc4[31:0]), .dout(store_data_dc5[31:0]), .clk(lsu_store_c1_dc5_clk));
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||||
|
||||
rvdff #(32) sadc2ff (.*, .din(lsu_addr_dc1[31:0]), .dout(lsu_addr_dc2[31:0]), .clk(lsu_freeze_c1_dc2_clk));
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||||
rvdff #(32) sadc3ff (.*, .din(lsu_addr_dc2[31:0]), .dout(lsu_addr_dc3[31:0]), .clk(lsu_freeze_c1_dc3_clk));
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||||
rvdffe #(32) sadc2ff (.*, .din(lsu_addr_dc1[31:0]), .dout(lsu_addr_dc2[31:0]), .en(lsu_freeze_c1_dc2_clken));
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||||
rvdffe #(32) sadc3ff (.*, .din(lsu_addr_dc2[31:0]), .dout(lsu_addr_dc3[31:0]), .en(lsu_freeze_c1_dc3_clken));
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||||
rvdff #(32) sadc4ff (.*, .din(lsu_addr_dc3[31:0]), .dout(lsu_addr_dc4[31:0]), .clk(lsu_c1_dc4_clk));
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||||
rvdff #(32) sadc5ff (.*, .din(lsu_addr_dc4[31:0]), .dout(lsu_addr_dc5[31:0]), .clk(lsu_c1_dc5_clk));
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||||
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||||
rvdff #(32) end_addr_dc2ff (.*, .din(end_addr_dc1[31:0]), .dout(end_addr_dc2[31:0]), .clk(lsu_freeze_c1_dc2_clk));
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||||
rvdff #(32) end_addr_dc3ff (.*, .din(end_addr_dc2[31:0]), .dout(end_addr_dc3[31:0]), .clk(lsu_freeze_c1_dc3_clk));
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||||
rvdffe #(32) end_addr_dc2ff (.*, .din(end_addr_dc1[31:0]), .dout(end_addr_dc2[31:0]), .en(lsu_freeze_c1_dc2_clken));
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||||
rvdffe #(32) end_addr_dc3ff (.*, .din(end_addr_dc2[31:0]), .dout(end_addr_dc3[31:0]), .en(lsu_freeze_c1_dc3_clken));
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||||
rvdff #(32) end_addr_dc4ff (.*, .din(end_addr_dc3[31:0]), .dout(end_addr_dc4[31:0]), .clk(lsu_c1_dc4_clk));
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||||
rvdff #(32) end_addr_dc5ff (.*, .din(end_addr_dc4[31:0]), .dout(end_addr_dc5[31:0]), .clk(lsu_c1_dc5_clk));
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||||
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||||
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@ -37,6 +37,9 @@ module lsu_stbuf
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|||
input logic lsu_freeze_c2_dc3_clk, // freeze clock
|
||||
input logic lsu_freeze_c1_dc2_clk, // freeze clock
|
||||
input logic lsu_freeze_c1_dc3_clk, // freeze clock
|
||||
|
||||
input logic lsu_freeze_c1_dc3_clken,
|
||||
|
||||
input logic lsu_c1_dc4_clk, // lsu pipe clock
|
||||
input logic lsu_c1_dc5_clk, // lsu pipe clock
|
||||
input logic lsu_c2_dc4_clk, // lsu pipe clock
|
||||
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|
@ -385,8 +388,8 @@ module lsu_stbuf
|
|||
rvdff #(.WIDTH(BYTE_WIDTH)) stbuf_fwdbyteen_hi_dc3ff (.din(stbuf_fwdbyteen_hi_fn_dc2[BYTE_WIDTH-1:0]), .dout(stbuf_fwdbyteen_hi_dc3[BYTE_WIDTH-1:0]), .clk(lsu_freeze_c1_dc3_clk), .*);
|
||||
rvdff #(.WIDTH(BYTE_WIDTH)) stbuf_fwdbyteen_lo_dc3ff (.din(stbuf_fwdbyteen_lo_fn_dc2[BYTE_WIDTH-1:0]), .dout(stbuf_fwdbyteen_lo_dc3[BYTE_WIDTH-1:0]), .clk(lsu_freeze_c1_dc3_clk), .*);
|
||||
|
||||
rvdff #(.WIDTH(DATA_WIDTH)) stbuf_fwddata_hi_dc3ff (.din(stbuf_fwddata_hi_fn_dc2[DATA_WIDTH-1:0]), .dout(stbuf_fwddata_hi_dc3[DATA_WIDTH-1:0]), .clk(lsu_freeze_c1_dc3_clk), .*);
|
||||
rvdff #(.WIDTH(DATA_WIDTH)) stbuf_fwddata_lo_dc3ff (.din(stbuf_fwddata_lo_fn_dc2[DATA_WIDTH-1:0]), .dout(stbuf_fwddata_lo_dc3[DATA_WIDTH-1:0]), .clk(lsu_freeze_c1_dc3_clk), .*);
|
||||
rvdffe #(.WIDTH(DATA_WIDTH)) stbuf_fwddata_hi_dc3ff (.din(stbuf_fwddata_hi_fn_dc2[DATA_WIDTH-1:0]), .dout(stbuf_fwddata_hi_dc3[DATA_WIDTH-1:0]), .en(lsu_freeze_c1_dc3_clken), .*);
|
||||
rvdffe #(.WIDTH(DATA_WIDTH)) stbuf_fwddata_lo_dc3ff (.din(stbuf_fwddata_lo_fn_dc2[DATA_WIDTH-1:0]), .dout(stbuf_fwddata_lo_dc3[DATA_WIDTH-1:0]), .en(lsu_freeze_c1_dc3_clken), .*);
|
||||
|
||||
`ifdef ASSERT_ON
|
||||
|
||||
|
|
|
|||
|
|
@ -147,11 +147,11 @@ logic [TOTAL_INT-1:0] extintsrc_req_gw;
|
|||
assign gw_config_c1_clken = (addr_config_gw_base_match & (picm_wren_ff | picm_rden_ff)) | clk_override;
|
||||
|
||||
// C1 - 1 clock pulse for data
|
||||
rvclkhdr pic_addr_c1_cgc ( .en(pic_addr_c1_clken), .l1clk(pic_addr_c1_clk), .* );
|
||||
rvclkhdr pic_data_c1_cgc ( .en(pic_data_c1_clken), .l1clk(pic_data_c1_clk), .* );
|
||||
rvclkhdr pic_pri_c1_cgc ( .en(pic_pri_c1_clken), .l1clk(pic_pri_c1_clk), .* );
|
||||
rvclkhdr pic_int_c1_cgc ( .en(pic_int_c1_clken), .l1clk(pic_int_c1_clk), .* );
|
||||
rvclkhdr gw_config_c1_cgc ( .en(gw_config_c1_clken), .l1clk(gw_config_c1_clk), .* );
|
||||
rvoclkhdr pic_addr_c1_cgc ( .en(pic_addr_c1_clken), .l1clk(pic_addr_c1_clk), .* );
|
||||
rvoclkhdr pic_data_c1_cgc ( .en(pic_data_c1_clken), .l1clk(pic_data_c1_clk), .* );
|
||||
rvoclkhdr pic_pri_c1_cgc ( .en(pic_pri_c1_clken), .l1clk(pic_pri_c1_clk), .* );
|
||||
rvoclkhdr pic_int_c1_cgc ( .en(pic_int_c1_clken), .l1clk(pic_int_c1_clk), .* );
|
||||
rvoclkhdr gw_config_c1_cgc ( .en(gw_config_c1_clken), .l1clk(gw_config_c1_clk), .* );
|
||||
|
||||
// ------ end clock gating section ------------------------
|
||||
|
||||
|
|
|
|||
|
|
@ -957,10 +957,10 @@ module swerv
|
|||
trace_pkt_t trace_rv_trace_pkt;
|
||||
|
||||
|
||||
assign active_state = ~dec_pause_state_cg | dec_tlu_flush_lower_wb;
|
||||
assign active_state = ~dec_pause_state_cg | dec_tlu_flush_lower_wb | dec_tlu_misc_clk_override;
|
||||
|
||||
rvclkhdr free_cg ( .en(1'b1), .l1clk(free_clk), .* );
|
||||
rvclkhdr active_cg ( .en(active_state), .l1clk(active_clk), .* );
|
||||
rvoclkhdr free_cg ( .en(1'b1), .l1clk(free_clk), .* );
|
||||
rvoclkhdr active_cg ( .en(active_state), .l1clk(active_clk), .* );
|
||||
|
||||
|
||||
assign core_dbg_cmd_done = dma_dbg_cmd_done | dec_dbg_cmd_done;
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
@00001000
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 48
|
||||
65 6C 6C 6F 20 57 6F 72 6C 64 20 66 72 6F 6D 20
|
||||
53 77 65 52 56 20 40 57 44 43 20 21 21 0A 2D 2D
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 00
|
||||
@00001000
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 48
|
||||
65 6C 6C 6F 20 57 6F 72 6C 64 20 66 72 6F 6D 20
|
||||
53 77 65 52 56 20 40 57 44 43 20 21 21 0A 2D 2D
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 00
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
@00000000
|
||||
73 10 20 B0 73 10 20 B8 B7 00 00 EE 73 90 50 30
|
||||
B7 50 55 55 93 80 50 55 73 90 00 7C B7 01 58 D0
|
||||
17 12 00 00 13 02 02 FE 83 02 02 00 23 80 51 00
|
||||
05 02 E3 9B 02 FE B7 01 58 D0 93 02 F0 0F 23 80
|
||||
51 00 E3 0A 00 FE
|
||||
@00000000
|
||||
73 10 20 B0 73 10 20 B8 B7 00 00 EE 73 90 50 30
|
||||
B7 50 55 55 93 80 50 55 73 90 00 7C B7 01 58 D0
|
||||
17 12 00 00 13 02 02 FE 83 02 02 00 23 80 51 00
|
||||
05 02 E3 9B 02 FE B7 01 58 D0 93 02 F0 0F 23 80
|
||||
51 00 E3 0A 00 FE
|
||||
|
|
|
|||
|
|
@ -22,7 +22,6 @@ module tb_top ( input logic core_clk, input logic reset_l, output finished);
|
|||
`ifndef VERILATOR
|
||||
logic reset_l;
|
||||
logic core_clk;
|
||||
logic finished;
|
||||
`endif
|
||||
logic nmi_int;
|
||||
|
||||
|
|
@ -101,6 +100,7 @@ module tb_top ( input logic core_clk, input logic reset_l, output finished);
|
|||
|
||||
logic [31:0] cycleCnt ;
|
||||
logic mailbox_data_val;
|
||||
logic finished;
|
||||
|
||||
wire dma_hready_out;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue