From 0f3f246df567631a0900e789b3a4b6cb27adf07b Mon Sep 17 00:00:00 2001 From: Joseph Rahmeh Date: Fri, 12 Jul 2019 06:22:01 -0700 Subject: [PATCH] Remove spurious carriage return characters. --- design/dmi/dmi_jtag_to_core_sync.v | 130 ++++++++++----------- design/dmi/dmi_wrapper.v | 182 ++++++++++++++--------------- testbench/hex/data.hex | 14 +-- testbench/hex/program.hex | 12 +- 4 files changed, 169 insertions(+), 169 deletions(-) diff --git a/design/dmi/dmi_jtag_to_core_sync.v b/design/dmi/dmi_jtag_to_core_sync.v index aa4c19f..0a304fe 100644 --- a/design/dmi/dmi_jtag_to_core_sync.v +++ b/design/dmi/dmi_jtag_to_core_sync.v @@ -1,65 +1,65 @@ -// SPDX-License-Identifier: Apache-2.0 -// Copyright 2019 Western Digital Corporation or its affiliates. -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -//------------------------------------------------------------------------------------ -// This module Synchronizes the signals between JTAG (TCK) and -// processor (clk) -// -//------------------------------------------------------------------------------------- - -module dmi_jtag_to_core_sync ( - // JTAG signals - input rd_en, // 1 bit Read Enable - input wr_en, // 1 bit Write enable - - - // Processor Signals - input rst_n, // Core clock - input clk, // Core reset - - output reg_en, // 1 bit Write interface bit to Processor - output reg_wr_en // 1 bit Write enable to Processor -); - - - - wire c_rd_en; - wire c_wr_en; - - - //Assign statements - - assign reg_en = c_wr_en | c_rd_en; - assign reg_wr_en = c_wr_en; - - reg [2:0] rden, wren; - -// synchronizers -always @ ( posedge clk or negedge rst_n) begin - if(!rst_n) begin - rden <= '0; - wren <= '0; - end - else begin - rden <= {rden[1:0], rd_en}; - wren <= {wren[1:0], wr_en}; - end -end - -assign c_rd_en = rden[1] & ~rden[2]; -assign c_wr_en = wren[1] & ~wren[2]; - - - -endmodule +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2019 Western Digital Corporation or its affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//------------------------------------------------------------------------------------ +// This module Synchronizes the signals between JTAG (TCK) and +// processor (clk) +// +//------------------------------------------------------------------------------------- + +module dmi_jtag_to_core_sync ( + // JTAG signals + input rd_en, // 1 bit Read Enable + input wr_en, // 1 bit Write enable + + + // Processor Signals + input rst_n, // Core clock + input clk, // Core reset + + output reg_en, // 1 bit Write interface bit to Processor + output reg_wr_en // 1 bit Write enable to Processor +); + + + + wire c_rd_en; + wire c_wr_en; + + + //Assign statements + + assign reg_en = c_wr_en | c_rd_en; + assign reg_wr_en = c_wr_en; + + reg [2:0] rden, wren; + +// synchronizers +always @ ( posedge clk or negedge rst_n) begin + if(!rst_n) begin + rden <= '0; + wren <= '0; + end + else begin + rden <= {rden[1:0], rd_en}; + wren <= {wren[1:0], wr_en}; + end +end + +assign c_rd_en = rden[1] & ~rden[2]; +assign c_wr_en = wren[1] & ~wren[2]; + + + +endmodule diff --git a/design/dmi/dmi_wrapper.v b/design/dmi/dmi_wrapper.v index 01d29d6..93e682a 100644 --- a/design/dmi/dmi_wrapper.v +++ b/design/dmi/dmi_wrapper.v @@ -1,91 +1,91 @@ -// SPDX-License-Identifier: Apache-2.0 -// Copyright 2019 Western Digital Corporation or its affiliates. -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -//------------------------------------------------------------------------------------ -// -// Copyright Western Digital, 2019 -// Owner : Anusha Narayanamoorthy -// Description: -// Wrapper module for JTAG_TAP and DMI synchronizer -// -//------------------------------------------------------------------------------------- - -module dmi_wrapper( - input scan_mode, // scan mode - - // JTAG signals - input trst_n, // JTAG reset - input tck, // JTAG clock - input tms, // Test mode select - input tdi, // Test Data Input - output tdo, // Test Data Output - output tdoEnable, // Test Data Output enable - - // Processor Signals - input core_rst_n, // Core reset - input core_clk, // Core clock - input [31:1] jtag_id, // JTAG ID - input [31:0] rd_data, // 32 bit Read data from Processor - output [31:0] reg_wr_data, // 32 bit Write data to Processor - output [6:0] reg_wr_addr, // 7 bit reg address to Processor - output reg_en, // 1 bit Read enable to Processor - output reg_wr_en, // 1 bit Write enable to Processor - output dmi_hard_reset -); - - - - - - //Wire Declaration - wire rd_en; - wire wr_en; - wire dmireset; - - - //jtag_tap instantiation - rvjtag_tap i_jtag_tap( - .trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset - .tck(tck), // dedicated JTAG TCK pad signal - .tms(tms), // dedicated JTAG TMS pad signal - .tdi(tdi), // dedicated JTAG TDI pad signal - .tdo(tdo), // dedicated JTAG TDO pad signal - .tdoEnable(tdoEnable), // enable for TDO pad - .wr_data(reg_wr_data), // 32 bit Write data - .wr_addr(reg_wr_addr), // 7 bit Write address - .rd_en(rd_en), // 1 bit read enable - .wr_en(wr_en), // 1 bit Write enable - .rd_data(rd_data), // 32 bit Read data - .rd_status(2'b0), - .idle(3'h0), // no need to wait to sample data - .dmi_stat(2'b0), // no need to wait or error possible - .version(4'h1), // debug spec 0.13 compliant - .jtag_id(jtag_id), - .dmi_hard_reset(dmi_hard_reset), - .dmi_reset(dmireset) -); - - - // dmi_jtag_to_core_sync instantiation - dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync( - .wr_en(wr_en), // 1 bit Write enable - .rd_en(rd_en), // 1 bit Read enable - - .rst_n(core_rst_n), - .clk(core_clk), - .reg_en(reg_en), // 1 bit Write interface bit - .reg_wr_en(reg_wr_en) // 1 bit Write enable - ); - -endmodule +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2019 Western Digital Corporation or its affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//------------------------------------------------------------------------------------ +// +// Copyright Western Digital, 2019 +// Owner : Anusha Narayanamoorthy +// Description: +// Wrapper module for JTAG_TAP and DMI synchronizer +// +//------------------------------------------------------------------------------------- + +module dmi_wrapper( + input scan_mode, // scan mode + + // JTAG signals + input trst_n, // JTAG reset + input tck, // JTAG clock + input tms, // Test mode select + input tdi, // Test Data Input + output tdo, // Test Data Output + output tdoEnable, // Test Data Output enable + + // Processor Signals + input core_rst_n, // Core reset + input core_clk, // Core clock + input [31:1] jtag_id, // JTAG ID + input [31:0] rd_data, // 32 bit Read data from Processor + output [31:0] reg_wr_data, // 32 bit Write data to Processor + output [6:0] reg_wr_addr, // 7 bit reg address to Processor + output reg_en, // 1 bit Read enable to Processor + output reg_wr_en, // 1 bit Write enable to Processor + output dmi_hard_reset +); + + + + + + //Wire Declaration + wire rd_en; + wire wr_en; + wire dmireset; + + + //jtag_tap instantiation + rvjtag_tap i_jtag_tap( + .trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset + .tck(tck), // dedicated JTAG TCK pad signal + .tms(tms), // dedicated JTAG TMS pad signal + .tdi(tdi), // dedicated JTAG TDI pad signal + .tdo(tdo), // dedicated JTAG TDO pad signal + .tdoEnable(tdoEnable), // enable for TDO pad + .wr_data(reg_wr_data), // 32 bit Write data + .wr_addr(reg_wr_addr), // 7 bit Write address + .rd_en(rd_en), // 1 bit read enable + .wr_en(wr_en), // 1 bit Write enable + .rd_data(rd_data), // 32 bit Read data + .rd_status(2'b0), + .idle(3'h0), // no need to wait to sample data + .dmi_stat(2'b0), // no need to wait or error possible + .version(4'h1), // debug spec 0.13 compliant + .jtag_id(jtag_id), + .dmi_hard_reset(dmi_hard_reset), + .dmi_reset(dmireset) +); + + + // dmi_jtag_to_core_sync instantiation + dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync( + .wr_en(wr_en), // 1 bit Write enable + .rd_en(rd_en), // 1 bit Read enable + + .rst_n(core_rst_n), + .clk(core_clk), + .reg_en(reg_en), // 1 bit Write interface bit + .reg_wr_en(reg_wr_en) // 1 bit Write enable + ); + +endmodule diff --git a/testbench/hex/data.hex b/testbench/hex/data.hex index 6def292..4b541f7 100755 --- a/testbench/hex/data.hex +++ b/testbench/hex/data.hex @@ -1,7 +1,7 @@ -@00001000 -2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D -2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 48 -65 6C 6C 6F 20 57 6F 72 6C 64 20 66 72 6F 6D 20 -53 77 65 52 56 20 40 57 44 43 20 21 21 0A 2D 2D -2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D -2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 00 +@00001000 +2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D +2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 48 +65 6C 6C 6F 20 57 6F 72 6C 64 20 66 72 6F 6D 20 +53 77 65 52 56 20 40 57 44 43 20 21 21 0A 2D 2D +2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D +2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 00 diff --git a/testbench/hex/program.hex b/testbench/hex/program.hex index 9a70923..bae8723 100644 --- a/testbench/hex/program.hex +++ b/testbench/hex/program.hex @@ -1,6 +1,6 @@ -@00000000 -73 10 20 B0 73 10 20 B8 B7 00 00 EE 73 90 50 30 -B7 50 55 55 93 80 50 55 73 90 00 7C B7 01 58 D0 -17 12 00 00 13 02 02 FE 83 02 02 00 23 80 51 00 -05 02 E3 9B 02 FE B7 01 58 D0 93 02 F0 0F 23 80 -51 00 E3 0A 00 FE +@00000000 +73 10 20 B0 73 10 20 B8 B7 00 00 EE 73 90 50 30 +B7 50 55 55 93 80 50 55 73 90 00 7C B7 01 58 D0 +17 12 00 00 13 02 02 FE 83 02 02 00 23 80 51 00 +05 02 E3 9B 02 FE B7 01 58 D0 93 02 F0 0F 23 80 +51 00 E3 0A 00 FE