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1651bdf99a
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@ -48,8 +48,8 @@ module dmi_jtag_to_core_sync (
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// synchronizers
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// synchronizers
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always @ ( posedge clk or negedge rst_n) begin
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always @ ( posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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if(!rst_n) begin
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rden <= '0;
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rden <= 3'b0;
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wren <= '0;
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wren <= 3'b0;
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end
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end
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else begin
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else begin
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rden <= {rden[1:0], rd_en};
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rden <= {rden[1:0], rd_en};
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