From 189ce250276d29c4c7c470632533e8cb4b7472a2 Mon Sep 17 00:00:00 2001
From: jrahmeh <joe.rahmeh@gmail.com>
Date: Tue, 13 Aug 2019 16:42:26 -0500
Subject: [PATCH] Updated release notes

---
 release-notes.md | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/release-notes.md b/release-notes.md
index 10c5ebb..ae00118 100644
--- a/release-notes.md
+++ b/release-notes.md
@@ -4,13 +4,14 @@
     * The ebreak and ecall instructions are no longer counted in the MINSRET
 	  control and status register.
     * Write to SBDATA0 does not start SB write access when both
-	  sbreadonaddr/sbreadondata are zero.
+	  sbreadonaddr/sbreadondata are zero. This fixes issue number
+	  5 on github.
 
 1. FPGA support: Add fpga_optimize option to swerv.config which
    eliminates over 90% of clock-gating enabling faster FPGA
    simulation.
    
-1. Usability: Untabified all the verilog files.
+1. Usability: Untabified all the verilog files.  This fixes issue number 3 on github.
 
 # SweRV RISC-V Core<sup>TM</sup> 1.1 from Western Digital
 ## Release Notes