From 1cf98e765db36311580ce370ca407b6b5ce1792c Mon Sep 17 00:00:00 2001
From: Joseph Rahmeh <joseph.rahmeh@wdc.com>
Date: Thu, 8 Aug 2019 07:51:56 -0700
Subject: [PATCH] fix synthesis syntax in rvdffe in beh_lib.sv

---
 design/lib/beh_lib.sv | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/design/lib/beh_lib.sv b/design/lib/beh_lib.sv
index 2a6ddc1..f79aba7 100644
--- a/design/lib/beh_lib.sv
+++ b/design/lib/beh_lib.sv
@@ -144,9 +144,15 @@ module rvdffe #( parameter WIDTH=1 )
    logic 		      l1clk;
 
 `ifdef RV_FPGA_OPTIMIZE
+
+`ifndef PHYSICAL   
    begin: genblock
+`endif
      rvdffs #(WIDTH) dff ( .* );
+`ifndef PHYSICAL   
    end
+`endif
+
 `else
    
 `ifndef PHYSICAL