From 1d1237c223f1a7c94324961aa46c4fdaf6145a45 Mon Sep 17 00:00:00 2001 From: colin Date: Sat, 26 Feb 2022 15:14:43 +0000 Subject: [PATCH] Add VexRiscv fpga generation to ecp5. --- VexRiscv/Murax.v | 7 +- VexRiscv/fpga/gen/soc.json | 132958 +++++++++++++++++++++++++++++++++ VexRiscv/fpga/gen/synth.log | 9320 +++ VexRiscv/fpga/gen/synth.v | 14036 ++++ VexRiscv/fpga/gen/synth.ys | 5 + VexRiscv/fpga/soc.cfg | 67147 +++++++++++++++++ VexRiscv/fpga/soc.lpf | 38 + VexRiscv/fpga/synth.sh | 49 + 8 files changed, 223557 insertions(+), 3 deletions(-) create mode 100644 VexRiscv/fpga/gen/soc.json create mode 100644 VexRiscv/fpga/gen/synth.log create mode 100644 VexRiscv/fpga/gen/synth.v create mode 100644 VexRiscv/fpga/gen/synth.ys create mode 100644 VexRiscv/fpga/soc.cfg create mode 100644 VexRiscv/fpga/soc.lpf create mode 100755 VexRiscv/fpga/synth.sh diff --git a/VexRiscv/Murax.v b/VexRiscv/Murax.v index b88889c..f89e369 100644 --- a/VexRiscv/Murax.v +++ b/VexRiscv/Murax.v @@ -11,13 +11,14 @@ module Murax ( input io_jtag_tdi, output io_jtag_tdo, input io_jtag_tck, - input [31:0] io_gpioA_read, - output [31:0] io_gpioA_write, - output [31:0] io_gpioA_writeEnable, output io_uart_txd, input io_uart_rxd ); + reg [31:0] io_gpioA_read; + wire [31:0] io_gpioA_write; + wire [31:0] io_gpioA_writeEnable; + wire [7:0] system_cpu_debug_bus_cmd_payload_address; wire system_cpu_dBus_cmd_ready; reg system_ram_io_bus_cmd_valid; diff --git a/VexRiscv/fpga/gen/soc.json b/VexRiscv/fpga/gen/soc.json new file mode 100644 index 0000000..1356839 --- /dev/null +++ b/VexRiscv/fpga/gen/soc.json @@ -0,0 +1,132958 @@ +{ + "creator": "Yosys 0.13+28 (git sha1 fc40df091, gcc 11.2.0-7ubuntu2 -fPIC -Os)", + "modules": { + "\\$__ABC9_LUT5": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "abc9_lut": "00000000000000000000000000000010", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ecp5/cells_sim.v:22.1-30.10" + }, + "ports": { + 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"CH1_FF_TX_D_0": { + "direction": "input", + "bits": [ 19 ] + }, + "CH0_FF_TX_D_1": { + "direction": "input", + "bits": [ 20 ] + }, + "CH1_FF_TX_D_1": { + "direction": "input", + "bits": [ 21 ] + }, + "CH0_FF_TX_D_2": { + "direction": "input", + "bits": [ 22 ] + }, + "CH1_FF_TX_D_2": { + "direction": "input", + "bits": [ 23 ] + }, + "CH0_FF_TX_D_3": { + "direction": "input", + "bits": [ 24 ] + }, + "CH1_FF_TX_D_3": { + "direction": "input", + "bits": [ 25 ] + }, + "CH0_FF_TX_D_4": { + "direction": "input", + "bits": [ 26 ] + }, + "CH1_FF_TX_D_4": { + "direction": "input", + "bits": [ 27 ] + }, + "CH0_FF_TX_D_5": { + "direction": "input", + "bits": [ 28 ] + }, + "CH1_FF_TX_D_5": { + "direction": "input", + "bits": [ 29 ] + }, + "CH0_FF_TX_D_6": { + "direction": "input", + "bits": [ 30 ] + }, + "CH1_FF_TX_D_6": { + "direction": "input", + "bits": [ 31 ] + }, + "CH0_FF_TX_D_7": { + "direction": "input", + "bits": [ 32 ] + }, + "CH1_FF_TX_D_7": { + "direction": "input", + "bits": [ 33 ] + }, + "CH0_FF_TX_D_8": { + "direction": "input", + "bits": [ 34 ] + }, + "CH1_FF_TX_D_8": { + "direction": "input", + "bits": [ 35 ] + }, + "CH0_FF_TX_D_9": { + "direction": "input", + "bits": [ 36 ] + }, + "CH1_FF_TX_D_9": { + "direction": "input", + "bits": [ 37 ] + }, + "CH0_FF_TX_D_10": { + "direction": "input", + "bits": [ 38 ] + }, + "CH1_FF_TX_D_10": { + "direction": "input", + "bits": [ 39 ] + }, + "CH0_FF_TX_D_11": { + "direction": "input", + "bits": [ 40 ] + }, + "CH1_FF_TX_D_11": { + "direction": "input", + "bits": [ 41 ] + }, + "CH0_FF_TX_D_12": { + "direction": "input", + "bits": [ 42 ] + }, + "CH1_FF_TX_D_12": { + "direction": "input", + "bits": [ 43 ] + }, + "CH0_FF_TX_D_13": { + "direction": "input", + "bits": [ 44 ] + }, + "CH1_FF_TX_D_13": { + "direction": "input", + "bits": [ 45 ] + }, + "CH0_FF_TX_D_14": { + "direction": "input", + "bits": [ 46 ] + }, + "CH1_FF_TX_D_14": { + "direction": "input", + "bits": [ 47 ] + }, + "CH0_FF_TX_D_15": { + "direction": "input", + "bits": [ 48 ] + }, + "CH1_FF_TX_D_15": { + "direction": "input", + "bits": [ 49 ] + }, + "CH0_FF_TX_D_16": { + "direction": "input", + "bits": [ 50 ] + }, + "CH1_FF_TX_D_16": { + "direction": "input", + "bits": [ 51 ] + }, + "CH0_FF_TX_D_17": { + "direction": "input", + "bits": [ 52 ] + }, + "CH1_FF_TX_D_17": { + "direction": "input", + "bits": [ 53 ] + }, + "CH0_FF_TX_D_18": { + "direction": "input", + "bits": [ 54 ] + }, + "CH1_FF_TX_D_18": { + "direction": "input", + "bits": [ 55 ] + }, + "CH0_FF_TX_D_19": { + "direction": "input", + "bits": [ 56 ] + }, + "CH1_FF_TX_D_19": { + "direction": "input", + "bits": [ 57 ] + }, + "CH0_FF_TX_D_20": { + "direction": "input", + "bits": [ 58 ] + }, + "CH1_FF_TX_D_20": { + "direction": "input", + "bits": [ 59 ] + }, + "CH0_FF_TX_D_21": { + "direction": "input", + "bits": [ 60 ] + }, + "CH1_FF_TX_D_21": { + "direction": "input", + "bits": [ 61 ] + }, + "CH0_FF_TX_D_22": { + "direction": "input", + "bits": [ 62 ] + }, + "CH1_FF_TX_D_22": { + "direction": "input", + "bits": [ 63 ] + }, + "CH0_FF_TX_D_23": { + "direction": "input", + "bits": [ 64 ] + }, + "CH1_FF_TX_D_23": { + "direction": "input", + "bits": [ 65 ] + }, + "CH0_FFC_EI_EN": { + "direction": "input", + "bits": [ 66 ] + }, + "CH1_FFC_EI_EN": { + "direction": "input", + "bits": [ 67 ] + }, + "CH0_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 68 ] + }, + "CH1_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 69 ] + }, + "CH0_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 70 ] + }, + "CH1_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 71 ] + }, + "CH0_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 72 ] + }, + "CH1_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 73 ] + }, + "CH0_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 74 ] + }, + "CH1_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 75 ] + }, + "CH0_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 76 ] + }, + "CH1_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 77 ] + }, + "CH0_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 78 ] + }, + "CH1_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 79 ] + }, + "CH0_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 80 ] + }, + "CH1_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 81 ] + }, + "CH0_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 82 ] + }, + "CH1_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 83 ] + }, + "CH0_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 84 ] + }, + "CH1_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 85 ] + }, + "CH0_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 86 ] + }, + "CH1_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 87 ] + }, + "CH0_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 88 ] + }, + "CH1_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 89 ] + }, + "CH0_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 90 ] + }, + "CH1_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 91 ] + }, + "CH0_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 92 ] + }, + "CH1_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 93 ] + }, + "CH0_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 94 ] + }, + "CH1_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 95 ] + }, + "CH0_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 96 ] + }, + "CH1_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 97 ] + }, + "CH0_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 98 ] + }, + "CH1_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 99 ] + }, + "CH0_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 100 ] + }, + "CH1_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 101 ] + }, + "CH0_FFC_RRST": { + "direction": "input", + "bits": [ 102 ] + }, + "CH1_FFC_RRST": { + "direction": "input", + "bits": [ 103 ] + }, + "CH0_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 104 ] + }, + "CH1_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 105 ] + }, + "CH0_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 106 ] + }, + "CH1_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 107 ] + }, + "CH0_LDR_CORE2TX": { + "direction": "input", + "bits": [ 108 ] + }, + "CH1_LDR_CORE2TX": { + "direction": "input", + "bits": [ 109 ] + }, + "D_SCIWDATA0": { + "direction": "input", + "bits": [ 110 ] + }, + "D_SCIWDATA1": { + "direction": "input", + "bits": [ 111 ] + }, + "D_SCIWDATA2": { + "direction": "input", + "bits": [ 112 ] + }, + "D_SCIWDATA3": { + "direction": "input", + "bits": [ 113 ] + }, + "D_SCIWDATA4": { + "direction": "input", + "bits": [ 114 ] + }, + "D_SCIWDATA5": { + "direction": "input", + "bits": [ 115 ] + }, + "D_SCIWDATA6": { + "direction": "input", + "bits": [ 116 ] + }, + "D_SCIWDATA7": { + "direction": "input", + "bits": [ 117 ] + }, + "D_SCIADDR0": { + "direction": "input", + "bits": [ 118 ] + }, + "D_SCIADDR1": { + "direction": "input", + "bits": [ 119 ] + }, + "D_SCIADDR2": { + "direction": "input", + "bits": [ 120 ] + }, + "D_SCIADDR3": { + "direction": "input", + "bits": [ 121 ] + }, + "D_SCIADDR4": { + "direction": "input", + "bits": [ 122 ] + }, + "D_SCIADDR5": { + "direction": "input", + "bits": [ 123 ] + }, + "D_SCIENAUX": { + "direction": "input", + "bits": [ 124 ] + }, + "D_SCISELAUX": { + "direction": "input", + "bits": [ 125 ] + }, + "CH0_SCIEN": { + "direction": "input", + "bits": [ 126 ] + }, + "CH1_SCIEN": { + "direction": "input", + "bits": [ 127 ] + }, + "CH0_SCISEL": { + "direction": "input", + "bits": [ 128 ] + }, + "CH1_SCISEL": { + "direction": "input", + "bits": [ 129 ] + }, + "D_SCIRD": { + "direction": "input", + "bits": [ 130 ] + }, + "D_SCIWSTN": { + "direction": "input", + "bits": [ 131 ] + }, + "D_CYAWSTN": { + "direction": "input", + "bits": [ 132 ] + }, + "D_FFC_SYNC_TOGGLE": { + "direction": "input", + "bits": [ 133 ] + }, + "D_FFC_DUAL_RST": { + "direction": "input", + "bits": [ 134 ] + }, + "D_FFC_MACRO_RST": { + "direction": "input", + "bits": [ 135 ] + }, + "D_FFC_MACROPDB": { + "direction": "input", + "bits": [ 136 ] + }, + "D_FFC_TRST": { + "direction": "input", + "bits": [ 137 ] + }, + "CH0_FFC_CDR_EN_BITSLIP": { + "direction": "input", + "bits": [ 138 ] + }, + "CH1_FFC_CDR_EN_BITSLIP": { + "direction": "input", + "bits": [ 139 ] + }, + "D_SCAN_ENABLE": { + "direction": "input", + "bits": [ 140 ] + }, + "D_SCAN_IN_0": { + "direction": "input", + "bits": [ 141 ] + }, + "D_SCAN_IN_1": { + "direction": "input", + "bits": [ 142 ] + }, + "D_SCAN_IN_2": { + "direction": "input", + "bits": [ 143 ] + }, + "D_SCAN_IN_3": { + "direction": "input", + "bits": [ 144 ] + }, + "D_SCAN_IN_4": { + "direction": "input", + "bits": [ 145 ] + }, + "D_SCAN_IN_5": { + "direction": "input", + "bits": [ 146 ] + }, + "D_SCAN_IN_6": { + "direction": "input", + "bits": [ 147 ] + }, + "D_SCAN_IN_7": { + "direction": "input", + "bits": [ 148 ] + }, + "D_SCAN_MODE": { + "direction": "input", + "bits": [ 149 ] + }, + "D_SCAN_RESET": { + "direction": "input", + "bits": [ 150 ] + }, + "D_CIN0": { + "direction": "input", + "bits": [ 151 ] + }, + "D_CIN1": { + "direction": "input", + "bits": [ 152 ] + }, + "D_CIN2": { + "direction": "input", + "bits": [ 153 ] + }, + "D_CIN3": { + "direction": "input", + "bits": [ 154 ] + }, + "D_CIN4": { + "direction": "input", + "bits": [ 155 ] + }, + "D_CIN5": { + "direction": "input", + "bits": [ 156 ] + }, + "D_CIN6": { + "direction": "input", + "bits": [ 157 ] + }, + "D_CIN7": { + "direction": "input", + "bits": [ 158 ] + }, + "D_CIN8": { + "direction": "input", + "bits": [ 159 ] + }, + "D_CIN9": { + "direction": "input", + "bits": [ 160 ] + }, + "D_CIN10": { + "direction": "input", + "bits": [ 161 ] + }, + "D_CIN11": { + "direction": "input", + "bits": [ 162 ] + }, + "CH0_HDOUTP": { + "direction": "output", + "bits": [ 163 ] + }, + "CH1_HDOUTP": { + "direction": "output", + "bits": [ 164 ] + }, + "CH0_HDOUTN": { + "direction": "output", + "bits": [ 165 ] + }, + "CH1_HDOUTN": { + "direction": "output", + "bits": [ 166 ] + }, + "D_TXBIT_CLKP_TO_ND": { + "direction": "output", + "bits": [ 167 ] + }, + "D_TXBIT_CLKN_TO_ND": { + "direction": "output", + "bits": [ 168 ] + }, + "D_SYNC_PULSE2ND": { + "direction": "output", + "bits": [ 169 ] + }, + "D_TXPLL_LOL_TO_ND": { + "direction": "output", + "bits": [ 170 ] + }, + "CH0_FF_RX_F_CLK": { + "direction": "output", + "bits": [ 171 ] + }, + "CH1_FF_RX_F_CLK": { + "direction": "output", + "bits": [ 172 ] + }, + "CH0_FF_RX_H_CLK": { + "direction": "output", + "bits": [ 173 ] + }, + "CH1_FF_RX_H_CLK": { + "direction": "output", + "bits": [ 174 ] + }, + "CH0_FF_TX_F_CLK": { + "direction": "output", + "bits": [ 175 ] + }, + "CH1_FF_TX_F_CLK": { + "direction": "output", + "bits": [ 176 ] + }, + "CH0_FF_TX_H_CLK": { + "direction": "output", + "bits": [ 177 ] + }, + "CH1_FF_TX_H_CLK": { + "direction": "output", + "bits": [ 178 ] + }, + "CH0_FF_RX_PCLK": { + "direction": "output", + "bits": [ 179 ] + }, + "CH1_FF_RX_PCLK": { + "direction": "output", + "bits": [ 180 ] + }, + "CH0_FF_TX_PCLK": { + "direction": "output", + "bits": [ 181 ] + }, + "CH1_FF_TX_PCLK": { + "direction": "output", + "bits": [ 182 ] + }, + "CH0_FF_RX_D_0": { + "direction": "output", + "bits": [ 183 ] + }, + "CH1_FF_RX_D_0": { + "direction": "output", + "bits": [ 184 ] + }, + "CH0_FF_RX_D_1": { + "direction": "output", + "bits": [ 185 ] + }, + "CH1_FF_RX_D_1": { + "direction": "output", + "bits": [ 186 ] + }, + "CH0_FF_RX_D_2": { + "direction": "output", + "bits": [ 187 ] + }, + "CH1_FF_RX_D_2": { + "direction": "output", + "bits": [ 188 ] + }, + "CH0_FF_RX_D_3": { + "direction": "output", + "bits": [ 189 ] + }, + "CH1_FF_RX_D_3": { + "direction": "output", + "bits": [ 190 ] + }, + "CH0_FF_RX_D_4": { + "direction": "output", + "bits": [ 191 ] + }, + "CH1_FF_RX_D_4": { + "direction": "output", + "bits": [ 192 ] + }, + "CH0_FF_RX_D_5": { + "direction": "output", + "bits": [ 193 ] + }, + "CH1_FF_RX_D_5": { + "direction": "output", + "bits": [ 194 ] + }, + "CH0_FF_RX_D_6": { + "direction": "output", + "bits": [ 195 ] + }, + "CH1_FF_RX_D_6": { + "direction": "output", + "bits": [ 196 ] + }, + "CH0_FF_RX_D_7": { + "direction": "output", + "bits": [ 197 ] + }, + "CH1_FF_RX_D_7": { + "direction": "output", + "bits": [ 198 ] + }, + "CH0_FF_RX_D_8": { + "direction": "output", + "bits": [ 199 ] + }, + "CH1_FF_RX_D_8": { + "direction": "output", + "bits": [ 200 ] + }, + "CH0_FF_RX_D_9": { + "direction": "output", + "bits": [ 201 ] + }, + "CH1_FF_RX_D_9": { + "direction": "output", + "bits": [ 202 ] + }, + "CH0_FF_RX_D_10": { + "direction": "output", + "bits": [ 203 ] + }, + "CH1_FF_RX_D_10": { + "direction": "output", + "bits": [ 204 ] + }, + "CH0_FF_RX_D_11": { + "direction": "output", + "bits": [ 205 ] + }, + "CH1_FF_RX_D_11": { + "direction": "output", + "bits": [ 206 ] + }, + "CH0_FF_RX_D_12": { + "direction": "output", + "bits": [ 207 ] + }, + "CH1_FF_RX_D_12": { + "direction": "output", + "bits": [ 208 ] + }, + "CH0_FF_RX_D_13": { + "direction": "output", + "bits": [ 209 ] + }, + "CH1_FF_RX_D_13": { + "direction": "output", + "bits": [ 210 ] + }, + "CH0_FF_RX_D_14": { + "direction": "output", + "bits": [ 211 ] + }, + "CH1_FF_RX_D_14": { + "direction": "output", + "bits": [ 212 ] + }, + "CH0_FF_RX_D_15": { + "direction": "output", + "bits": [ 213 ] + }, + "CH1_FF_RX_D_15": { + "direction": "output", + "bits": [ 214 ] + }, + "CH0_FF_RX_D_16": { + "direction": "output", + "bits": [ 215 ] + }, + "CH1_FF_RX_D_16": { + "direction": "output", + "bits": [ 216 ] + }, + "CH0_FF_RX_D_17": { + "direction": "output", + "bits": [ 217 ] + }, + "CH1_FF_RX_D_17": { + "direction": "output", + "bits": [ 218 ] + }, + "CH0_FF_RX_D_18": { + "direction": "output", + "bits": [ 219 ] + }, + "CH1_FF_RX_D_18": { + "direction": "output", + "bits": [ 220 ] + }, + "CH0_FF_RX_D_19": { + "direction": "output", + "bits": [ 221 ] + }, + "CH1_FF_RX_D_19": { + "direction": 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"/usr/local/bin/../share/yosys/ecp5/cells_sim.v:445.9-445.13" + } + }, + "WDO1": { + "hide_name": 0, + "bits": [ 36 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ecp5/cells_sim.v:445.15-445.19" + } + }, + "WDO2": { + "hide_name": 0, + "bits": [ 37 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ecp5/cells_sim.v:445.21-445.25" + } + }, + "WDO3": { + "hide_name": 0, + "bits": [ 38 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ecp5/cells_sim.v:445.27-445.31" + } + }, + "WRE": { + "hide_name": 0, + "bits": [ 26 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ecp5/cells_sim.v:439.8-439.11" + } + } + } + }, + "TSHX2DQA": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ecp5/cells_bb.v:298.1-304.10" + }, + "parameter_default_values": { + "GSR": "ENABLED", + "REGSET": "SET" + }, + "ports": { + "T0": { + "direction": "input", + "bits": [ 2 ] + }, + "T1": { + "direction": "input", + "bits": [ 3 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 4 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 5 ] + }, + "DQSW270": { + "direction": "input", + "bits": [ 6 ] + }, + "RST": { + "direction": "input", + "bits": [ 7 ] + }, + "Q": { + "direction": "output", + "bits": [ 8 ] + } + }, + "cells": { + }, + "netnames": { + "DQSW270": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ecp5/cells_bb.v:299.28-299.35" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ecp5/cells_bb.v:299.22-299.26" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ecp5/cells_bb.v:300.9-300.10" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ecp5/cells_bb.v:299.37-299.40" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ecp5/cells_bb.v:299.16-299.20" + } + }, + "T0": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ecp5/cells_bb.v:299.8-299.10" + } + }, + "T1": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ecp5/cells_bb.v:299.12-299.14" + } + } + } + }, + "TSHX2DQSA": { + "attributes": { + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ecp5/cells_bb.v:307.1-313.10" + }, + "parameter_default_values": { + "GSR": "ENABLED", + "REGSET": "SET" + }, + "ports": { + "T0": { + "direction": "input", + "bits": [ 2 ] + }, + "T1": { + "direction": "input", + "bits": [ 3 ] + }, + "SCLK": { + "direction": "input", + "bits": [ 4 ] + }, + "ECLK": { + "direction": "input", + "bits": [ 5 ] + }, + "DQSW": { + "direction": "input", + "bits": [ 6 ] + }, + "RST": { + "direction": "input", + "bits": [ 7 ] + }, + "Q": { + "direction": "output", + "bits": [ 8 ] + } + }, + "cells": { + }, + "netnames": { + "DQSW": { + "hide_name": 0, + "bits": [ 6 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ecp5/cells_bb.v:308.28-308.32" + } + }, + "ECLK": { + "hide_name": 0, + "bits": [ 5 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ecp5/cells_bb.v:308.22-308.26" + } + }, + "Q": { + "hide_name": 0, + "bits": [ 8 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ecp5/cells_bb.v:309.9-309.10" + } + }, + "RST": { + "hide_name": 0, + "bits": [ 7 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ecp5/cells_bb.v:308.34-308.37" + } + }, + "SCLK": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ecp5/cells_bb.v:308.16-308.20" + } + }, + "T0": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ecp5/cells_bb.v:308.8-308.10" + } + }, + "T1": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ecp5/cells_bb.v:308.12-308.14" + } + } + } + }, + "USRMCLK": { + "attributes": { + "keep": "00000000000000000000000000000001", + "blackbox": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ecp5/cells_bb.v:182.1-186.10" + }, + "ports": { + "USRMCLKI": { + "direction": "input", + "bits": [ 2 ] + }, + "USRMCLKTS": { + "direction": "input", + "bits": [ 3 ] + }, + "USRMCLKO": { + "direction": "output", + "bits": [ 4 ] + } + }, + "cells": { + }, + "netnames": { + "USRMCLKI": { + "hide_name": 0, + "bits": [ 2 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ecp5/cells_bb.v:183.8-183.16" + } + }, + "USRMCLKO": { + "hide_name": 0, + "bits": [ 4 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ecp5/cells_bb.v:184.9-184.17" + } + }, + "USRMCLKTS": { + "hide_name": 0, + "bits": [ 3 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ecp5/cells_bb.v:183.18-183.27" + } + } + } + } + } +} diff --git a/VexRiscv/fpga/gen/synth.log b/VexRiscv/fpga/gen/synth.log new file mode 100644 index 0000000..d94bb6f --- /dev/null +++ b/VexRiscv/fpga/gen/synth.log @@ -0,0 +1,9320 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.13+28 (git sha1 fc40df091, gcc 11.2.0-7ubuntu2 -fPIC -Os) + + +-- Executing script file `gen/synth.ys' -- + +1. Executing Verilog-2005 frontend: ../Murax.v +Parsing Verilog input from `../Murax.v' to AST representation. +Generating RTLIL representation for module `\Murax'. +Generating RTLIL representation for module `\Apb3Router'. +Generating RTLIL representation for module `\Apb3Decoder'. +Generating RTLIL representation for module `\MuraxApb3Timer'. +Generating RTLIL representation for module `\Apb3UartCtrl'. +Generating RTLIL representation for module `\Apb3Gpio'. +Generating RTLIL representation for module `\PipelinedMemoryBusToApbBridge'. +Generating RTLIL representation for module `\MuraxPipelinedMemoryBusRam'. +Generating RTLIL representation for module `\SystemDebugger'. +Generating RTLIL representation for module `\JtagBridge'. +Generating RTLIL representation for module `\VexRiscv'. +Generating RTLIL representation for module `\MuraxMasterArbiter'. +Generating RTLIL representation for module `\BufferCC_3'. +Generating RTLIL representation for module `\InterruptCtrl'. +Generating RTLIL representation for module `\Timer'. +Generating RTLIL representation for module `\Prescaler'. +Generating RTLIL representation for module `\StreamFifo'. +Generating RTLIL representation for module `\UartCtrl'. +Generating RTLIL representation for module `\BufferCC_2'. +Generating RTLIL representation for module `\FlowCCByToggle'. +Generating RTLIL representation for module `\StreamFifoLowLatency'. +Generating RTLIL representation for module `\UartCtrlRx'. +Generating RTLIL representation for module `\UartCtrlTx'. +Generating RTLIL representation for module `\BufferCC_1'. +Generating RTLIL representation for module `\BufferCC'. +Successfully finished Verilog frontend. + +2. Executing HIERARCHY pass (managing design hierarchy). + +2.1. Analyzing design hierarchy.. +Top module: \Murax +Used module: \Apb3Router +Used module: \Apb3Decoder +Used module: \MuraxApb3Timer +Used module: \InterruptCtrl +Used module: \Timer +Used module: \Prescaler +Used module: \Apb3UartCtrl +Used module: \StreamFifo +Used module: \UartCtrl +Used module: \UartCtrlRx +Used module: \BufferCC +Used module: \UartCtrlTx +Used module: \Apb3Gpio +Used module: \BufferCC_2 +Used module: \PipelinedMemoryBusToApbBridge +Used module: \MuraxPipelinedMemoryBusRam +Used module: \SystemDebugger +Used module: \JtagBridge +Used module: \FlowCCByToggle +Used module: \BufferCC_1 +Used module: \VexRiscv +Used module: \StreamFifoLowLatency +Used module: \MuraxMasterArbiter +Used module: \BufferCC_3 + +2.2. Analyzing design hierarchy.. +Top module: \Murax +Used module: \Apb3Router +Used module: \Apb3Decoder +Used module: \MuraxApb3Timer +Used module: \InterruptCtrl +Used module: \Timer +Used module: \Prescaler +Used module: \Apb3UartCtrl +Used module: \StreamFifo +Used module: \UartCtrl +Used module: \UartCtrlRx +Used module: \BufferCC +Used module: \UartCtrlTx +Used module: \Apb3Gpio +Used module: \BufferCC_2 +Used module: \PipelinedMemoryBusToApbBridge +Used module: \MuraxPipelinedMemoryBusRam +Used module: \SystemDebugger +Used module: \JtagBridge +Used module: \FlowCCByToggle +Used module: \BufferCC_1 +Used module: \VexRiscv +Used module: \StreamFifoLowLatency +Used module: \MuraxMasterArbiter +Used module: \BufferCC_3 +Removed 0 unused modules. + +3. Executing SYNTH pass. + +3.1. Executing PROC pass (convert processes to netlists). + +3.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `FlowCCByToggle.$proc$../Murax.v:0$942'. +Removing empty process `JtagBridge.$proc$../Murax.v:0$263'. +Cleaned up 0 empty switches. + +3.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$../Murax.v:6826$1043 in module BufferCC. +Marked 3 switch rules as full_case in process $proc$../Murax.v:6714$1034 in module UartCtrlTx. +Marked 3 switch rules as full_case in process $proc$../Murax.v:6688$1027 in module UartCtrlTx. +Marked 1 switch rules as full_case in process $proc$../Murax.v:6669$1025 in module UartCtrlTx. +Marked 2 switch rules as full_case in process $proc$../Murax.v:6658$1023 in module UartCtrlTx. +Marked 1 switch rules as full_case in process $proc$../Murax.v:6648$1020 in module UartCtrlTx. +Marked 2 switch rules as full_case in process $proc$../Murax.v:6519$998 in module UartCtrlRx. +Marked 6 switch rules as full_case in process $proc$../Murax.v:6440$985 in module UartCtrlRx. +Marked 2 switch rules as full_case in process $proc$../Murax.v:6418$970 in module UartCtrlRx. +Marked 5 switch rules as full_case in process $proc$../Murax.v:6389$968 in module UartCtrlRx. +Marked 1 switch rules as full_case in process $proc$../Murax.v:6270$962 in module StreamFifoLowLatency. +Marked 1 switch rules as full_case in process $proc$../Murax.v:6259$959 in module StreamFifoLowLatency. +Marked 1 switch rules as full_case in process $proc$../Murax.v:6251$958 in module StreamFifoLowLatency. +Marked 1 switch rules as full_case in process $proc$../Murax.v:6243$957 in module StreamFifoLowLatency. +Marked 1 switch rules as full_case in process $proc$../Murax.v:6224$948 in module StreamFifoLowLatency. +Marked 1 switch rules as full_case in process $proc$../Murax.v:6217$947 in module StreamFifoLowLatency. +Marked 1 switch rules as full_case in process $proc$../Murax.v:6208$945 in module StreamFifoLowLatency. +Marked 1 switch rules as full_case in process $proc$../Murax.v:6201$944 in module StreamFifoLowLatency. +Marked 1 switch rules as full_case in process $proc$../Murax.v:6194$943 in module StreamFifoLowLatency. +Marked 1 switch rules as full_case in process $proc$../Murax.v:6145$941 in module FlowCCByToggle. +Marked 1 switch rules as full_case in process $proc$../Murax.v:6049$934 in module UartCtrl. +Marked 1 switch rules as full_case in process $proc$../Murax.v:6035$933 in module UartCtrl. +Marked 1 switch rules as full_case in process $proc$../Murax.v:6028$932 in module UartCtrl. +Marked 1 switch rules as full_case in process $proc$../Murax.v:5914$929 in module StreamFifo. +Marked 1 switch rules as full_case in process $proc$../Murax.v:5895$910 in module StreamFifo. +Marked 1 switch rules as full_case in process $proc$../Murax.v:5886$907 in module StreamFifo. +Marked 1 switch rules as full_case in process $proc$../Murax.v:5879$906 in module StreamFifo. +Marked 1 switch rules as full_case in process $proc$../Murax.v:5872$904 in module StreamFifo. +Marked 1 switch rules as full_case in process $proc$../Murax.v:5863$901 in module StreamFifo. +Marked 1 switch rules as full_case in process $proc$../Murax.v:5856$900 in module StreamFifo. +Marked 1 switch rules as full_case in process $proc$../Murax.v:5849$899 in module StreamFifo. +Marked 1 switch rules as full_case in process $proc$../Murax.v:5843$892 in module StreamFifo. +Marked 1 switch rules as full_case in process $proc$../Murax.v:5735$881 in module Timer. +Marked 1 switch rules as full_case in process $proc$../Murax.v:5701$872 in module InterruptCtrl. +Marked 1 switch rules as full_case in process $proc$../Murax.v:5653$869 in module MuraxMasterArbiter. +Marked 1 switch rules as full_case in process $proc$../Murax.v:5637$860 in module MuraxMasterArbiter. +Marked 1 switch rules as full_case in process $proc$../Murax.v:5630$857 in module MuraxMasterArbiter. +Marked 1 switch rules as full_case in process $proc$../Murax.v:5615$855 in module MuraxMasterArbiter. +Marked 1 switch rules as full_case in process $proc$../Murax.v:5605$851 in module MuraxMasterArbiter. +Marked 1 switch rules as full_case in process $proc$../Murax.v:5502$850 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:5018$829 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:5007$821 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4998$820 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4989$819 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4980$818 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4963$811 in module VexRiscv. +Marked 3 switch rules as full_case in process $proc$../Murax.v:4841$690 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4829$688 in module VexRiscv. +Marked 3 switch rules as full_case in process $proc$../Murax.v:4814$687 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4794$679 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4714$673 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4697$670 in module VexRiscv. +Marked 12 switch rules as full_case in process $proc$../Murax.v:4642$648 in module VexRiscv. +Marked 12 switch rules as full_case in process $proc$../Murax.v:4609$647 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4596$643 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4583$632 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4566$631 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4501$628 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4487$627 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4473$623 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4466$622 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4459$621 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4452$619 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4411$589 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4399$581 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4392$578 in module VexRiscv. +Marked 2 switch rules as full_case in process $proc$../Murax.v:4381$574 in module VexRiscv. +Marked 8 switch rules as full_case in process $proc$../Murax.v:4354$573 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4337$560 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4326$559 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4316$556 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4291$537 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4276$535 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4208$528 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4191$520 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4175$512 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4165$502 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4138$493 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4102$477 in module VexRiscv. +Marked 2 switch rules as full_case in process $proc$../Murax.v:4073$461 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4045$447 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4026$438 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4017$436 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:4007$431 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:3998$428 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:3987$424 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:3980$423 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:3973$422 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:3966$421 in module VexRiscv. +Marked 3 switch rules as full_case in process $proc$../Murax.v:3950$420 in module VexRiscv. +Marked 2 switch rules as full_case in process $proc$../Murax.v:3940$419 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:3933$418 in module VexRiscv. +Marked 2 switch rules as full_case in process $proc$../Murax.v:3920$417 in module VexRiscv. +Marked 6 switch rules as full_case in process $proc$../Murax.v:3899$416 in module VexRiscv. +Marked 2 switch rules as full_case in process $proc$../Murax.v:3885$415 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:3877$414 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:3868$413 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:3860$412 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:3852$411 in module VexRiscv. +Marked 2 switch rules as full_case in process $proc$../Murax.v:3843$410 in module VexRiscv. +Marked 2 switch rules as full_case in process $proc$../Murax.v:3834$409 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:3827$408 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:3820$407 in module VexRiscv. +Marked 5 switch rules as full_case in process $proc$../Murax.v:3803$406 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:3794$405 in module VexRiscv. +Marked 3 switch rules as full_case in process $proc$../Murax.v:3781$404 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:3770$403 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:3759$402 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:3741$401 in module VexRiscv. +Marked 2 switch rules as full_case in process $proc$../Murax.v:3724$400 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:3717$399 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:3709$397 in module VexRiscv. +Marked 1 switch rules as full_case in process $proc$../Murax.v:3102$374 in module VexRiscv. +Marked 3 switch rules as full_case in process $proc$../Murax.v:1995$235 in module JtagBridge. +Marked 2 switch rules as full_case in process $proc$../Murax.v:1977$234 in module JtagBridge. +Marked 1 switch rules as full_case in process $proc$../Murax.v:1923$217 in module JtagBridge. +Marked 1 switch rules as full_case in process $proc$../Murax.v:1718$213 in module SystemDebugger. +Marked 1 switch rules as full_case in process $proc$../Murax.v:1692$211 in module SystemDebugger. +Marked 1 switch rules as full_case in process $proc$../Murax.v:1633$198 in module MuraxPipelinedMemoryBusRam. +Marked 4 switch rules as full_case in process $proc$../Murax.v:1612$163 in module MuraxPipelinedMemoryBusRam. +Marked 2 switch rules as full_case in process $proc$../Murax.v:1534$151 in module PipelinedMemoryBusToApbBridge. +Marked 2 switch rules as full_case in process $proc$../Murax.v:1523$147 in module PipelinedMemoryBusToApbBridge. +Marked 2 switch rules as full_case in process $proc$../Murax.v:1509$145 in module PipelinedMemoryBusToApbBridge. +Marked 1 switch rules as full_case in process $proc$../Murax.v:1417$141 in module Apb3Gpio. +Marked 1 switch rules as full_case in process $proc$../Murax.v:1393$128 in module Apb3Gpio. +Marked 1 switch rules as full_case in process $proc$../Murax.v:1297$126 in module Apb3UartCtrl. +Marked 2 switch rules as full_case in process $proc$../Murax.v:1282$125 in module Apb3UartCtrl. +Marked 2 switch rules as full_case in process $proc$../Murax.v:1268$124 in module Apb3UartCtrl. +Marked 2 switch rules as full_case in process $proc$../Murax.v:1254$123 in module Apb3UartCtrl. +Marked 2 switch rules as full_case in process $proc$../Murax.v:1238$118 in module Apb3UartCtrl. +Marked 2 switch rules as full_case in process $proc$../Murax.v:1224$117 in module Apb3UartCtrl. +Marked 2 switch rules as full_case in process $proc$../Murax.v:1208$112 in module Apb3UartCtrl. +Marked 1 switch rules as full_case in process $proc$../Murax.v:1200$111 in module Apb3UartCtrl. +Marked 1 switch rules as full_case in process $proc$../Murax.v:1193$110 in module Apb3UartCtrl. +Marked 2 switch rules as full_case in process $proc$../Murax.v:1177$109 in module Apb3UartCtrl. +Marked 1 switch rules as full_case in process $proc$../Murax.v:1141$94 in module Apb3UartCtrl. +Marked 1 switch rules as full_case in process $proc$../Murax.v:920$90 in module MuraxApb3Timer. +Marked 2 switch rules as full_case in process $proc$../Murax.v:901$87 in module MuraxApb3Timer. +Marked 2 switch rules as full_case in process $proc$../Murax.v:886$81 in module MuraxApb3Timer. +Marked 2 switch rules as full_case in process $proc$../Murax.v:873$80 in module MuraxApb3Timer. +Marked 2 switch rules as full_case in process $proc$../Murax.v:863$79 in module MuraxApb3Timer. +Marked 2 switch rules as full_case in process $proc$../Murax.v:848$73 in module MuraxApb3Timer. +Marked 2 switch rules as full_case in process $proc$../Murax.v:835$72 in module MuraxApb3Timer. +Marked 2 switch rules as full_case in process $proc$../Murax.v:825$71 in module MuraxApb3Timer. +Marked 2 switch rules as full_case in process $proc$../Murax.v:812$70 in module MuraxApb3Timer. +Marked 1 switch rules as full_case in process $proc$../Murax.v:770$57 in module MuraxApb3Timer. +Marked 1 switch rules as full_case in process $proc$../Murax.v:679$54 in module Apb3Decoder. +Marked 1 switch rules as full_case in process $proc$../Murax.v:671$53 in module Apb3Decoder. +Marked 1 switch rules as full_case in process $proc$../Murax.v:593$41 in module Apb3Router. +Marked 1 switch rules as full_case in process $proc$../Murax.v:538$39 in module Murax. +Marked 1 switch rules as full_case in process $proc$../Murax.v:497$36 in module Murax. +Marked 1 switch rules as full_case in process $proc$../Murax.v:467$19 in module Murax. +Marked 1 switch rules as full_case in process $proc$../Murax.v:458$15 in module Murax. +Marked 1 switch rules as full_case in process $proc$../Murax.v:449$11 in module Murax. +Marked 1 switch rules as full_case in process $proc$../Murax.v:419$5 in module Murax. +Marked 1 switch rules as full_case in process $proc$../Murax.v:412$4 in module Murax. +Marked 1 switch rules as full_case in process $proc$../Murax.v:402$2 in module Murax. +Marked 1 switch rules as full_case in process $proc$../Murax.v:395$1 in module Murax. +Removed a total of 0 dead cases. + +3.1.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 28 redundant assignments. +Promoted 341 assignments to connections. + +3.1.4. Executing PROC_INIT pass (extract init attributes). +Found init rule in `\Murax.$proc$../Murax.v:0$40'. + Set init value: \resetCtrl_systemClkResetCounter = 6'000000 + +3.1.5. Executing PROC_ARST pass (detect async resets in processes). +Found async reset \resetCtrl_systemReset in `\BufferCC.$proc$../Murax.v:6826$1043'. +Found async reset \resetCtrl_systemReset in `\UartCtrlTx.$proc$../Murax.v:6714$1034'. +Found async reset \resetCtrl_systemReset in `\UartCtrlRx.$proc$../Murax.v:6440$985'. +Found async reset \resetCtrl_systemReset in `\StreamFifoLowLatency.$proc$../Murax.v:6270$962'. +Found async reset \resetCtrl_mainClkReset in `\FlowCCByToggle.$proc$../Murax.v:6145$941'. +Found async reset \resetCtrl_systemReset in `\UartCtrl.$proc$../Murax.v:6049$934'. +Found async reset \resetCtrl_systemReset in `\StreamFifo.$proc$../Murax.v:5914$929'. +Found async reset \resetCtrl_systemReset in `\Timer.$proc$../Murax.v:5735$881'. +Found async reset \resetCtrl_systemReset in `\InterruptCtrl.$proc$../Murax.v:5701$872'. +Found async reset \resetCtrl_systemReset in `\MuraxMasterArbiter.$proc$../Murax.v:5653$869'. +Found async reset \resetCtrl_mainClkReset in `\VexRiscv.$proc$../Murax.v:5502$850'. +Found async reset \resetCtrl_systemReset in `\VexRiscv.$proc$../Murax.v:5018$829'. +Found async reset \resetCtrl_mainClkReset in `\SystemDebugger.$proc$../Murax.v:1692$211'. +Found async reset \resetCtrl_systemReset in `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1633$198'. +Found async reset \resetCtrl_systemReset in `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1534$151'. +Found async reset \resetCtrl_systemReset in `\Apb3Gpio.$proc$../Murax.v:1417$141'. +Found async reset \resetCtrl_systemReset in `\Apb3UartCtrl.$proc$../Murax.v:1297$126'. +Found async reset \resetCtrl_systemReset in `\MuraxApb3Timer.$proc$../Murax.v:920$90'. +Found async reset \resetCtrl_mainClkReset in `\Murax.$proc$../Murax.v:538$39'. +Found async reset \resetCtrl_systemReset in `\Murax.$proc$../Murax.v:497$36'. + +3.1.6. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\BufferCC.$proc$../Murax.v:6826$1043'. + 1/2: $0\buffers_1[0:0] + 2/2: $0\buffers_0[0:0] +Creating decoders for process `\BufferCC_1.$proc$../Murax.v:6807$1042'. +Creating decoders for process `\UartCtrlTx.$proc$../Murax.v:6760$1038'. + 1/2: $0\tickCounter_value[2:0] + 2/2: $0\stateMachine_parity[0:0] +Creating decoders for process `\UartCtrlTx.$proc$../Murax.v:6714$1034'. + 1/3: $0\_zz_io_txd[0:0] + 2/3: $0\clockDivider_counter_value[2:0] + 3/3: $0\stateMachine_state[2:0] +Creating decoders for process `\UartCtrlTx.$proc$../Murax.v:6688$1027'. + 1/3: $3\io_write_ready[0:0] + 2/3: $2\io_write_ready[0:0] + 3/3: $1\io_write_ready[0:0] +Creating decoders for process `\UartCtrlTx.$proc$../Murax.v:6669$1025'. + 1/1: $1\stateMachine_txd[0:0] +Creating decoders for process `\UartCtrlTx.$proc$../Murax.v:6658$1023'. + 1/2: $2\clockDivider_counter_valueNext[2:0] + 2/2: $1\clockDivider_counter_valueNext[2:0] +Creating decoders for process `\UartCtrlTx.$proc$../Murax.v:6648$1020'. + 1/1: $1\clockDivider_counter_willIncrement[0:0] +Creating decoders for process `\UartCtrlRx.$proc$../Murax.v:6519$998'. + 1/9: $2$lookahead\stateMachine_shifter$997[7:0]$1011 + 2/9: $2$bitselwrite$data$../Murax.v:6546$965[7:0]$1010 + 3/9: $2$bitselwrite$mask$../Murax.v:6546$964[7:0]$1009 + 4/9: $1$lookahead\stateMachine_shifter$997[7:0]$1007 + 5/9: $1$bitselwrite$data$../Murax.v:6546$965[7:0]$1006 + 6/9: $1$bitselwrite$mask$../Murax.v:6546$964[7:0]$1005 + 7/9: $0\stateMachine_parity[0:0] + 8/9: $0\bitCounter_value[2:0] + 9/9: $0\bitTimer_counter[2:0] +Creating decoders for process `\UartCtrlRx.$proc$../Murax.v:6440$985'. + 1/8: $0\stateMachine_validReg[0:0] + 2/8: $0\sampler_tick[0:0] + 3/8: $0\sampler_value[0:0] + 4/8: $0\_zz_io_rts[0:0] + 5/8: $0\stateMachine_state[2:0] + 6/8: $0\break_counter[6:0] + 7/8: $0\sampler_samples_2[0:0] + 8/8: $0\sampler_samples_1[0:0] +Creating decoders for process `\UartCtrlRx.$proc$../Murax.v:6418$970'. + 1/2: $2\bitTimer_tick[0:0] + 2/2: $1\bitTimer_tick[0:0] +Creating decoders for process `\UartCtrlRx.$proc$../Murax.v:6389$968'. + 1/5: $5\io_error[0:0] + 2/5: $4\io_error[0:0] + 3/5: $3\io_error[0:0] + 4/5: $2\io_error[0:0] + 5/5: $1\io_error[0:0] +Creating decoders for process `\StreamFifoLowLatency.$proc$../Murax.v:6283$963'. + 1/1: $0\_zz_readed_error_2[32:0] +Creating decoders for process `\StreamFifoLowLatency.$proc$../Murax.v:6270$962'. + 1/1: $0\risingOccupancy[0:0] +Creating decoders for process `\StreamFifoLowLatency.$proc$../Murax.v:6259$959'. + 1/1: $1\io_pop_payload_inst[31:0] +Creating decoders for process `\StreamFifoLowLatency.$proc$../Murax.v:6251$958'. + 1/1: $1\io_pop_payload_error[0:0] +Creating decoders for process `\StreamFifoLowLatency.$proc$../Murax.v:6243$957'. + 1/1: $1\io_pop_valid[0:0] +Creating decoders for process `\StreamFifoLowLatency.$proc$../Murax.v:6224$948'. + 1/1: $1\popPtr_willClear[0:0] +Creating decoders for process `\StreamFifoLowLatency.$proc$../Murax.v:6217$947'. + 1/1: $1\popPtr_willIncrement[0:0] +Creating decoders for process `\StreamFifoLowLatency.$proc$../Murax.v:6208$945'. + 1/1: $1\pushPtr_willClear[0:0] +Creating decoders for process `\StreamFifoLowLatency.$proc$../Murax.v:6201$944'. + 1/1: $1\pushPtr_willIncrement[0:0] +Creating decoders for process `\StreamFifoLowLatency.$proc$../Murax.v:6194$943'. + 1/1: $1\when_Phase_l623[0:0] +Creating decoders for process `\FlowCCByToggle.$proc$../Murax.v:6145$941'. + 1/1: $0\outputArea_flow_m2sPipe_valid[0:0] +Creating decoders for process `\FlowCCByToggle.$proc$../Murax.v:6137$940'. + 1/2: $0\outputArea_flow_m2sPipe_payload_fragment[0:0] + 2/2: $0\outputArea_flow_m2sPipe_payload_last[0:0] +Creating decoders for process `\FlowCCByToggle.$proc$../Murax.v:6129$938'. + 1/3: $0\inputArea_data_fragment[0:0] + 2/3: $0\inputArea_data_last[0:0] + 3/3: $0\inputArea_target[0:0] +Creating decoders for process `\BufferCC_2.$proc$../Murax.v:6076$936'. +Creating decoders for process `\UartCtrl.$proc$../Murax.v:6049$934'. + 1/2: $0\clockDivider_counter[19:0] + 2/2: $0\clockDivider_tickReg[0:0] +Creating decoders for process `\UartCtrl.$proc$../Murax.v:6035$933'. + 1/1: $1\io_write_ready[0:0] +Creating decoders for process `\UartCtrl.$proc$../Murax.v:6028$932'. + 1/1: $1\io_write_thrown_valid[0:0] +Creating decoders for process `\StreamFifo.$proc$../Murax.v:5914$929'. + 1/4: $0\_zz_io_pop_valid[0:0] + 2/4: $0\logic_popPtr_value[3:0] + 3/4: $0\logic_pushPtr_value[3:0] + 4/4: $0\logic_risingOccupancy[0:0] +Creating decoders for process `\StreamFifo.$proc$../Murax.v:5895$910'. + 1/1: $1\logic_popPtr_valueNext[3:0] +Creating decoders for process `\StreamFifo.$proc$../Murax.v:5886$907'. + 1/1: $1\logic_popPtr_willClear[0:0] +Creating decoders for process `\StreamFifo.$proc$../Murax.v:5879$906'. + 1/1: $1\logic_popPtr_willIncrement[0:0] +Creating decoders for process `\StreamFifo.$proc$../Murax.v:5872$904'. + 1/1: $1\logic_pushPtr_valueNext[3:0] +Creating decoders for process `\StreamFifo.$proc$../Murax.v:5863$901'. + 1/1: $1\logic_pushPtr_willClear[0:0] +Creating decoders for process `\StreamFifo.$proc$../Murax.v:5856$900'. + 1/1: $1\logic_pushPtr_willIncrement[0:0] +Creating decoders for process `\StreamFifo.$proc$../Murax.v:5849$899'. + 1/1: $1\_zz_1[0:0] +Creating decoders for process `\StreamFifo.$proc$../Murax.v:5843$892'. + 1/3: $1$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$898 + 2/3: $1$memwr$\logic_ram$../Murax.v:5845$888_DATA[7:0]$897 + 3/3: $1$memwr$\logic_ram$../Murax.v:5845$888_ADDR[3:0]$896 +Creating decoders for process `\StreamFifo.$proc$../Murax.v:5837$890'. + 1/1: $0\_zz_logic_ram_port0[7:0] +Creating decoders for process `\Prescaler.$proc$../Murax.v:5773$886'. + 1/1: $0\counter[15:0] +Creating decoders for process `\Timer.$proc$../Murax.v:5748$882'. + 1/1: $0\counter[15:0] +Creating decoders for process `\Timer.$proc$../Murax.v:5735$881'. + 1/1: $0\inhibitFull[0:0] +Creating decoders for process `\InterruptCtrl.$proc$../Murax.v:5701$872'. + 1/1: $0\pendings[1:0] +Creating decoders for process `\BufferCC_3.$proc$../Murax.v:5681$870'. +Creating decoders for process `\MuraxMasterArbiter.$proc$../Murax.v:5653$869'. + 1/2: $0\rspTarget[0:0] + 2/2: $0\rspPending[0:0] +Creating decoders for process `\MuraxMasterArbiter.$proc$../Murax.v:5637$860'. + 1/1: $1\io_dBus_cmd_ready[0:0] +Creating decoders for process `\MuraxMasterArbiter.$proc$../Murax.v:5630$857'. + 1/1: $1\io_iBus_cmd_ready[0:0] +Creating decoders for process `\MuraxMasterArbiter.$proc$../Murax.v:5615$855'. + 1/1: $1\_zz_io_masterBus_cmd_payload_mask[3:0] +Creating decoders for process `\MuraxMasterArbiter.$proc$../Murax.v:5605$851'. + 1/1: $1\io_masterBus_cmd_valid[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:5502$850'. + 1/7: $0\DebugPlugin_disableEbreak[0:0] + 2/7: $0\DebugPlugin_debugUsed[0:0] + 3/7: $0\DebugPlugin_haltedByBreak[0:0] + 4/7: $0\DebugPlugin_godmode[0:0] + 5/7: $0\DebugPlugin_stepIt[0:0] + 6/7: $0\DebugPlugin_haltIt[0:0] + 7/7: $0\DebugPlugin_resetIt[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:5485$847'. + 1/2: $0\DebugPlugin_firstCycle[0:0] + 2/2: $0\DebugPlugin_busReadDataReg[31:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:5280$840'. + 1/62: $0\CsrPlugin_mip_MSIP[0:0] + 2/62: $0\execute_CsrPlugin_csr_834[0:0] + 3/62: $0\execute_CsrPlugin_csr_772[0:0] + 4/62: $0\execute_CsrPlugin_csr_836[0:0] + 5/62: $0\execute_CsrPlugin_csr_768[0:0] + 6/62: $0\memory_to_writeBack_MEMORY_READ_DATA[31:0] + 7/62: $0\execute_to_memory_BRANCH_CALC[31:0] + 8/62: $0\execute_to_memory_BRANCH_DO[0:0] + 9/62: $0\memory_to_writeBack_REGFILE_WRITE_DATA[31:0] + 10/62: $0\execute_to_memory_REGFILE_WRITE_DATA[31:0] + 11/62: $0\memory_to_writeBack_MEMORY_ADDRESS_LOW[1:0] + 12/62: $0\execute_to_memory_MEMORY_ADDRESS_LOW[1:0] + 13/62: $0\decode_to_execute_DO_EBREAK[0:0] + 14/62: $0\decode_to_execute_SRC2[31:0] + 15/62: $0\decode_to_execute_SRC1[31:0] + 16/62: $0\decode_to_execute_SRC2_FORCE_ZERO[0:0] + 17/62: $0\decode_to_execute_RS2[31:0] + 18/62: $0\decode_to_execute_RS1[31:0] + 19/62: $0\decode_to_execute_BRANCH_CTRL[1:0] + 20/62: $0\decode_to_execute_SHIFT_CTRL[1:0] + 21/62: $0\decode_to_execute_ALU_BITWISE_CTRL[1:0] + 22/62: $0\decode_to_execute_SRC_LESS_UNSIGNED[0:0] + 23/62: $0\decode_to_execute_ALU_CTRL[1:0] + 24/62: $0\memory_to_writeBack_ENV_CTRL[0:0] + 25/62: $0\execute_to_memory_ENV_CTRL[0:0] + 26/62: $0\decode_to_execute_ENV_CTRL[0:0] + 27/62: $0\decode_to_execute_IS_CSR[0:0] + 28/62: $0\execute_to_memory_MEMORY_STORE[0:0] + 29/62: $0\decode_to_execute_MEMORY_STORE[0:0] + 30/62: $0\execute_to_memory_BYPASSABLE_MEMORY_STAGE[0:0] + 31/62: $0\decode_to_execute_BYPASSABLE_MEMORY_STAGE[0:0] + 32/62: $0\decode_to_execute_BYPASSABLE_EXECUTE_STAGE[0:0] + 33/62: $0\memory_to_writeBack_REGFILE_WRITE_VALID[0:0] + 34/62: $0\execute_to_memory_REGFILE_WRITE_VALID[0:0] + 35/62: $0\decode_to_execute_REGFILE_WRITE_VALID[0:0] + 36/62: $0\memory_to_writeBack_MEMORY_ENABLE[0:0] + 37/62: $0\execute_to_memory_MEMORY_ENABLE[0:0] + 38/62: $0\decode_to_execute_MEMORY_ENABLE[0:0] + 39/62: $0\decode_to_execute_SRC_USE_SUB_LESS[0:0] + 40/62: $0\decode_to_execute_CSR_READ_OPCODE[0:0] + 41/62: $0\decode_to_execute_CSR_WRITE_OPCODE[0:0] + 42/62: $0\memory_to_writeBack_FORMAL_PC_NEXT[31:0] + 43/62: $0\execute_to_memory_FORMAL_PC_NEXT[31:0] + 44/62: $0\decode_to_execute_FORMAL_PC_NEXT[31:0] + 45/62: $0\memory_to_writeBack_INSTRUCTION[31:0] + 46/62: $0\execute_to_memory_INSTRUCTION[31:0] + 47/62: $0\decode_to_execute_INSTRUCTION[31:0] + 48/62: $0\memory_to_writeBack_PC[31:0] + 49/62: $0\execute_to_memory_PC[31:0] + 50/62: $0\decode_to_execute_PC[31:0] + 51/62: $0\execute_LightShifterPlugin_amplitudeReg[4:0] + 52/62: $0\CsrPlugin_interrupt_targetPrivilege[1:0] + 53/62: $0\CsrPlugin_interrupt_code[3:0] + 54/62: $0\CsrPlugin_mcause_exceptionCode[3:0] + 55/62: $0\CsrPlugin_mcause_interrupt[0:0] + 56/62: $0\CsrPlugin_mepc[31:0] + 57/62: $0\IBusSimplePlugin_injector_formal_rawInDecode[31:0] + 58/62: $0\_zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc[0:0] + 59/62: $0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0] + 60/62: $0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error[0:0] + 61/62: $0\_zz_IBusSimplePlugin_injector_decodeInput_payload_pc[31:0] + 62/62: $0\_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload[31:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:5018$829'. + 1/36: $0\HazardSimplePlugin_writeBackBuffer_valid[0:0] + 2/36: $0\_zz_2[0:0] + 3/36: $0\execute_CsrPlugin_wfiWake[0:0] + 4/36: $0\CsrPlugin_hadException[0:0] + 5/36: $0\CsrPlugin_interrupt_valid[0:0] + 6/36: $0\CsrPlugin_mcycle[63:0] + 7/36: $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0] + 8/36: $0\IBusSimplePlugin_pending_value[2:0] + 9/36: $0\IBusSimplePlugin_fetchPc_booted[0:0] + 10/36: $0\switch_Fetcher_l362[2:0] + 11/36: $0\execute_LightShifterPlugin_isActive[0:0] + 12/36: $0\CsrPlugin_pipelineLiberator_pcValids_2[0:0] + 13/36: $0\CsrPlugin_pipelineLiberator_pcValids_1[0:0] + 14/36: $0\CsrPlugin_pipelineLiberator_pcValids_0[0:0] + 15/36: $0\CsrPlugin_minstret[63:0] + 16/36: $0\CsrPlugin_mie_MSIE[0:0] + 17/36: $0\CsrPlugin_mie_MTIE[0:0] + 18/36: $0\CsrPlugin_mie_MEIE[0:0] + 19/36: $0\CsrPlugin_mstatus_MPP[1:0] + 20/36: $0\CsrPlugin_mstatus_MPIE[0:0] + 21/36: $0\CsrPlugin_mstatus_MIE[0:0] + 22/36: $0\IBusSimplePlugin_injector_nextPcCalc_valids_5[0:0] + 23/36: $0\IBusSimplePlugin_injector_nextPcCalc_valids_4[0:0] + 24/36: $0\IBusSimplePlugin_injector_nextPcCalc_valids_3[0:0] + 25/36: $0\IBusSimplePlugin_injector_nextPcCalc_valids_2[0:0] + 26/36: $0\IBusSimplePlugin_injector_nextPcCalc_valids_1[0:0] + 27/36: $0\IBusSimplePlugin_injector_nextPcCalc_valids_0[0:0] + 28/36: $0\_zz_IBusSimplePlugin_injector_decodeInput_valid[0:0] + 29/36: $0\_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid[0:0] + 30/36: $0\_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2[0:0] + 31/36: $0\IBusSimplePlugin_fetchPc_inc[0:0] + 32/36: $0\IBusSimplePlugin_fetchPc_correctionReg[0:0] + 33/36: $0\IBusSimplePlugin_fetchPc_pcReg[31:0] + 34/36: $0\writeBack_arbitration_isValid[0:0] + 35/36: $0\memory_arbitration_isValid[0:0] + 36/36: $0\execute_arbitration_isValid[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:5007$821'. + 1/2: $1\_zz_CsrPlugin_csrMapping_readDataInit_3[3:0] + 2/2: $2\_zz_CsrPlugin_csrMapping_readDataInit_3[31:31] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4998$820'. + 1/3: $1\_zz_CsrPlugin_csrMapping_readDataInit_2[3:3] + 2/3: $2\_zz_CsrPlugin_csrMapping_readDataInit_2[7:7] + 3/3: $3\_zz_CsrPlugin_csrMapping_readDataInit_2[11:11] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4989$819'. + 1/3: $1\_zz_CsrPlugin_csrMapping_readDataInit_1[3:3] + 2/3: $2\_zz_CsrPlugin_csrMapping_readDataInit_1[7:7] + 3/3: $3\_zz_CsrPlugin_csrMapping_readDataInit_1[11:11] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4980$818'. + 1/3: $1\_zz_CsrPlugin_csrMapping_readDataInit[3:3] + 2/3: $2\_zz_CsrPlugin_csrMapping_readDataInit[7:7] + 3/3: $3\_zz_CsrPlugin_csrMapping_readDataInit[12:11] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4963$811'. + 1/1: $1\IBusSimplePlugin_injectionPort_ready[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4841$690'. + 1/3: $3\IBusSimplePlugin_injectionPort_valid[0:0] + 2/3: $2\IBusSimplePlugin_injectionPort_valid[0:0] + 3/3: $1\IBusSimplePlugin_injectionPort_valid[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4829$688'. + 1/5: $1\debug_bus_rsp_data[4:0] [4] + 2/5: $1\debug_bus_rsp_data[4:0] [2] + 3/5: $1\debug_bus_rsp_data[4:0] [1] + 4/5: $1\debug_bus_rsp_data[4:0] [0] + 5/5: $1\debug_bus_rsp_data[4:0] [3] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4814$687'. + 1/3: $3\debug_bus_cmd_ready[0:0] + 2/3: $2\debug_bus_cmd_ready[0:0] + 3/3: $1\debug_bus_cmd_ready[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4794$679'. + 1/1: $1\_zz_execute_BranchPlugin_branch_src2_6[31:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4772$678'. +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4748$677'. +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4733$676'. +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4714$673'. + 1/1: $1\_zz_execute_BRANCH_DO_1[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4697$670'. + 1/1: $1\_zz_execute_BRANCH_DO[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4642$648'. + 1/12: $12\HazardSimplePlugin_src1Hazard[0:0] + 2/12: $11\HazardSimplePlugin_src1Hazard[0:0] + 3/12: $10\HazardSimplePlugin_src1Hazard[0:0] + 4/12: $9\HazardSimplePlugin_src1Hazard[0:0] + 5/12: $8\HazardSimplePlugin_src1Hazard[0:0] + 6/12: $7\HazardSimplePlugin_src1Hazard[0:0] + 7/12: $6\HazardSimplePlugin_src1Hazard[0:0] + 8/12: $5\HazardSimplePlugin_src1Hazard[0:0] + 9/12: $4\HazardSimplePlugin_src1Hazard[0:0] + 10/12: $3\HazardSimplePlugin_src1Hazard[0:0] + 11/12: $2\HazardSimplePlugin_src1Hazard[0:0] + 12/12: $1\HazardSimplePlugin_src1Hazard[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4609$647'. + 1/12: $12\HazardSimplePlugin_src0Hazard[0:0] + 2/12: $11\HazardSimplePlugin_src0Hazard[0:0] + 3/12: $10\HazardSimplePlugin_src0Hazard[0:0] + 4/12: $9\HazardSimplePlugin_src0Hazard[0:0] + 5/12: $8\HazardSimplePlugin_src0Hazard[0:0] + 6/12: $7\HazardSimplePlugin_src0Hazard[0:0] + 7/12: $6\HazardSimplePlugin_src0Hazard[0:0] + 8/12: $5\HazardSimplePlugin_src0Hazard[0:0] + 9/12: $4\HazardSimplePlugin_src0Hazard[0:0] + 10/12: $3\HazardSimplePlugin_src0Hazard[0:0] + 11/12: $2\HazardSimplePlugin_src0Hazard[0:0] + 12/12: $1\HazardSimplePlugin_src0Hazard[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4596$643'. + 1/1: $1\_zz_execute_to_memory_REGFILE_WRITE_DATA_1[31:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4583$632'. + 1/1: $1\execute_SrcPlugin_addSub[31:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4566$631'. + 1/1: $1\_zz_decode_SRC2_6[31:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4543$630'. +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4519$629'. +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4501$628'. + 1/1: $1\_zz_decode_SRC1_1[31:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4487$627'. + 1/1: $1\_zz_execute_REGFILE_WRITE_DATA[31:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4473$623'. + 1/1: $1\execute_IntAluPlugin_bitwise[31:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4466$622'. + 1/1: $1\lastStageRegFileWrite_payload_data[31:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4459$621'. + 1/1: $1\lastStageRegFileWrite_payload_address[4:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4452$619'. + 1/1: $1\lastStageRegFileWrite_valid[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4411$589'. + 1/1: $1\_zz_CsrPlugin_csrMapping_writeDataSignal[31:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4399$581'. + 1/1: $1\execute_CsrPlugin_readInstruction[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4392$578'. + 1/1: $1\execute_CsrPlugin_writeInstruction[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4381$574'. + 1/2: $2\execute_CsrPlugin_illegalInstruction[0:0] + 2/2: $1\execute_CsrPlugin_illegalInstruction[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4354$573'. + 1/8: $8\execute_CsrPlugin_illegalAccess[0:0] + 2/8: $7\execute_CsrPlugin_illegalAccess[0:0] + 3/8: $6\execute_CsrPlugin_illegalAccess[0:0] + 4/8: $5\execute_CsrPlugin_illegalAccess[0:0] + 5/8: $4\execute_CsrPlugin_illegalAccess[0:0] + 6/8: $3\execute_CsrPlugin_illegalAccess[0:0] + 7/8: $2\execute_CsrPlugin_illegalAccess[0:0] + 8/8: $1\execute_CsrPlugin_illegalAccess[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4337$560'. + 1/1: $1\CsrPlugin_xtvec_base[29:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4326$559'. + 1/1: $1\CsrPlugin_xtvec_mode[1:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4316$556'. + 1/1: $1\CsrPlugin_pipelineLiberator_done[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4291$537'. + 1/1: $1\CsrPlugin_privilege[1:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4276$535'. + 1/1: $1\writeBack_DBusSimplePlugin_rspFormated[31:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4256$534'. +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4227$531'. +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4208$528'. + 1/2: $1\writeBack_DBusSimplePlugin_rspShifted[15:0] [15:8] + 2/2: $1\writeBack_DBusSimplePlugin_rspShifted[15:0] [7:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4191$520'. + 1/1: $1\_zz_execute_DBusSimplePlugin_formalMask[3:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4175$512'. + 1/1: $1\_zz_dBus_cmd_payload_data[31:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4165$502'. + 1/1: $1\execute_DBusSimplePlugin_skipCmd[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4138$493'. + 1/1: $1\IBusSimplePlugin_rspJoin_fetchRsp_rsp_error[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4102$477'. + 1/1: $1\decode_arbitration_isValid[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4073$461'. + 1/2: $2\IBusSimplePlugin_iBusRsp_readyForError[0:0] + 2/2: $1\IBusSimplePlugin_iBusRsp_readyForError[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4045$447'. + 1/1: $1\IBusSimplePlugin_iBusRsp_stages_1_halt[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4026$438'. + 1/1: $1\IBusSimplePlugin_fetchPc_flushed[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4017$436'. + 1/1: $1\IBusSimplePlugin_fetchPc_pc[31:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:4007$431'. + 1/1: $1\IBusSimplePlugin_fetchPc_pcRegPropagate[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3998$428'. + 1/1: $1\IBusSimplePlugin_fetchPc_correction[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3987$424'. + 1/1: $1\CsrPlugin_allowEbreakException[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3980$423'. + 1/1: $1\CsrPlugin_allowException[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3973$422'. + 1/1: $1\CsrPlugin_allowInterrupts[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3966$421'. + 1/1: $1\CsrPlugin_forceMachineWire[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3950$420'. + 1/3: $3\CsrPlugin_jumpInterface_payload[31:0] + 2/3: $2\CsrPlugin_jumpInterface_payload[31:0] + 3/3: $1\CsrPlugin_jumpInterface_payload[31:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3940$419'. + 1/2: $2\CsrPlugin_jumpInterface_valid[0:0] + 2/2: $1\CsrPlugin_jumpInterface_valid[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3933$418'. + 1/1: $1\CsrPlugin_thirdPartyWake[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3920$417'. + 1/2: $2\IBusSimplePlugin_incomingInstruction[0:0] + 2/2: $1\IBusSimplePlugin_incomingInstruction[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3899$416'. + 1/6: $6\IBusSimplePlugin_fetcherHalt[0:0] + 2/6: $5\IBusSimplePlugin_fetcherHalt[0:0] + 3/6: $4\IBusSimplePlugin_fetcherHalt[0:0] + 4/6: $3\IBusSimplePlugin_fetcherHalt[0:0] + 5/6: $2\IBusSimplePlugin_fetcherHalt[0:0] + 6/6: $1\IBusSimplePlugin_fetcherHalt[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3885$415'. + 1/2: $2\writeBack_arbitration_flushNext[0:0] + 2/2: $1\writeBack_arbitration_flushNext[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3877$414'. + 1/1: $1\writeBack_arbitration_removeIt[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3868$413'. + 1/1: $1\memory_arbitration_flushNext[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3860$412'. + 1/1: $1\memory_arbitration_removeIt[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3852$411'. + 1/1: $1\memory_arbitration_haltItself[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3843$410'. + 1/2: $2\execute_arbitration_flushNext[0:0] + 2/2: $1\execute_arbitration_flushNext[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3834$409'. + 1/2: $2\execute_arbitration_flushIt[0:0] + 2/2: $1\execute_arbitration_flushIt[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3827$408'. + 1/1: $1\execute_arbitration_removeIt[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3820$407'. + 1/1: $1\execute_arbitration_haltByOther[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3803$406'. + 1/5: $5\execute_arbitration_haltItself[0:0] + 2/5: $4\execute_arbitration_haltItself[0:0] + 3/5: $3\execute_arbitration_haltItself[0:0] + 4/5: $2\execute_arbitration_haltItself[0:0] + 5/5: $1\execute_arbitration_haltItself[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3794$405'. + 1/1: $1\decode_arbitration_removeIt[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3781$404'. + 1/3: $3\decode_arbitration_haltByOther[0:0] + 2/3: $2\decode_arbitration_haltByOther[0:0] + 3/3: $1\decode_arbitration_haltByOther[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3770$403'. + 1/1: $1\decode_arbitration_haltItself[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3759$402'. + 1/1: $1\_zz_memory_to_writeBack_FORMAL_PC_NEXT[31:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3741$401'. + 1/1: $1\_zz_lastStageRegFileWrite_payload_data[31:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3724$400'. + 1/2: $2\_zz_execute_to_memory_REGFILE_WRITE_DATA[31:0] + 2/2: $1\_zz_execute_to_memory_REGFILE_WRITE_DATA[31:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3717$399'. + 1/1: $1\decode_REGFILE_WRITE_VALID[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3709$397'. + 1/1: $1\_zz_1[0:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3102$374'. + 1/3: $1$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$380 + 2/3: $1$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_DATA[31:0]$379 + 3/3: $1$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_ADDR[4:0]$378 +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3096$372'. + 1/1: $0\_zz_RegFilePlugin_regFile_port1[31:0] +Creating decoders for process `\VexRiscv.$proc$../Murax.v:3090$370'. + 1/1: $0\_zz_RegFilePlugin_regFile_port0[31:0] +Creating decoders for process `\JtagBridge.$proc$../Murax.v:2092$262'. +Creating decoders for process `\JtagBridge.$proc$../Murax.v:2050$256'. + 1/4: $0\jtag_readArea_full_shifter[33:0] + 2/4: $0\jtag_idcodeArea_shifter[31:0] + 3/4: $0\jtag_tap_instructionShift[3:0] + 4/4: $0\jtag_tap_instruction[3:0] +Creating decoders for process `\JtagBridge.$proc$../Murax.v:2039$255'. + 1/3: $0\system_rsp_payload_data[31:0] + 2/3: $0\system_rsp_payload_error[0:0] + 3/3: $0\system_rsp_valid[0:0] +Creating decoders for process `\JtagBridge.$proc$../Murax.v:1995$235'. + 1/3: $3\jtag_tap_tdoDr[0:0] + 2/3: $2\jtag_tap_tdoDr[0:0] + 3/3: $1\jtag_tap_tdoDr[0:0] +Creating decoders for process `\JtagBridge.$proc$../Murax.v:1977$234'. + 1/2: $2\jtag_tap_tdoUnbufferd[0:0] + 2/2: $1\jtag_tap_tdoUnbufferd[0:0] +Creating decoders for process `\JtagBridge.$proc$../Murax.v:1923$217'. + 1/1: $1\_zz_jtag_tap_fsm_stateNext[3:0] +Creating decoders for process `\SystemDebugger.$proc$../Murax.v:1718$213'. + 1/2: $0\dispatcher_headerShifter[7:0] + 2/2: $0\dispatcher_dataShifter[66:0] +Creating decoders for process `\SystemDebugger.$proc$../Murax.v:1692$211'. + 1/3: $0\dispatcher_counter[2:0] + 2/3: $0\dispatcher_headerLoaded[0:0] + 3/3: $0\dispatcher_dataLoaded[0:0] +Creating decoders for process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1633$198'. + 1/1: $0\_zz_io_bus_rsp_valid[0:0] +Creating decoders for process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'. + 1/12: $1$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$195 + 2/12: $1$memwr$\ram_symbol3$../Murax.v:1623$156_DATA[7:0]$194 + 3/12: $1$memwr$\ram_symbol3$../Murax.v:1623$156_ADDR[10:0]$193 + 4/12: $1$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$190 + 5/12: $1$memwr$\ram_symbol2$../Murax.v:1620$155_DATA[7:0]$189 + 6/12: $1$memwr$\ram_symbol2$../Murax.v:1620$155_ADDR[10:0]$188 + 7/12: $1$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$185 + 8/12: $1$memwr$\ram_symbol1$../Murax.v:1617$154_DATA[7:0]$184 + 9/12: $1$memwr$\ram_symbol1$../Murax.v:1617$154_ADDR[10:0]$183 + 10/12: $1$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$180 + 11/12: $1$memwr$\ram_symbol0$../Murax.v:1614$153_DATA[7:0]$179 + 12/12: $1$memwr$\ram_symbol0$../Murax.v:1614$153_ADDR[10:0]$178 +Creating decoders for process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1603$158'. + 1/4: $0\_zz_ramsymbol_read_3[7:0] + 2/4: $0\_zz_ramsymbol_read_2[7:0] + 3/4: $0\_zz_ramsymbol_read_1[7:0] + 4/4: $0\_zz_ramsymbol_read[7:0] +Creating decoders for process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1600$157'. +Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1557$152'. + 1/4: $0\io_pipelinedMemoryBus_cmd_rData_mask[3:0] + 2/4: $0\io_pipelinedMemoryBus_cmd_rData_data[31:0] + 3/4: $0\io_pipelinedMemoryBus_cmd_rData_address[31:0] + 4/4: $0\io_pipelinedMemoryBus_cmd_rData_write[0:0] +Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1534$151'. + 1/3: $0\pipelinedMemoryBusStage_rsp_regNext_valid[0:0] + 2/3: $0\state[0:0] + 3/3: $0\io_pipelinedMemoryBus_cmd_rValid[0:0] +Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1523$147'. + 1/2: $2\pipelinedMemoryBusStage_rsp_valid[0:0] + 2/2: $1\pipelinedMemoryBusStage_rsp_valid[0:0] +Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1509$145'. + 1/2: $2\pipelinedMemoryBusStage_cmd_ready[0:0] + 2/2: $1\pipelinedMemoryBusStage_cmd_ready[0:0] +Creating decoders for process `\Apb3Gpio.$proc$../Murax.v:1433$142'. + 1/1: $0\io_gpio_write_driver[31:0] +Creating decoders for process `\Apb3Gpio.$proc$../Murax.v:1417$141'. + 1/1: $0\io_gpio_writeEnable_driver[31:0] +Creating decoders for process `\Apb3Gpio.$proc$../Murax.v:1393$128'. + 1/1: $1\io_apb_PRDATA[31:0] +Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1353$127'. +Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1297$126'. + 1/6: $0\bridge_misc_doBreak[0:0] + 2/6: $0\bridge_misc_breakDetected[0:0] + 3/6: $0\bridge_misc_readOverflowError[0:0] + 4/6: $0\bridge_misc_readError[0:0] + 5/6: $0\bridge_interruptCtrl_readIntEnable[0:0] + 6/6: $0\bridge_interruptCtrl_writeIntEnable[0:0] +Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1282$125'. + 1/2: $2\when_BusSlaveFactory_l335_3[0:0] + 2/2: $1\when_BusSlaveFactory_l335_3[0:0] +Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1268$124'. + 1/2: $2\when_BusSlaveFactory_l366[0:0] + 2/2: $1\when_BusSlaveFactory_l366[0:0] +Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1254$123'. + 1/2: $2\when_BusSlaveFactory_l335_2[0:0] + 2/2: $1\when_BusSlaveFactory_l335_2[0:0] +Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1238$118'. + 1/2: $2\when_BusSlaveFactory_l335_1[0:0] + 2/2: $1\when_BusSlaveFactory_l335_1[0:0] +Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1224$117'. + 1/2: $2\when_BusSlaveFactory_l335[0:0] + 2/2: $1\when_BusSlaveFactory_l335[0:0] +Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1208$112'. + 1/2: $2\bridge_read_streamBreaked_ready[0:0] + 2/2: $1\bridge_read_streamBreaked_ready[0:0] +Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1200$111'. + 1/1: $1\uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready[0:0] +Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1193$110'. + 1/1: $1\bridge_read_streamBreaked_valid[0:0] +Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1177$109'. + 1/2: $2\_zz_bridge_write_streamUnbuffered_valid[0:0] + 2/2: $1\_zz_bridge_write_streamUnbuffered_valid[0:0] +Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1173$108'. +Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1141$94'. + 1/9: $2\io_apb_PRDATA[20:15] [5:2] + 2/9: $1\io_apb_PRDATA[9:0] [7:2] + 3/9: $2\io_apb_PRDATA[20:15] [1] + 4/9: $1\io_apb_PRDATA[9:0] [8] + 5/9: $2\io_apb_PRDATA[20:15] [0] + 6/9: $1\io_apb_PRDATA[9:0] [1] + 7/9: $3\io_apb_PRDATA[28:24] + 8/9: $1\io_apb_PRDATA[9:0] [9] + 9/9: $1\io_apb_PRDATA[9:0] [0] +Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:952$91'. + 1/3: $0\timerB_io_limit_driver[15:0] + 2/3: $0\timerA_io_limit_driver[15:0] + 3/3: $0\_zz_io_limit[15:0] +Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:920$90'. + 1/5: $0\interruptCtrl_1_io_masks_driver[1:0] + 2/5: $0\timerBBridge_clearsEnable[0:0] + 3/5: $0\timerBBridge_ticksEnable[1:0] + 4/5: $0\timerABridge_clearsEnable[0:0] + 5/5: $0\timerABridge_ticksEnable[1:0] +Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:914$88'. +Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:901$87'. + 1/2: $2\interruptCtrl_1_io_clears[1:0] + 2/2: $1\interruptCtrl_1_io_clears[1:0] +Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:886$81'. + 1/2: $2\when_Timer_l44_1[0:0] + 2/2: $1\when_Timer_l44_1[0:0] +Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:873$80'. + 1/2: $2\when_Timer_l40_1[0:0] + 2/2: $1\when_Timer_l40_1[0:0] +Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:863$79'. + 1/2: $2\timerBBridge_busClearing[0:0] + 2/2: $1\timerBBridge_busClearing[0:0] +Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:848$73'. + 1/2: $2\when_Timer_l44[0:0] + 2/2: $1\when_Timer_l44[0:0] +Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:835$72'. + 1/2: $2\when_Timer_l40[0:0] + 2/2: $1\when_Timer_l40[0:0] +Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:825$71'. + 1/2: $2\timerABridge_busClearing[0:0] + 2/2: $1\timerABridge_busClearing[0:0] +Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:812$70'. + 1/2: $2\_zz_io_clear[0:0] + 2/2: $1\_zz_io_clear[0:0] +Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:770$57'. + 1/3: $1\io_apb_PRDATA[16:0] [16] + 2/3: $1\io_apb_PRDATA[16:0] [15:2] + 3/3: $1\io_apb_PRDATA[16:0] [1:0] +Creating decoders for process `\Apb3Decoder.$proc$../Murax.v:679$54'. + 1/1: $1\io_input_PSLVERROR[0:0] +Creating decoders for process `\Apb3Decoder.$proc$../Murax.v:671$53'. + 1/1: $1\io_input_PREADY[0:0] +Creating decoders for process `\Apb3Decoder.$proc$../Murax.v:665$43'. +Creating decoders for process `\Apb3Router.$proc$../Murax.v:633$42'. +Creating decoders for process `\Apb3Router.$proc$../Murax.v:593$41'. + 1/3: $1\_zz_io_input_PSLVERROR[0:0] + 2/3: $1\_zz_io_input_PRDATA[31:0] + 3/3: $1\_zz_io_input_PREADY[0:0] +Creating decoders for process `\Murax.$proc$../Murax.v:0$40'. +Creating decoders for process `\Murax.$proc$../Murax.v:538$39'. + 1/1: $0\system_cpu_debug_bus_cmd_fire_regNext[0:0] +Creating decoders for process `\Murax.$proc$../Murax.v:534$38'. +Creating decoders for process `\Murax.$proc$../Murax.v:522$37'. + 1/5: $0\system_mainBusDecoder_logic_rspSourceId[0:0] + 2/5: $0\system_cpu_dBus_cmd_rData_size[1:0] + 3/5: $0\system_cpu_dBus_cmd_rData_data[31:0] + 4/5: $0\system_cpu_dBus_cmd_rData_address[31:0] + 5/5: $0\system_cpu_dBus_cmd_rData_wr[0:0] +Creating decoders for process `\Murax.$proc$../Murax.v:497$36'. + 1/3: $0\system_mainBusDecoder_logic_rspNoHit[0:0] + 2/3: $0\system_mainBusDecoder_logic_rspPending[0:0] + 3/3: $0\system_cpu_dBus_cmd_rValid[0:0] +Creating decoders for process `\Murax.$proc$../Murax.v:489$35'. + 1/1: $0\resetCtrl_systemReset[0:0] +Creating decoders for process `\Murax.$proc$../Murax.v:480$33'. + 1/1: $0\resetCtrl_systemClkResetCounter[5:0] +Creating decoders for process `\Murax.$proc$../Murax.v:467$19'. + 1/1: $1\system_mainBusDecoder_logic_masterPipelined_cmd_ready[0:0] +Creating decoders for process `\Murax.$proc$../Murax.v:458$15'. + 1/1: $1\system_apbBridge_io_pipelinedMemoryBus_cmd_valid[0:0] +Creating decoders for process `\Murax.$proc$../Murax.v:449$11'. + 1/1: $1\system_ram_io_bus_cmd_valid[0:0] +Creating decoders for process `\Murax.$proc$../Murax.v:419$5'. + 1/1: $1\system_externalInterrupt[0:0] +Creating decoders for process `\Murax.$proc$../Murax.v:412$4'. + 1/1: $1\system_timerInterrupt[0:0] +Creating decoders for process `\Murax.$proc$../Murax.v:402$2'. + 1/1: $1\resetCtrl_mainClkResetUnbuffered[0:0] +Creating decoders for process `\Murax.$proc$../Murax.v:395$1'. + 1/1: $1\_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[31:0] + +3.1.7. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `\UartCtrlTx.\io_write_ready' from process `\UartCtrlTx.$proc$../Murax.v:6688$1027'. +No latch inferred for signal `\UartCtrlTx.\stateMachine_txd' from process `\UartCtrlTx.$proc$../Murax.v:6669$1025'. +No latch inferred for signal `\UartCtrlTx.\clockDivider_counter_valueNext' from process `\UartCtrlTx.$proc$../Murax.v:6658$1023'. +No latch inferred for signal `\UartCtrlTx.\clockDivider_counter_willIncrement' from process `\UartCtrlTx.$proc$../Murax.v:6648$1020'. +No latch inferred for signal `\UartCtrlRx.\bitTimer_tick' from process `\UartCtrlRx.$proc$../Murax.v:6418$970'. +No latch inferred for signal `\UartCtrlRx.\io_error' from process `\UartCtrlRx.$proc$../Murax.v:6389$968'. +No latch inferred for signal `\StreamFifoLowLatency.\io_pop_payload_inst' from process `\StreamFifoLowLatency.$proc$../Murax.v:6259$959'. +No latch inferred for signal `\StreamFifoLowLatency.\io_pop_payload_error' from process `\StreamFifoLowLatency.$proc$../Murax.v:6251$958'. +No latch inferred for signal `\StreamFifoLowLatency.\io_pop_valid' from process `\StreamFifoLowLatency.$proc$../Murax.v:6243$957'. +No latch inferred for signal `\StreamFifoLowLatency.\popPtr_willClear' from process `\StreamFifoLowLatency.$proc$../Murax.v:6224$948'. +No latch inferred for signal `\StreamFifoLowLatency.\popPtr_willIncrement' from process `\StreamFifoLowLatency.$proc$../Murax.v:6217$947'. +No latch inferred for signal `\StreamFifoLowLatency.\pushPtr_willClear' from process `\StreamFifoLowLatency.$proc$../Murax.v:6208$945'. +No latch inferred for signal `\StreamFifoLowLatency.\pushPtr_willIncrement' from process `\StreamFifoLowLatency.$proc$../Murax.v:6201$944'. +No latch inferred for signal `\StreamFifoLowLatency.\when_Phase_l623' from process `\StreamFifoLowLatency.$proc$../Murax.v:6194$943'. +No latch inferred for signal `\UartCtrl.\io_write_ready' from process `\UartCtrl.$proc$../Murax.v:6035$933'. +No latch inferred for signal `\UartCtrl.\io_write_thrown_valid' from process `\UartCtrl.$proc$../Murax.v:6028$932'. +No latch inferred for signal `\StreamFifo.\logic_popPtr_valueNext' from process `\StreamFifo.$proc$../Murax.v:5895$910'. +No latch inferred for signal `\StreamFifo.\logic_popPtr_willClear' from process `\StreamFifo.$proc$../Murax.v:5886$907'. +No latch inferred for signal `\StreamFifo.\logic_popPtr_willIncrement' from process `\StreamFifo.$proc$../Murax.v:5879$906'. +No latch inferred for signal `\StreamFifo.\logic_pushPtr_valueNext' from process `\StreamFifo.$proc$../Murax.v:5872$904'. +No latch inferred for signal `\StreamFifo.\logic_pushPtr_willClear' from process `\StreamFifo.$proc$../Murax.v:5863$901'. +No latch inferred for signal `\StreamFifo.\logic_pushPtr_willIncrement' from process `\StreamFifo.$proc$../Murax.v:5856$900'. +No latch inferred for signal `\StreamFifo.\_zz_1' from process `\StreamFifo.$proc$../Murax.v:5849$899'. +No latch inferred for signal `\MuraxMasterArbiter.\io_dBus_cmd_ready' from process `\MuraxMasterArbiter.$proc$../Murax.v:5637$860'. +No latch inferred for signal `\MuraxMasterArbiter.\io_iBus_cmd_ready' from process `\MuraxMasterArbiter.$proc$../Murax.v:5630$857'. +No latch inferred for signal `\MuraxMasterArbiter.\_zz_io_masterBus_cmd_payload_mask' from process `\MuraxMasterArbiter.$proc$../Murax.v:5615$855'. +No latch inferred for signal `\MuraxMasterArbiter.\io_masterBus_cmd_valid' from process `\MuraxMasterArbiter.$proc$../Murax.v:5605$851'. +No latch inferred for signal `\VexRiscv.\_zz_CsrPlugin_csrMapping_readDataInit_3' from process `\VexRiscv.$proc$../Murax.v:5007$821'. +No latch inferred for signal `\VexRiscv.\_zz_CsrPlugin_csrMapping_readDataInit_2' from process `\VexRiscv.$proc$../Murax.v:4998$820'. +No latch inferred for signal `\VexRiscv.\_zz_CsrPlugin_csrMapping_readDataInit_1' from process `\VexRiscv.$proc$../Murax.v:4989$819'. +No latch inferred for signal `\VexRiscv.\_zz_CsrPlugin_csrMapping_readDataInit' from process `\VexRiscv.$proc$../Murax.v:4980$818'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_injectionPort_ready' from process `\VexRiscv.$proc$../Murax.v:4963$811'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_injectionPort_valid' from process `\VexRiscv.$proc$../Murax.v:4841$690'. +No latch inferred for signal `\VexRiscv.\debug_bus_rsp_data' from process `\VexRiscv.$proc$../Murax.v:4829$688'. +No latch inferred for signal `\VexRiscv.\debug_bus_cmd_ready' from process `\VexRiscv.$proc$../Murax.v:4814$687'. +No latch inferred for signal `\VexRiscv.\_zz_execute_BranchPlugin_branch_src2_6' from process `\VexRiscv.$proc$../Murax.v:4794$679'. +No latch inferred for signal `\VexRiscv.\_zz_execute_BranchPlugin_branch_src2_5' from process `\VexRiscv.$proc$../Murax.v:4772$678'. +No latch inferred for signal `\VexRiscv.\_zz_execute_BranchPlugin_branch_src2_3' from process `\VexRiscv.$proc$../Murax.v:4748$677'. +No latch inferred for signal `\VexRiscv.\_zz_execute_BranchPlugin_branch_src2_1' from process `\VexRiscv.$proc$../Murax.v:4733$676'. +No latch inferred for signal `\VexRiscv.\_zz_execute_BRANCH_DO_1' from process `\VexRiscv.$proc$../Murax.v:4714$673'. +No latch inferred for signal `\VexRiscv.\_zz_execute_BRANCH_DO' from process `\VexRiscv.$proc$../Murax.v:4697$670'. +No latch inferred for signal `\VexRiscv.\HazardSimplePlugin_src1Hazard' from process `\VexRiscv.$proc$../Murax.v:4642$648'. +No latch inferred for signal `\VexRiscv.\HazardSimplePlugin_src0Hazard' from process `\VexRiscv.$proc$../Murax.v:4609$647'. +No latch inferred for signal `\VexRiscv.\_zz_execute_to_memory_REGFILE_WRITE_DATA_1' from process `\VexRiscv.$proc$../Murax.v:4596$643'. +No latch inferred for signal `\VexRiscv.\execute_SrcPlugin_addSub' from process `\VexRiscv.$proc$../Murax.v:4583$632'. +No latch inferred for signal `\VexRiscv.\_zz_decode_SRC2_6' from process `\VexRiscv.$proc$../Murax.v:4566$631'. +No latch inferred for signal `\VexRiscv.\_zz_decode_SRC2_5' from process `\VexRiscv.$proc$../Murax.v:4543$630'. +No latch inferred for signal `\VexRiscv.\_zz_decode_SRC2_3' from process `\VexRiscv.$proc$../Murax.v:4519$629'. +No latch inferred for signal `\VexRiscv.\_zz_decode_SRC1_1' from process `\VexRiscv.$proc$../Murax.v:4501$628'. +No latch inferred for signal `\VexRiscv.\_zz_execute_REGFILE_WRITE_DATA' from process `\VexRiscv.$proc$../Murax.v:4487$627'. +No latch inferred for signal `\VexRiscv.\execute_IntAluPlugin_bitwise' from process `\VexRiscv.$proc$../Murax.v:4473$623'. +No latch inferred for signal `\VexRiscv.\lastStageRegFileWrite_payload_data' from process `\VexRiscv.$proc$../Murax.v:4466$622'. +No latch inferred for signal `\VexRiscv.\lastStageRegFileWrite_payload_address' from process `\VexRiscv.$proc$../Murax.v:4459$621'. +No latch inferred for signal `\VexRiscv.\lastStageRegFileWrite_valid' from process `\VexRiscv.$proc$../Murax.v:4452$619'. +No latch inferred for signal `\VexRiscv.\_zz_CsrPlugin_csrMapping_writeDataSignal' from process `\VexRiscv.$proc$../Murax.v:4411$589'. +No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_readInstruction' from process `\VexRiscv.$proc$../Murax.v:4399$581'. +No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_writeInstruction' from process `\VexRiscv.$proc$../Murax.v:4392$578'. +No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_illegalInstruction' from process `\VexRiscv.$proc$../Murax.v:4381$574'. +No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_illegalAccess' from process `\VexRiscv.$proc$../Murax.v:4354$573'. +No latch inferred for signal `\VexRiscv.\CsrPlugin_xtvec_base' from process `\VexRiscv.$proc$../Murax.v:4337$560'. +No latch inferred for signal `\VexRiscv.\CsrPlugin_xtvec_mode' from process `\VexRiscv.$proc$../Murax.v:4326$559'. +No latch inferred for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_done' from process `\VexRiscv.$proc$../Murax.v:4316$556'. +No latch inferred for signal `\VexRiscv.\CsrPlugin_privilege' from process `\VexRiscv.$proc$../Murax.v:4291$537'. +No latch inferred for signal `\VexRiscv.\writeBack_DBusSimplePlugin_rspFormated' from process `\VexRiscv.$proc$../Murax.v:4276$535'. +No latch inferred for signal `\VexRiscv.\_zz_writeBack_DBusSimplePlugin_rspFormated_3' from process `\VexRiscv.$proc$../Murax.v:4256$534'. +No latch inferred for signal `\VexRiscv.\_zz_writeBack_DBusSimplePlugin_rspFormated_1' from process `\VexRiscv.$proc$../Murax.v:4227$531'. +No latch inferred for signal `\VexRiscv.\writeBack_DBusSimplePlugin_rspShifted' from process `\VexRiscv.$proc$../Murax.v:4208$528'. +No latch inferred for signal `\VexRiscv.\_zz_execute_DBusSimplePlugin_formalMask' from process `\VexRiscv.$proc$../Murax.v:4191$520'. +No latch inferred for signal `\VexRiscv.\_zz_dBus_cmd_payload_data' from process `\VexRiscv.$proc$../Murax.v:4175$512'. +No latch inferred for signal `\VexRiscv.\execute_DBusSimplePlugin_skipCmd' from process `\VexRiscv.$proc$../Murax.v:4165$502'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_rspJoin_fetchRsp_rsp_error' from process `\VexRiscv.$proc$../Murax.v:4138$493'. +No latch inferred for signal `\VexRiscv.\decode_arbitration_isValid' from process `\VexRiscv.$proc$../Murax.v:4102$477'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_iBusRsp_readyForError' from process `\VexRiscv.$proc$../Murax.v:4073$461'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_iBusRsp_stages_1_halt' from process `\VexRiscv.$proc$../Murax.v:4045$447'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_flushed' from process `\VexRiscv.$proc$../Murax.v:4026$438'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_pc' from process `\VexRiscv.$proc$../Murax.v:4017$436'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_pcRegPropagate' from process `\VexRiscv.$proc$../Murax.v:4007$431'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_correction' from process `\VexRiscv.$proc$../Murax.v:3998$428'. +No latch inferred for signal `\VexRiscv.\CsrPlugin_allowEbreakException' from process `\VexRiscv.$proc$../Murax.v:3987$424'. +No latch inferred for signal `\VexRiscv.\CsrPlugin_allowException' from process `\VexRiscv.$proc$../Murax.v:3980$423'. +No latch inferred for signal `\VexRiscv.\CsrPlugin_allowInterrupts' from process `\VexRiscv.$proc$../Murax.v:3973$422'. +No latch inferred for signal `\VexRiscv.\CsrPlugin_forceMachineWire' from process `\VexRiscv.$proc$../Murax.v:3966$421'. +No latch inferred for signal `\VexRiscv.\CsrPlugin_jumpInterface_payload' from process `\VexRiscv.$proc$../Murax.v:3950$420'. +No latch inferred for signal `\VexRiscv.\CsrPlugin_jumpInterface_valid' from process `\VexRiscv.$proc$../Murax.v:3940$419'. +No latch inferred for signal `\VexRiscv.\CsrPlugin_thirdPartyWake' from process `\VexRiscv.$proc$../Murax.v:3933$418'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_incomingInstruction' from process `\VexRiscv.$proc$../Murax.v:3920$417'. +No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetcherHalt' from process `\VexRiscv.$proc$../Murax.v:3899$416'. +No latch inferred for signal `\VexRiscv.\writeBack_arbitration_flushNext' from process `\VexRiscv.$proc$../Murax.v:3885$415'. +No latch inferred for signal `\VexRiscv.\writeBack_arbitration_removeIt' from process `\VexRiscv.$proc$../Murax.v:3877$414'. +No latch inferred for signal `\VexRiscv.\memory_arbitration_flushNext' from process `\VexRiscv.$proc$../Murax.v:3868$413'. +No latch inferred for signal `\VexRiscv.\memory_arbitration_removeIt' from process `\VexRiscv.$proc$../Murax.v:3860$412'. +No latch inferred for signal `\VexRiscv.\memory_arbitration_haltItself' from process `\VexRiscv.$proc$../Murax.v:3852$411'. +No latch inferred for signal `\VexRiscv.\execute_arbitration_flushNext' from process `\VexRiscv.$proc$../Murax.v:3843$410'. +No latch inferred for signal `\VexRiscv.\execute_arbitration_flushIt' from process `\VexRiscv.$proc$../Murax.v:3834$409'. +No latch inferred for signal `\VexRiscv.\execute_arbitration_removeIt' from process `\VexRiscv.$proc$../Murax.v:3827$408'. +No latch inferred for signal `\VexRiscv.\execute_arbitration_haltByOther' from process `\VexRiscv.$proc$../Murax.v:3820$407'. +No latch inferred for signal `\VexRiscv.\execute_arbitration_haltItself' from process `\VexRiscv.$proc$../Murax.v:3803$406'. +No latch inferred for signal `\VexRiscv.\decode_arbitration_removeIt' from process `\VexRiscv.$proc$../Murax.v:3794$405'. +No latch inferred for signal `\VexRiscv.\decode_arbitration_haltByOther' from process `\VexRiscv.$proc$../Murax.v:3781$404'. +No latch inferred for signal `\VexRiscv.\decode_arbitration_haltItself' from process `\VexRiscv.$proc$../Murax.v:3770$403'. +No latch inferred for signal `\VexRiscv.\_zz_memory_to_writeBack_FORMAL_PC_NEXT' from process `\VexRiscv.$proc$../Murax.v:3759$402'. +No latch inferred for signal `\VexRiscv.\_zz_lastStageRegFileWrite_payload_data' from process `\VexRiscv.$proc$../Murax.v:3741$401'. +No latch inferred for signal `\VexRiscv.\_zz_execute_to_memory_REGFILE_WRITE_DATA' from process `\VexRiscv.$proc$../Murax.v:3724$400'. +No latch inferred for signal `\VexRiscv.\decode_REGFILE_WRITE_VALID' from process `\VexRiscv.$proc$../Murax.v:3717$399'. +No latch inferred for signal `\VexRiscv.\_zz_1' from process `\VexRiscv.$proc$../Murax.v:3709$397'. +No latch inferred for signal `\JtagBridge.\jtag_tap_tdoDr' from process `\JtagBridge.$proc$../Murax.v:1995$235'. +No latch inferred for signal `\JtagBridge.\jtag_tap_tdoUnbufferd' from process `\JtagBridge.$proc$../Murax.v:1977$234'. +No latch inferred for signal `\JtagBridge.\_zz_jtag_tap_fsm_stateNext' from process `\JtagBridge.$proc$../Murax.v:1923$217'. +No latch inferred for signal `\MuraxPipelinedMemoryBusRam.\_zz_ram_port0' from process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1600$157'. +No latch inferred for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_rsp_valid' from process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1523$147'. +No latch inferred for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_cmd_ready' from process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1509$145'. +No latch inferred for signal `\Apb3Gpio.\io_apb_PRDATA' from process `\Apb3Gpio.$proc$../Murax.v:1393$128'. +No latch inferred for signal `\Apb3UartCtrl.\when_BusSlaveFactory_l335_3' from process `\Apb3UartCtrl.$proc$../Murax.v:1282$125'. +No latch inferred for signal `\Apb3UartCtrl.\when_BusSlaveFactory_l366' from process `\Apb3UartCtrl.$proc$../Murax.v:1268$124'. +No latch inferred for signal `\Apb3UartCtrl.\when_BusSlaveFactory_l335_2' from process `\Apb3UartCtrl.$proc$../Murax.v:1254$123'. +No latch inferred for signal `\Apb3UartCtrl.\when_BusSlaveFactory_l335_1' from process `\Apb3UartCtrl.$proc$../Murax.v:1238$118'. +No latch inferred for signal `\Apb3UartCtrl.\when_BusSlaveFactory_l335' from process `\Apb3UartCtrl.$proc$../Murax.v:1224$117'. +No latch inferred for signal `\Apb3UartCtrl.\bridge_read_streamBreaked_ready' from process `\Apb3UartCtrl.$proc$../Murax.v:1208$112'. +No latch inferred for signal `\Apb3UartCtrl.\uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready' from process `\Apb3UartCtrl.$proc$../Murax.v:1200$111'. +No latch inferred for signal `\Apb3UartCtrl.\bridge_read_streamBreaked_valid' from process `\Apb3UartCtrl.$proc$../Murax.v:1193$110'. +No latch inferred for signal `\Apb3UartCtrl.\_zz_bridge_write_streamUnbuffered_valid' from process `\Apb3UartCtrl.$proc$../Murax.v:1177$109'. +No latch inferred for signal `\Apb3UartCtrl.\bridge_uartConfigReg_clockDivider' from process `\Apb3UartCtrl.$proc$../Murax.v:1173$108'. +No latch inferred for signal `\Apb3UartCtrl.\io_apb_PRDATA' from process `\Apb3UartCtrl.$proc$../Murax.v:1141$94'. +No latch inferred for signal `\MuraxApb3Timer.\interruptCtrl_1_io_inputs' from process `\MuraxApb3Timer.$proc$../Murax.v:914$88'. +No latch inferred for signal `\MuraxApb3Timer.\interruptCtrl_1_io_clears' from process `\MuraxApb3Timer.$proc$../Murax.v:901$87'. +No latch inferred for signal `\MuraxApb3Timer.\when_Timer_l44_1' from process `\MuraxApb3Timer.$proc$../Murax.v:886$81'. +No latch inferred for signal `\MuraxApb3Timer.\when_Timer_l40_1' from process `\MuraxApb3Timer.$proc$../Murax.v:873$80'. +No latch inferred for signal `\MuraxApb3Timer.\timerBBridge_busClearing' from process `\MuraxApb3Timer.$proc$../Murax.v:863$79'. +No latch inferred for signal `\MuraxApb3Timer.\when_Timer_l44' from process `\MuraxApb3Timer.$proc$../Murax.v:848$73'. +No latch inferred for signal `\MuraxApb3Timer.\when_Timer_l40' from process `\MuraxApb3Timer.$proc$../Murax.v:835$72'. +No latch inferred for signal `\MuraxApb3Timer.\timerABridge_busClearing' from process `\MuraxApb3Timer.$proc$../Murax.v:825$71'. +No latch inferred for signal `\MuraxApb3Timer.\_zz_io_clear' from process `\MuraxApb3Timer.$proc$../Murax.v:812$70'. +No latch inferred for signal `\MuraxApb3Timer.\io_apb_PRDATA' from process `\MuraxApb3Timer.$proc$../Murax.v:770$57'. +No latch inferred for signal `\Apb3Decoder.\io_input_PSLVERROR' from process `\Apb3Decoder.$proc$../Murax.v:679$54'. +No latch inferred for signal `\Apb3Decoder.\io_input_PREADY' from process `\Apb3Decoder.$proc$../Murax.v:671$53'. +No latch inferred for signal `\Apb3Decoder.\io_output_PSEL' from process `\Apb3Decoder.$proc$../Murax.v:665$43'. +No latch inferred for signal `\Apb3Router.\_zz_io_input_PREADY' from process `\Apb3Router.$proc$../Murax.v:593$41'. +No latch inferred for signal `\Apb3Router.\_zz_io_input_PRDATA' from process `\Apb3Router.$proc$../Murax.v:593$41'. +No latch inferred for signal `\Apb3Router.\_zz_io_input_PSLVERROR' from process `\Apb3Router.$proc$../Murax.v:593$41'. +No latch inferred for signal `\Murax.\system_mainBusDecoder_logic_masterPipelined_cmd_ready' from process `\Murax.$proc$../Murax.v:467$19'. +No latch inferred for signal `\Murax.\system_apbBridge_io_pipelinedMemoryBus_cmd_valid' from process `\Murax.$proc$../Murax.v:458$15'. +No latch inferred for signal `\Murax.\system_ram_io_bus_cmd_valid' from process `\Murax.$proc$../Murax.v:449$11'. +No latch inferred for signal `\Murax.\system_externalInterrupt' from process `\Murax.$proc$../Murax.v:419$5'. +No latch inferred for signal `\Murax.\system_timerInterrupt' from process `\Murax.$proc$../Murax.v:412$4'. +No latch inferred for signal `\Murax.\resetCtrl_mainClkResetUnbuffered' from process `\Murax.$proc$../Murax.v:402$2'. +No latch inferred for signal `\Murax.\_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data' from process `\Murax.$proc$../Murax.v:395$1'. + +3.1.8. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\BufferCC.\buffers_0' using process `\BufferCC.$proc$../Murax.v:6826$1043'. + created $adff cell `$procdff$2879' with positive edge clock and positive level reset. +Creating register for signal `\BufferCC.\buffers_1' using process `\BufferCC.$proc$../Murax.v:6826$1043'. + created $adff cell `$procdff$2880' with positive edge clock and positive level reset. +Creating register for signal `\BufferCC_1.\buffers_0' using process `\BufferCC_1.$proc$../Murax.v:6807$1042'. + created $dff cell `$procdff$2881' with positive edge clock. +Creating register for signal `\BufferCC_1.\buffers_1' using process `\BufferCC_1.$proc$../Murax.v:6807$1042'. + created $dff cell `$procdff$2882' with positive edge clock. +Creating register for signal `\UartCtrlTx.\stateMachine_parity' using process `\UartCtrlTx.$proc$../Murax.v:6760$1038'. + created $dff cell `$procdff$2883' with positive edge clock. +Creating register for signal `\UartCtrlTx.\tickCounter_value' using process `\UartCtrlTx.$proc$../Murax.v:6760$1038'. + created $dff cell `$procdff$2884' with positive edge clock. +Creating register for signal `\UartCtrlTx.\stateMachine_state' using process `\UartCtrlTx.$proc$../Murax.v:6714$1034'. + created $adff cell `$procdff$2885' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrlTx.\clockDivider_counter_value' using process `\UartCtrlTx.$proc$../Murax.v:6714$1034'. + created $adff cell `$procdff$2886' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrlTx.\_zz_io_txd' using process `\UartCtrlTx.$proc$../Murax.v:6714$1034'. + created $adff cell `$procdff$2887' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrlRx.\bitTimer_counter' using process `\UartCtrlRx.$proc$../Murax.v:6519$998'. + created $dff cell `$procdff$2888' with positive edge clock. +Creating register for signal `\UartCtrlRx.\bitCounter_value' using process `\UartCtrlRx.$proc$../Murax.v:6519$998'. + created $dff cell `$procdff$2889' with positive edge clock. +Creating register for signal `\UartCtrlRx.\stateMachine_parity' using process `\UartCtrlRx.$proc$../Murax.v:6519$998'. + created $dff cell `$procdff$2890' with positive edge clock. +Creating register for signal `\UartCtrlRx.\stateMachine_shifter' using process `\UartCtrlRx.$proc$../Murax.v:6519$998'. + created $dff cell `$procdff$2891' with positive edge clock. +Creating register for signal `\UartCtrlRx.$bitselwrite$mask$../Murax.v:6546$964' using process `\UartCtrlRx.$proc$../Murax.v:6519$998'. + created $dff cell `$procdff$2892' with positive edge clock. +Creating register for signal `\UartCtrlRx.$bitselwrite$data$../Murax.v:6546$965' using process `\UartCtrlRx.$proc$../Murax.v:6519$998'. + created $dff cell `$procdff$2893' with positive edge clock. +Creating register for signal `\UartCtrlRx.$lookahead\stateMachine_shifter$997' using process `\UartCtrlRx.$proc$../Murax.v:6519$998'. + created $dff cell `$procdff$2894' with positive edge clock. +Creating register for signal `\UartCtrlRx.\_zz_io_rts' using process `\UartCtrlRx.$proc$../Murax.v:6440$985'. + created $adff cell `$procdff$2895' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrlRx.\sampler_samples_1' using process `\UartCtrlRx.$proc$../Murax.v:6440$985'. + created $adff cell `$procdff$2896' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrlRx.\sampler_samples_2' using process `\UartCtrlRx.$proc$../Murax.v:6440$985'. + created $adff cell `$procdff$2897' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrlRx.\sampler_value' using process `\UartCtrlRx.$proc$../Murax.v:6440$985'. + created $adff cell `$procdff$2898' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrlRx.\sampler_tick' using process `\UartCtrlRx.$proc$../Murax.v:6440$985'. + created $adff cell `$procdff$2899' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrlRx.\break_counter' using process `\UartCtrlRx.$proc$../Murax.v:6440$985'. + created $adff cell `$procdff$2900' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrlRx.\stateMachine_state' using process `\UartCtrlRx.$proc$../Murax.v:6440$985'. + created $adff cell `$procdff$2901' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrlRx.\stateMachine_validReg' using process `\UartCtrlRx.$proc$../Murax.v:6440$985'. + created $adff cell `$procdff$2902' with positive edge clock and positive level reset. +Creating register for signal `\StreamFifoLowLatency.\_zz_readed_error_2' using process `\StreamFifoLowLatency.$proc$../Murax.v:6283$963'. + created $dff cell `$procdff$2903' with positive edge clock. +Creating register for signal `\StreamFifoLowLatency.\risingOccupancy' using process `\StreamFifoLowLatency.$proc$../Murax.v:6270$962'. + created $adff cell `$procdff$2904' with positive edge clock and positive level reset. +Creating register for signal `\FlowCCByToggle.\outputArea_flow_m2sPipe_valid' using process `\FlowCCByToggle.$proc$../Murax.v:6145$941'. + created $adff cell `$procdff$2905' with positive edge clock and positive level reset. +Creating register for signal `\FlowCCByToggle.\outputArea_hit' using process `\FlowCCByToggle.$proc$../Murax.v:6137$940'. + created $dff cell `$procdff$2906' with positive edge clock. +Creating register for signal `\FlowCCByToggle.\outputArea_flow_m2sPipe_payload_last' using process `\FlowCCByToggle.$proc$../Murax.v:6137$940'. + created $dff cell `$procdff$2907' with positive edge clock. +Creating register for signal `\FlowCCByToggle.\outputArea_flow_m2sPipe_payload_fragment' using process `\FlowCCByToggle.$proc$../Murax.v:6137$940'. + created $dff cell `$procdff$2908' with positive edge clock. +Creating register for signal `\FlowCCByToggle.\inputArea_target' using process `\FlowCCByToggle.$proc$../Murax.v:6129$938'. + created $dff cell `$procdff$2909' with positive edge clock. +Creating register for signal `\FlowCCByToggle.\inputArea_data_last' using process `\FlowCCByToggle.$proc$../Murax.v:6129$938'. + created $dff cell `$procdff$2910' with positive edge clock. +Creating register for signal `\FlowCCByToggle.\inputArea_data_fragment' using process `\FlowCCByToggle.$proc$../Murax.v:6129$938'. + created $dff cell `$procdff$2911' with positive edge clock. +Creating register for signal `\BufferCC_2.\buffers_0' using process `\BufferCC_2.$proc$../Murax.v:6076$936'. + created $dff cell `$procdff$2912' with positive edge clock. +Creating register for signal `\BufferCC_2.\buffers_1' using process `\BufferCC_2.$proc$../Murax.v:6076$936'. + created $dff cell `$procdff$2913' with positive edge clock. +Creating register for signal `\UartCtrl.\clockDivider_counter' using process `\UartCtrl.$proc$../Murax.v:6049$934'. + created $adff cell `$procdff$2914' with positive edge clock and positive level reset. +Creating register for signal `\UartCtrl.\clockDivider_tickReg' using process `\UartCtrl.$proc$../Murax.v:6049$934'. + created $adff cell `$procdff$2915' with positive edge clock and positive level reset. +Creating register for signal `\StreamFifo.\logic_pushPtr_value' using process `\StreamFifo.$proc$../Murax.v:5914$929'. + created $adff cell `$procdff$2916' with positive edge clock and positive level reset. +Creating register for signal `\StreamFifo.\logic_popPtr_value' using process `\StreamFifo.$proc$../Murax.v:5914$929'. + created $adff cell `$procdff$2917' with positive edge clock and positive level reset. +Creating register for signal `\StreamFifo.\logic_risingOccupancy' using process `\StreamFifo.$proc$../Murax.v:5914$929'. + created $adff cell `$procdff$2918' with positive edge clock and positive level reset. +Creating register for signal `\StreamFifo.\_zz_io_pop_valid' using process `\StreamFifo.$proc$../Murax.v:5914$929'. + created $adff cell `$procdff$2919' with positive edge clock and positive level reset. +Creating register for signal `\StreamFifo.$memwr$\logic_ram$../Murax.v:5845$888_ADDR' using process `\StreamFifo.$proc$../Murax.v:5843$892'. + created $dff cell `$procdff$2920' with positive edge clock. +Creating register for signal `\StreamFifo.$memwr$\logic_ram$../Murax.v:5845$888_DATA' using process `\StreamFifo.$proc$../Murax.v:5843$892'. + created $dff cell `$procdff$2921' with positive edge clock. +Creating register for signal `\StreamFifo.$memwr$\logic_ram$../Murax.v:5845$888_EN' using process `\StreamFifo.$proc$../Murax.v:5843$892'. + created $dff cell `$procdff$2922' with positive edge clock. +Creating register for signal `\StreamFifo.\_zz_logic_ram_port0' using process `\StreamFifo.$proc$../Murax.v:5837$890'. + created $dff cell `$procdff$2923' with positive edge clock. +Creating register for signal `\Prescaler.\counter' using process `\Prescaler.$proc$../Murax.v:5773$886'. + created $dff cell `$procdff$2924' with positive edge clock. +Creating register for signal `\Timer.\counter' using process `\Timer.$proc$../Murax.v:5748$882'. + created $dff cell `$procdff$2925' with positive edge clock. +Creating register for signal `\Timer.\inhibitFull' using process `\Timer.$proc$../Murax.v:5735$881'. + created $adff cell `$procdff$2926' with positive edge clock and positive level reset. +Creating register for signal `\InterruptCtrl.\pendings' using process `\InterruptCtrl.$proc$../Murax.v:5701$872'. + created $adff cell `$procdff$2927' with positive edge clock and positive level reset. +Creating register for signal `\BufferCC_3.\buffers_0' using process `\BufferCC_3.$proc$../Murax.v:5681$870'. + created $dff cell `$procdff$2928' with positive edge clock. +Creating register for signal `\BufferCC_3.\buffers_1' using process `\BufferCC_3.$proc$../Murax.v:5681$870'. + created $dff cell `$procdff$2929' with positive edge clock. +Creating register for signal `\MuraxMasterArbiter.\rspPending' using process `\MuraxMasterArbiter.$proc$../Murax.v:5653$869'. + created $adff cell `$procdff$2930' with positive edge clock and positive level reset. +Creating register for signal `\MuraxMasterArbiter.\rspTarget' using process `\MuraxMasterArbiter.$proc$../Murax.v:5653$869'. + created $adff cell `$procdff$2931' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\DebugPlugin_resetIt' using process `\VexRiscv.$proc$../Murax.v:5502$850'. + created $adff cell `$procdff$2932' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\DebugPlugin_haltIt' using process `\VexRiscv.$proc$../Murax.v:5502$850'. + created $adff cell `$procdff$2933' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\DebugPlugin_stepIt' using process `\VexRiscv.$proc$../Murax.v:5502$850'. + created $adff cell `$procdff$2934' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\DebugPlugin_godmode' using process `\VexRiscv.$proc$../Murax.v:5502$850'. + created $adff cell `$procdff$2935' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\DebugPlugin_haltedByBreak' using process `\VexRiscv.$proc$../Murax.v:5502$850'. + created $adff cell `$procdff$2936' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\DebugPlugin_debugUsed' using process `\VexRiscv.$proc$../Murax.v:5502$850'. + created $adff cell `$procdff$2937' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\DebugPlugin_disableEbreak' using process `\VexRiscv.$proc$../Murax.v:5502$850'. + created $adff cell `$procdff$2938' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\DebugPlugin_firstCycle' using process `\VexRiscv.$proc$../Murax.v:5485$847'. + created $dff cell `$procdff$2939' with positive edge clock. +Creating register for signal `\VexRiscv.\DebugPlugin_secondCycle' using process `\VexRiscv.$proc$../Murax.v:5485$847'. + created $dff cell `$procdff$2940' with positive edge clock. +Creating register for signal `\VexRiscv.\DebugPlugin_isPipBusy' using process `\VexRiscv.$proc$../Murax.v:5485$847'. + created $dff cell `$procdff$2941' with positive edge clock. +Creating register for signal `\VexRiscv.\DebugPlugin_busReadDataReg' using process `\VexRiscv.$proc$../Murax.v:5485$847'. + created $dff cell `$procdff$2942' with positive edge clock. +Creating register for signal `\VexRiscv.\_zz_when_DebugPlugin_l244' using process `\VexRiscv.$proc$../Murax.v:5485$847'. + created $dff cell `$procdff$2943' with positive edge clock. +Creating register for signal `\VexRiscv.\DebugPlugin_resetIt_regNext' using process `\VexRiscv.$proc$../Murax.v:5485$847'. + created $dff cell `$procdff$2944' with positive edge clock. +Creating register for signal `\VexRiscv.\_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2945' with positive edge clock. +Creating register for signal `\VexRiscv.\_zz_IBusSimplePlugin_injector_decodeInput_payload_pc' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2946' with positive edge clock. +Creating register for signal `\VexRiscv.\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2947' with positive edge clock. +Creating register for signal `\VexRiscv.\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2948' with positive edge clock. +Creating register for signal `\VexRiscv.\_zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2949' with positive edge clock. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_formal_rawInDecode' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2950' with positive edge clock. +Creating register for signal `\VexRiscv.\CsrPlugin_mepc' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2951' with positive edge clock. +Creating register for signal `\VexRiscv.\CsrPlugin_mip_MEIP' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2952' with positive edge clock. +Creating register for signal `\VexRiscv.\CsrPlugin_mip_MTIP' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2953' with positive edge clock. +Creating register for signal `\VexRiscv.\CsrPlugin_mip_MSIP' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2954' with positive edge clock. +Creating register for signal `\VexRiscv.\CsrPlugin_mcause_interrupt' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2955' with positive edge clock. +Creating register for signal `\VexRiscv.\CsrPlugin_mcause_exceptionCode' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2956' with positive edge clock. +Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_code' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2957' with positive edge clock. +Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_targetPrivilege' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2958' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_LightShifterPlugin_amplitudeReg' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2959' with positive edge clock. +Creating register for signal `\VexRiscv.\HazardSimplePlugin_writeBackBuffer_payload_address' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2960' with positive edge clock. +Creating register for signal `\VexRiscv.\HazardSimplePlugin_writeBackBuffer_payload_data' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2961' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_PC' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2962' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_PC' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2963' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_to_writeBack_PC' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2964' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_INSTRUCTION' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2965' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_INSTRUCTION' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2966' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_to_writeBack_INSTRUCTION' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2967' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2968' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2969' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_to_writeBack_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2970' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_CSR_WRITE_OPCODE' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2971' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_CSR_READ_OPCODE' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2972' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_SRC_USE_SUB_LESS' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2973' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_MEMORY_ENABLE' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2974' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_ENABLE' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2975' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_ENABLE' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2976' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2977' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2978' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_to_writeBack_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2979' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_BYPASSABLE_EXECUTE_STAGE' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2980' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_BYPASSABLE_MEMORY_STAGE' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2981' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_BYPASSABLE_MEMORY_STAGE' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2982' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_MEMORY_STORE' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2983' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_STORE' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2984' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_IS_CSR' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2985' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_ENV_CTRL' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2986' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_ENV_CTRL' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2987' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_to_writeBack_ENV_CTRL' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2988' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_ALU_CTRL' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2989' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_SRC_LESS_UNSIGNED' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2990' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_ALU_BITWISE_CTRL' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2991' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_SHIFT_CTRL' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2992' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_BRANCH_CTRL' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2993' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_RS1' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2994' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_RS2' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2995' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_SRC2_FORCE_ZERO' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2996' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_SRC1' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2997' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_SRC2' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2998' with positive edge clock. +Creating register for signal `\VexRiscv.\decode_to_execute_DO_EBREAK' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$2999' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_ADDRESS_LOW' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$3000' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_ADDRESS_LOW' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$3001' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_REGFILE_WRITE_DATA' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$3002' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_to_writeBack_REGFILE_WRITE_DATA' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$3003' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_BRANCH_DO' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$3004' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_to_memory_BRANCH_CALC' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$3005' with positive edge clock. +Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_READ_DATA' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$3006' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_768' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$3007' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_836' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$3008' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_772' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$3009' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_834' using process `\VexRiscv.$proc$../Murax.v:5280$840'. + created $dff cell `$procdff$3010' with positive edge clock. +Creating register for signal `\VexRiscv.\execute_arbitration_isValid' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3011' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\memory_arbitration_isValid' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3012' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\writeBack_arbitration_isValid' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3013' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_pcReg' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3014' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_correctionReg' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3015' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_booted' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3016' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_inc' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3017' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3018' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3019' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\_zz_IBusSimplePlugin_injector_decodeInput_valid' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3020' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_0' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3021' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_1' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3022' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_2' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3023' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_3' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3024' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_4' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3025' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_5' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3026' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_pending_value' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3027' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3028' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MIE' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3029' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MPIE' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3030' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MPP' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3031' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_mie_MEIE' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3032' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_mie_MTIE' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3033' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_mie_MSIE' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3034' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_mcycle' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3035' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_minstret' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3036' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_valid' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3037' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_0' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3038' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_1' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3039' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_2' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3040' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\CsrPlugin_hadException' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3041' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\execute_CsrPlugin_wfiWake' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3042' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\_zz_2' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3043' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\execute_LightShifterPlugin_isActive' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3044' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\HazardSimplePlugin_writeBackBuffer_valid' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3045' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.\switch_Fetcher_l362' using process `\VexRiscv.$proc$../Murax.v:5018$829'. + created $adff cell `$procdff$3046' with positive edge clock and positive level reset. +Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_ADDR' using process `\VexRiscv.$proc$../Murax.v:3102$374'. + created $dff cell `$procdff$3047' with positive edge clock. +Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_DATA' using process `\VexRiscv.$proc$../Murax.v:3102$374'. + created $dff cell `$procdff$3048' with positive edge clock. +Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN' using process `\VexRiscv.$proc$../Murax.v:3102$374'. + created $dff cell `$procdff$3049' with positive edge clock. +Creating register for signal `\VexRiscv.\_zz_RegFilePlugin_regFile_port1' using process `\VexRiscv.$proc$../Murax.v:3096$372'. + created $dff cell `$procdff$3050' with positive edge clock. +Creating register for signal `\VexRiscv.\_zz_RegFilePlugin_regFile_port0' using process `\VexRiscv.$proc$../Murax.v:3090$370'. + created $dff cell `$procdff$3051' with positive edge clock. +Creating register for signal `\JtagBridge.\jtag_tap_tdoUnbufferd_regNext' using process `\JtagBridge.$proc$../Murax.v:2092$262'. + created $dff cell `$procdff$3052' with negative edge clock. +Creating register for signal `\JtagBridge.\jtag_tap_fsm_state' using process `\JtagBridge.$proc$../Murax.v:2050$256'. + created $dff cell `$procdff$3053' with positive edge clock. +Creating register for signal `\JtagBridge.\jtag_tap_instruction' using process `\JtagBridge.$proc$../Murax.v:2050$256'. + created $dff cell `$procdff$3054' with positive edge clock. +Creating register for signal `\JtagBridge.\jtag_tap_instructionShift' using process `\JtagBridge.$proc$../Murax.v:2050$256'. + created $dff cell `$procdff$3055' with positive edge clock. +Creating register for signal `\JtagBridge.\jtag_tap_bypass' using process `\JtagBridge.$proc$../Murax.v:2050$256'. + created $dff cell `$procdff$3056' with positive edge clock. +Creating register for signal `\JtagBridge.\jtag_idcodeArea_shifter' using process `\JtagBridge.$proc$../Murax.v:2050$256'. + created $dff cell `$procdff$3057' with positive edge clock. +Creating register for signal `\JtagBridge.\jtag_writeArea_valid' using process `\JtagBridge.$proc$../Murax.v:2050$256'. + created $dff cell `$procdff$3058' with positive edge clock. +Creating register for signal `\JtagBridge.\jtag_writeArea_data' using process `\JtagBridge.$proc$../Murax.v:2050$256'. + created $dff cell `$procdff$3059' with positive edge clock. +Creating register for signal `\JtagBridge.\jtag_readArea_full_shifter' using process `\JtagBridge.$proc$../Murax.v:2050$256'. + created $dff cell `$procdff$3060' with positive edge clock. +Creating register for signal `\JtagBridge.\system_rsp_valid' using process `\JtagBridge.$proc$../Murax.v:2039$255'. + created $dff cell `$procdff$3061' with positive edge clock. +Creating register for signal `\JtagBridge.\system_rsp_payload_error' using process `\JtagBridge.$proc$../Murax.v:2039$255'. + created $dff cell `$procdff$3062' with positive edge clock. +Creating register for signal `\JtagBridge.\system_rsp_payload_data' using process `\JtagBridge.$proc$../Murax.v:2039$255'. + created $dff cell `$procdff$3063' with positive edge clock. +Creating register for signal `\SystemDebugger.\dispatcher_dataShifter' using process `\SystemDebugger.$proc$../Murax.v:1718$213'. + created $dff cell `$procdff$3064' with positive edge clock. +Creating register for signal `\SystemDebugger.\dispatcher_headerShifter' using process `\SystemDebugger.$proc$../Murax.v:1718$213'. + created $dff cell `$procdff$3065' with positive edge clock. +Creating register for signal `\SystemDebugger.\dispatcher_dataLoaded' using process `\SystemDebugger.$proc$../Murax.v:1692$211'. + created $adff cell `$procdff$3066' with positive edge clock and positive level reset. +Creating register for signal `\SystemDebugger.\dispatcher_headerLoaded' using process `\SystemDebugger.$proc$../Murax.v:1692$211'. + created $adff cell `$procdff$3067' with positive edge clock and positive level reset. +Creating register for signal `\SystemDebugger.\dispatcher_counter' using process `\SystemDebugger.$proc$../Murax.v:1692$211'. + created $adff cell `$procdff$3068' with positive edge clock and positive level reset. +Creating register for signal `\MuraxPipelinedMemoryBusRam.\_zz_io_bus_rsp_valid' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1633$198'. + created $adff cell `$procdff$3069' with positive edge clock and positive level reset. +Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol0$../Murax.v:1614$153_ADDR' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'. + created $dff cell `$procdff$3070' with positive edge clock. +Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol0$../Murax.v:1614$153_DATA' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'. + created $dff cell `$procdff$3071' with positive edge clock. +Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol0$../Murax.v:1614$153_EN' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'. + created $dff cell `$procdff$3072' with positive edge clock. +Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol1$../Murax.v:1617$154_ADDR' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'. + created $dff cell `$procdff$3073' with positive edge clock. +Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol1$../Murax.v:1617$154_DATA' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'. + created $dff cell `$procdff$3074' with positive edge clock. +Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol1$../Murax.v:1617$154_EN' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'. + created $dff cell `$procdff$3075' with positive edge clock. +Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol2$../Murax.v:1620$155_ADDR' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'. + created $dff cell `$procdff$3076' with positive edge clock. +Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol2$../Murax.v:1620$155_DATA' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'. + created $dff cell `$procdff$3077' with positive edge clock. +Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol2$../Murax.v:1620$155_EN' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'. + created $dff cell `$procdff$3078' with positive edge clock. +Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol3$../Murax.v:1623$156_ADDR' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'. + created $dff cell `$procdff$3079' with positive edge clock. +Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol3$../Murax.v:1623$156_DATA' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'. + created $dff cell `$procdff$3080' with positive edge clock. +Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol3$../Murax.v:1623$156_EN' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'. + created $dff cell `$procdff$3081' with positive edge clock. +Creating register for signal `\MuraxPipelinedMemoryBusRam.\_zz_ramsymbol_read' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1603$158'. + created $dff cell `$procdff$3082' with positive edge clock. +Creating register for signal `\MuraxPipelinedMemoryBusRam.\_zz_ramsymbol_read_1' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1603$158'. + created $dff cell `$procdff$3083' with positive edge clock. +Creating register for signal `\MuraxPipelinedMemoryBusRam.\_zz_ramsymbol_read_2' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1603$158'. + created $dff cell `$procdff$3084' with positive edge clock. +Creating register for signal `\MuraxPipelinedMemoryBusRam.\_zz_ramsymbol_read_3' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1603$158'. + created $dff cell `$procdff$3085' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusToApbBridge.\io_pipelinedMemoryBus_cmd_rData_write' using process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1557$152'. + created $dff cell `$procdff$3086' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusToApbBridge.\io_pipelinedMemoryBus_cmd_rData_address' using process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1557$152'. + created $dff cell `$procdff$3087' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusToApbBridge.\io_pipelinedMemoryBus_cmd_rData_data' using process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1557$152'. + created $dff cell `$procdff$3088' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusToApbBridge.\io_pipelinedMemoryBus_cmd_rData_mask' using process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1557$152'. + created $dff cell `$procdff$3089' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_rsp_regNext_payload_data' using process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1557$152'. + created $dff cell `$procdff$3090' with positive edge clock. +Creating register for signal `\PipelinedMemoryBusToApbBridge.\io_pipelinedMemoryBus_cmd_rValid' using process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1534$151'. + created $adff cell `$procdff$3091' with positive edge clock and positive level reset. +Creating register for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_rsp_regNext_valid' using process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1534$151'. + created $adff cell `$procdff$3092' with positive edge clock and positive level reset. +Creating register for signal `\PipelinedMemoryBusToApbBridge.\state' using process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1534$151'. + created $adff cell `$procdff$3093' with positive edge clock and positive level reset. +Creating register for signal `\Apb3Gpio.\io_gpio_write_driver' using process `\Apb3Gpio.$proc$../Murax.v:1433$142'. + created $dff cell `$procdff$3094' with positive edge clock. +Creating register for signal `\Apb3Gpio.\io_gpio_writeEnable_driver' using process `\Apb3Gpio.$proc$../Murax.v:1417$141'. + created $adff cell `$procdff$3095' with positive edge clock and positive level reset. +Creating register for signal `\Apb3UartCtrl.\uartCtrl_1_io_readBreak_regNext' using process `\Apb3UartCtrl.$proc$../Murax.v:1353$127'. + created $dff cell `$procdff$3096' with positive edge clock. +Creating register for signal `\Apb3UartCtrl.\bridge_interruptCtrl_writeIntEnable' using process `\Apb3UartCtrl.$proc$../Murax.v:1297$126'. + created $adff cell `$procdff$3097' with positive edge clock and positive level reset. +Creating register for signal `\Apb3UartCtrl.\bridge_interruptCtrl_readIntEnable' using process `\Apb3UartCtrl.$proc$../Murax.v:1297$126'. + created $adff cell `$procdff$3098' with positive edge clock and positive level reset. +Creating register for signal `\Apb3UartCtrl.\bridge_misc_readError' using process `\Apb3UartCtrl.$proc$../Murax.v:1297$126'. + created $adff cell `$procdff$3099' with positive edge clock and positive level reset. +Creating register for signal `\Apb3UartCtrl.\bridge_misc_readOverflowError' using process `\Apb3UartCtrl.$proc$../Murax.v:1297$126'. + created $adff cell `$procdff$3100' with positive edge clock and positive level reset. +Creating register for signal `\Apb3UartCtrl.\bridge_misc_breakDetected' using process `\Apb3UartCtrl.$proc$../Murax.v:1297$126'. + created $adff cell `$procdff$3101' with positive edge clock and positive level reset. +Creating register for signal `\Apb3UartCtrl.\bridge_misc_doBreak' using process `\Apb3UartCtrl.$proc$../Murax.v:1297$126'. + created $adff cell `$procdff$3102' with positive edge clock and positive level reset. +Creating register for signal `\MuraxApb3Timer.\_zz_io_limit' using process `\MuraxApb3Timer.$proc$../Murax.v:952$91'. + created $dff cell `$procdff$3103' with positive edge clock. +Creating register for signal `\MuraxApb3Timer.\timerA_io_limit_driver' using process `\MuraxApb3Timer.$proc$../Murax.v:952$91'. + created $dff cell `$procdff$3104' with positive edge clock. +Creating register for signal `\MuraxApb3Timer.\timerB_io_limit_driver' using process `\MuraxApb3Timer.$proc$../Murax.v:952$91'. + created $dff cell `$procdff$3105' with positive edge clock. +Creating register for signal `\MuraxApb3Timer.\timerABridge_ticksEnable' using process `\MuraxApb3Timer.$proc$../Murax.v:920$90'. + created $adff cell `$procdff$3106' with positive edge clock and positive level reset. +Creating register for signal `\MuraxApb3Timer.\timerABridge_clearsEnable' using process `\MuraxApb3Timer.$proc$../Murax.v:920$90'. + created $adff cell `$procdff$3107' with positive edge clock and positive level reset. +Creating register for signal `\MuraxApb3Timer.\timerBBridge_ticksEnable' using process `\MuraxApb3Timer.$proc$../Murax.v:920$90'. + created $adff cell `$procdff$3108' with positive edge clock and positive level reset. +Creating register for signal `\MuraxApb3Timer.\timerBBridge_clearsEnable' using process `\MuraxApb3Timer.$proc$../Murax.v:920$90'. + created $adff cell `$procdff$3109' with positive edge clock and positive level reset. +Creating register for signal `\MuraxApb3Timer.\interruptCtrl_1_io_masks_driver' using process `\MuraxApb3Timer.$proc$../Murax.v:920$90'. + created $adff cell `$procdff$3110' with positive edge clock and positive level reset. +Creating register for signal `\Apb3Router.\selIndex' using process `\Apb3Router.$proc$../Murax.v:633$42'. + created $dff cell `$procdff$3111' with positive edge clock. +Creating register for signal `\Murax.\system_cpu_debug_bus_cmd_fire_regNext' using process `\Murax.$proc$../Murax.v:538$39'. + created $adff cell `$procdff$3112' with positive edge clock and positive level reset. +Creating register for signal `\Murax.\system_cpu_debug_resetOut_regNext' using process `\Murax.$proc$../Murax.v:534$38'. + created $dff cell `$procdff$3113' with positive edge clock. +Creating register for signal `\Murax.\system_cpu_dBus_cmd_rData_wr' using process `\Murax.$proc$../Murax.v:522$37'. + created $dff cell `$procdff$3114' with positive edge clock. +Creating register for signal `\Murax.\system_cpu_dBus_cmd_rData_address' using process `\Murax.$proc$../Murax.v:522$37'. + created $dff cell `$procdff$3115' with positive edge clock. +Creating register for signal `\Murax.\system_cpu_dBus_cmd_rData_data' using process `\Murax.$proc$../Murax.v:522$37'. + created $dff cell `$procdff$3116' with positive edge clock. +Creating register for signal `\Murax.\system_cpu_dBus_cmd_rData_size' using process `\Murax.$proc$../Murax.v:522$37'. + created $dff cell `$procdff$3117' with positive edge clock. +Creating register for signal `\Murax.\system_mainBusDecoder_logic_rspSourceId' using process `\Murax.$proc$../Murax.v:522$37'. + created $dff cell `$procdff$3118' with positive edge clock. +Creating register for signal `\Murax.\system_cpu_dBus_cmd_rValid' using process `\Murax.$proc$../Murax.v:497$36'. + created $adff cell `$procdff$3119' with positive edge clock and positive level reset. +Creating register for signal `\Murax.\system_mainBusDecoder_logic_rspPending' using process `\Murax.$proc$../Murax.v:497$36'. + created $adff cell `$procdff$3120' with positive edge clock and positive level reset. +Creating register for signal `\Murax.\system_mainBusDecoder_logic_rspNoHit' using process `\Murax.$proc$../Murax.v:497$36'. + created $adff cell `$procdff$3121' with positive edge clock and positive level reset. +Creating register for signal `\Murax.\resetCtrl_mainClkReset' using process `\Murax.$proc$../Murax.v:489$35'. + created $dff cell `$procdff$3122' with positive edge clock. +Creating register for signal `\Murax.\resetCtrl_systemReset' using process `\Murax.$proc$../Murax.v:489$35'. + created $dff cell `$procdff$3123' with positive edge clock. +Creating register for signal `\Murax.\resetCtrl_systemClkResetCounter' using process `\Murax.$proc$../Murax.v:480$33'. + created $dff cell `$procdff$3124' with positive edge clock. + +3.1.9. Executing PROC_MEMWR pass (convert process memory writes to cells). + +3.1.10. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `BufferCC.$proc$../Murax.v:6826$1043'. +Removing empty process `BufferCC_1.$proc$../Murax.v:6807$1042'. +Found and cleaned up 7 empty switches in `\UartCtrlTx.$proc$../Murax.v:6760$1038'. +Removing empty process `UartCtrlTx.$proc$../Murax.v:6760$1038'. +Found and cleaned up 9 empty switches in `\UartCtrlTx.$proc$../Murax.v:6714$1034'. +Removing empty process `UartCtrlTx.$proc$../Murax.v:6714$1034'. +Found and cleaned up 3 empty switches in `\UartCtrlTx.$proc$../Murax.v:6688$1027'. +Removing empty process `UartCtrlTx.$proc$../Murax.v:6688$1027'. +Found and cleaned up 1 empty switch in `\UartCtrlTx.$proc$../Murax.v:6669$1025'. +Removing empty process `UartCtrlTx.$proc$../Murax.v:6669$1025'. +Found and cleaned up 2 empty switches in `\UartCtrlTx.$proc$../Murax.v:6658$1023'. +Removing empty process `UartCtrlTx.$proc$../Murax.v:6658$1023'. +Found and cleaned up 1 empty switch in `\UartCtrlTx.$proc$../Murax.v:6648$1020'. +Removing empty process `UartCtrlTx.$proc$../Murax.v:6648$1020'. +Found and cleaned up 10 empty switches in `\UartCtrlRx.$proc$../Murax.v:6519$998'. +Removing empty process `UartCtrlRx.$proc$../Murax.v:6519$998'. +Found and cleaned up 16 empty switches in `\UartCtrlRx.$proc$../Murax.v:6440$985'. +Removing empty process `UartCtrlRx.$proc$../Murax.v:6440$985'. +Found and cleaned up 2 empty switches in `\UartCtrlRx.$proc$../Murax.v:6418$970'. +Removing empty process `UartCtrlRx.$proc$../Murax.v:6418$970'. +Found and cleaned up 5 empty switches in `\UartCtrlRx.$proc$../Murax.v:6389$968'. +Removing empty process `UartCtrlRx.$proc$../Murax.v:6389$968'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$../Murax.v:6283$963'. +Removing empty process `StreamFifoLowLatency.$proc$../Murax.v:6283$963'. +Found and cleaned up 2 empty switches in `\StreamFifoLowLatency.$proc$../Murax.v:6270$962'. +Removing empty process `StreamFifoLowLatency.$proc$../Murax.v:6270$962'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$../Murax.v:6259$959'. +Removing empty process `StreamFifoLowLatency.$proc$../Murax.v:6259$959'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$../Murax.v:6251$958'. +Removing empty process `StreamFifoLowLatency.$proc$../Murax.v:6251$958'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$../Murax.v:6243$957'. +Removing empty process `StreamFifoLowLatency.$proc$../Murax.v:6243$957'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$../Murax.v:6224$948'. +Removing empty process `StreamFifoLowLatency.$proc$../Murax.v:6224$948'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$../Murax.v:6217$947'. +Removing empty process `StreamFifoLowLatency.$proc$../Murax.v:6217$947'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$../Murax.v:6208$945'. +Removing empty process `StreamFifoLowLatency.$proc$../Murax.v:6208$945'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$../Murax.v:6201$944'. +Removing empty process `StreamFifoLowLatency.$proc$../Murax.v:6201$944'. +Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$../Murax.v:6194$943'. +Removing empty process `StreamFifoLowLatency.$proc$../Murax.v:6194$943'. +Removing empty process `FlowCCByToggle.$proc$../Murax.v:6145$941'. +Found and cleaned up 1 empty switch in `\FlowCCByToggle.$proc$../Murax.v:6137$940'. +Removing empty process `FlowCCByToggle.$proc$../Murax.v:6137$940'. +Found and cleaned up 1 empty switch in `\FlowCCByToggle.$proc$../Murax.v:6129$938'. +Removing empty process `FlowCCByToggle.$proc$../Murax.v:6129$938'. +Removing empty process `BufferCC_2.$proc$../Murax.v:6076$936'. +Found and cleaned up 1 empty switch in `\UartCtrl.$proc$../Murax.v:6049$934'. +Removing empty process `UartCtrl.$proc$../Murax.v:6049$934'. +Found and cleaned up 1 empty switch in `\UartCtrl.$proc$../Murax.v:6035$933'. +Removing empty process `UartCtrl.$proc$../Murax.v:6035$933'. +Found and cleaned up 1 empty switch in `\UartCtrl.$proc$../Murax.v:6028$932'. +Removing empty process `UartCtrl.$proc$../Murax.v:6028$932'. +Found and cleaned up 2 empty switches in `\StreamFifo.$proc$../Murax.v:5914$929'. +Removing empty process `StreamFifo.$proc$../Murax.v:5914$929'. +Found and cleaned up 1 empty switch in `\StreamFifo.$proc$../Murax.v:5895$910'. +Removing empty process `StreamFifo.$proc$../Murax.v:5895$910'. +Found and cleaned up 1 empty switch in `\StreamFifo.$proc$../Murax.v:5886$907'. +Removing empty process `StreamFifo.$proc$../Murax.v:5886$907'. +Found and cleaned up 1 empty switch in `\StreamFifo.$proc$../Murax.v:5879$906'. +Removing empty process `StreamFifo.$proc$../Murax.v:5879$906'. +Found and cleaned up 1 empty switch in `\StreamFifo.$proc$../Murax.v:5872$904'. +Removing empty process `StreamFifo.$proc$../Murax.v:5872$904'. +Found and cleaned up 1 empty switch in `\StreamFifo.$proc$../Murax.v:5863$901'. +Removing empty process `StreamFifo.$proc$../Murax.v:5863$901'. +Found and cleaned up 1 empty switch in `\StreamFifo.$proc$../Murax.v:5856$900'. +Removing empty process `StreamFifo.$proc$../Murax.v:5856$900'. +Found and cleaned up 1 empty switch in `\StreamFifo.$proc$../Murax.v:5849$899'. +Removing empty process `StreamFifo.$proc$../Murax.v:5849$899'. +Found and cleaned up 1 empty switch in `\StreamFifo.$proc$../Murax.v:5843$892'. +Removing empty process `StreamFifo.$proc$../Murax.v:5843$892'. +Found and cleaned up 1 empty switch in `\StreamFifo.$proc$../Murax.v:5837$890'. +Removing empty process `StreamFifo.$proc$../Murax.v:5837$890'. +Found and cleaned up 1 empty switch in `\Prescaler.$proc$../Murax.v:5773$886'. +Removing empty process `Prescaler.$proc$../Murax.v:5773$886'. +Found and cleaned up 2 empty switches in `\Timer.$proc$../Murax.v:5748$882'. +Removing empty process `Timer.$proc$../Murax.v:5748$882'. +Found and cleaned up 2 empty switches in `\Timer.$proc$../Murax.v:5735$881'. +Removing empty process `Timer.$proc$../Murax.v:5735$881'. +Removing empty process `InterruptCtrl.$proc$../Murax.v:5701$872'. +Removing empty process `BufferCC_3.$proc$../Murax.v:5681$870'. +Found and cleaned up 2 empty switches in `\MuraxMasterArbiter.$proc$../Murax.v:5653$869'. +Removing empty process `MuraxMasterArbiter.$proc$../Murax.v:5653$869'. +Found and cleaned up 1 empty switch in `\MuraxMasterArbiter.$proc$../Murax.v:5637$860'. +Removing empty process `MuraxMasterArbiter.$proc$../Murax.v:5637$860'. +Found and cleaned up 1 empty switch in `\MuraxMasterArbiter.$proc$../Murax.v:5630$857'. +Removing empty process `MuraxMasterArbiter.$proc$../Murax.v:5630$857'. +Found and cleaned up 1 empty switch in `\MuraxMasterArbiter.$proc$../Murax.v:5615$855'. +Removing empty process `MuraxMasterArbiter.$proc$../Murax.v:5615$855'. +Found and cleaned up 1 empty switch in `\MuraxMasterArbiter.$proc$../Murax.v:5605$851'. +Removing empty process `MuraxMasterArbiter.$proc$../Murax.v:5605$851'. +Found and cleaned up 17 empty switches in `\VexRiscv.$proc$../Murax.v:5502$850'. +Removing empty process `VexRiscv.$proc$../Murax.v:5502$850'. +Found and cleaned up 3 empty switches in `\VexRiscv.$proc$../Murax.v:5485$847'. +Removing empty process `VexRiscv.$proc$../Murax.v:5485$847'. +Found and cleaned up 63 empty switches in `\VexRiscv.$proc$../Murax.v:5280$840'. +Removing empty process `VexRiscv.$proc$../Murax.v:5280$840'. +Found and cleaned up 62 empty switches in `\VexRiscv.$proc$../Murax.v:5018$829'. +Removing empty process `VexRiscv.$proc$../Murax.v:5018$829'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:5007$821'. +Removing empty process `VexRiscv.$proc$../Murax.v:5007$821'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4998$820'. +Removing empty process `VexRiscv.$proc$../Murax.v:4998$820'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4989$819'. +Removing empty process `VexRiscv.$proc$../Murax.v:4989$819'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4980$818'. +Removing empty process `VexRiscv.$proc$../Murax.v:4980$818'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4963$811'. +Removing empty process `VexRiscv.$proc$../Murax.v:4963$811'. +Found and cleaned up 3 empty switches in `\VexRiscv.$proc$../Murax.v:4841$690'. +Removing empty process `VexRiscv.$proc$../Murax.v:4841$690'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4829$688'. +Removing empty process `VexRiscv.$proc$../Murax.v:4829$688'. +Found and cleaned up 3 empty switches in `\VexRiscv.$proc$../Murax.v:4814$687'. +Removing empty process `VexRiscv.$proc$../Murax.v:4814$687'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4794$679'. +Removing empty process `VexRiscv.$proc$../Murax.v:4794$679'. +Removing empty process `VexRiscv.$proc$../Murax.v:4772$678'. +Removing empty process `VexRiscv.$proc$../Murax.v:4748$677'. +Removing empty process `VexRiscv.$proc$../Murax.v:4733$676'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4714$673'. +Removing empty process `VexRiscv.$proc$../Murax.v:4714$673'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4697$670'. +Removing empty process `VexRiscv.$proc$../Murax.v:4697$670'. +Found and cleaned up 12 empty switches in `\VexRiscv.$proc$../Murax.v:4642$648'. +Removing empty process `VexRiscv.$proc$../Murax.v:4642$648'. +Found and cleaned up 12 empty switches in `\VexRiscv.$proc$../Murax.v:4609$647'. +Removing empty process `VexRiscv.$proc$../Murax.v:4609$647'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4596$643'. +Removing empty process `VexRiscv.$proc$../Murax.v:4596$643'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4583$632'. +Removing empty process `VexRiscv.$proc$../Murax.v:4583$632'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4566$631'. +Removing empty process `VexRiscv.$proc$../Murax.v:4566$631'. +Removing empty process `VexRiscv.$proc$../Murax.v:4543$630'. +Removing empty process `VexRiscv.$proc$../Murax.v:4519$629'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4501$628'. +Removing empty process `VexRiscv.$proc$../Murax.v:4501$628'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4487$627'. +Removing empty process `VexRiscv.$proc$../Murax.v:4487$627'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4473$623'. +Removing empty process `VexRiscv.$proc$../Murax.v:4473$623'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4466$622'. +Removing empty process `VexRiscv.$proc$../Murax.v:4466$622'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4459$621'. +Removing empty process `VexRiscv.$proc$../Murax.v:4459$621'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4452$619'. +Removing empty process `VexRiscv.$proc$../Murax.v:4452$619'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4411$589'. +Removing empty process `VexRiscv.$proc$../Murax.v:4411$589'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4399$581'. +Removing empty process `VexRiscv.$proc$../Murax.v:4399$581'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4392$578'. +Removing empty process `VexRiscv.$proc$../Murax.v:4392$578'. +Found and cleaned up 2 empty switches in `\VexRiscv.$proc$../Murax.v:4381$574'. +Removing empty process `VexRiscv.$proc$../Murax.v:4381$574'. +Found and cleaned up 8 empty switches in `\VexRiscv.$proc$../Murax.v:4354$573'. +Removing empty process `VexRiscv.$proc$../Murax.v:4354$573'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4337$560'. +Removing empty process `VexRiscv.$proc$../Murax.v:4337$560'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4326$559'. +Removing empty process `VexRiscv.$proc$../Murax.v:4326$559'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4316$556'. +Removing empty process `VexRiscv.$proc$../Murax.v:4316$556'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4291$537'. +Removing empty process `VexRiscv.$proc$../Murax.v:4291$537'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4276$535'. +Removing empty process `VexRiscv.$proc$../Murax.v:4276$535'. +Removing empty process `VexRiscv.$proc$../Murax.v:4256$534'. +Removing empty process `VexRiscv.$proc$../Murax.v:4227$531'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4208$528'. +Removing empty process `VexRiscv.$proc$../Murax.v:4208$528'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4191$520'. +Removing empty process `VexRiscv.$proc$../Murax.v:4191$520'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4175$512'. +Removing empty process `VexRiscv.$proc$../Murax.v:4175$512'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4165$502'. +Removing empty process `VexRiscv.$proc$../Murax.v:4165$502'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4138$493'. +Removing empty process `VexRiscv.$proc$../Murax.v:4138$493'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4102$477'. +Removing empty process `VexRiscv.$proc$../Murax.v:4102$477'. +Found and cleaned up 2 empty switches in `\VexRiscv.$proc$../Murax.v:4073$461'. +Removing empty process `VexRiscv.$proc$../Murax.v:4073$461'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4045$447'. +Removing empty process `VexRiscv.$proc$../Murax.v:4045$447'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4026$438'. +Removing empty process `VexRiscv.$proc$../Murax.v:4026$438'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4017$436'. +Removing empty process `VexRiscv.$proc$../Murax.v:4017$436'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4007$431'. +Removing empty process `VexRiscv.$proc$../Murax.v:4007$431'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3998$428'. +Removing empty process `VexRiscv.$proc$../Murax.v:3998$428'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3987$424'. +Removing empty process `VexRiscv.$proc$../Murax.v:3987$424'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3980$423'. +Removing empty process `VexRiscv.$proc$../Murax.v:3980$423'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3973$422'. +Removing empty process `VexRiscv.$proc$../Murax.v:3973$422'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3966$421'. +Removing empty process `VexRiscv.$proc$../Murax.v:3966$421'. +Found and cleaned up 3 empty switches in `\VexRiscv.$proc$../Murax.v:3950$420'. +Removing empty process `VexRiscv.$proc$../Murax.v:3950$420'. +Found and cleaned up 2 empty switches in `\VexRiscv.$proc$../Murax.v:3940$419'. +Removing empty process `VexRiscv.$proc$../Murax.v:3940$419'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3933$418'. +Removing empty process `VexRiscv.$proc$../Murax.v:3933$418'. +Found and cleaned up 2 empty switches in `\VexRiscv.$proc$../Murax.v:3920$417'. +Removing empty process `VexRiscv.$proc$../Murax.v:3920$417'. +Found and cleaned up 6 empty switches in `\VexRiscv.$proc$../Murax.v:3899$416'. +Removing empty process `VexRiscv.$proc$../Murax.v:3899$416'. +Found and cleaned up 2 empty switches in `\VexRiscv.$proc$../Murax.v:3885$415'. +Removing empty process `VexRiscv.$proc$../Murax.v:3885$415'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3877$414'. +Removing empty process `VexRiscv.$proc$../Murax.v:3877$414'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3868$413'. +Removing empty process `VexRiscv.$proc$../Murax.v:3868$413'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3860$412'. +Removing empty process `VexRiscv.$proc$../Murax.v:3860$412'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3852$411'. +Removing empty process `VexRiscv.$proc$../Murax.v:3852$411'. +Found and cleaned up 2 empty switches in `\VexRiscv.$proc$../Murax.v:3843$410'. +Removing empty process `VexRiscv.$proc$../Murax.v:3843$410'. +Found and cleaned up 2 empty switches in `\VexRiscv.$proc$../Murax.v:3834$409'. +Removing empty process `VexRiscv.$proc$../Murax.v:3834$409'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3827$408'. +Removing empty process `VexRiscv.$proc$../Murax.v:3827$408'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3820$407'. +Removing empty process `VexRiscv.$proc$../Murax.v:3820$407'. +Found and cleaned up 5 empty switches in `\VexRiscv.$proc$../Murax.v:3803$406'. +Removing empty process `VexRiscv.$proc$../Murax.v:3803$406'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3794$405'. +Removing empty process `VexRiscv.$proc$../Murax.v:3794$405'. +Found and cleaned up 3 empty switches in `\VexRiscv.$proc$../Murax.v:3781$404'. +Removing empty process `VexRiscv.$proc$../Murax.v:3781$404'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3770$403'. +Removing empty process `VexRiscv.$proc$../Murax.v:3770$403'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3759$402'. +Removing empty process `VexRiscv.$proc$../Murax.v:3759$402'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3741$401'. +Removing empty process `VexRiscv.$proc$../Murax.v:3741$401'. +Found and cleaned up 2 empty switches in `\VexRiscv.$proc$../Murax.v:3724$400'. +Removing empty process `VexRiscv.$proc$../Murax.v:3724$400'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3717$399'. +Removing empty process `VexRiscv.$proc$../Murax.v:3717$399'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3709$397'. +Removing empty process `VexRiscv.$proc$../Murax.v:3709$397'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3102$374'. +Removing empty process `VexRiscv.$proc$../Murax.v:3102$374'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3096$372'. +Removing empty process `VexRiscv.$proc$../Murax.v:3096$372'. +Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3090$370'. +Removing empty process `VexRiscv.$proc$../Murax.v:3090$370'. +Removing empty process `JtagBridge.$proc$../Murax.v:2092$262'. +Found and cleaned up 8 empty switches in `\JtagBridge.$proc$../Murax.v:2050$256'. +Removing empty process `JtagBridge.$proc$../Murax.v:2050$256'. +Found and cleaned up 2 empty switches in `\JtagBridge.$proc$../Murax.v:2039$255'. +Removing empty process `JtagBridge.$proc$../Murax.v:2039$255'. +Found and cleaned up 3 empty switches in `\JtagBridge.$proc$../Murax.v:1995$235'. +Removing empty process `JtagBridge.$proc$../Murax.v:1995$235'. +Found and cleaned up 2 empty switches in `\JtagBridge.$proc$../Murax.v:1977$234'. +Removing empty process `JtagBridge.$proc$../Murax.v:1977$234'. +Found and cleaned up 1 empty switch in `\JtagBridge.$proc$../Murax.v:1923$217'. +Removing empty process `JtagBridge.$proc$../Murax.v:1923$217'. +Found and cleaned up 2 empty switches in `\SystemDebugger.$proc$../Murax.v:1718$213'. +Removing empty process `SystemDebugger.$proc$../Murax.v:1718$213'. +Found and cleaned up 5 empty switches in `\SystemDebugger.$proc$../Murax.v:1692$211'. +Removing empty process `SystemDebugger.$proc$../Murax.v:1692$211'. +Removing empty process `MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1633$198'. +Found and cleaned up 4 empty switches in `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'. +Removing empty process `MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'. +Found and cleaned up 1 empty switch in `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1603$158'. +Removing empty process `MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1603$158'. +Removing empty process `MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1600$157'. +Found and cleaned up 1 empty switch in `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1557$152'. +Removing empty process `PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1557$152'. +Found and cleaned up 4 empty switches in `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1534$151'. +Removing empty process `PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1534$151'. +Found and cleaned up 2 empty switches in `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1523$147'. +Removing empty process `PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1523$147'. +Found and cleaned up 2 empty switches in `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1509$145'. +Removing empty process `PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1509$145'. +Found and cleaned up 2 empty switches in `\Apb3Gpio.$proc$../Murax.v:1433$142'. +Removing empty process `Apb3Gpio.$proc$../Murax.v:1433$142'. +Found and cleaned up 2 empty switches in `\Apb3Gpio.$proc$../Murax.v:1417$141'. +Removing empty process `Apb3Gpio.$proc$../Murax.v:1417$141'. +Found and cleaned up 1 empty switch in `\Apb3Gpio.$proc$../Murax.v:1393$128'. +Removing empty process `Apb3Gpio.$proc$../Murax.v:1393$128'. +Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1353$127'. +Found and cleaned up 15 empty switches in `\Apb3UartCtrl.$proc$../Murax.v:1297$126'. +Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1297$126'. +Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$../Murax.v:1282$125'. +Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1282$125'. +Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$../Murax.v:1268$124'. +Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1268$124'. +Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$../Murax.v:1254$123'. +Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1254$123'. +Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$../Murax.v:1238$118'. +Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1238$118'. +Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$../Murax.v:1224$117'. +Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1224$117'. +Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$../Murax.v:1208$112'. +Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1208$112'. +Found and cleaned up 1 empty switch in `\Apb3UartCtrl.$proc$../Murax.v:1200$111'. +Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1200$111'. +Found and cleaned up 1 empty switch in `\Apb3UartCtrl.$proc$../Murax.v:1193$110'. +Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1193$110'. +Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$../Murax.v:1177$109'. +Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1177$109'. +Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1173$108'. +Found and cleaned up 1 empty switch in `\Apb3UartCtrl.$proc$../Murax.v:1141$94'. +Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1141$94'. +Found and cleaned up 4 empty switches in `\MuraxApb3Timer.$proc$../Murax.v:952$91'. +Removing empty process `MuraxApb3Timer.$proc$../Murax.v:952$91'. +Found and cleaned up 4 empty switches in `\MuraxApb3Timer.$proc$../Murax.v:920$90'. +Removing empty process `MuraxApb3Timer.$proc$../Murax.v:920$90'. +Removing empty process `MuraxApb3Timer.$proc$../Murax.v:914$88'. +Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$../Murax.v:901$87'. +Removing empty process `MuraxApb3Timer.$proc$../Murax.v:901$87'. +Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$../Murax.v:886$81'. +Removing empty process `MuraxApb3Timer.$proc$../Murax.v:886$81'. +Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$../Murax.v:873$80'. +Removing empty process `MuraxApb3Timer.$proc$../Murax.v:873$80'. +Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$../Murax.v:863$79'. +Removing empty process `MuraxApb3Timer.$proc$../Murax.v:863$79'. +Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$../Murax.v:848$73'. +Removing empty process `MuraxApb3Timer.$proc$../Murax.v:848$73'. +Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$../Murax.v:835$72'. +Removing empty process `MuraxApb3Timer.$proc$../Murax.v:835$72'. +Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$../Murax.v:825$71'. +Removing empty process `MuraxApb3Timer.$proc$../Murax.v:825$71'. +Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$../Murax.v:812$70'. +Removing empty process `MuraxApb3Timer.$proc$../Murax.v:812$70'. +Found and cleaned up 1 empty switch in `\MuraxApb3Timer.$proc$../Murax.v:770$57'. +Removing empty process `MuraxApb3Timer.$proc$../Murax.v:770$57'. +Found and cleaned up 1 empty switch in `\Apb3Decoder.$proc$../Murax.v:679$54'. +Removing empty process `Apb3Decoder.$proc$../Murax.v:679$54'. +Found and cleaned up 1 empty switch in `\Apb3Decoder.$proc$../Murax.v:671$53'. +Removing empty process `Apb3Decoder.$proc$../Murax.v:671$53'. +Removing empty process `Apb3Decoder.$proc$../Murax.v:665$43'. +Removing empty process `Apb3Router.$proc$../Murax.v:633$42'. +Found and cleaned up 1 empty switch in `\Apb3Router.$proc$../Murax.v:593$41'. +Removing empty process `Apb3Router.$proc$../Murax.v:593$41'. +Removing empty process `Murax.$proc$../Murax.v:0$40'. +Removing empty process `Murax.$proc$../Murax.v:538$39'. +Removing empty process `Murax.$proc$../Murax.v:534$38'. +Found and cleaned up 2 empty switches in `\Murax.$proc$../Murax.v:522$37'. +Removing empty process `Murax.$proc$../Murax.v:522$37'. +Found and cleaned up 5 empty switches in `\Murax.$proc$../Murax.v:497$36'. +Removing empty process `Murax.$proc$../Murax.v:497$36'. +Found and cleaned up 1 empty switch in `\Murax.$proc$../Murax.v:489$35'. +Removing empty process `Murax.$proc$../Murax.v:489$35'. +Found and cleaned up 2 empty switches in `\Murax.$proc$../Murax.v:480$33'. +Removing empty process `Murax.$proc$../Murax.v:480$33'. +Found and cleaned up 1 empty switch in `\Murax.$proc$../Murax.v:467$19'. +Removing empty process `Murax.$proc$../Murax.v:467$19'. +Found and cleaned up 1 empty switch in `\Murax.$proc$../Murax.v:458$15'. +Removing empty process `Murax.$proc$../Murax.v:458$15'. +Found and cleaned up 1 empty switch in `\Murax.$proc$../Murax.v:449$11'. +Removing empty process `Murax.$proc$../Murax.v:449$11'. +Found and cleaned up 1 empty switch in `\Murax.$proc$../Murax.v:419$5'. +Removing empty process `Murax.$proc$../Murax.v:419$5'. +Found and cleaned up 1 empty switch in `\Murax.$proc$../Murax.v:412$4'. +Removing empty process `Murax.$proc$../Murax.v:412$4'. +Found and cleaned up 1 empty switch in `\Murax.$proc$../Murax.v:402$2'. +Removing empty process `Murax.$proc$../Murax.v:402$2'. +Found and cleaned up 1 empty switch in `\Murax.$proc$../Murax.v:395$1'. +Removing empty process `Murax.$proc$../Murax.v:395$1'. +Cleaned up 486 empty switches. + +3.1.11. Executing OPT_EXPR pass (perform const folding). +Optimizing module BufferCC. +Optimizing module BufferCC_1. +Optimizing module UartCtrlTx. + +Optimizing module UartCtrlRx. + +Optimizing module StreamFifoLowLatency. + +Optimizing module FlowCCByToggle. +Optimizing module BufferCC_2. +Optimizing module UartCtrl. + +Optimizing module StreamFifo. + +Optimizing module Prescaler. +Optimizing module Timer. +Optimizing module InterruptCtrl. +Optimizing module BufferCC_3. +Optimizing module MuraxMasterArbiter. + +Optimizing module VexRiscv. + +Optimizing module JtagBridge. + +Optimizing module SystemDebugger. + +Optimizing module MuraxPipelinedMemoryBusRam. + +Optimizing module PipelinedMemoryBusToApbBridge. + +Optimizing module Apb3Gpio. + +Optimizing module Apb3UartCtrl. + +Optimizing module MuraxApb3Timer. + +Optimizing module Apb3Decoder. + +Optimizing module Apb3Router. + +Optimizing module Murax. + + +3.2. Executing OPT_EXPR pass (perform const folding). +Optimizing module BufferCC. +Optimizing module BufferCC_1. +Optimizing module UartCtrlTx. +Optimizing module UartCtrlRx. +Optimizing module StreamFifoLowLatency. +Optimizing module FlowCCByToggle. +Optimizing module BufferCC_2. +Optimizing module UartCtrl. +Optimizing module StreamFifo. +Optimizing module Prescaler. +Optimizing module Timer. +Optimizing module InterruptCtrl. +Optimizing module BufferCC_3. +Optimizing module MuraxMasterArbiter. +Optimizing module VexRiscv. +Optimizing module JtagBridge. +Optimizing module SystemDebugger. +Optimizing module MuraxPipelinedMemoryBusRam. +Optimizing module PipelinedMemoryBusToApbBridge. +Optimizing module Apb3Gpio. +Optimizing module Apb3UartCtrl. +Optimizing module MuraxApb3Timer. +Optimizing module Apb3Decoder. +Optimizing module Apb3Router. +Optimizing module Murax. + +3.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \BufferCC.. +Finding unused cells or wires in module \BufferCC_1.. +Finding unused cells or wires in module \UartCtrlTx.. +Finding unused cells or wires in module \UartCtrlRx.. +Finding unused cells or wires in module \StreamFifoLowLatency.. +Finding unused cells or wires in module \FlowCCByToggle.. +Finding unused cells or wires in module \BufferCC_2.. +Finding unused cells or wires in module \UartCtrl.. +Finding unused cells or wires in module \StreamFifo.. +Finding unused cells or wires in module \Prescaler.. +Finding unused cells or wires in module \Timer.. +Finding unused cells or wires in module \InterruptCtrl.. +Finding unused cells or wires in module \BufferCC_3.. +Finding unused cells or wires in module \MuraxMasterArbiter.. +Finding unused cells or wires in module \VexRiscv.. +Finding unused cells or wires in module \JtagBridge.. +Finding unused cells or wires in module \SystemDebugger.. +Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam.. +Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge.. +Finding unused cells or wires in module \Apb3Gpio.. +Finding unused cells or wires in module \Apb3UartCtrl.. +Finding unused cells or wires in module \MuraxApb3Timer.. +Finding unused cells or wires in module \Apb3Decoder.. +Finding unused cells or wires in module \Apb3Router.. +Finding unused cells or wires in module \Murax.. +Removed 275 unused cells and 2158 unused wires. + + +3.4. Executing CHECK pass (checking for obvious problems). +Checking module Apb3Decoder... +Checking module Apb3Gpio... +Checking module Apb3Router... +Checking module Apb3UartCtrl... +Checking module BufferCC... +Checking module BufferCC_1... +Checking module BufferCC_2... +Checking module BufferCC_3... +Checking module FlowCCByToggle... +Checking module InterruptCtrl... +Checking module JtagBridge... +Checking module Murax... +Warning: Wire Murax.\io_gpioA_read [31] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [30] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [29] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [28] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [27] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [26] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [25] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [24] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [23] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [22] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [21] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [20] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [19] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [18] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [17] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [16] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [15] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [14] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [13] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [12] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [11] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [10] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [9] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [8] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [7] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [6] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [5] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [4] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [3] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [2] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [1] is used but has no driver. +Warning: Wire Murax.\io_gpioA_read [0] is used but has no driver. +Checking module MuraxApb3Timer... +Checking module MuraxMasterArbiter... +Checking module MuraxPipelinedMemoryBusRam... +Checking module PipelinedMemoryBusToApbBridge... +Checking module Prescaler... +Checking module StreamFifo... +Checking module StreamFifoLowLatency... +Checking module SystemDebugger... +Checking module Timer... +Checking module UartCtrl... +Checking module UartCtrlRx... +Checking module UartCtrlTx... +Checking module VexRiscv... +Found and reported 32 problems. + +3.5. Executing OPT pass (performing simple optimizations). + +3.5.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module Apb3Decoder. +Optimizing module Apb3Gpio. +Optimizing module Apb3Router. +Optimizing module Apb3UartCtrl. +Optimizing module BufferCC. +Optimizing module BufferCC_1. +Optimizing module BufferCC_2. +Optimizing module BufferCC_3. +Optimizing module FlowCCByToggle. +Optimizing module InterruptCtrl. +Optimizing module JtagBridge. +Optimizing module Murax. +Optimizing module MuraxApb3Timer. +Optimizing module MuraxMasterArbiter. +Optimizing module MuraxPipelinedMemoryBusRam. +Optimizing module PipelinedMemoryBusToApbBridge. +Optimizing module Prescaler. +Optimizing module StreamFifo. +Optimizing module StreamFifoLowLatency. +Optimizing module SystemDebugger. +Optimizing module Timer. +Optimizing module UartCtrl. +Optimizing module UartCtrlRx. +Optimizing module UartCtrlTx. +Optimizing module VexRiscv. + +3.5.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Apb3Decoder'. + +Finding identical cells in module `\Apb3Gpio'. + +Finding identical cells in module `\Apb3Router'. + +Finding identical cells in module `\Apb3UartCtrl'. + +Finding identical cells in module `\BufferCC'. +Finding identical cells in module `\BufferCC_1'. +Finding identical cells in module `\BufferCC_2'. +Finding identical cells in module `\BufferCC_3'. +Finding identical cells in module `\FlowCCByToggle'. +Finding identical cells in module `\InterruptCtrl'. +Finding identical cells in module `\JtagBridge'. + +Finding identical cells in module `\Murax'. + +Finding identical cells in module `\MuraxApb3Timer'. + +Finding identical cells in module `\MuraxMasterArbiter'. +Finding identical cells in module `\MuraxPipelinedMemoryBusRam'. +Finding identical cells in module `\PipelinedMemoryBusToApbBridge'. +Finding identical cells in module `\Prescaler'. +Finding identical cells in module `\StreamFifo'. + +Finding identical cells in module `\StreamFifoLowLatency'. +Finding identical cells in module `\SystemDebugger'. +Finding identical cells in module `\Timer'. +Finding identical cells in module `\UartCtrl'. +Finding identical cells in module `\UartCtrlRx'. + +Finding identical cells in module `\UartCtrlTx'. + +Finding identical cells in module `\VexRiscv'. + +Removed a total of 168 cells. + +3.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \Apb3Decoder.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Gpio.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Router.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$2574. + dead port 2/2 on $mux $procmux$2583. + dead port 2/2 on $mux $procmux$2592. + dead port 2/2 on $mux $procmux$2601. + dead port 2/2 on $mux $procmux$2610. + dead port 2/2 on $mux $procmux$2619. + dead port 2/2 on $mux $procmux$2634. +Running muxtree optimizer on module \BufferCC.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_2.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_3.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \FlowCCByToggle.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \InterruptCtrl.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \JtagBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$2389. +Running muxtree optimizer on module \Murax.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxApb3Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$2724. + dead port 2/2 on $mux $procmux$2733. + dead port 2/2 on $mux $procmux$2742. + dead port 2/2 on $mux $procmux$2757. + dead port 2/2 on $mux $procmux$2766. + dead port 2/2 on $mux $procmux$2781. +Running muxtree optimizer on module \MuraxMasterArbiter.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Replacing known input bits on port A of cell $procmux$2496: \state -> 1'1 + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$2509. + dead port 2/2 on $mux $procmux$2518. +Running muxtree optimizer on module \Prescaler.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \StreamFifo.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \StreamFifoLowLatency.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \SystemDebugger.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Replacing known input bits on port B of cell $procmux$2430: \dispatcher_headerLoaded -> 1'1 + Replacing known input bits on port A of cell $procmux$2428: \dispatcher_headerLoaded -> 1'0 + Analyzing evaluation results. +Running muxtree optimizer on module \Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlRx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$1129. + dead port 2/2 on $mux $procmux$1254. + dead port 2/2 on $mux $procmux$1263. + dead port 1/5 on $pmux $procmux$1266. + dead port 2/5 on $pmux $procmux$1266. + dead port 3/5 on $pmux $procmux$1266. + dead port 4/5 on $pmux $procmux$1266. + dead port 1/5 on $pmux $procmux$1275. + dead port 2/5 on $pmux $procmux$1275. + dead port 3/5 on $pmux $procmux$1275. + dead port 4/5 on $pmux $procmux$1275. + dead port 2/2 on $mux $procmux$1285. + dead port 2/2 on $mux $procmux$1287. + dead port 2/2 on $mux $procmux$1293. +Running muxtree optimizer on module \UartCtrlTx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$1095. + dead port 2/2 on $mux $procmux$1097. + dead port 2/2 on $mux $procmux$1104. +Running muxtree optimizer on module \VexRiscv.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$1845. + dead port 2/2 on $mux $procmux$1847. + dead port 2/2 on $mux $procmux$1853. + dead port 2/2 on $mux $procmux$1878. + dead port 2/2 on $mux $procmux$1880. + dead port 2/2 on $mux $procmux$1886. + dead port 2/2 on $mux $procmux$1915. + dead port 2/2 on $mux $procmux$1921. + dead port 2/2 on $mux $procmux$1933. + dead port 2/2 on $mux $procmux$1939. + dead port 2/2 on $mux $procmux$1951. + dead port 2/2 on $mux $procmux$1957. + dead port 2/2 on $mux $procmux$1966. + dead port 2/2 on $mux $procmux$1981. + dead port 2/2 on $mux $procmux$1987. + dead port 2/2 on $mux $procmux$1999. + dead port 2/2 on $mux $procmux$2005. + dead port 2/2 on $mux $procmux$2017. + dead port 2/2 on $mux $procmux$2023. + dead port 2/2 on $mux $procmux$2032. + dead port 2/2 on $mux $procmux$2194. + dead port 2/2 on $mux $procmux$2227. + dead port 2/2 on $mux $procmux$2260. + dead port 2/2 on $mux $procmux$2269. + dead port 2/2 on $mux $procmux$2284. + dead port 2/2 on $mux $procmux$2293. +Removed 59 multiplexer ports. + + +3.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \Apb3Decoder. + Optimizing cells in module \Apb3Gpio. + Optimizing cells in module \Apb3Router. + Optimizing cells in module \Apb3UartCtrl. + Optimizing cells in module \BufferCC. + Optimizing cells in module \BufferCC_1. + Optimizing cells in module \BufferCC_2. + Optimizing cells in module \BufferCC_3. + Optimizing cells in module \FlowCCByToggle. + Optimizing cells in module \InterruptCtrl. + Optimizing cells in module \JtagBridge. + New ctrl vector for $pmux cell $procmux$2359: { $procmux$2362_CMP $auto$opt_reduce.cc:134:opt_pmux$3132 } + Optimizing cells in module \JtagBridge. + Optimizing cells in module \Murax. + Optimizing cells in module \MuraxApb3Timer. + Optimizing cells in module \MuraxMasterArbiter. + Optimizing cells in module \MuraxPipelinedMemoryBusRam. + Consolidated identical input bits for $mux cell $procmux$2445: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$175 + New ports: A=1'0, B=1'1, Y=$0$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$175 [0] + New connections: $0$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$175 [7:1] = { $0$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$175 [0] $0$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$175 [0] $0$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$175 [0] $0$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$175 [0] $0$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$175 [0] $0$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$175 [0] $0$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$175 [0] } + Consolidated identical input bits for $mux cell $procmux$2454: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$172 + New ports: A=1'0, B=1'1, Y=$0$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$172 [0] + New connections: $0$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$172 [7:1] = { $0$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$172 [0] $0$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$172 [0] $0$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$172 [0] $0$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$172 [0] $0$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$172 [0] $0$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$172 [0] $0$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$172 [0] } + Consolidated identical input bits for $mux cell $procmux$2463: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$169 + New ports: A=1'0, B=1'1, Y=$0$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$169 [0] + New connections: $0$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$169 [7:1] = { $0$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$169 [0] $0$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$169 [0] $0$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$169 [0] $0$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$169 [0] $0$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$169 [0] $0$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$169 [0] $0$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$169 [0] } + Consolidated identical input bits for $mux cell $procmux$2472: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$166 + New ports: A=1'0, B=1'1, Y=$0$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$166 [0] + New connections: $0$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$166 [7:1] = { $0$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$166 [0] $0$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$166 [0] $0$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$166 [0] $0$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$166 [0] $0$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$166 [0] $0$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$166 [0] $0$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$166 [0] } + Optimizing cells in module \MuraxPipelinedMemoryBusRam. + Optimizing cells in module \PipelinedMemoryBusToApbBridge. + Optimizing cells in module \Prescaler. + Optimizing cells in module \StreamFifo. + Consolidated identical input bits for $mux cell $procmux$1375: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$895 + New ports: A=1'0, B=1'1, Y=$0$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$895 [0] + New connections: $0$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$895 [7:1] = { $0$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$895 [0] $0$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$895 [0] $0$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$895 [0] $0$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$895 [0] $0$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$895 [0] $0$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$895 [0] $0$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$895 [0] } + Optimizing cells in module \StreamFifo. + Optimizing cells in module \StreamFifoLowLatency. + Optimizing cells in module \SystemDebugger. + Optimizing cells in module \Timer. + Optimizing cells in module \UartCtrl. + Optimizing cells in module \UartCtrlRx. + New ctrl vector for $pmux cell $procmux$1296: { $auto$opt_reduce.cc:134:opt_pmux$3134 $procmux$1172_CMP } + Optimizing cells in module \UartCtrlRx. + Optimizing cells in module \UartCtrlTx. + Optimizing cells in module \VexRiscv. + New ctrl vector for $pmux cell $procmux$1896: { $procmux$1899_CMP $auto$opt_reduce.cc:134:opt_pmux$3136 } + New ctrl vector for $pmux cell $procmux$2154: $auto$opt_reduce.cc:134:opt_pmux$3138 + Consolidated identical input bits for $mux cell $procmux$2335: + Old ports: A=0, B=32'11111111111111111111111111111111, Y=$0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 + New ports: A=1'0, B=1'1, Y=$0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] + New connections: $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [31:1] = { $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] } + Optimizing cells in module \VexRiscv. +Performed a total of 10 changes. + +3.5.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Apb3Decoder'. +Finding identical cells in module `\Apb3Gpio'. +Finding identical cells in module `\Apb3Router'. +Finding identical cells in module `\Apb3UartCtrl'. + +Finding identical cells in module `\BufferCC'. +Finding identical cells in module `\BufferCC_1'. +Finding identical cells in module `\BufferCC_2'. +Finding identical cells in module `\BufferCC_3'. +Finding identical cells in module `\FlowCCByToggle'. +Finding identical cells in module `\InterruptCtrl'. +Finding identical cells in module `\JtagBridge'. + +Finding identical cells in module `\Murax'. +Finding identical cells in module `\MuraxApb3Timer'. + +Finding identical cells in module `\MuraxMasterArbiter'. +Finding identical cells in module `\MuraxPipelinedMemoryBusRam'. +Finding identical cells in module `\PipelinedMemoryBusToApbBridge'. +Finding identical cells in module `\Prescaler'. +Finding identical cells in module `\StreamFifo'. + +Finding identical cells in module `\StreamFifoLowLatency'. +Finding identical cells in module `\SystemDebugger'. +Finding identical cells in module `\Timer'. +Finding identical cells in module `\UartCtrl'. +Finding identical cells in module `\UartCtrlRx'. + +Finding identical cells in module `\UartCtrlTx'. + +Finding identical cells in module `\VexRiscv'. + +Removed a total of 28 cells. + +3.5.6. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 0-bit at position 0 on $procdff$3041 ($adff) from module VexRiscv. + +3.5.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Apb3Decoder.. +Finding unused cells or wires in module \Apb3Gpio.. +Finding unused cells or wires in module \Apb3Router.. +Finding unused cells or wires in module \Apb3UartCtrl.. +Finding unused cells or wires in module \BufferCC.. +Finding unused cells or wires in module \BufferCC_1.. +Finding unused cells or wires in module \BufferCC_2.. +Finding unused cells or wires in module \BufferCC_3.. +Finding unused cells or wires in module \FlowCCByToggle.. +Finding unused cells or wires in module \InterruptCtrl.. +Finding unused cells or wires in module \JtagBridge.. +Finding unused cells or wires in module \Murax.. +Finding unused cells or wires in module \MuraxApb3Timer.. +Finding unused cells or wires in module \MuraxMasterArbiter.. +Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam.. +Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge.. +Finding unused cells or wires in module \Prescaler.. +Finding unused cells or wires in module \StreamFifo.. +Finding unused cells or wires in module \StreamFifoLowLatency.. +Finding unused cells or wires in module \SystemDebugger.. +Finding unused cells or wires in module \Timer.. +Finding unused cells or wires in module \UartCtrl.. +Finding unused cells or wires in module \UartCtrlRx.. +Finding unused cells or wires in module \UartCtrlTx.. +Finding unused cells or wires in module \VexRiscv.. +Removed 0 unused cells and 250 unused wires. + + +3.5.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module Apb3Decoder. +Optimizing module Apb3Gpio. +Optimizing module Apb3Router. +Optimizing module Apb3UartCtrl. +Optimizing module BufferCC. +Optimizing module BufferCC_1. +Optimizing module BufferCC_2. +Optimizing module BufferCC_3. +Optimizing module FlowCCByToggle. +Optimizing module InterruptCtrl. +Optimizing module JtagBridge. +Optimizing module Murax. +Optimizing module MuraxApb3Timer. +Optimizing module MuraxMasterArbiter. +Optimizing module MuraxPipelinedMemoryBusRam. +Optimizing module PipelinedMemoryBusToApbBridge. +Optimizing module Prescaler. +Optimizing module StreamFifo. +Optimizing module StreamFifoLowLatency. +Optimizing module SystemDebugger. +Optimizing module Timer. +Optimizing module UartCtrl. +Optimizing module UartCtrlRx. +Optimizing module UartCtrlTx. +Optimizing module VexRiscv. + + +3.5.9. Rerunning OPT passes. (Maybe there is more to do..) + +3.5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \Apb3Decoder.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Gpio.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Router.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \BufferCC.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_2.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_3.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \FlowCCByToggle.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \InterruptCtrl.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \JtagBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Murax.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxApb3Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxMasterArbiter.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Prescaler.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \StreamFifo.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \StreamFifoLowLatency.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \SystemDebugger.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlRx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlTx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \VexRiscv.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \Apb3Decoder. + Optimizing cells in module \Apb3Gpio. + Optimizing cells in module \Apb3Router. + Optimizing cells in module \Apb3UartCtrl. + Optimizing cells in module \BufferCC. + Optimizing cells in module \BufferCC_1. + Optimizing cells in module \BufferCC_2. + Optimizing cells in module \BufferCC_3. + Optimizing cells in module \FlowCCByToggle. + Optimizing cells in module \InterruptCtrl. + Optimizing cells in module \JtagBridge. + New ctrl vector for $pmux cell $procmux$2396: { $procmux$2410_CMP $auto$opt_reduce.cc:134:opt_pmux$3144 $procmux$2407_CMP $procmux$2406_CMP $procmux$2405_CMP $procmux$2403_CMP $auto$opt_reduce.cc:134:opt_pmux$3142 $procmux$2400_CMP $procmux$2399_CMP $procmux$2398_CMP $auto$opt_reduce.cc:134:opt_pmux$3140 } + Optimizing cells in module \JtagBridge. + Optimizing cells in module \Murax. + Optimizing cells in module \MuraxApb3Timer. + Optimizing cells in module \MuraxMasterArbiter. + Optimizing cells in module \MuraxPipelinedMemoryBusRam. + Optimizing cells in module \PipelinedMemoryBusToApbBridge. + Optimizing cells in module \Prescaler. + Optimizing cells in module \StreamFifo. + Optimizing cells in module \StreamFifoLowLatency. + Optimizing cells in module \SystemDebugger. + Optimizing cells in module \Timer. + Optimizing cells in module \UartCtrl. + Optimizing cells in module \UartCtrlRx. + New ctrl vector for $pmux cell $procmux$1171: { $procmux$1130_CMP $auto$opt_reduce.cc:134:opt_pmux$3146 } + Optimizing cells in module \UartCtrlRx. + Optimizing cells in module \UartCtrlTx. + New ctrl vector for $pmux cell $procmux$1048: { $procmux$1054_CMP $auto$opt_reduce.cc:134:opt_pmux$3148 } + Optimizing cells in module \UartCtrlTx. + Optimizing cells in module \VexRiscv. +Performed a total of 3 changes. + +3.5.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Apb3Decoder'. +Finding identical cells in module `\Apb3Gpio'. +Finding identical cells in module `\Apb3Router'. +Finding identical cells in module `\Apb3UartCtrl'. +Finding identical cells in module `\BufferCC'. +Finding identical cells in module `\BufferCC_1'. +Finding identical cells in module `\BufferCC_2'. +Finding identical cells in module `\BufferCC_3'. +Finding identical cells in module `\FlowCCByToggle'. +Finding identical cells in module `\InterruptCtrl'. +Finding identical cells in module `\JtagBridge'. +Finding identical cells in module `\Murax'. +Finding identical cells in module `\MuraxApb3Timer'. +Finding identical cells in module `\MuraxMasterArbiter'. +Finding identical cells in module `\MuraxPipelinedMemoryBusRam'. +Finding identical cells in module `\PipelinedMemoryBusToApbBridge'. +Finding identical cells in module `\Prescaler'. +Finding identical cells in module `\StreamFifo'. +Finding identical cells in module `\StreamFifoLowLatency'. +Finding identical cells in module `\SystemDebugger'. +Finding identical cells in module `\Timer'. +Finding identical cells in module `\UartCtrl'. +Finding identical cells in module `\UartCtrlRx'. +Finding identical cells in module `\UartCtrlTx'. +Finding identical cells in module `\VexRiscv'. +Removed a total of 0 cells. + +3.5.13. Executing OPT_DFF pass (perform DFF optimizations). + +3.5.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Apb3Decoder.. +Finding unused cells or wires in module \Apb3Gpio.. +Finding unused cells or wires in module \Apb3Router.. +Finding unused cells or wires in module \Apb3UartCtrl.. +Finding unused cells or wires in module \BufferCC.. +Finding unused cells or wires in module \BufferCC_1.. +Finding unused cells or wires in module \BufferCC_2.. +Finding unused cells or wires in module \BufferCC_3.. +Finding unused cells or wires in module \FlowCCByToggle.. +Finding unused cells or wires in module \InterruptCtrl.. +Finding unused cells or wires in module \JtagBridge.. +Finding unused cells or wires in module \Murax.. +Finding unused cells or wires in module \MuraxApb3Timer.. +Finding unused cells or wires in module \MuraxMasterArbiter.. +Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam.. +Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge.. +Finding unused cells or wires in module \Prescaler.. +Finding unused cells or wires in module \StreamFifo.. +Finding unused cells or wires in module \StreamFifoLowLatency.. +Finding unused cells or wires in module \SystemDebugger.. +Finding unused cells or wires in module \Timer.. +Finding unused cells or wires in module \UartCtrl.. +Finding unused cells or wires in module \UartCtrlRx.. +Finding unused cells or wires in module \UartCtrlTx.. +Finding unused cells or wires in module \VexRiscv.. +Removed 0 unused cells and 1 unused wires. + + +3.5.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module Apb3Decoder. +Optimizing module Apb3Gpio. +Optimizing module Apb3Router. +Optimizing module Apb3UartCtrl. +Optimizing module BufferCC. +Optimizing module BufferCC_1. +Optimizing module BufferCC_2. +Optimizing module BufferCC_3. +Optimizing module FlowCCByToggle. +Optimizing module InterruptCtrl. +Optimizing module JtagBridge. +Optimizing module Murax. +Optimizing module MuraxApb3Timer. +Optimizing module MuraxMasterArbiter. +Optimizing module MuraxPipelinedMemoryBusRam. +Optimizing module PipelinedMemoryBusToApbBridge. +Optimizing module Prescaler. +Optimizing module StreamFifo. +Optimizing module StreamFifoLowLatency. +Optimizing module SystemDebugger. +Optimizing module Timer. +Optimizing module UartCtrl. +Optimizing module UartCtrlRx. +Optimizing module UartCtrlTx. +Optimizing module VexRiscv. + +3.5.16. Rerunning OPT passes. (Maybe there is more to do..) + +3.5.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \Apb3Decoder.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Gpio.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Router.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \BufferCC.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_2.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_3.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \FlowCCByToggle.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \InterruptCtrl.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \JtagBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Murax.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxApb3Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxMasterArbiter.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Prescaler.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \StreamFifo.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \StreamFifoLowLatency.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \SystemDebugger.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlRx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlTx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \VexRiscv.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.5.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \Apb3Decoder. + Optimizing cells in module \Apb3Gpio. + Optimizing cells in module \Apb3Router. + Optimizing cells in module \Apb3UartCtrl. + Optimizing cells in module \BufferCC. + Optimizing cells in module \BufferCC_1. + Optimizing cells in module \BufferCC_2. + Optimizing cells in module \BufferCC_3. + Optimizing cells in module \FlowCCByToggle. + Optimizing cells in module \InterruptCtrl. + Optimizing cells in module \JtagBridge. + Optimizing cells in module \Murax. + Optimizing cells in module \MuraxApb3Timer. + Optimizing cells in module \MuraxMasterArbiter. + Optimizing cells in module \MuraxPipelinedMemoryBusRam. + Optimizing cells in module \PipelinedMemoryBusToApbBridge. + Optimizing cells in module \Prescaler. + Optimizing cells in module \StreamFifo. + Optimizing cells in module \StreamFifoLowLatency. + Optimizing cells in module \SystemDebugger. + Optimizing cells in module \Timer. + Optimizing cells in module \UartCtrl. + Optimizing cells in module \UartCtrlRx. + Optimizing cells in module \UartCtrlTx. + Optimizing cells in module \VexRiscv. +Performed a total of 0 changes. + +3.5.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Apb3Decoder'. +Finding identical cells in module `\Apb3Gpio'. +Finding identical cells in module `\Apb3Router'. +Finding identical cells in module `\Apb3UartCtrl'. +Finding identical cells in module `\BufferCC'. +Finding identical cells in module `\BufferCC_1'. +Finding identical cells in module `\BufferCC_2'. +Finding identical cells in module `\BufferCC_3'. +Finding identical cells in module `\FlowCCByToggle'. +Finding identical cells in module `\InterruptCtrl'. +Finding identical cells in module `\JtagBridge'. +Finding identical cells in module `\Murax'. +Finding identical cells in module `\MuraxApb3Timer'. +Finding identical cells in module `\MuraxMasterArbiter'. +Finding identical cells in module `\MuraxPipelinedMemoryBusRam'. +Finding identical cells in module `\PipelinedMemoryBusToApbBridge'. +Finding identical cells in module `\Prescaler'. +Finding identical cells in module `\StreamFifo'. +Finding identical cells in module `\StreamFifoLowLatency'. +Finding identical cells in module `\SystemDebugger'. +Finding identical cells in module `\Timer'. +Finding identical cells in module `\UartCtrl'. +Finding identical cells in module `\UartCtrlRx'. +Finding identical cells in module `\UartCtrlTx'. +Finding identical cells in module `\VexRiscv'. +Removed a total of 0 cells. + +3.5.20. Executing OPT_DFF pass (perform DFF optimizations). + +3.5.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Apb3Decoder.. +Finding unused cells or wires in module \Apb3Gpio.. +Finding unused cells or wires in module \Apb3Router.. +Finding unused cells or wires in module \Apb3UartCtrl.. +Finding unused cells or wires in module \BufferCC.. +Finding unused cells or wires in module \BufferCC_1.. +Finding unused cells or wires in module \BufferCC_2.. +Finding unused cells or wires in module \BufferCC_3.. +Finding unused cells or wires in module \FlowCCByToggle.. +Finding unused cells or wires in module \InterruptCtrl.. +Finding unused cells or wires in module \JtagBridge.. +Finding unused cells or wires in module \Murax.. +Finding unused cells or wires in module \MuraxApb3Timer.. +Finding unused cells or wires in module \MuraxMasterArbiter.. +Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam.. +Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge.. +Finding unused cells or wires in module \Prescaler.. +Finding unused cells or wires in module \StreamFifo.. +Finding unused cells or wires in module \StreamFifoLowLatency.. +Finding unused cells or wires in module \SystemDebugger.. +Finding unused cells or wires in module \Timer.. +Finding unused cells or wires in module \UartCtrl.. +Finding unused cells or wires in module \UartCtrlRx.. +Finding unused cells or wires in module \UartCtrlTx.. +Finding unused cells or wires in module \VexRiscv.. + +3.5.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module Apb3Decoder. +Optimizing module Apb3Gpio. +Optimizing module Apb3Router. +Optimizing module Apb3UartCtrl. +Optimizing module BufferCC. +Optimizing module BufferCC_1. +Optimizing module BufferCC_2. +Optimizing module BufferCC_3. +Optimizing module FlowCCByToggle. +Optimizing module InterruptCtrl. +Optimizing module JtagBridge. +Optimizing module Murax. +Optimizing module MuraxApb3Timer. +Optimizing module MuraxMasterArbiter. +Optimizing module MuraxPipelinedMemoryBusRam. +Optimizing module PipelinedMemoryBusToApbBridge. +Optimizing module Prescaler. +Optimizing module StreamFifo. +Optimizing module StreamFifoLowLatency. +Optimizing module SystemDebugger. +Optimizing module Timer. +Optimizing module UartCtrl. +Optimizing module UartCtrlRx. +Optimizing module UartCtrlTx. +Optimizing module VexRiscv. + +3.5.23. Finished OPT passes. (There is nothing left to do.) + +3.6. Executing FSM pass (extract and optimize FSM). + +3.6.1. Executing FSM_DETECT pass (finding FSMs in design). +Found FSM state register JtagBridge.jtag_tap_fsm_state. +Found FSM state register UartCtrlRx.stateMachine_state. +Found FSM state register UartCtrlTx.stateMachine_state. +Not marking VexRiscv.CsrPlugin_interrupt_code as FSM state register: + Users of register don't seem to benefit from recoding. +Found FSM state register VexRiscv.CsrPlugin_interrupt_targetPrivilege. +Not marking VexRiscv.switch_Fetcher_l362 as FSM state register: + Users of register don't seem to benefit from recoding. + +3.6.2. Executing FSM_EXTRACT pass (extracting FSM from design). +Extracting FSM `\jtag_tap_fsm_state' from module `\JtagBridge'. + found $dff cell for state register: $procdff$3053 + root of input selection tree: \_zz_jtag_tap_fsm_stateNext + found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$3140 + found ctrl input: $procmux$2398_CMP + found ctrl input: $procmux$2399_CMP + found ctrl input: $procmux$2400_CMP + found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$3142 + found ctrl input: $procmux$2403_CMP + found ctrl input: $procmux$2405_CMP + found ctrl input: $procmux$2406_CMP + found ctrl input: $procmux$2407_CMP + found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$3144 + found ctrl input: $procmux$2410_CMP + found ctrl input: \io_jtag_tms + found state code: 4'0001 + found state code: 4'0000 + found state code: 4'1001 + found state code: 4'1011 + found state code: 4'1111 + found state code: 4'1101 + found state code: 4'1110 + found state code: 4'1100 + found state code: 4'1010 + found state code: 4'0010 + found state code: 4'0100 + found state code: 4'1000 + found state code: 4'0110 + found state code: 4'0111 + found state code: 4'0101 + found state code: 4'0011 + found ctrl output: \jtag_idcodeArea_ctrl_capture + found ctrl output: \jtag_idcodeArea_ctrl_shift + found ctrl output: \when_JtagTap_l120 + found ctrl output: $procmux$2361_CMP + found ctrl output: $procmux$2362_CMP + found ctrl output: $procmux$2365_CMP + found ctrl output: $procmux$2397_CMP + found ctrl output: $procmux$2398_CMP + found ctrl output: $procmux$2399_CMP + found ctrl output: $procmux$2400_CMP + found ctrl output: $procmux$2403_CMP + found ctrl output: $procmux$2405_CMP + found ctrl output: $procmux$2406_CMP + found ctrl output: $procmux$2407_CMP + found ctrl output: $procmux$2410_CMP + found ctrl output: $procmux$2411_CMP + ctrl inputs: { $auto$opt_reduce.cc:134:opt_pmux$3140 $auto$opt_reduce.cc:134:opt_pmux$3144 $auto$opt_reduce.cc:134:opt_pmux$3142 \io_jtag_tms } + ctrl outputs: { $procmux$2411_CMP $procmux$2410_CMP $procmux$2407_CMP $procmux$2406_CMP $procmux$2405_CMP $procmux$2403_CMP $procmux$2400_CMP $procmux$2399_CMP $procmux$2398_CMP $procmux$2397_CMP $procmux$2365_CMP $procmux$2362_CMP $procmux$2361_CMP \when_JtagTap_l120 \jtag_idcodeArea_ctrl_shift \jtag_idcodeArea_ctrl_capture \_zz_jtag_tap_fsm_stateNext } + transition: 4'0000 4'---0 -> 4'0001 20'00000000000001000001 + transition: 4'0000 4'---1 -> 4'0000 20'00000000000001000000 + transition: 4'1000 4'-000 -> 4'0001 20'00000000001000000001 + transition: 4'1000 4'-001 -> 4'1001 20'00000000001000001001 + transition: 4'0100 4'---0 -> 4'0100 20'00000000000010000100 + transition: 4'0100 4'---1 -> 4'0101 20'00000000000010000101 + transition: 4'1100 4'---0 -> 4'1101 20'00000010000000001101 + transition: 4'1100 4'---1 -> 4'1111 20'00000010000000001111 + transition: 4'0010 4'---0 -> 4'0011 20'01000000000000000011 + transition: 4'0010 4'---1 -> 4'0000 20'01000000000000000000 + transition: 4'1010 4'-0-0 -> 4'1011 20'00000000000000011011 + transition: 4'1010 4'-0-1 -> 4'1100 20'00000000000000011100 + transition: 4'0110 4'---0 -> 4'0110 20'00010000000000000110 + transition: 4'0110 4'---1 -> 4'0111 20'00010000000000000111 + transition: 4'1110 4'---0 -> 4'1011 20'00000000100000001011 + transition: 4'1110 4'---1 -> 4'1111 20'00000000100000001111 + transition: 4'0001 4'-000 -> 4'0001 20'10000000000000000001 + transition: 4'0001 4'-001 -> 4'1001 20'10000000000000001001 + transition: 4'1001 4'---0 -> 4'1010 20'00000100000000001010 + transition: 4'1001 4'---1 -> 4'0010 20'00000100000000000010 + transition: 4'0101 4'---0 -> 4'0110 20'00100000000000000110 + transition: 4'0101 4'---1 -> 4'1000 20'00100000000000001000 + transition: 4'1101 4'---0 -> 4'1101 20'00000001000000001101 + transition: 4'1101 4'---1 -> 4'1110 20'00000001000000001110 + transition: 4'0011 4'---0 -> 4'0100 20'00000000000100000100 + transition: 4'0011 4'---1 -> 4'0101 20'00000000000100000101 + transition: 4'1011 4'-0-0 -> 4'1011 20'00000000000000101011 + transition: 4'1011 4'-0-1 -> 4'1100 20'00000000000000101100 + transition: 4'0111 4'---0 -> 4'0100 20'00001000000000000100 + transition: 4'0111 4'---1 -> 4'1000 20'00001000000000001000 + transition: 4'1111 4'-000 -> 4'0001 20'00000000010000000001 + transition: 4'1111 4'-001 -> 4'1001 20'00000000010000001001 +Extracting FSM `\stateMachine_state' from module `\UartCtrlRx'. + found $adff cell for state register: $procdff$2901 + root of input selection tree: $0\stateMachine_state[2:0] + found reset state: 3'000 (from async reset) + found ctrl input: $procmux$1172_CMP + found ctrl input: $procmux$1130_CMP + found ctrl input: $procmux$1165_CMP + found ctrl input: $procmux$1193_CMP + found ctrl input: \bitTimer_tick + found ctrl input: \sampler_value + found ctrl input: \when_UartCtrlRx_l139 + found ctrl input: \when_UartCtrlRx_l125 + found state code: 3'100 + found ctrl input: \when_UartCtrlRx_l111 + found ctrl input: \when_UartCtrlRx_l113 + found state code: 3'011 + found state code: 3'010 + found ctrl input: \when_UartCtrlRx_l93 + found state code: 3'001 + found ctrl output: $procmux$1130_CMP + found ctrl output: $procmux$1165_CMP + found ctrl output: $procmux$1172_CMP + found ctrl output: $procmux$1193_CMP + ctrl inputs: { \when_UartCtrlRx_l139 \when_UartCtrlRx_l125 \when_UartCtrlRx_l113 \when_UartCtrlRx_l111 \when_UartCtrlRx_l93 \bitTimer_tick \sampler_value } + ctrl outputs: { $procmux$1193_CMP $procmux$1172_CMP $procmux$1165_CMP $procmux$1130_CMP $0\stateMachine_state[2:0] } + transition: 3'000 7'----0-- -> 3'000 7'1000000 + transition: 3'000 7'----1-- -> 3'001 7'1000001 + transition: 3'100 7'-----0- -> 3'100 7'0000100 + transition: 3'100 7'-----10 -> 3'000 7'0000000 + transition: 3'100 7'0----11 -> 3'100 7'0000100 + transition: 3'100 7'1----11 -> 3'000 7'0000000 + transition: 3'010 7'-----0- -> 3'010 7'0001010 + transition: 3'010 7'---0-1- -> 3'010 7'0001010 + transition: 3'010 7'--01-1- -> 3'011 7'0001011 + transition: 3'010 7'--11-1- -> 3'100 7'0001100 + transition: 3'001 7'-----0- -> 3'001 7'0010001 + transition: 3'001 7'-----10 -> 3'010 7'0010010 + transition: 3'001 7'-----11 -> 3'000 7'0010000 + transition: 3'011 7'-----0- -> 3'011 7'0100011 + transition: 3'011 7'-0---1- -> 3'000 7'0100000 + transition: 3'011 7'-1---1- -> 3'100 7'0100100 +Extracting FSM `\stateMachine_state' from module `\UartCtrlTx'. + found $adff cell for state register: $procdff$2885 + root of input selection tree: $0\stateMachine_state[2:0] + found reset state: 3'000 (from async reset) + found ctrl input: $procmux$1049_CMP + found ctrl input: $procmux$1054_CMP + found ctrl input: $procmux$1057_CMP + found ctrl input: $procmux$1088_CMP + found ctrl input: \clockDivider_counter_willOverflow + found ctrl input: \when_UartCtrlTx_l93 + found ctrl input: \io_write_valid + found state code: 3'001 + found state code: 3'100 + found ctrl input: \when_UartCtrlTx_l73 + found ctrl input: \when_UartCtrlTx_l76 + found state code: 3'011 + found state code: 3'010 + found ctrl input: \when_UartCtrlTx_l58 + found ctrl output: $procmux$1049_CMP + found ctrl output: $procmux$1054_CMP + found ctrl output: $procmux$1057_CMP + found ctrl output: $procmux$1088_CMP + ctrl inputs: { \when_UartCtrlTx_l93 \when_UartCtrlTx_l76 \when_UartCtrlTx_l73 \when_UartCtrlTx_l58 \clockDivider_counter_willOverflow \io_write_valid } + ctrl outputs: { $procmux$1088_CMP $procmux$1057_CMP $procmux$1054_CMP $procmux$1049_CMP $0\stateMachine_state[2:0] } + transition: 3'000 6'---0-- -> 3'000 7'1000000 + transition: 3'000 6'---1-- -> 3'001 7'1000001 + transition: 3'100 6'----0- -> 3'100 7'0000100 + transition: 3'100 6'0---1- -> 3'100 7'0000100 + transition: 3'100 6'1---10 -> 3'000 7'0000000 + transition: 3'100 6'1---11 -> 3'001 7'0000001 + transition: 3'010 6'----0- -> 3'010 7'0010010 + transition: 3'010 6'--0-1- -> 3'010 7'0010010 + transition: 3'010 6'-01-1- -> 3'011 7'0010011 + transition: 3'010 6'-11-1- -> 3'100 7'0010100 + transition: 3'001 6'----0- -> 3'001 7'0100001 + transition: 3'001 6'----1- -> 3'010 7'0100010 + transition: 3'011 6'----0- -> 3'011 7'0001011 + transition: 3'011 6'----1- -> 3'100 7'0001100 +Extracting FSM `\CsrPlugin_interrupt_targetPrivilege' from module `\VexRiscv'. + found $dff cell for state register: $procdff$2958 + root of input selection tree: $0\CsrPlugin_interrupt_targetPrivilege[1:0] + found ctrl input: \CsrPlugin_mstatus_MIE + found ctrl input: \_zz_when_CsrPlugin_l952_2 + found ctrl input: \_zz_when_CsrPlugin_l952_1 + found ctrl input: \_zz_when_CsrPlugin_l952 + found state code: 2'11 + fsm extraction failed: at least two states are required. + +3.6.3. Executing FSM_OPT pass (simple optimizations of FSMs). +Optimizing FSM `$fsm$\jtag_tap_fsm_state$3149' from module `\JtagBridge'. + Removing unused input signal $auto$opt_reduce.cc:134:opt_pmux$3140. +Optimizing FSM `$fsm$\stateMachine_state$3167' from module `\UartCtrlRx'. +Optimizing FSM `$fsm$\stateMachine_state$3173' from module `\UartCtrlTx'. + +3.6.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Apb3Decoder.. +Finding unused cells or wires in module \Apb3Gpio.. +Finding unused cells or wires in module \Apb3Router.. +Finding unused cells or wires in module \Apb3UartCtrl.. +Finding unused cells or wires in module \BufferCC.. +Finding unused cells or wires in module \BufferCC_1.. +Finding unused cells or wires in module \BufferCC_2.. +Finding unused cells or wires in module \BufferCC_3.. +Finding unused cells or wires in module \FlowCCByToggle.. +Finding unused cells or wires in module \InterruptCtrl.. +Finding unused cells or wires in module \JtagBridge.. +Finding unused cells or wires in module \Murax.. +Finding unused cells or wires in module \MuraxApb3Timer.. +Finding unused cells or wires in module \MuraxMasterArbiter.. +Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam.. +Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge.. +Finding unused cells or wires in module \Prescaler.. +Finding unused cells or wires in module \StreamFifo.. +Finding unused cells or wires in module \StreamFifoLowLatency.. +Finding unused cells or wires in module \SystemDebugger.. +Finding unused cells or wires in module \Timer.. +Finding unused cells or wires in module \UartCtrl.. +Finding unused cells or wires in module \UartCtrlRx.. +Finding unused cells or wires in module \UartCtrlTx.. +Finding unused cells or wires in module \VexRiscv.. +Removed 63 unused cells and 63 unused wires. + + +3.6.5. Executing FSM_OPT pass (simple optimizations of FSMs). +Optimizing FSM `$fsm$\jtag_tap_fsm_state$3149' from module `\JtagBridge'. + Removing unused output signal \_zz_jtag_tap_fsm_stateNext [0]. + Removing unused output signal \_zz_jtag_tap_fsm_stateNext [1]. + Removing unused output signal \_zz_jtag_tap_fsm_stateNext [2]. + Removing unused output signal \_zz_jtag_tap_fsm_stateNext [3]. + Removing unused output signal $procmux$2397_CMP. + Removing unused output signal $procmux$2398_CMP. + Removing unused output signal $procmux$2399_CMP. + Removing unused output signal $procmux$2400_CMP. + Removing unused output signal $procmux$2403_CMP. + Removing unused output signal $procmux$2405_CMP. + Removing unused output signal $procmux$2406_CMP. + Removing unused output signal $procmux$2407_CMP. + Removing unused output signal $procmux$2410_CMP. + Removing unused output signal $procmux$2411_CMP. +Optimizing FSM `$fsm$\stateMachine_state$3167' from module `\UartCtrlRx'. + Removing unused output signal $0\stateMachine_state[2:0] [0]. + Removing unused output signal $0\stateMachine_state[2:0] [1]. + Removing unused output signal $0\stateMachine_state[2:0] [2]. +Optimizing FSM `$fsm$\stateMachine_state$3173' from module `\UartCtrlTx'. + Removing unused output signal $0\stateMachine_state[2:0] [0]. + Removing unused output signal $0\stateMachine_state[2:0] [1]. + Removing unused output signal $0\stateMachine_state[2:0] [2]. + Removing unused output signal $procmux$1088_CMP. + +3.6.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). +Recoding FSM `$fsm$\jtag_tap_fsm_state$3149' from module `\JtagBridge' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 0000 -> ---------------1 + 1000 -> --------------1- + 0100 -> -------------1-- + 1100 -> ------------1--- + 0010 -> -----------1---- + 1010 -> ----------1----- + 0110 -> ---------1------ + 1110 -> --------1------- + 0001 -> -------1-------- + 1001 -> ------1--------- + 0101 -> -----1---------- + 1101 -> ----1----------- + 0011 -> ---1------------ + 1011 -> --1------------- + 0111 -> -1-------------- + 1111 -> 1--------------- +Recoding FSM `$fsm$\stateMachine_state$3167' from module `\UartCtrlRx' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 000 -> ----1 + 100 -> ---1- + 010 -> --1-- + 001 -> -1--- + 011 -> 1---- +Recoding FSM `$fsm$\stateMachine_state$3173' from module `\UartCtrlTx' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 000 -> ----1 + 100 -> ---1- + 010 -> --1-- + 001 -> -1--- + 011 -> 1---- + +3.6.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +FSM `$fsm$\jtag_tap_fsm_state$3149' from module `JtagBridge': +------------------------------------- + + Information on FSM $fsm$\jtag_tap_fsm_state$3149 (\jtag_tap_fsm_state): + + Number of input signals: 3 + Number of output signals: 6 + Number of state bits: 16 + + Input signals: + 0: \io_jtag_tms + 1: $auto$opt_reduce.cc:134:opt_pmux$3142 + 2: $auto$opt_reduce.cc:134:opt_pmux$3144 + + Output signals: + 0: \jtag_idcodeArea_ctrl_capture + 1: \jtag_idcodeArea_ctrl_shift + 2: \when_JtagTap_l120 + 3: $procmux$2361_CMP + 4: $procmux$2362_CMP + 5: $procmux$2365_CMP + + State encoding: + 0: 16'---------------1 + 1: 16'--------------1- + 2: 16'-------------1-- + 3: 16'------------1--- + 4: 16'-----------1---- + 5: 16'----------1----- + 6: 16'---------1------ + 7: 16'--------1------- + 8: 16'-------1-------- + 9: 16'------1--------- + 10: 16'-----1---------- + 11: 16'----1----------- + 12: 16'---1------------ + 13: 16'--1------------- + 14: 16'-1-------------- + 15: 16'1--------------- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 3'--1 -> 0 6'000100 + 1: 0 3'--0 -> 8 6'000100 + 2: 1 3'000 -> 8 6'100000 + 3: 1 3'001 -> 9 6'100000 + 4: 2 3'--0 -> 2 6'001000 + 5: 2 3'--1 -> 10 6'001000 + 6: 3 3'--0 -> 11 6'000000 + 7: 3 3'--1 -> 15 6'000000 + 8: 4 3'--1 -> 0 6'000000 + 9: 4 3'--0 -> 12 6'000000 + 10: 5 3'0-1 -> 3 6'000001 + 11: 5 3'0-0 -> 13 6'000001 + 12: 6 3'--0 -> 6 6'000000 + 13: 6 3'--1 -> 14 6'000000 + 14: 7 3'--0 -> 13 6'000000 + 15: 7 3'--1 -> 15 6'000000 + 16: 8 3'000 -> 8 6'000000 + 17: 8 3'001 -> 9 6'000000 + 18: 9 3'--1 -> 4 6'000000 + 19: 9 3'--0 -> 5 6'000000 + 20: 10 3'--1 -> 1 6'000000 + 21: 10 3'--0 -> 6 6'000000 + 22: 11 3'--1 -> 7 6'000000 + 23: 11 3'--0 -> 11 6'000000 + 24: 12 3'--0 -> 2 6'010000 + 25: 12 3'--1 -> 10 6'010000 + 26: 13 3'0-1 -> 3 6'000010 + 27: 13 3'0-0 -> 13 6'000010 + 28: 14 3'--1 -> 1 6'000000 + 29: 14 3'--0 -> 2 6'000000 + 30: 15 3'000 -> 8 6'000000 + 31: 15 3'001 -> 9 6'000000 + +------------------------------------- + +FSM `$fsm$\stateMachine_state$3167' from module `UartCtrlRx': +------------------------------------- + + Information on FSM $fsm$\stateMachine_state$3167 (\stateMachine_state): + + Number of input signals: 7 + Number of output signals: 4 + Number of state bits: 5 + + Input signals: + 0: \sampler_value + 1: \bitTimer_tick + 2: \when_UartCtrlRx_l93 + 3: \when_UartCtrlRx_l111 + 4: \when_UartCtrlRx_l113 + 5: \when_UartCtrlRx_l125 + 6: \when_UartCtrlRx_l139 + + Output signals: + 0: $procmux$1130_CMP + 1: $procmux$1165_CMP + 2: $procmux$1172_CMP + 3: $procmux$1193_CMP + + State encoding: + 0: 5'----1 + 1: 5'---1- + 2: 5'--1-- + 3: 5'-1--- + 4: 5'1---- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 7'----0-- -> 0 4'1000 + 1: 0 7'----1-- -> 3 4'1000 + 2: 1 7'-----10 -> 0 4'0000 + 3: 1 7'1----11 -> 0 4'0000 + 4: 1 7'0----11 -> 1 4'0000 + 5: 1 7'-----0- -> 1 4'0000 + 6: 2 7'--11-1- -> 1 4'0001 + 7: 2 7'-----0- -> 2 4'0001 + 8: 2 7'---0-1- -> 2 4'0001 + 9: 2 7'--01-1- -> 4 4'0001 + 10: 3 7'-----11 -> 0 4'0010 + 11: 3 7'-----10 -> 2 4'0010 + 12: 3 7'-----0- -> 3 4'0010 + 13: 4 7'-0---1- -> 0 4'0100 + 14: 4 7'-1---1- -> 1 4'0100 + 15: 4 7'-----0- -> 4 4'0100 + +------------------------------------- + +FSM `$fsm$\stateMachine_state$3173' from module `UartCtrlTx': +------------------------------------- + + Information on FSM $fsm$\stateMachine_state$3173 (\stateMachine_state): + + Number of input signals: 6 + Number of output signals: 3 + Number of state bits: 5 + + Input signals: + 0: \io_write_valid + 1: \clockDivider_counter_willOverflow + 2: \when_UartCtrlTx_l58 + 3: \when_UartCtrlTx_l73 + 4: \when_UartCtrlTx_l76 + 5: \when_UartCtrlTx_l93 + + Output signals: + 0: $procmux$1049_CMP + 1: $procmux$1054_CMP + 2: $procmux$1057_CMP + + State encoding: + 0: 5'----1 + 1: 5'---1- + 2: 5'--1-- + 3: 5'-1--- + 4: 5'1---- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 6'---0-- -> 0 3'000 + 1: 0 6'---1-- -> 3 3'000 + 2: 1 6'1---10 -> 0 3'000 + 3: 1 6'----0- -> 1 3'000 + 4: 1 6'0---1- -> 1 3'000 + 5: 1 6'1---11 -> 3 3'000 + 6: 2 6'-11-1- -> 1 3'010 + 7: 2 6'----0- -> 2 3'010 + 8: 2 6'--0-1- -> 2 3'010 + 9: 2 6'-01-1- -> 4 3'010 + 10: 3 6'----1- -> 2 3'100 + 11: 3 6'----0- -> 3 3'100 + 12: 4 6'----1- -> 1 3'001 + 13: 4 6'----0- -> 4 3'001 + +------------------------------------- + +3.6.8. Executing FSM_MAP pass (mapping FSMs to basic logic). +Mapping FSM `$fsm$\jtag_tap_fsm_state$3149' from module `\JtagBridge'. +Mapping FSM `$fsm$\stateMachine_state$3167' from module `\UartCtrlRx'. +Mapping FSM `$fsm$\stateMachine_state$3173' from module `\UartCtrlTx'. + +3.7. Executing OPT pass (performing simple optimizations). + +3.7.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module Apb3Decoder. +Optimizing module Apb3Gpio. +Optimizing module Apb3Router. +Optimizing module Apb3UartCtrl. +Optimizing module BufferCC. +Optimizing module BufferCC_1. +Optimizing module BufferCC_2. +Optimizing module BufferCC_3. +Optimizing module FlowCCByToggle. +Optimizing module InterruptCtrl. +Optimizing module JtagBridge. + +Optimizing module Murax. +Optimizing module MuraxApb3Timer. +Optimizing module MuraxMasterArbiter. +Optimizing module MuraxPipelinedMemoryBusRam. +Optimizing module PipelinedMemoryBusToApbBridge. +Optimizing module Prescaler. +Optimizing module StreamFifo. +Optimizing module StreamFifoLowLatency. +Optimizing module SystemDebugger. +Optimizing module Timer. +Optimizing module UartCtrl. +Optimizing module UartCtrlRx. + +Optimizing module UartCtrlTx. + +Optimizing module VexRiscv. + +3.7.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Apb3Decoder'. +Finding identical cells in module `\Apb3Gpio'. +Finding identical cells in module `\Apb3Router'. +Finding identical cells in module `\Apb3UartCtrl'. +Finding identical cells in module `\BufferCC'. +Finding identical cells in module `\BufferCC_1'. +Finding identical cells in module `\BufferCC_2'. +Finding identical cells in module `\BufferCC_3'. +Finding identical cells in module `\FlowCCByToggle'. +Finding identical cells in module `\InterruptCtrl'. +Finding identical cells in module `\JtagBridge'. + +Finding identical cells in module `\Murax'. +Finding identical cells in module `\MuraxApb3Timer'. +Finding identical cells in module `\MuraxMasterArbiter'. +Finding identical cells in module `\MuraxPipelinedMemoryBusRam'. +Finding identical cells in module `\PipelinedMemoryBusToApbBridge'. +Finding identical cells in module `\Prescaler'. +Finding identical cells in module `\StreamFifo'. +Finding identical cells in module `\StreamFifoLowLatency'. +Finding identical cells in module `\SystemDebugger'. +Finding identical cells in module `\Timer'. +Finding identical cells in module `\UartCtrl'. +Finding identical cells in module `\UartCtrlRx'. + +Finding identical cells in module `\UartCtrlTx'. + +Finding identical cells in module `\VexRiscv'. +Removed a total of 17 cells. + +3.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \Apb3Decoder.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Gpio.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Router.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \BufferCC.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_2.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_3.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \FlowCCByToggle.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \InterruptCtrl.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \JtagBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Murax.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxApb3Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxMasterArbiter.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Prescaler.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \StreamFifo.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \StreamFifoLowLatency.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \SystemDebugger.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlRx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlTx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \VexRiscv.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \Apb3Decoder. + Optimizing cells in module \Apb3Gpio. + Optimizing cells in module \Apb3Router. + Optimizing cells in module \Apb3UartCtrl. + Optimizing cells in module \BufferCC. + Optimizing cells in module \BufferCC_1. + Optimizing cells in module \BufferCC_2. + Optimizing cells in module \BufferCC_3. + Optimizing cells in module \FlowCCByToggle. + Optimizing cells in module \InterruptCtrl. + Optimizing cells in module \JtagBridge. + Optimizing cells in module \Murax. + Optimizing cells in module \MuraxApb3Timer. + Optimizing cells in module \MuraxMasterArbiter. + Optimizing cells in module \MuraxPipelinedMemoryBusRam. + Optimizing cells in module \PipelinedMemoryBusToApbBridge. + Optimizing cells in module \Prescaler. + Optimizing cells in module \StreamFifo. + Optimizing cells in module \StreamFifoLowLatency. + Optimizing cells in module \SystemDebugger. + Optimizing cells in module \Timer. + Optimizing cells in module \UartCtrl. + Optimizing cells in module \UartCtrlRx. + Optimizing cells in module \UartCtrlTx. + Optimizing cells in module \VexRiscv. +Performed a total of 0 changes. + +3.7.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Apb3Decoder'. +Finding identical cells in module `\Apb3Gpio'. +Finding identical cells in module `\Apb3Router'. +Finding identical cells in module `\Apb3UartCtrl'. +Finding identical cells in module `\BufferCC'. +Finding identical cells in module `\BufferCC_1'. +Finding identical cells in module `\BufferCC_2'. +Finding identical cells in module `\BufferCC_3'. +Finding identical cells in module `\FlowCCByToggle'. +Finding identical cells in module `\InterruptCtrl'. +Finding identical cells in module `\JtagBridge'. +Finding identical cells in module `\Murax'. +Finding identical cells in module `\MuraxApb3Timer'. +Finding identical cells in module `\MuraxMasterArbiter'. +Finding identical cells in module `\MuraxPipelinedMemoryBusRam'. +Finding identical cells in module `\PipelinedMemoryBusToApbBridge'. +Finding identical cells in module `\Prescaler'. +Finding identical cells in module `\StreamFifo'. +Finding identical cells in module `\StreamFifoLowLatency'. +Finding identical cells in module `\SystemDebugger'. +Finding identical cells in module `\Timer'. +Finding identical cells in module `\UartCtrl'. +Finding identical cells in module `\UartCtrlRx'. +Finding identical cells in module `\UartCtrlTx'. +Finding identical cells in module `\VexRiscv'. +Removed a total of 0 cells. + +3.7.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding EN signal on $procdff$3095 ($adff) from module Apb3Gpio (D = \io_apb_PWDATA, Q = \io_gpio_writeEnable_driver). +Adding EN signal on $procdff$3094 ($dff) from module Apb3Gpio (D = \io_apb_PWDATA, Q = \io_gpio_write_driver). +Adding EN signal on $procdff$3100 ($adff) from module Apb3UartCtrl (D = $0\bridge_misc_readOverflowError[0:0], Q = \bridge_misc_readOverflowError). +Adding EN signal on $procdff$3099 ($adff) from module Apb3UartCtrl (D = $0\bridge_misc_readError[0:0], Q = \bridge_misc_readError). +Adding EN signal on $procdff$3098 ($adff) from module Apb3UartCtrl (D = \io_apb_PWDATA [1], Q = \bridge_interruptCtrl_readIntEnable). +Adding EN signal on $procdff$3097 ($adff) from module Apb3UartCtrl (D = \io_apb_PWDATA [0], Q = \bridge_interruptCtrl_writeIntEnable). +Adding EN signal on $procdff$2911 ($dff) from module FlowCCByToggle (D = \io_input_payload_fragment, Q = \inputArea_data_fragment). +Adding EN signal on $procdff$2910 ($dff) from module FlowCCByToggle (D = \io_input_payload_last, Q = \inputArea_data_last). +Adding EN signal on $procdff$2909 ($dff) from module FlowCCByToggle (D = $logic_not$../Murax.v:6131$939_Y, Q = \inputArea_target). +Adding EN signal on $procdff$2908 ($dff) from module FlowCCByToggle (D = \inputArea_data_fragment, Q = \outputArea_flow_m2sPipe_payload_fragment). +Adding EN signal on $procdff$2907 ($dff) from module FlowCCByToggle (D = \inputArea_data_last, Q = \outputArea_flow_m2sPipe_payload_last). +Adding EN signal on $procdff$3063 ($dff) from module JtagBridge (D = \io_remote_rsp_payload_data, Q = \system_rsp_payload_data). +Adding EN signal on $procdff$3062 ($dff) from module JtagBridge (D = \io_remote_rsp_payload_error, Q = \system_rsp_payload_error). +Adding SRST signal on $procdff$3061 ($dff) from module JtagBridge (D = $procmux$2372_Y, Q = \system_rsp_valid, rval = 1'1). +Adding EN signal on $auto$ff.cc:262:slice$3450 ($sdff) from module JtagBridge (D = 1'0, Q = \system_rsp_valid). +Adding EN signal on $procdff$3060 ($dff) from module JtagBridge (D = $procmux$2349_Y, Q = \jtag_readArea_full_shifter). +Adding SRST signal on $procdff$3057 ($dff) from module JtagBridge (D = $procmux$2355_Y, Q = \jtag_idcodeArea_shifter, rval = 268443647). +Adding EN signal on $auto$ff.cc:262:slice$3457 ($sdff) from module JtagBridge (D = { \io_jtag_tdi \jtag_idcodeArea_shifter [31:1] }, Q = \jtag_idcodeArea_shifter). +Adding EN signal on $procdff$3055 ($dff) from module JtagBridge (D = $0\jtag_tap_instructionShift[3:0], Q = \jtag_tap_instructionShift). +Adding SRST signal on $procdff$3054 ($dff) from module JtagBridge (D = $procmux$2364_Y, Q = \jtag_tap_instruction, rval = 4'0001). +Adding EN signal on $auto$ff.cc:262:slice$3464 ($sdff) from module JtagBridge (D = \jtag_tap_instructionShift, Q = \jtag_tap_instruction). +Adding SRST signal on $procdff$3124 ($dff) from module Murax (D = $procmux$2854_Y, Q = \resetCtrl_systemClkResetCounter, rval = 6'000000). +Adding EN signal on $auto$ff.cc:262:slice$3466 ($sdff) from module Murax (D = $add$../Murax.v:482$34_Y, Q = \resetCtrl_systemClkResetCounter). +Adding SRST signal on $procdff$3123 ($dff) from module Murax (D = \resetCtrl_mainClkResetUnbuffered, Q = \resetCtrl_systemReset, rval = 1'1). +Adding EN signal on $procdff$3120 ($adff) from module Murax (D = $0\system_mainBusDecoder_logic_rspPending[0:0], Q = \system_mainBusDecoder_logic_rspPending). +Adding EN signal on $procdff$3119 ($adff) from module Murax (D = $0\system_cpu_dBus_cmd_rValid[0:0], Q = \system_cpu_dBus_cmd_rValid). +Adding EN signal on $procdff$3118 ($dff) from module Murax (D = \system_mainBusDecoder_logic_hits_1, Q = \system_mainBusDecoder_logic_rspSourceId). +Adding EN signal on $procdff$3117 ($dff) from module Murax (D = \system_cpu_dBus_cmd_payload_size, Q = \system_cpu_dBus_cmd_rData_size). +Adding EN signal on $procdff$3116 ($dff) from module Murax (D = \system_cpu_dBus_cmd_payload_data, Q = \system_cpu_dBus_cmd_rData_data). +Adding EN signal on $procdff$3115 ($dff) from module Murax (D = \system_cpu_dBus_cmd_payload_address, Q = \system_cpu_dBus_cmd_rData_address). +Adding EN signal on $procdff$3114 ($dff) from module Murax (D = \system_cpu_dBus_cmd_payload_wr, Q = \system_cpu_dBus_cmd_rData_wr). +Adding EN signal on $procdff$3110 ($adff) from module MuraxApb3Timer (D = \io_apb_PWDATA [1:0], Q = \interruptCtrl_1_io_masks_driver). +Adding EN signal on $procdff$3109 ($adff) from module MuraxApb3Timer (D = \io_apb_PWDATA [16], Q = \timerBBridge_clearsEnable). +Adding EN signal on $procdff$3108 ($adff) from module MuraxApb3Timer (D = \io_apb_PWDATA [1:0], Q = \timerBBridge_ticksEnable). +Adding EN signal on $procdff$3107 ($adff) from module MuraxApb3Timer (D = \io_apb_PWDATA [16], Q = \timerABridge_clearsEnable). +Adding EN signal on $procdff$3106 ($adff) from module MuraxApb3Timer (D = \io_apb_PWDATA [1:0], Q = \timerABridge_ticksEnable). +Adding EN signal on $procdff$3105 ($dff) from module MuraxApb3Timer (D = \io_apb_PWDATA [15:0], Q = \timerB_io_limit_driver). +Adding EN signal on $procdff$3104 ($dff) from module MuraxApb3Timer (D = \io_apb_PWDATA [15:0], Q = \timerA_io_limit_driver). +Adding EN signal on $procdff$3103 ($dff) from module MuraxApb3Timer (D = \io_apb_PWDATA [15:0], Q = \_zz_io_limit). +Adding EN signal on $procdff$2931 ($adff) from module MuraxMasterArbiter (D = \io_dBus_cmd_valid, Q = \rspTarget). +Adding EN signal on $procdff$2930 ($adff) from module MuraxMasterArbiter (D = $0\rspPending[0:0], Q = \rspPending). +Adding EN signal on $procdff$3085 ($dff) from module MuraxPipelinedMemoryBusRam (D = $memrd$\ram_symbol3$../Murax.v:1608$162_DATA, Q = \_zz_ramsymbol_read_3). +Adding EN signal on $procdff$3084 ($dff) from module MuraxPipelinedMemoryBusRam (D = $memrd$\ram_symbol2$../Murax.v:1607$161_DATA, Q = \_zz_ramsymbol_read_2). +Adding EN signal on $procdff$3083 ($dff) from module MuraxPipelinedMemoryBusRam (D = $memrd$\ram_symbol1$../Murax.v:1606$160_DATA, Q = \_zz_ramsymbol_read_1). +Adding EN signal on $procdff$3082 ($dff) from module MuraxPipelinedMemoryBusRam (D = $memrd$\ram_symbol0$../Murax.v:1605$159_DATA, Q = \_zz_ramsymbol_read). +Adding EN signal on $procdff$3091 ($adff) from module PipelinedMemoryBusToApbBridge (D = $0\io_pipelinedMemoryBus_cmd_rValid[0:0], Q = \io_pipelinedMemoryBus_cmd_rValid). +Adding EN signal on $procdff$3088 ($dff) from module PipelinedMemoryBusToApbBridge (D = \io_pipelinedMemoryBus_cmd_payload_data, Q = \io_pipelinedMemoryBus_cmd_rData_data). +Adding EN signal on $procdff$3087 ($dff) from module PipelinedMemoryBusToApbBridge (D = \io_pipelinedMemoryBus_cmd_payload_address, Q = \io_pipelinedMemoryBus_cmd_rData_address). +Adding EN signal on $procdff$3086 ($dff) from module PipelinedMemoryBusToApbBridge (D = \io_pipelinedMemoryBus_cmd_payload_write, Q = \io_pipelinedMemoryBus_cmd_rData_write). +Adding SRST signal on $procdff$2924 ($dff) from module Prescaler (D = $add$../Murax.v:5774$887_Y, Q = \counter, rval = 16'0000000000000000). +Adding EN signal on $procdff$2918 ($adff) from module StreamFifo (D = $0\logic_risingOccupancy[0:0], Q = \logic_risingOccupancy). +Adding EN signal on $procdff$2904 ($adff) from module StreamFifoLowLatency (D = $0\risingOccupancy[0:0], Q = \risingOccupancy). +Adding EN signal on $procdff$2903 ($dff) from module StreamFifoLowLatency (D = { \io_push_payload_inst \io_push_payload_error }, Q = \_zz_readed_error_2). +Adding EN signal on $procdff$3068 ($adff) from module SystemDebugger (D = $procmux$2424_Y, Q = \dispatcher_counter). +Adding EN signal on $procdff$3067 ($adff) from module SystemDebugger (D = $0\dispatcher_headerLoaded[0:0], Q = \dispatcher_headerLoaded). +Adding EN signal on $procdff$3066 ($adff) from module SystemDebugger (D = $0\dispatcher_dataLoaded[0:0], Q = \dispatcher_dataLoaded). +Adding EN signal on $procdff$3065 ($dff) from module SystemDebugger (D = { \io_remote_cmd_payload_fragment \dispatcher_headerShifter [7:1] }, Q = \dispatcher_headerShifter). +Adding EN signal on $procdff$3064 ($dff) from module SystemDebugger (D = { \io_remote_cmd_payload_fragment \dispatcher_dataShifter [66:1] }, Q = \dispatcher_dataShifter). +Adding EN signal on $procdff$2926 ($adff) from module Timer (D = $0\inhibitFull[0:0], Q = \inhibitFull). +Adding SRST signal on $procdff$2925 ($dff) from module Timer (D = $procmux$1387_Y, Q = \counter, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:262:slice$3552 ($sdff) from module Timer (D = $add$../Murax.v:5750$883_Y, Q = \counter). +Adding EN signal on $procdff$2900 ($adff) from module UartCtrlRx (D = $0\break_counter[6:0], Q = \break_counter). +Adding EN signal on $procdff$2897 ($adff) from module UartCtrlRx (D = \sampler_samples_1, Q = \sampler_samples_2). +Adding EN signal on $procdff$2896 ($adff) from module UartCtrlRx (D = \io_rxd_buffercc_io_dataOut, Q = \sampler_samples_1). +Adding EN signal on $procdff$2891 ($dff) from module UartCtrlRx (D = $or$../Murax.v:0$1017_Y, Q = \stateMachine_shifter). +Adding EN signal on $procdff$3046 ($adff) from module VexRiscv (D = $0\switch_Fetcher_l362[2:0], Q = \switch_Fetcher_l362). +Adding EN signal on $procdff$3044 ($adff) from module VexRiscv (D = $0\execute_LightShifterPlugin_isActive[0:0], Q = \execute_LightShifterPlugin_isActive). +Adding EN signal on $procdff$3040 ($adff) from module VexRiscv (D = $0\CsrPlugin_pipelineLiberator_pcValids_2[0:0], Q = \CsrPlugin_pipelineLiberator_pcValids_2). +Adding EN signal on $procdff$3039 ($adff) from module VexRiscv (D = $0\CsrPlugin_pipelineLiberator_pcValids_1[0:0], Q = \CsrPlugin_pipelineLiberator_pcValids_1). +Adding EN signal on $procdff$3038 ($adff) from module VexRiscv (D = $0\CsrPlugin_pipelineLiberator_pcValids_0[0:0], Q = \CsrPlugin_pipelineLiberator_pcValids_0). +Adding EN signal on $procdff$3034 ($adff) from module VexRiscv (D = \_zz_CsrPlugin_csrMapping_writeDataSignal [3], Q = \CsrPlugin_mie_MSIE). +Adding EN signal on $procdff$3033 ($adff) from module VexRiscv (D = \_zz_CsrPlugin_csrMapping_writeDataSignal [7], Q = \CsrPlugin_mie_MTIE). +Adding EN signal on $procdff$3032 ($adff) from module VexRiscv (D = \_zz_CsrPlugin_csrMapping_writeDataSignal [11], Q = \CsrPlugin_mie_MEIE). +Adding EN signal on $procdff$3020 ($adff) from module VexRiscv (D = $0\_zz_IBusSimplePlugin_injector_decodeInput_valid[0:0], Q = \_zz_IBusSimplePlugin_injector_decodeInput_valid). +Adding EN signal on $procdff$3019 ($adff) from module VexRiscv (D = $0\_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid[0:0], Q = \_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid). +Adding EN signal on $procdff$3018 ($adff) from module VexRiscv (D = $0\_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2[0:0], Q = \_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2). +Adding EN signal on $procdff$3017 ($adff) from module VexRiscv (D = $0\IBusSimplePlugin_fetchPc_inc[0:0], Q = \IBusSimplePlugin_fetchPc_inc). +Adding EN signal on $procdff$3014 ($adff) from module VexRiscv (D = { \IBusSimplePlugin_fetchPc_pc [31:2] 2'00 }, Q = \IBusSimplePlugin_fetchPc_pcReg). +Adding EN signal on $procdff$3012 ($adff) from module VexRiscv (D = $0\memory_arbitration_isValid[0:0], Q = \memory_arbitration_isValid). +Adding EN signal on $procdff$3011 ($adff) from module VexRiscv (D = $0\execute_arbitration_isValid[0:0], Q = \execute_arbitration_isValid). +Adding EN signal on $procdff$3010 ($dff) from module VexRiscv (D = $eq$../Murax.v:5476$846_Y, Q = \execute_CsrPlugin_csr_834). +Adding EN signal on $procdff$3009 ($dff) from module VexRiscv (D = $eq$../Murax.v:5473$845_Y, Q = \execute_CsrPlugin_csr_772). +Adding EN signal on $procdff$3008 ($dff) from module VexRiscv (D = $eq$../Murax.v:5470$844_Y, Q = \execute_CsrPlugin_csr_836). +Adding EN signal on $procdff$3007 ($dff) from module VexRiscv (D = $eq$../Murax.v:5467$843_Y, Q = \execute_CsrPlugin_csr_768). +Adding EN signal on $procdff$3005 ($dff) from module VexRiscv (D = { \execute_BranchPlugin_branchAdder [31:1] 1'0 }, Q = \execute_to_memory_BRANCH_CALC). +Adding EN signal on $procdff$3004 ($dff) from module VexRiscv (D = \_zz_execute_BRANCH_DO_1, Q = \execute_to_memory_BRANCH_DO). +Adding EN signal on $procdff$3002 ($dff) from module VexRiscv (D = \_zz_execute_to_memory_REGFILE_WRITE_DATA, Q = \execute_to_memory_REGFILE_WRITE_DATA). +Adding EN signal on $procdff$3000 ($dff) from module VexRiscv (D = \execute_SrcPlugin_addSub [1:0], Q = \execute_to_memory_MEMORY_ADDRESS_LOW). +Adding EN signal on $procdff$2999 ($dff) from module VexRiscv (D = \decode_DO_EBREAK, Q = \decode_to_execute_DO_EBREAK). +Adding EN signal on $procdff$2998 ($dff) from module VexRiscv (D = \_zz_decode_SRC2_6, Q = \decode_to_execute_SRC2). +Adding EN signal on $procdff$2997 ($dff) from module VexRiscv (D = \_zz_decode_SRC1_1, Q = \decode_to_execute_SRC1). +Adding EN signal on $procdff$2996 ($dff) from module VexRiscv (D = \decode_SRC2_FORCE_ZERO, Q = \decode_to_execute_SRC2_FORCE_ZERO). +Adding EN signal on $procdff$2995 ($dff) from module VexRiscv (D = \_zz_RegFilePlugin_regFile_port1, Q = \decode_to_execute_RS2). +Adding EN signal on $procdff$2994 ($dff) from module VexRiscv (D = \_zz_RegFilePlugin_regFile_port0, Q = \decode_to_execute_RS1). +Adding EN signal on $procdff$2993 ($dff) from module VexRiscv (D = \_zz_decode_BRANCH_CTRL, Q = \decode_to_execute_BRANCH_CTRL). +Adding EN signal on $procdff$2992 ($dff) from module VexRiscv (D = { \_zz__zz_decode_BRANCH_CTRL_2_4 \_zz_decode_BRANCH_CTRL_2 [21] }, Q = \decode_to_execute_SHIFT_CTRL). +Adding EN signal on $procdff$2991 ($dff) from module VexRiscv (D = { \_zz__zz_decode_BRANCH_CTRL_2_13 \_zz__zz_decode_BRANCH_CTRL_2_17 }, Q = \decode_to_execute_ALU_BITWISE_CTRL). +Adding EN signal on $procdff$2990 ($dff) from module VexRiscv (D = \decode_SRC_LESS_UNSIGNED, Q = \decode_to_execute_SRC_LESS_UNSIGNED). +Adding EN signal on $procdff$2989 ($dff) from module VexRiscv (D = { \_zz__zz_decode_BRANCH_CTRL_2_21 \_zz__zz_decode_BRANCH_CTRL_2_26 }, Q = \decode_to_execute_ALU_CTRL). +Adding EN signal on $procdff$2987 ($dff) from module VexRiscv (D = \decode_to_execute_ENV_CTRL, Q = \execute_to_memory_ENV_CTRL). +Adding EN signal on $procdff$2986 ($dff) from module VexRiscv (D = \_zz__zz_decode_BRANCH_CTRL_2_28, Q = \decode_to_execute_ENV_CTRL). +Adding EN signal on $procdff$2985 ($dff) from module VexRiscv (D = \decode_IS_CSR, Q = \decode_to_execute_IS_CSR). +Adding EN signal on $procdff$2984 ($dff) from module VexRiscv (D = \decode_to_execute_MEMORY_STORE, Q = \execute_to_memory_MEMORY_STORE). +Adding EN signal on $procdff$2983 ($dff) from module VexRiscv (D = \_zz__zz_decode_BRANCH_CTRL_2_43, Q = \decode_to_execute_MEMORY_STORE). +Adding EN signal on $procdff$2978 ($dff) from module VexRiscv (D = \decode_to_execute_REGFILE_WRITE_VALID, Q = \execute_to_memory_REGFILE_WRITE_VALID). +Adding EN signal on $procdff$2977 ($dff) from module VexRiscv (D = \decode_REGFILE_WRITE_VALID, Q = \decode_to_execute_REGFILE_WRITE_VALID). +Adding SRST signal on $auto$ff.cc:262:slice$3648 ($dffe) from module VexRiscv (D = \_zz__zz_decode_BRANCH_CTRL_2_47, Q = \decode_to_execute_REGFILE_WRITE_VALID, rval = 1'0). +Adding EN signal on $procdff$2975 ($dff) from module VexRiscv (D = \decode_to_execute_MEMORY_ENABLE, Q = \execute_to_memory_MEMORY_ENABLE). +Adding EN signal on $procdff$2974 ($dff) from module VexRiscv (D = \_zz__zz_decode_BRANCH_CTRL_2_71, Q = \decode_to_execute_MEMORY_ENABLE). +Adding EN signal on $procdff$2973 ($dff) from module VexRiscv (D = \decode_SRC_USE_SUB_LESS, Q = \decode_to_execute_SRC_USE_SUB_LESS). +Adding EN signal on $procdff$2971 ($dff) from module VexRiscv (D = \decode_CSR_WRITE_OPCODE, Q = \decode_to_execute_CSR_WRITE_OPCODE). +Adding EN signal on $procdff$2966 ($dff) from module VexRiscv (D = \decode_to_execute_INSTRUCTION, Q = \execute_to_memory_INSTRUCTION). +Adding EN signal on $procdff$2965 ($dff) from module VexRiscv (D = \_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst, Q = \decode_to_execute_INSTRUCTION). +Adding EN signal on $procdff$2962 ($dff) from module VexRiscv (D = \_zz_IBusSimplePlugin_injector_decodeInput_payload_pc, Q = \decode_to_execute_PC). +Adding EN signal on $procdff$2959 ($dff) from module VexRiscv (D = $sub$../Murax.v:5323$842_Y, Q = \execute_LightShifterPlugin_amplitudeReg). +Adding EN signal on $procdff$2958 ($dff) from module VexRiscv (D = $procmux$1598_Y, Q = \CsrPlugin_interrupt_targetPrivilege). +Adding SRST signal on $auto$ff.cc:262:slice$3662 ($dffe) from module VexRiscv (D = 2'x, Q = \CsrPlugin_interrupt_targetPrivilege, rval = 2'11). +Adding EN signal on $procdff$2957 ($dff) from module VexRiscv (D = $procmux$1606_Y, Q = \CsrPlugin_interrupt_code). +Adding SRST signal on $auto$ff.cc:262:slice$3670 ($dffe) from module VexRiscv (D = 2'x, Q = \CsrPlugin_interrupt_code [1:0], rval = 2'11). +Adding SRST signal on $auto$ff.cc:262:slice$3670 ($dffe) from module VexRiscv (D = $procmux$1602_Y [2], Q = \CsrPlugin_interrupt_code [2], rval = 1'0). +Adding SRST signal on $auto$ff.cc:262:slice$3670 ($dffe) from module VexRiscv (D = $procmux$1604_Y [3], Q = \CsrPlugin_interrupt_code [3], rval = 1'1). +Adding EN signal on $procdff$2956 ($dff) from module VexRiscv (D = \CsrPlugin_interrupt_code, Q = \CsrPlugin_mcause_exceptionCode). +Adding EN signal on $procdff$2955 ($dff) from module VexRiscv (D = 1'1, Q = \CsrPlugin_mcause_interrupt). +Adding EN signal on $procdff$2951 ($dff) from module VexRiscv (D = \_zz_IBusSimplePlugin_injector_decodeInput_payload_pc, Q = \CsrPlugin_mepc). +Adding EN signal on $procdff$2948 ($dff) from module VexRiscv (D = { $0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0] [31:25] $0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0] [14:0] }, Q = { \_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst [31:25] \_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst [14:0] }). +Adding EN signal on $procdff$2946 ($dff) from module VexRiscv (D = \_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload, Q = \_zz_IBusSimplePlugin_injector_decodeInput_payload_pc). +Adding EN signal on $procdff$2945 ($dff) from module VexRiscv (D = \IBusSimplePlugin_fetchPc_pcReg, Q = \_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload). +Adding EN signal on $procdff$2942 ($dff) from module VexRiscv (D = $0\DebugPlugin_busReadDataReg[31:0], Q = \DebugPlugin_busReadDataReg). +Adding EN signal on $procdff$2938 ($adff) from module VexRiscv (D = $procmux$1416_Y, Q = \DebugPlugin_disableEbreak). +Adding EN signal on $procdff$2937 ($adff) from module VexRiscv (D = 1'1, Q = \DebugPlugin_debugUsed). +Adding EN signal on $procdff$2934 ($adff) from module VexRiscv (D = \debug_bus_cmd_payload_data [4], Q = \DebugPlugin_stepIt). +Adding EN signal on $procdff$2932 ($adff) from module VexRiscv (D = $procmux$1474_Y, Q = \DebugPlugin_resetIt). +Setting constant 1-bit at position 0 on $auto$ff.cc:262:slice$3675 ($sdffce) from module VexRiscv. +Setting constant 1-bit at position 1 on $auto$ff.cc:262:slice$3675 ($sdffce) from module VexRiscv. +Setting constant 1-bit at position 0 on $auto$ff.cc:262:slice$3685 ($dffe) from module VexRiscv. +Setting constant 1-bit at position 0 on $auto$ff.cc:262:slice$3667 ($sdffce) from module VexRiscv. +Setting constant 1-bit at position 1 on $auto$ff.cc:262:slice$3667 ($sdffce) from module VexRiscv. +Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$3627 ($dffe) from module VexRiscv. +Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$3616 ($adffe) from module VexRiscv. +Setting constant 0-bit at position 1 on $auto$ff.cc:262:slice$3616 ($adffe) from module VexRiscv. + +3.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Apb3Decoder.. +Finding unused cells or wires in module \Apb3Gpio.. +Finding unused cells or wires in module \Apb3Router.. +Finding unused cells or wires in module \Apb3UartCtrl.. +Finding unused cells or wires in module \BufferCC.. +Finding unused cells or wires in module \BufferCC_1.. +Finding unused cells or wires in module \BufferCC_2.. +Finding unused cells or wires in module \BufferCC_3.. +Finding unused cells or wires in module \FlowCCByToggle.. +Finding unused cells or wires in module \InterruptCtrl.. +Finding unused cells or wires in module \JtagBridge.. +Finding unused cells or wires in module \Murax.. +Finding unused cells or wires in module \MuraxApb3Timer.. +Finding unused cells or wires in module \MuraxMasterArbiter.. +Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam.. +Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge.. +Finding unused cells or wires in module \Prescaler.. +Finding unused cells or wires in module \StreamFifo.. +Finding unused cells or wires in module \StreamFifoLowLatency.. +Finding unused cells or wires in module \SystemDebugger.. +Finding unused cells or wires in module \Timer.. +Finding unused cells or wires in module \UartCtrl.. +Finding unused cells or wires in module \UartCtrlRx.. +Finding unused cells or wires in module \UartCtrlTx.. +Finding unused cells or wires in module \VexRiscv.. +Removed 140 unused cells and 199 unused wires. + + +3.7.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module Apb3Decoder. +Optimizing module Apb3Gpio. +Optimizing module Apb3Router. +Optimizing module Apb3UartCtrl. + +Optimizing module BufferCC. +Optimizing module BufferCC_1. +Optimizing module BufferCC_2. +Optimizing module BufferCC_3. +Optimizing module FlowCCByToggle. +Optimizing module InterruptCtrl. +Optimizing module JtagBridge. + +Optimizing module Murax. + +Optimizing module MuraxApb3Timer. +Optimizing module MuraxMasterArbiter. + +Optimizing module MuraxPipelinedMemoryBusRam. +Optimizing module PipelinedMemoryBusToApbBridge. + +Optimizing module Prescaler. +Optimizing module StreamFifo. + +Optimizing module StreamFifoLowLatency. + +Optimizing module SystemDebugger. + +Optimizing module Timer. + +Optimizing module UartCtrl. +Optimizing module UartCtrlRx. + +Optimizing module UartCtrlTx. +Optimizing module VexRiscv. + + +3.7.9. Rerunning OPT passes. (Maybe there is more to do..) + +3.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \Apb3Decoder.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Gpio.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Router.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \BufferCC.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_2.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_3.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \FlowCCByToggle.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \InterruptCtrl.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \JtagBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Murax.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxApb3Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxMasterArbiter.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Prescaler.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \StreamFifo.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \StreamFifoLowLatency.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \SystemDebugger.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlRx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlTx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \VexRiscv.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \Apb3Decoder. + Optimizing cells in module \Apb3Gpio. + Optimizing cells in module \Apb3Router. + Optimizing cells in module \Apb3UartCtrl. + Optimizing cells in module \BufferCC. + Optimizing cells in module \BufferCC_1. + Optimizing cells in module \BufferCC_2. + Optimizing cells in module \BufferCC_3. + Optimizing cells in module \FlowCCByToggle. + Optimizing cells in module \InterruptCtrl. + Optimizing cells in module \JtagBridge. + Optimizing cells in module \Murax. + Optimizing cells in module \MuraxApb3Timer. + Optimizing cells in module \MuraxMasterArbiter. + Optimizing cells in module \MuraxPipelinedMemoryBusRam. + Optimizing cells in module \PipelinedMemoryBusToApbBridge. + Optimizing cells in module \Prescaler. + Optimizing cells in module \StreamFifo. + Optimizing cells in module \StreamFifoLowLatency. + Optimizing cells in module \SystemDebugger. + Optimizing cells in module \Timer. + Optimizing cells in module \UartCtrl. + Optimizing cells in module \UartCtrlRx. + Optimizing cells in module \UartCtrlTx. + Optimizing cells in module \VexRiscv. +Performed a total of 0 changes. + +3.7.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Apb3Decoder'. +Finding identical cells in module `\Apb3Gpio'. +Finding identical cells in module `\Apb3Router'. +Finding identical cells in module `\Apb3UartCtrl'. + +Finding identical cells in module `\BufferCC'. +Finding identical cells in module `\BufferCC_1'. +Finding identical cells in module `\BufferCC_2'. +Finding identical cells in module `\BufferCC_3'. +Finding identical cells in module `\FlowCCByToggle'. +Finding identical cells in module `\InterruptCtrl'. +Finding identical cells in module `\JtagBridge'. +Finding identical cells in module `\Murax'. +Finding identical cells in module `\MuraxApb3Timer'. + +Finding identical cells in module `\MuraxMasterArbiter'. +Finding identical cells in module `\MuraxPipelinedMemoryBusRam'. +Finding identical cells in module `\PipelinedMemoryBusToApbBridge'. +Finding identical cells in module `\Prescaler'. +Finding identical cells in module `\StreamFifo'. +Finding identical cells in module `\StreamFifoLowLatency'. +Finding identical cells in module `\SystemDebugger'. + +Finding identical cells in module `\Timer'. +Finding identical cells in module `\UartCtrl'. +Finding identical cells in module `\UartCtrlRx'. +Finding identical cells in module `\UartCtrlTx'. +Finding identical cells in module `\VexRiscv'. + +Removed a total of 9 cells. + +3.7.13. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 1-bit at position 0 on $auto$ff.cc:262:slice$3682 ($dffe) from module VexRiscv. +Setting constant 1-bit at position 1 on $auto$ff.cc:262:slice$3682 ($dffe) from module VexRiscv. +Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$3696 ($dffe) from module VexRiscv. +Setting constant 0-bit at position 1 on $auto$ff.cc:262:slice$3696 ($dffe) from module VexRiscv. + +3.7.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Apb3Decoder.. +Finding unused cells or wires in module \Apb3Gpio.. +Finding unused cells or wires in module \Apb3Router.. +Finding unused cells or wires in module \Apb3UartCtrl.. +Finding unused cells or wires in module \BufferCC.. +Finding unused cells or wires in module \BufferCC_1.. +Finding unused cells or wires in module \BufferCC_2.. +Finding unused cells or wires in module \BufferCC_3.. +Finding unused cells or wires in module \FlowCCByToggle.. +Finding unused cells or wires in module \InterruptCtrl.. +Finding unused cells or wires in module \JtagBridge.. +Finding unused cells or wires in module \Murax.. +Finding unused cells or wires in module \MuraxApb3Timer.. +Finding unused cells or wires in module \MuraxMasterArbiter.. +Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam.. +Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge.. +Finding unused cells or wires in module \Prescaler.. +Finding unused cells or wires in module \StreamFifo.. +Finding unused cells or wires in module \StreamFifoLowLatency.. +Finding unused cells or wires in module \SystemDebugger.. +Finding unused cells or wires in module \Timer.. +Finding unused cells or wires in module \UartCtrl.. +Finding unused cells or wires in module \UartCtrlRx.. +Finding unused cells or wires in module \UartCtrlTx.. +Finding unused cells or wires in module \VexRiscv.. +Removed 0 unused cells and 15 unused wires. + + +3.7.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module Apb3Decoder. +Optimizing module Apb3Gpio. +Optimizing module Apb3Router. +Optimizing module Apb3UartCtrl. +Optimizing module BufferCC. +Optimizing module BufferCC_1. +Optimizing module BufferCC_2. +Optimizing module BufferCC_3. +Optimizing module FlowCCByToggle. +Optimizing module InterruptCtrl. +Optimizing module JtagBridge. +Optimizing module Murax. +Optimizing module MuraxApb3Timer. +Optimizing module MuraxMasterArbiter. +Optimizing module MuraxPipelinedMemoryBusRam. +Optimizing module PipelinedMemoryBusToApbBridge. +Optimizing module Prescaler. +Optimizing module StreamFifo. +Optimizing module StreamFifoLowLatency. +Optimizing module SystemDebugger. +Optimizing module Timer. +Optimizing module UartCtrl. +Optimizing module UartCtrlRx. +Optimizing module UartCtrlTx. +Optimizing module VexRiscv. + +3.7.16. Rerunning OPT passes. (Maybe there is more to do..) + +3.7.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \Apb3Decoder.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Gpio.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Router.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \BufferCC.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_2.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_3.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \FlowCCByToggle.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \InterruptCtrl.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \JtagBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Murax.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxApb3Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxMasterArbiter.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Prescaler.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \StreamFifo.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \StreamFifoLowLatency.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \SystemDebugger.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlRx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlTx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \VexRiscv.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.7.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \Apb3Decoder. + Optimizing cells in module \Apb3Gpio. + Optimizing cells in module \Apb3Router. + Optimizing cells in module \Apb3UartCtrl. + Optimizing cells in module \BufferCC. + Optimizing cells in module \BufferCC_1. + Optimizing cells in module \BufferCC_2. + Optimizing cells in module \BufferCC_3. + Optimizing cells in module \FlowCCByToggle. + Optimizing cells in module \InterruptCtrl. + Optimizing cells in module \JtagBridge. + Optimizing cells in module \Murax. + Optimizing cells in module \MuraxApb3Timer. + Optimizing cells in module \MuraxMasterArbiter. + Optimizing cells in module \MuraxPipelinedMemoryBusRam. + Optimizing cells in module \PipelinedMemoryBusToApbBridge. + Optimizing cells in module \Prescaler. + Optimizing cells in module \StreamFifo. + Optimizing cells in module \StreamFifoLowLatency. + Optimizing cells in module \SystemDebugger. + Optimizing cells in module \Timer. + Optimizing cells in module \UartCtrl. + Optimizing cells in module \UartCtrlRx. + Optimizing cells in module \UartCtrlTx. + Optimizing cells in module \VexRiscv. +Performed a total of 0 changes. + +3.7.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Apb3Decoder'. +Finding identical cells in module `\Apb3Gpio'. +Finding identical cells in module `\Apb3Router'. +Finding identical cells in module `\Apb3UartCtrl'. +Finding identical cells in module `\BufferCC'. +Finding identical cells in module `\BufferCC_1'. +Finding identical cells in module `\BufferCC_2'. +Finding identical cells in module `\BufferCC_3'. +Finding identical cells in module `\FlowCCByToggle'. +Finding identical cells in module `\InterruptCtrl'. +Finding identical cells in module `\JtagBridge'. +Finding identical cells in module `\Murax'. +Finding identical cells in module `\MuraxApb3Timer'. +Finding identical cells in module `\MuraxMasterArbiter'. +Finding identical cells in module `\MuraxPipelinedMemoryBusRam'. +Finding identical cells in module `\PipelinedMemoryBusToApbBridge'. +Finding identical cells in module `\Prescaler'. +Finding identical cells in module `\StreamFifo'. +Finding identical cells in module `\StreamFifoLowLatency'. +Finding identical cells in module `\SystemDebugger'. +Finding identical cells in module `\Timer'. +Finding identical cells in module `\UartCtrl'. +Finding identical cells in module `\UartCtrlRx'. +Finding identical cells in module `\UartCtrlTx'. +Finding identical cells in module `\VexRiscv'. +Removed a total of 0 cells. + +3.7.20. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$3695 ($dffe) from module VexRiscv. +Setting constant 0-bit at position 1 on $auto$ff.cc:262:slice$3695 ($dffe) from module VexRiscv. + +3.7.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Apb3Decoder.. +Finding unused cells or wires in module \Apb3Gpio.. +Finding unused cells or wires in module \Apb3Router.. +Finding unused cells or wires in module \Apb3UartCtrl.. +Finding unused cells or wires in module \BufferCC.. +Finding unused cells or wires in module \BufferCC_1.. +Finding unused cells or wires in module \BufferCC_2.. +Finding unused cells or wires in module \BufferCC_3.. +Finding unused cells or wires in module \FlowCCByToggle.. +Finding unused cells or wires in module \InterruptCtrl.. +Finding unused cells or wires in module \JtagBridge.. +Finding unused cells or wires in module \Murax.. +Finding unused cells or wires in module \MuraxApb3Timer.. +Finding unused cells or wires in module \MuraxMasterArbiter.. +Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam.. +Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge.. +Finding unused cells or wires in module \Prescaler.. +Finding unused cells or wires in module \StreamFifo.. +Finding unused cells or wires in module \StreamFifoLowLatency.. +Finding unused cells or wires in module \SystemDebugger.. +Finding unused cells or wires in module \Timer.. +Finding unused cells or wires in module \UartCtrl.. +Finding unused cells or wires in module \UartCtrlRx.. +Finding unused cells or wires in module \UartCtrlTx.. +Finding unused cells or wires in module \VexRiscv.. + +3.7.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module Apb3Decoder. +Optimizing module Apb3Gpio. +Optimizing module Apb3Router. +Optimizing module Apb3UartCtrl. +Optimizing module BufferCC. +Optimizing module BufferCC_1. +Optimizing module BufferCC_2. +Optimizing module BufferCC_3. +Optimizing module FlowCCByToggle. +Optimizing module InterruptCtrl. +Optimizing module JtagBridge. +Optimizing module Murax. +Optimizing module MuraxApb3Timer. +Optimizing module MuraxMasterArbiter. +Optimizing module MuraxPipelinedMemoryBusRam. +Optimizing module PipelinedMemoryBusToApbBridge. +Optimizing module Prescaler. +Optimizing module StreamFifo. +Optimizing module StreamFifoLowLatency. +Optimizing module SystemDebugger. +Optimizing module Timer. +Optimizing module UartCtrl. +Optimizing module UartCtrlRx. +Optimizing module UartCtrlTx. +Optimizing module VexRiscv. + +3.7.23. Rerunning OPT passes. (Maybe there is more to do..) + +3.7.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \Apb3Decoder.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Gpio.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Router.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \BufferCC.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_2.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_3.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \FlowCCByToggle.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \InterruptCtrl.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \JtagBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Murax.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxApb3Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxMasterArbiter.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Prescaler.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \StreamFifo.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \StreamFifoLowLatency.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \SystemDebugger.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlRx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlTx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \VexRiscv.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.7.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \Apb3Decoder. + Optimizing cells in module \Apb3Gpio. + Optimizing cells in module \Apb3Router. + Optimizing cells in module \Apb3UartCtrl. + Optimizing cells in module \BufferCC. + Optimizing cells in module \BufferCC_1. + Optimizing cells in module \BufferCC_2. + Optimizing cells in module \BufferCC_3. + Optimizing cells in module \FlowCCByToggle. + Optimizing cells in module \InterruptCtrl. + Optimizing cells in module \JtagBridge. + Optimizing cells in module \Murax. + Optimizing cells in module \MuraxApb3Timer. + Optimizing cells in module \MuraxMasterArbiter. + Optimizing cells in module \MuraxPipelinedMemoryBusRam. + Optimizing cells in module \PipelinedMemoryBusToApbBridge. + Optimizing cells in module \Prescaler. + Optimizing cells in module \StreamFifo. + Optimizing cells in module \StreamFifoLowLatency. + Optimizing cells in module \SystemDebugger. + Optimizing cells in module \Timer. + Optimizing cells in module \UartCtrl. + Optimizing cells in module \UartCtrlRx. + Optimizing cells in module \UartCtrlTx. + Optimizing cells in module \VexRiscv. +Performed a total of 0 changes. + +3.7.26. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Apb3Decoder'. +Finding identical cells in module `\Apb3Gpio'. +Finding identical cells in module `\Apb3Router'. +Finding identical cells in module `\Apb3UartCtrl'. +Finding identical cells in module `\BufferCC'. +Finding identical cells in module `\BufferCC_1'. +Finding identical cells in module `\BufferCC_2'. +Finding identical cells in module `\BufferCC_3'. +Finding identical cells in module `\FlowCCByToggle'. +Finding identical cells in module `\InterruptCtrl'. +Finding identical cells in module `\JtagBridge'. +Finding identical cells in module `\Murax'. +Finding identical cells in module `\MuraxApb3Timer'. +Finding identical cells in module `\MuraxMasterArbiter'. +Finding identical cells in module `\MuraxPipelinedMemoryBusRam'. +Finding identical cells in module `\PipelinedMemoryBusToApbBridge'. +Finding identical cells in module `\Prescaler'. +Finding identical cells in module `\StreamFifo'. +Finding identical cells in module `\StreamFifoLowLatency'. +Finding identical cells in module `\SystemDebugger'. +Finding identical cells in module `\Timer'. +Finding identical cells in module `\UartCtrl'. +Finding identical cells in module `\UartCtrlRx'. +Finding identical cells in module `\UartCtrlTx'. +Finding identical cells in module `\VexRiscv'. +Removed a total of 0 cells. + +3.7.27. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$3656 ($dffe) from module VexRiscv. +Setting constant 0-bit at position 1 on $auto$ff.cc:262:slice$3656 ($dffe) from module VexRiscv. +Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$3688 ($dffe) from module VexRiscv. +Setting constant 0-bit at position 1 on $auto$ff.cc:262:slice$3688 ($dffe) from module VexRiscv. + +3.7.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Apb3Decoder.. +Finding unused cells or wires in module \Apb3Gpio.. +Finding unused cells or wires in module \Apb3Router.. +Finding unused cells or wires in module \Apb3UartCtrl.. +Finding unused cells or wires in module \BufferCC.. +Finding unused cells or wires in module \BufferCC_1.. +Finding unused cells or wires in module \BufferCC_2.. +Finding unused cells or wires in module \BufferCC_3.. +Finding unused cells or wires in module \FlowCCByToggle.. +Finding unused cells or wires in module \InterruptCtrl.. +Finding unused cells or wires in module \JtagBridge.. +Finding unused cells or wires in module \Murax.. +Finding unused cells or wires in module \MuraxApb3Timer.. +Finding unused cells or wires in module \MuraxMasterArbiter.. +Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam.. +Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge.. +Finding unused cells or wires in module \Prescaler.. +Finding unused cells or wires in module \StreamFifo.. +Finding unused cells or wires in module \StreamFifoLowLatency.. +Finding unused cells or wires in module \SystemDebugger.. +Finding unused cells or wires in module \Timer.. +Finding unused cells or wires in module \UartCtrl.. +Finding unused cells or wires in module \UartCtrlRx.. +Finding unused cells or wires in module \UartCtrlTx.. +Finding unused cells or wires in module \VexRiscv.. + +3.7.29. Executing OPT_EXPR pass (perform const folding). +Optimizing module Apb3Decoder. +Optimizing module Apb3Gpio. +Optimizing module Apb3Router. +Optimizing module Apb3UartCtrl. +Optimizing module BufferCC. +Optimizing module BufferCC_1. +Optimizing module BufferCC_2. +Optimizing module BufferCC_3. +Optimizing module FlowCCByToggle. +Optimizing module InterruptCtrl. +Optimizing module JtagBridge. +Optimizing module Murax. +Optimizing module MuraxApb3Timer. +Optimizing module MuraxMasterArbiter. +Optimizing module MuraxPipelinedMemoryBusRam. +Optimizing module PipelinedMemoryBusToApbBridge. +Optimizing module Prescaler. +Optimizing module StreamFifo. +Optimizing module StreamFifoLowLatency. +Optimizing module SystemDebugger. +Optimizing module Timer. +Optimizing module UartCtrl. +Optimizing module UartCtrlRx. +Optimizing module UartCtrlTx. +Optimizing module VexRiscv. + +3.7.30. Rerunning OPT passes. (Maybe there is more to do..) + +3.7.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \Apb3Decoder.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Gpio.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Router.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \BufferCC.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_2.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_3.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \FlowCCByToggle.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \InterruptCtrl.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \JtagBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Murax.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxApb3Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxMasterArbiter.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Prescaler.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \StreamFifo.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \StreamFifoLowLatency.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \SystemDebugger.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlRx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlTx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \VexRiscv.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.7.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \Apb3Decoder. + Optimizing cells in module \Apb3Gpio. + Optimizing cells in module \Apb3Router. + Optimizing cells in module \Apb3UartCtrl. + Optimizing cells in module \BufferCC. + Optimizing cells in module \BufferCC_1. + Optimizing cells in module \BufferCC_2. + Optimizing cells in module \BufferCC_3. + Optimizing cells in module \FlowCCByToggle. + Optimizing cells in module \InterruptCtrl. + Optimizing cells in module \JtagBridge. + Optimizing cells in module \Murax. + Optimizing cells in module \MuraxApb3Timer. + Optimizing cells in module \MuraxMasterArbiter. + Optimizing cells in module \MuraxPipelinedMemoryBusRam. + Optimizing cells in module \PipelinedMemoryBusToApbBridge. + Optimizing cells in module \Prescaler. + Optimizing cells in module \StreamFifo. + Optimizing cells in module \StreamFifoLowLatency. + Optimizing cells in module \SystemDebugger. + Optimizing cells in module \Timer. + Optimizing cells in module \UartCtrl. + Optimizing cells in module \UartCtrlRx. + Optimizing cells in module \UartCtrlTx. + Optimizing cells in module \VexRiscv. +Performed a total of 0 changes. + +3.7.33. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Apb3Decoder'. +Finding identical cells in module `\Apb3Gpio'. +Finding identical cells in module `\Apb3Router'. +Finding identical cells in module `\Apb3UartCtrl'. +Finding identical cells in module `\BufferCC'. +Finding identical cells in module `\BufferCC_1'. +Finding identical cells in module `\BufferCC_2'. +Finding identical cells in module `\BufferCC_3'. +Finding identical cells in module `\FlowCCByToggle'. +Finding identical cells in module `\InterruptCtrl'. +Finding identical cells in module `\JtagBridge'. +Finding identical cells in module `\Murax'. +Finding identical cells in module `\MuraxApb3Timer'. +Finding identical cells in module `\MuraxMasterArbiter'. +Finding identical cells in module `\MuraxPipelinedMemoryBusRam'. +Finding identical cells in module `\PipelinedMemoryBusToApbBridge'. +Finding identical cells in module `\Prescaler'. +Finding identical cells in module `\StreamFifo'. +Finding identical cells in module `\StreamFifoLowLatency'. +Finding identical cells in module `\SystemDebugger'. +Finding identical cells in module `\Timer'. +Finding identical cells in module `\UartCtrl'. +Finding identical cells in module `\UartCtrlRx'. +Finding identical cells in module `\UartCtrlTx'. +Finding identical cells in module `\VexRiscv'. +Removed a total of 0 cells. + +3.7.34. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $auto$ff.cc:262:slice$3697 ($dffe) from module VexRiscv (D = $procmux$1484_Y [1:0], Q = \DebugPlugin_busReadDataReg [1:0], rval = 2'00). + +3.7.35. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Apb3Decoder.. +Finding unused cells or wires in module \Apb3Gpio.. +Finding unused cells or wires in module \Apb3Router.. +Finding unused cells or wires in module \Apb3UartCtrl.. +Finding unused cells or wires in module \BufferCC.. +Finding unused cells or wires in module \BufferCC_1.. +Finding unused cells or wires in module \BufferCC_2.. +Finding unused cells or wires in module \BufferCC_3.. +Finding unused cells or wires in module \FlowCCByToggle.. +Finding unused cells or wires in module \InterruptCtrl.. +Finding unused cells or wires in module \JtagBridge.. +Finding unused cells or wires in module \Murax.. +Finding unused cells or wires in module \MuraxApb3Timer.. +Finding unused cells or wires in module \MuraxMasterArbiter.. +Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam.. +Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge.. +Finding unused cells or wires in module \Prescaler.. +Finding unused cells or wires in module \StreamFifo.. +Finding unused cells or wires in module \StreamFifoLowLatency.. +Finding unused cells or wires in module \SystemDebugger.. +Finding unused cells or wires in module \Timer.. +Finding unused cells or wires in module \UartCtrl.. +Finding unused cells or wires in module \UartCtrlRx.. +Finding unused cells or wires in module \UartCtrlTx.. +Finding unused cells or wires in module \VexRiscv.. + +3.7.36. Executing OPT_EXPR pass (perform const folding). +Optimizing module Apb3Decoder. +Optimizing module Apb3Gpio. +Optimizing module Apb3Router. +Optimizing module Apb3UartCtrl. +Optimizing module BufferCC. +Optimizing module BufferCC_1. +Optimizing module BufferCC_2. +Optimizing module BufferCC_3. +Optimizing module FlowCCByToggle. +Optimizing module InterruptCtrl. +Optimizing module JtagBridge. +Optimizing module Murax. +Optimizing module MuraxApb3Timer. +Optimizing module MuraxMasterArbiter. +Optimizing module MuraxPipelinedMemoryBusRam. +Optimizing module PipelinedMemoryBusToApbBridge. +Optimizing module Prescaler. +Optimizing module StreamFifo. +Optimizing module StreamFifoLowLatency. +Optimizing module SystemDebugger. +Optimizing module Timer. +Optimizing module UartCtrl. +Optimizing module UartCtrlRx. +Optimizing module UartCtrlTx. +Optimizing module VexRiscv. + +3.7.37. Rerunning OPT passes. (Maybe there is more to do..) + +3.7.38. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \Apb3Decoder.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Gpio.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Router.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \BufferCC.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_2.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_3.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \FlowCCByToggle.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \InterruptCtrl.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \JtagBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Murax.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxApb3Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxMasterArbiter.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Prescaler.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \StreamFifo.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \StreamFifoLowLatency.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \SystemDebugger.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlRx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlTx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \VexRiscv.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.7.39. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \Apb3Decoder. + Optimizing cells in module \Apb3Gpio. + Optimizing cells in module \Apb3Router. + Optimizing cells in module \Apb3UartCtrl. + Optimizing cells in module \BufferCC. + Optimizing cells in module \BufferCC_1. + Optimizing cells in module \BufferCC_2. + Optimizing cells in module \BufferCC_3. + Optimizing cells in module \FlowCCByToggle. + Optimizing cells in module \InterruptCtrl. + Optimizing cells in module \JtagBridge. + Optimizing cells in module \Murax. + Optimizing cells in module \MuraxApb3Timer. + Optimizing cells in module \MuraxMasterArbiter. + Optimizing cells in module \MuraxPipelinedMemoryBusRam. + Optimizing cells in module \PipelinedMemoryBusToApbBridge. + Optimizing cells in module \Prescaler. + Optimizing cells in module \StreamFifo. + Optimizing cells in module \StreamFifoLowLatency. + Optimizing cells in module \SystemDebugger. + Optimizing cells in module \Timer. + Optimizing cells in module \UartCtrl. + Optimizing cells in module \UartCtrlRx. + Optimizing cells in module \UartCtrlTx. + Optimizing cells in module \VexRiscv. +Performed a total of 0 changes. + +3.7.40. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Apb3Decoder'. +Finding identical cells in module `\Apb3Gpio'. +Finding identical cells in module `\Apb3Router'. +Finding identical cells in module `\Apb3UartCtrl'. +Finding identical cells in module `\BufferCC'. +Finding identical cells in module `\BufferCC_1'. +Finding identical cells in module `\BufferCC_2'. +Finding identical cells in module `\BufferCC_3'. +Finding identical cells in module `\FlowCCByToggle'. +Finding identical cells in module `\InterruptCtrl'. +Finding identical cells in module `\JtagBridge'. +Finding identical cells in module `\Murax'. +Finding identical cells in module `\MuraxApb3Timer'. +Finding identical cells in module `\MuraxMasterArbiter'. +Finding identical cells in module `\MuraxPipelinedMemoryBusRam'. +Finding identical cells in module `\PipelinedMemoryBusToApbBridge'. +Finding identical cells in module `\Prescaler'. +Finding identical cells in module `\StreamFifo'. +Finding identical cells in module `\StreamFifoLowLatency'. +Finding identical cells in module `\SystemDebugger'. +Finding identical cells in module `\Timer'. +Finding identical cells in module `\UartCtrl'. +Finding identical cells in module `\UartCtrlRx'. +Finding identical cells in module `\UartCtrlTx'. +Finding identical cells in module `\VexRiscv'. +Removed a total of 0 cells. + +3.7.41. Executing OPT_DFF pass (perform DFF optimizations). + +3.7.42. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Apb3Decoder.. +Finding unused cells or wires in module \Apb3Gpio.. +Finding unused cells or wires in module \Apb3Router.. +Finding unused cells or wires in module \Apb3UartCtrl.. +Finding unused cells or wires in module \BufferCC.. +Finding unused cells or wires in module \BufferCC_1.. +Finding unused cells or wires in module \BufferCC_2.. +Finding unused cells or wires in module \BufferCC_3.. +Finding unused cells or wires in module \FlowCCByToggle.. +Finding unused cells or wires in module \InterruptCtrl.. +Finding unused cells or wires in module \JtagBridge.. +Finding unused cells or wires in module \Murax.. +Finding unused cells or wires in module \MuraxApb3Timer.. +Finding unused cells or wires in module \MuraxMasterArbiter.. +Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam.. +Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge.. +Finding unused cells or wires in module \Prescaler.. +Finding unused cells or wires in module \StreamFifo.. +Finding unused cells or wires in module \StreamFifoLowLatency.. +Finding unused cells or wires in module \SystemDebugger.. +Finding unused cells or wires in module \Timer.. +Finding unused cells or wires in module \UartCtrl.. +Finding unused cells or wires in module \UartCtrlRx.. +Finding unused cells or wires in module \UartCtrlTx.. +Finding unused cells or wires in module \VexRiscv.. + +3.7.43. Executing OPT_EXPR pass (perform const folding). +Optimizing module Apb3Decoder. +Optimizing module Apb3Gpio. +Optimizing module Apb3Router. +Optimizing module Apb3UartCtrl. +Optimizing module BufferCC. +Optimizing module BufferCC_1. +Optimizing module BufferCC_2. +Optimizing module BufferCC_3. +Optimizing module FlowCCByToggle. +Optimizing module InterruptCtrl. +Optimizing module JtagBridge. +Optimizing module Murax. +Optimizing module MuraxApb3Timer. +Optimizing module MuraxMasterArbiter. +Optimizing module MuraxPipelinedMemoryBusRam. +Optimizing module PipelinedMemoryBusToApbBridge. +Optimizing module Prescaler. +Optimizing module StreamFifo. +Optimizing module StreamFifoLowLatency. +Optimizing module SystemDebugger. +Optimizing module Timer. +Optimizing module UartCtrl. +Optimizing module UartCtrlRx. +Optimizing module UartCtrlTx. +Optimizing module VexRiscv. + +3.7.44. Finished OPT passes. (There is nothing left to do.) + +3.8. Executing WREDUCE pass (reducing word size of cells). +Removed top 3 bits (of 20) from port B of cell Apb3Decoder.$eq$../Murax.v:667$48 ($eq). +Removed top 2 bits (of 20) from port B of cell Apb3Decoder.$eq$../Murax.v:668$51 ($eq). +Removed top 1 bits (of 4) from port B of cell Apb3Gpio.$procmux$2526_CMP0 ($eq). +Removed top 1 bits (of 2) from port B of cell Apb3Router.$procmux$2822_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell Apb3UartCtrl.$auto$opt_dff.cc:195:make_patterns_logic$3425 ($ne). +Removed cell Apb3UartCtrl.$procmux$2550 ($mux). +Removed cell Apb3UartCtrl.$procmux$2552 ($mux). +Removed cell Apb3UartCtrl.$procmux$2556 ($mux). +Removed cell Apb3UartCtrl.$procmux$2558 ($mux). +Removed top 2 bits (of 5) from port B of cell Apb3UartCtrl.$procmux$2565_CMP0 ($eq). +Removed top 3 bits (of 4) from port B of cell JtagBridge.$eq$../Murax.v:2009$236 ($eq). +Removed top 3 bits (of 4) from port B of cell JtagBridge.$eq$../Murax.v:2013$237 ($eq). +Removed top 2 bits (of 4) from port B of cell JtagBridge.$eq$../Murax.v:2027$245 ($eq). +Removed top 2 bits (of 4) from port B of cell JtagBridge.$eq$../Murax.v:2034$250 ($eq). +Removed top 1 bits (of 2) from port B of cell JtagBridge.$auto$fsm_map.cc:77:implement_pattern_cache$3202 ($eq). +Removed top 2 bits (of 3) from port B of cell JtagBridge.$auto$fsm_map.cc:77:implement_pattern_cache$3237 ($eq). +Removed cell JtagBridge.$procmux$2347 ($mux). +Removed top 5 bits (of 6) from port B of cell Murax.$add$../Murax.v:482$34 ($add). +Removed cell Murax.$procmux$2844 ($mux). +Removed cell Murax.$procmux$2848 ($mux). +Removed top 1 bits (of 8) from port B of cell MuraxApb3Timer.$procmux$2682_CMP0 ($eq). +Removed top 1 bits (of 8) from port B of cell MuraxApb3Timer.$procmux$2687_CMP0 ($eq). +Removed top 3 bits (of 8) from port B of cell MuraxApb3Timer.$procmux$2697_CMP0 ($eq). +Removed top 1 bits (of 8) from port B of cell MuraxApb3Timer.$procmux$2702_CMP0 ($eq). +Removed top 1 bits (of 8) from port B of cell MuraxApb3Timer.$procmux$2713_CMP0 ($eq). +Removed top 3 bits (of 8) from port B of cell MuraxApb3Timer.$procmux$2725_CMP0 ($eq). +Removed top 1 bits (of 8) from port B of cell MuraxApb3Timer.$procmux$2734_CMP0 ($eq). +Removed top 1 bits (of 8) from port B of cell MuraxApb3Timer.$procmux$2758_CMP0 ($eq). +Removed cell MuraxMasterArbiter.$procmux$1397 ($mux). +Removed top 1 bits (of 2) from port B of cell MuraxMasterArbiter.$procmux$1409_CMP0 ($eq). +Removed cell MuraxPipelinedMemoryBusRam.$procmux$2448 ($mux). +Removed cell MuraxPipelinedMemoryBusRam.$procmux$2451 ($mux). +Removed cell MuraxPipelinedMemoryBusRam.$procmux$2457 ($mux). +Removed cell MuraxPipelinedMemoryBusRam.$procmux$2460 ($mux). +Removed cell MuraxPipelinedMemoryBusRam.$procmux$2466 ($mux). +Removed cell MuraxPipelinedMemoryBusRam.$procmux$2469 ($mux). +Removed cell MuraxPipelinedMemoryBusRam.$procmux$2475 ($mux). +Removed cell MuraxPipelinedMemoryBusRam.$procmux$2478 ($mux). +Removed cell PipelinedMemoryBusToApbBridge.$procmux$2501 ($mux). +Removed top 12 bits (of 32) from FF cell PipelinedMemoryBusToApbBridge.$auto$ff.cc:262:slice$3516 ($dffe). +Removed top 15 bits (of 16) from port B of cell Prescaler.$add$../Murax.v:5774$887 ($add). +Removed top 3 bits (of 4) from port B of cell StreamFifo.$add$../Murax.v:5873$905 ($add). +Removed top 3 bits (of 4) from port B of cell StreamFifo.$add$../Murax.v:5896$911 ($add). +Removed cell StreamFifo.$procmux$1349 ($mux). +Removed cell StreamFifo.$procmux$1378 ($mux). +Removed cell StreamFifo.$procmux$1381 ($mux). +Removed cell StreamFifoLowLatency.$procmux$1303 ($mux). +Removed top 2 bits (of 3) from port B of cell SystemDebugger.$add$../Murax.v:1700$212 ($add). +Removed top 2 bits (of 3) from port B of cell SystemDebugger.$auto$opt_dff.cc:195:make_patterns_logic$3538 ($ne). +Removed cell SystemDebugger.$procmux$2422 ($mux). +Removed cell SystemDebugger.$procmux$2434 ($mux). +Removed cell SystemDebugger.$procmux$2438 ($mux). +Removed cell SystemDebugger.$procmux$2440 ($mux). +Removed top 15 bits (of 16) from port B of cell Timer.$add$../Murax.v:5750$883 ($add). +Removed cell Timer.$procmux$1391 ($mux). +Removed top 19 bits (of 20) from port B of cell UartCtrl.$sub$../Murax.v:6055$935 ($sub). +Removed top 1 bits (of 2) from port B of cell UartCtrlRx.$auto$fsm_map.cc:77:implement_pattern_cache$3296 ($eq). +Removed top 1 bits (of 3) from port B of cell UartCtrlRx.$auto$fsm_map.cc:77:implement_pattern_cache$3305 ($eq). +Removed top 2 bits (of 3) from port B of cell UartCtrlRx.$eq$../Murax.v:6438$984 ($eq). +Removed top 6 bits (of 7) from port B of cell UartCtrlRx.$add$../Murax.v:6464$996 ($add). +Removed top 2 bits (of 3) from port B of cell UartCtrlRx.$sub$../Murax.v:6521$1002 ($sub). +Removed top 2 bits (of 3) from port B of cell UartCtrlRx.$add$../Murax.v:6527$1003 ($add). +Removed top 7 bits (of 8) from port A of cell UartCtrlRx.$shl$../Murax.v:0$1014 ($shl). +Removed cell UartCtrlRx.$procmux$1241 ($mux). +Removed top 1 bits (of 2) from port B of cell UartCtrlRx.$auto$fsm_map.cc:77:implement_pattern_cache$3330 ($eq). +Removed top 1 bits (of 3) from port B of cell UartCtrlRx.$auto$fsm_map.cc:77:implement_pattern_cache$3348 ($eq). +Removed top 2 bits (of 3) from port B of cell UartCtrlTx.$add$../Murax.v:6662$1024 ($add). +Removed top 2 bits (of 3) from port B of cell UartCtrlTx.$eq$../Murax.v:6712$1033 ($eq). +Removed top 2 bits (of 3) from port B of cell UartCtrlTx.$add$../Murax.v:6762$1039 ($add). +Removed top 1 bits (of 2) from port B of cell UartCtrlTx.$auto$fsm_map.cc:77:implement_pattern_cache$3374 ($eq). +Removed top 1 bits (of 2) from port B of cell UartCtrlTx.$auto$fsm_map.cc:77:implement_pattern_cache$3387 ($eq). +Removed top 1 bits (of 3) from port B of cell UartCtrlTx.$auto$fsm_map.cc:77:implement_pattern_cache$3413 ($eq). +Removed top 1 bits (of 2) from port Y of cell VexRiscv.$and$../Murax.v:2979$266 ($and). +Removed top 1 bits (of 2) from port A of cell VexRiscv.$and$../Murax.v:2979$266 ($and). +Removed top 1 bits (of 2) from port B of cell VexRiscv.$and$../Murax.v:2979$266 ($and). +Removed top 1 bits (of 2) from port B of cell VexRiscv.$sub$../Murax.v:2980$267 ($sub). +Removed top 2 bits (of 3) from port B of cell VexRiscv.$add$../Murax.v:2983$268 ($add). +Removed top 31 bits (of 32) from mux cell VexRiscv.$ternary$../Murax.v:2998$275 ($mux). +Removed top 27 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3007$279 ($and). +Removed top 25 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3009$280 ($and). +Removed top 17 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3011$281 ($and). +Removed top 17 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3011$282 ($eq). +Removed top 19 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3012$284 ($eq). +Removed top 1 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3012$285 ($and). +Removed top 1 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3012$286 ($eq). +Removed top 19 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3013$287 ($eq). +Removed top 26 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3013$288 ($eq). +Removed top 19 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3014$290 ($eq). +Removed top 25 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3018$294 ($and). +Removed top 18 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3020$295 ($and). +Removed top 19 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3022$296 ($and). +Removed top 18 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3024$297 ($and). +Removed top 18 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3024$298 ($eq). +Removed top 17 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3025$299 ($and). +Removed top 19 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3025$300 ($eq). +Removed top 18 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3025$301 ($and). +Removed top 18 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3025$302 ($eq). +Removed top 17 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3026$303 ($eq). +Removed top 17 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3026$304 ($eq). +Removed top 17 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3031$309 ($and). +Removed top 17 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3033$310 ($and). +Removed top 11 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3035$311 ($and). +Removed top 25 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3035$312 ($eq). +Removed top 18 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3036$313 ($and). +Removed top 18 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3036$314 ($eq). +Removed top 19 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3036$315 ($and). +Removed top 19 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3036$316 ($eq). +Removed top 26 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3037$317 ($eq). +Removed top 26 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3037$318 ($eq). +Removed top 26 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3042$323 ($and). +Removed top 26 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3049$329 ($and). +Removed top 26 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3049$330 ($eq). +Removed top 19 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3057$336 ($eq). +Removed top 26 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3058$337 ($eq). +Removed top 19 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3062$341 ($and). +Removed top 18 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3064$343 ($eq). +Removed top 29 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3066$345 ($eq). +Removed top 25 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3067$346 ($and). +Removed top 25 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3070$349 ($and). +Removed top 28 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3076$356 ($and). +Removed top 26 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3078$357 ($and). +Removed top 19 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3081$359 ($eq). +Removed top 25 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3083$361 ($eq). +Removed top 18 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3084$362 ($and). +Removed top 18 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3084$363 ($eq). +Removed top 1 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3085$364 ($and). +Removed top 1 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3085$365 ($eq). +Removed top 27 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3086$366 ($and). +Removed top 29 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3086$367 ($eq). +Removed top 29 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3088$369 ($eq). +Removed top 1 bits (of 2) from port B of cell VexRiscv.$eq$../Murax.v:3669$388 ($eq). +Removed top 29 bits (of 32) from port B of cell VexRiscv.$add$../Murax.v:4018$437 ($add). +Removed top 2 bits (of 3) from port B of cell VexRiscv.$sub$../Murax.v:4119$478 ($sub). +Removed top 17 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:4426$597 ($and). +Removed top 17 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:4426$598 ($eq). +Removed top 18 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:4427$600 ($eq). +Removed top 27 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:4428$601 ($and). +Removed top 29 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:4429$603 ($and). +Removed top 29 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:4429$604 ($eq). +Removed top 25 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:4430$605 ($and). +Removed top 27 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:4430$606 ($eq). +Removed top 25 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:4431$607 ($and). +Removed top 25 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:4431$608 ($eq). +Removed top 25 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:4432$611 ($eq). +Removed top 29 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:4432$613 ($eq). +Removed top 3 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:4432$615 ($and). +Removed top 25 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:4432$616 ($eq). +Removed top 19 bits (of 32) from port A of cell VexRiscv.$or$../Murax.v:5015$822 ($or). +Removed top 20 bits (of 32) from port B of cell VexRiscv.$or$../Murax.v:5015$822 ($or). +Removed top 19 bits (of 32) from port Y of cell VexRiscv.$or$../Murax.v:5015$822 ($or). +Removed top 20 bits (of 32) from port A of cell VexRiscv.$or$../Murax.v:5015$823 ($or). +Removed top 19 bits (of 32) from port A of cell VexRiscv.$or$../Murax.v:5015$824 ($or). +Removed top 2 bits (of 3) from port B of cell VexRiscv.$sub$../Murax.v:5146$835 ($sub). +Removed top 4 bits (of 5) from port B of cell VexRiscv.$sub$../Murax.v:5323$842 ($sub). +Removed top 2 bits (of 12) from port B of cell VexRiscv.$eq$../Murax.v:5467$843 ($eq). +Removed top 2 bits (of 12) from port B of cell VexRiscv.$eq$../Murax.v:5470$844 ($eq). +Removed top 2 bits (of 12) from port B of cell VexRiscv.$eq$../Murax.v:5473$845 ($eq). +Removed top 2 bits (of 12) from port B of cell VexRiscv.$eq$../Murax.v:5476$846 ($eq). +Removed cell VexRiscv.$procmux$1414 ($mux). +Removed cell VexRiscv.$procmux$1472 ($mux). +Removed cell VexRiscv.$procmux$1484 ($mux). +Removed cell VexRiscv.$procmux$1602 ($mux). +Removed cell VexRiscv.$procmux$1604 ($mux). +Removed top 7 bits (of 32) from mux cell VexRiscv.$procmux$1626 ($mux). +Removed cell VexRiscv.$procmux$1650 ($mux). +Removed top 1 bits (of 3) from port B of cell VexRiscv.$procmux$1652_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell VexRiscv.$procmux$1653_CMP0 ($eq). +Removed top 2 bits (of 3) from port B of cell VexRiscv.$procmux$1654_CMP0 ($eq). +Removed cell VexRiscv.$procmux$1655 ($mux). +Removed cell VexRiscv.$procmux$1660 ($mux). +Removed cell VexRiscv.$procmux$1662 ($mux). +Removed cell VexRiscv.$procmux$1668 ($mux). +Removed cell VexRiscv.$procmux$1672 ($mux). +Removed cell VexRiscv.$procmux$1674 ($mux). +Removed cell VexRiscv.$procmux$1678 ($mux). +Removed cell VexRiscv.$procmux$1680 ($mux). +Removed cell VexRiscv.$procmux$1768 ($mux). +Removed cell VexRiscv.$procmux$1772 ($mux). +Removed cell VexRiscv.$procmux$1780 ($mux). +Removed cell VexRiscv.$procmux$1796 ($mux). +Removed cell VexRiscv.$procmux$1800 ($mux). +Removed top 5 bits (of 6) from port B of cell VexRiscv.$procmux$1846_CMP0 ($eq). +Removed top 12 bits (of 32) from mux cell VexRiscv.$procmux$1892 ($pmux). +Removed top 2 bits (of 3) from port B of cell VexRiscv.$procmux$1903_CMP0 ($eq). +Removed top 1 bits (of 2) from port B of cell VexRiscv.$procmux$2039_CMP0 ($eq). +Removed top 1 bits (of 2) from port B of cell VexRiscv.$procmux$2046_CMP0 ($eq). +Removed top 1 bits (of 2) from port B of cell VexRiscv.$procmux$2050_CMP0 ($eq). +Removed top 1 bits (of 2) from port B of cell VexRiscv.$procmux$2055_CMP0 ($eq). +Removed top 1 bits (of 2) from port B of cell VexRiscv.$procmux$2059_CMP0 ($eq). +Removed top 19 bits (of 32) from mux cell VexRiscv.$procmux$2071 ($mux). +Removed top 1 bits (of 2) from port B of cell VexRiscv.$procmux$2128_CMP0 ($eq). +Removed top 1 bits (of 2) from port B of cell VexRiscv.$procmux$2138_CMP0 ($eq). +Removed top 1 bits (of 2) from port B of cell VexRiscv.$procmux$2145_CMP0 ($eq). +Removed cell VexRiscv.$procmux$2200 ($mux). +Removed cell VexRiscv.$procmux$2338 ($mux). +Removed cell VexRiscv.$procmux$2341 ($mux). +Removed top 1 bits (of 2) from port B of cell VexRiscv.$auto$opt_dff.cc:195:make_patterns_logic$3693 ($ne). +Removed top 1 bits (of 3) from port B of cell VexRiscv.$auto$opt_dff.cc:195:make_patterns_logic$3583 ($ne). +Removed top 1 bits (of 3) from port B of cell VexRiscv.$auto$opt_dff.cc:195:make_patterns_logic$3590 ($ne). +Removed top 2 bits (of 32) from FF cell VexRiscv.$procdff$2967 ($dff). +Removed top 2 bits (of 32) from FF cell VexRiscv.$auto$ff.cc:262:slice$3654 ($dffe). +Removed top 1 bits (of 2) from port Y of cell VexRiscv.$not$../Murax.v:2979$265 ($not). +Removed top 1 bits (of 2) from port A of cell VexRiscv.$not$../Murax.v:2979$265 ($not). +Removed top 1 bits (of 2) from port Y of cell VexRiscv.$sub$../Murax.v:2980$267 ($sub). +Removed top 1 bits (of 2) from port A of cell VexRiscv.$sub$../Murax.v:2980$267 ($sub). +Removed top 19 bits (of 32) from mux cell VexRiscv.$ternary$../Murax.v:4417$593 ($mux). +Removed top 19 bits (of 32) from port Y of cell VexRiscv.$and$../Murax.v:4417$591 ($and). +Removed top 19 bits (of 32) from port A of cell VexRiscv.$and$../Murax.v:4417$591 ($and). +Removed top 19 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:4417$591 ($and). +Removed top 19 bits (of 32) from port Y of cell VexRiscv.$or$../Murax.v:4417$592 ($or). +Removed top 19 bits (of 32) from port A of cell VexRiscv.$or$../Murax.v:4417$592 ($or). +Removed top 19 bits (of 32) from port B of cell VexRiscv.$or$../Murax.v:4417$592 ($or). +Removed top 19 bits (of 32) from port Y of cell VexRiscv.$not$../Murax.v:4417$590 ($not). +Removed top 19 bits (of 32) from port A of cell VexRiscv.$not$../Murax.v:4417$590 ($not). +Removed top 19 bits (of 32) from wire VexRiscv.$and$../Murax.v:4417$591_Y. +Removed top 1 bits (of 2) from wire VexRiscv.$not$../Murax.v:2979$265_Y. +Removed top 19 bits (of 32) from wire VexRiscv.$not$../Murax.v:4417$590_Y. +Removed top 19 bits (of 32) from wire VexRiscv.CsrPlugin_csrMapping_writeDataSignal. +Removed top 19 bits (of 32) from wire VexRiscv._zz_CsrPlugin_csrMapping_readDataInit. +Removed top 20 bits (of 32) from wire VexRiscv._zz_CsrPlugin_csrMapping_readDataInit_1. +Removed top 20 bits (of 32) from wire VexRiscv._zz_CsrPlugin_csrMapping_readDataInit_2. +Removed top 19 bits (of 32) from wire VexRiscv._zz_CsrPlugin_csrMapping_writeDataSignal. +Removed top 1 bits (of 2) from wire VexRiscv._zz_IBusSimplePlugin_jump_pcLoad_payload_1. +Removed top 31 bits (of 32) from wire VexRiscv._zz_execute_SrcPlugin_addSub_4. +Removed top 2 bits (of 32) from wire VexRiscv._zz_lastStageRegFileWrite_payload_address. +Removed top 2 bits (of 32) from wire VexRiscv.execute_to_memory_INSTRUCTION. + +3.9. Executing PEEPOPT pass (run peephole optimizers). + +3.10. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Apb3Decoder.. +Finding unused cells or wires in module \Apb3Gpio.. +Finding unused cells or wires in module \Apb3Router.. +Finding unused cells or wires in module \Apb3UartCtrl.. +Finding unused cells or wires in module \BufferCC.. +Finding unused cells or wires in module \BufferCC_1.. +Finding unused cells or wires in module \BufferCC_2.. +Finding unused cells or wires in module \BufferCC_3.. +Finding unused cells or wires in module \FlowCCByToggle.. +Finding unused cells or wires in module \InterruptCtrl.. +Finding unused cells or wires in module \JtagBridge.. +Finding unused cells or wires in module \Murax.. +Finding unused cells or wires in module \MuraxApb3Timer.. +Finding unused cells or wires in module \MuraxMasterArbiter.. +Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam.. +Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge.. +Finding unused cells or wires in module \Prescaler.. +Finding unused cells or wires in module \StreamFifo.. +Finding unused cells or wires in module \StreamFifoLowLatency.. +Finding unused cells or wires in module \SystemDebugger.. +Finding unused cells or wires in module \Timer.. +Finding unused cells or wires in module \UartCtrl.. +Finding unused cells or wires in module \UartCtrlRx.. +Finding unused cells or wires in module \UartCtrlTx.. +Finding unused cells or wires in module \VexRiscv.. +Removed 0 unused cells and 61 unused wires. + + +3.11. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module Apb3Decoder: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module Apb3Gpio: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module Apb3Router: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module Apb3UartCtrl: + creating $macc model for $sub$../Murax.v:1075$93 ($sub). + creating $alu model for $macc $sub$../Murax.v:1075$93. + creating $alu cell for $sub$../Murax.v:1075$93: $auto$alumacc.cc:485:replace_alu$3735 + created 1 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module BufferCC: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module BufferCC_1: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module BufferCC_2: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module BufferCC_3: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module FlowCCByToggle: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module InterruptCtrl: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module JtagBridge: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module Murax: + creating $macc model for $add$../Murax.v:482$34 ($add). + creating $alu model for $macc $add$../Murax.v:482$34. + creating $alu cell for $add$../Murax.v:482$34: $auto$alumacc.cc:485:replace_alu$3738 + created 1 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module MuraxApb3Timer: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module MuraxMasterArbiter: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module MuraxPipelinedMemoryBusRam: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module PipelinedMemoryBusToApbBridge: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module Prescaler: + creating $macc model for $add$../Murax.v:5774$887 ($add). + creating $alu model for $macc $add$../Murax.v:5774$887. + creating $alu cell for $add$../Murax.v:5774$887: $auto$alumacc.cc:485:replace_alu$3741 + created 1 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module StreamFifo: + creating $macc model for $add$../Murax.v:5873$905 ($add). + creating $macc model for $add$../Murax.v:5896$911 ($add). + creating $macc model for $sub$../Murax.v:5835$889 ($sub). + creating $macc model for $sub$../Murax.v:5911$925 ($sub). + creating $alu model for $macc $sub$../Murax.v:5911$925. + creating $alu model for $macc $sub$../Murax.v:5835$889. + creating $alu model for $macc $add$../Murax.v:5896$911. + creating $alu model for $macc $add$../Murax.v:5873$905. + creating $alu model for $eq$../Murax.v:5902$912 ($eq): merged with $sub$../Murax.v:5911$925. + creating $alu cell for $add$../Murax.v:5873$905: $auto$alumacc.cc:485:replace_alu$3744 + creating $alu cell for $add$../Murax.v:5896$911: $auto$alumacc.cc:485:replace_alu$3747 + creating $alu cell for $sub$../Murax.v:5835$889: $auto$alumacc.cc:485:replace_alu$3750 + creating $alu cell for $sub$../Murax.v:5911$925, $eq$../Murax.v:5902$912: $auto$alumacc.cc:485:replace_alu$3753 + created 4 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module StreamFifoLowLatency: + created 0 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module SystemDebugger: + creating $macc model for $add$../Murax.v:1700$212 ($add). + creating $alu model for $macc $add$../Murax.v:1700$212. + creating $alu cell for $add$../Murax.v:1700$212: $auto$alumacc.cc:485:replace_alu$3758 + created 1 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module Timer: + creating $macc model for $add$../Murax.v:5750$883 ($add). + creating $alu model for $macc $add$../Murax.v:5750$883. + creating $alu cell for $add$../Murax.v:5750$883: $auto$alumacc.cc:485:replace_alu$3761 + created 1 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module UartCtrl: + creating $macc model for $sub$../Murax.v:6055$935 ($sub). + creating $alu model for $macc $sub$../Murax.v:6055$935. + creating $alu cell for $sub$../Murax.v:6055$935: $auto$alumacc.cc:485:replace_alu$3764 + created 1 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module UartCtrlRx: + creating $macc model for $add$../Murax.v:6464$996 ($add). + creating $macc model for $add$../Murax.v:6527$1003 ($add). + creating $macc model for $sub$../Murax.v:6521$1002 ($sub). + creating $alu model for $macc $sub$../Murax.v:6521$1002. + creating $alu model for $macc $add$../Murax.v:6527$1003. + creating $alu model for $macc $add$../Murax.v:6464$996. + creating $alu cell for $add$../Murax.v:6464$996: $auto$alumacc.cc:485:replace_alu$3767 + creating $alu cell for $add$../Murax.v:6527$1003: $auto$alumacc.cc:485:replace_alu$3770 + creating $alu cell for $sub$../Murax.v:6521$1002: $auto$alumacc.cc:485:replace_alu$3773 + created 3 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module UartCtrlTx: + creating $macc model for $add$../Murax.v:6662$1024 ($add). + creating $macc model for $add$../Murax.v:6762$1039 ($add). + creating $alu model for $macc $add$../Murax.v:6762$1039. + creating $alu model for $macc $add$../Murax.v:6662$1024. + creating $alu cell for $add$../Murax.v:6662$1024: $auto$alumacc.cc:485:replace_alu$3776 + creating $alu cell for $add$../Murax.v:6762$1039: $auto$alumacc.cc:485:replace_alu$3779 + created 2 $alu and 0 $macc cells. +Extracting $alu and $macc cells in module VexRiscv: + creating $macc model for $add$../Murax.v:2983$268 ($add). + creating $macc model for $add$../Murax.v:2994$271 ($add). + creating $macc model for $add$../Murax.v:2995$272 ($add). + creating $macc model for $add$../Murax.v:4018$437 ($add). + creating $macc model for $add$../Murax.v:4809$680 ($add). + creating $macc model for $sub$../Murax.v:2980$267 ($sub). + creating $macc model for $sub$../Murax.v:4119$478 ($sub). + creating $macc model for $sub$../Murax.v:5146$835 ($sub). + creating $macc model for $sub$../Murax.v:5323$842 ($sub). + merging $macc model for $add$../Murax.v:2983$268 into $sub$../Murax.v:4119$478. + merging $macc model for $add$../Murax.v:2995$272 into $add$../Murax.v:2994$271. + creating $alu model for $macc $sub$../Murax.v:2980$267. + creating $alu model for $macc $add$../Murax.v:4809$680. + creating $alu model for $macc $add$../Murax.v:4018$437. + creating $alu model for $macc $sub$../Murax.v:5323$842. + creating $alu model for $macc $sub$../Murax.v:5146$835. + creating $macc cell for $add$../Murax.v:2994$271: $auto$alumacc.cc:365:replace_macc$3782 + creating $macc cell for $sub$../Murax.v:4119$478: $auto$alumacc.cc:365:replace_macc$3783 + creating $alu model for $lt$../Murax.v:5016$825 ($lt): new $alu + creating $alu cell for $lt$../Murax.v:5016$825: $auto$alumacc.cc:485:replace_alu$3785 + creating $alu cell for $sub$../Murax.v:5146$835: $auto$alumacc.cc:485:replace_alu$3790 + creating $alu cell for $sub$../Murax.v:5323$842: $auto$alumacc.cc:485:replace_alu$3793 + creating $alu cell for $add$../Murax.v:4018$437: $auto$alumacc.cc:485:replace_alu$3796 + creating $alu cell for $add$../Murax.v:4809$680: $auto$alumacc.cc:485:replace_alu$3799 + creating $alu cell for $sub$../Murax.v:2980$267: $auto$alumacc.cc:485:replace_alu$3802 + created 6 $alu and 2 $macc cells. + +3.12. Executing SHARE pass (SAT-based resource sharing). + +3.13. Executing OPT pass (performing simple optimizations). + +3.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module Apb3Decoder. +Optimizing module Apb3Gpio. +Optimizing module Apb3Router. +Optimizing module Apb3UartCtrl. +Optimizing module BufferCC. +Optimizing module BufferCC_1. +Optimizing module BufferCC_2. +Optimizing module BufferCC_3. +Optimizing module FlowCCByToggle. +Optimizing module InterruptCtrl. +Optimizing module JtagBridge. +Optimizing module Murax. +Optimizing module MuraxApb3Timer. +Optimizing module MuraxMasterArbiter. +Optimizing module MuraxPipelinedMemoryBusRam. +Optimizing module PipelinedMemoryBusToApbBridge. +Optimizing module Prescaler. +Optimizing module StreamFifo. +Optimizing module StreamFifoLowLatency. +Optimizing module SystemDebugger. +Optimizing module Timer. +Optimizing module UartCtrl. +Optimizing module UartCtrlRx. +Optimizing module UartCtrlTx. +Optimizing module VexRiscv. + + +3.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Apb3Decoder'. +Finding identical cells in module `\Apb3Gpio'. +Finding identical cells in module `\Apb3Router'. +Finding identical cells in module `\Apb3UartCtrl'. +Finding identical cells in module `\BufferCC'. +Finding identical cells in module `\BufferCC_1'. +Finding identical cells in module `\BufferCC_2'. +Finding identical cells in module `\BufferCC_3'. +Finding identical cells in module `\FlowCCByToggle'. +Finding identical cells in module `\InterruptCtrl'. +Finding identical cells in module `\JtagBridge'. +Finding identical cells in module `\Murax'. +Finding identical cells in module `\MuraxApb3Timer'. +Finding identical cells in module `\MuraxMasterArbiter'. +Finding identical cells in module `\MuraxPipelinedMemoryBusRam'. +Finding identical cells in module `\PipelinedMemoryBusToApbBridge'. +Finding identical cells in module `\Prescaler'. +Finding identical cells in module `\StreamFifo'. +Finding identical cells in module `\StreamFifoLowLatency'. +Finding identical cells in module `\SystemDebugger'. +Finding identical cells in module `\Timer'. +Finding identical cells in module `\UartCtrl'. +Finding identical cells in module `\UartCtrlRx'. +Finding identical cells in module `\UartCtrlTx'. +Finding identical cells in module `\VexRiscv'. +Removed a total of 0 cells. + +3.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \Apb3Decoder.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Gpio.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Router.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \BufferCC.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_2.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_3.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \FlowCCByToggle.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \InterruptCtrl.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \JtagBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Murax.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxApb3Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxMasterArbiter.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Prescaler.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \StreamFifo.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \StreamFifoLowLatency.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \SystemDebugger.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlRx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlTx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \VexRiscv.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \Apb3Decoder. + Optimizing cells in module \Apb3Gpio. + Optimizing cells in module \Apb3Router. + Optimizing cells in module \Apb3UartCtrl. + Optimizing cells in module \BufferCC. + Optimizing cells in module \BufferCC_1. + Optimizing cells in module \BufferCC_2. + Optimizing cells in module \BufferCC_3. + Optimizing cells in module \FlowCCByToggle. + Optimizing cells in module \InterruptCtrl. + Optimizing cells in module \JtagBridge. + Optimizing cells in module \Murax. + Optimizing cells in module \MuraxApb3Timer. + Optimizing cells in module \MuraxMasterArbiter. + Optimizing cells in module \MuraxPipelinedMemoryBusRam. + Optimizing cells in module \PipelinedMemoryBusToApbBridge. + Optimizing cells in module \Prescaler. + Optimizing cells in module \StreamFifo. + Optimizing cells in module \StreamFifoLowLatency. + Optimizing cells in module \SystemDebugger. + Optimizing cells in module \Timer. + Optimizing cells in module \UartCtrl. + Optimizing cells in module \UartCtrlRx. + Optimizing cells in module \UartCtrlTx. + Optimizing cells in module \VexRiscv. +Performed a total of 0 changes. + +3.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Apb3Decoder'. +Finding identical cells in module `\Apb3Gpio'. +Finding identical cells in module `\Apb3Router'. +Finding identical cells in module `\Apb3UartCtrl'. +Finding identical cells in module `\BufferCC'. +Finding identical cells in module `\BufferCC_1'. +Finding identical cells in module `\BufferCC_2'. +Finding identical cells in module `\BufferCC_3'. +Finding identical cells in module `\FlowCCByToggle'. +Finding identical cells in module `\InterruptCtrl'. +Finding identical cells in module `\JtagBridge'. +Finding identical cells in module `\Murax'. +Finding identical cells in module `\MuraxApb3Timer'. +Finding identical cells in module `\MuraxMasterArbiter'. +Finding identical cells in module `\MuraxPipelinedMemoryBusRam'. +Finding identical cells in module `\PipelinedMemoryBusToApbBridge'. +Finding identical cells in module `\Prescaler'. +Finding identical cells in module `\StreamFifo'. +Finding identical cells in module `\StreamFifoLowLatency'. +Finding identical cells in module `\SystemDebugger'. +Finding identical cells in module `\Timer'. +Finding identical cells in module `\UartCtrl'. +Finding identical cells in module `\UartCtrlRx'. +Finding identical cells in module `\UartCtrlTx'. +Finding identical cells in module `\VexRiscv'. +Removed a total of 0 cells. + +3.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Apb3Decoder.. +Finding unused cells or wires in module \Apb3Gpio.. +Finding unused cells or wires in module \Apb3Router.. +Finding unused cells or wires in module \Apb3UartCtrl.. +Finding unused cells or wires in module \BufferCC.. +Finding unused cells or wires in module \BufferCC_1.. +Finding unused cells or wires in module \BufferCC_2.. +Finding unused cells or wires in module \BufferCC_3.. +Finding unused cells or wires in module \FlowCCByToggle.. +Finding unused cells or wires in module \InterruptCtrl.. +Finding unused cells or wires in module \JtagBridge.. +Finding unused cells or wires in module \Murax.. +Finding unused cells or wires in module \MuraxApb3Timer.. +Finding unused cells or wires in module \MuraxMasterArbiter.. +Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam.. +Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge.. +Finding unused cells or wires in module \Prescaler.. +Finding unused cells or wires in module \StreamFifo.. +Finding unused cells or wires in module \StreamFifoLowLatency.. +Finding unused cells or wires in module \SystemDebugger.. +Finding unused cells or wires in module \Timer.. +Finding unused cells or wires in module \UartCtrl.. +Finding unused cells or wires in module \UartCtrlRx.. +Finding unused cells or wires in module \UartCtrlTx.. +Finding unused cells or wires in module \VexRiscv.. +Removed 3 unused cells and 5 unused wires. + + +3.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module Apb3Decoder. +Optimizing module Apb3Gpio. +Optimizing module Apb3Router. +Optimizing module Apb3UartCtrl. +Optimizing module BufferCC. +Optimizing module BufferCC_1. +Optimizing module BufferCC_2. +Optimizing module BufferCC_3. +Optimizing module FlowCCByToggle. +Optimizing module InterruptCtrl. +Optimizing module JtagBridge. +Optimizing module Murax. +Optimizing module MuraxApb3Timer. +Optimizing module MuraxMasterArbiter. +Optimizing module MuraxPipelinedMemoryBusRam. +Optimizing module PipelinedMemoryBusToApbBridge. +Optimizing module Prescaler. +Optimizing module StreamFifo. +Optimizing module StreamFifoLowLatency. +Optimizing module SystemDebugger. +Optimizing module Timer. +Optimizing module UartCtrl. +Optimizing module UartCtrlRx. +Optimizing module UartCtrlTx. +Optimizing module VexRiscv. + +3.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +3.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \Apb3Decoder.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Gpio.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Router.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \BufferCC.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_2.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_3.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \FlowCCByToggle.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \InterruptCtrl.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \JtagBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Murax.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxApb3Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxMasterArbiter.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Prescaler.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \StreamFifo.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \StreamFifoLowLatency.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \SystemDebugger.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlRx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlTx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \VexRiscv.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \Apb3Decoder. + Optimizing cells in module \Apb3Gpio. + Optimizing cells in module \Apb3Router. + Optimizing cells in module \Apb3UartCtrl. + Optimizing cells in module \BufferCC. + Optimizing cells in module \BufferCC_1. + Optimizing cells in module \BufferCC_2. + Optimizing cells in module \BufferCC_3. + Optimizing cells in module \FlowCCByToggle. + Optimizing cells in module \InterruptCtrl. + Optimizing cells in module \JtagBridge. + Optimizing cells in module \Murax. + Optimizing cells in module \MuraxApb3Timer. + Optimizing cells in module \MuraxMasterArbiter. + Optimizing cells in module \MuraxPipelinedMemoryBusRam. + Optimizing cells in module \PipelinedMemoryBusToApbBridge. + Optimizing cells in module \Prescaler. + Optimizing cells in module \StreamFifo. + Optimizing cells in module \StreamFifoLowLatency. + Optimizing cells in module \SystemDebugger. + Optimizing cells in module \Timer. + Optimizing cells in module \UartCtrl. + Optimizing cells in module \UartCtrlRx. + Optimizing cells in module \UartCtrlTx. + Optimizing cells in module \VexRiscv. +Performed a total of 0 changes. + +3.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Apb3Decoder'. +Finding identical cells in module `\Apb3Gpio'. +Finding identical cells in module `\Apb3Router'. +Finding identical cells in module `\Apb3UartCtrl'. +Finding identical cells in module `\BufferCC'. +Finding identical cells in module `\BufferCC_1'. +Finding identical cells in module `\BufferCC_2'. +Finding identical cells in module `\BufferCC_3'. +Finding identical cells in module `\FlowCCByToggle'. +Finding identical cells in module `\InterruptCtrl'. +Finding identical cells in module `\JtagBridge'. +Finding identical cells in module `\Murax'. +Finding identical cells in module `\MuraxApb3Timer'. +Finding identical cells in module `\MuraxMasterArbiter'. +Finding identical cells in module `\MuraxPipelinedMemoryBusRam'. +Finding identical cells in module `\PipelinedMemoryBusToApbBridge'. +Finding identical cells in module `\Prescaler'. +Finding identical cells in module `\StreamFifo'. +Finding identical cells in module `\StreamFifoLowLatency'. +Finding identical cells in module `\SystemDebugger'. +Finding identical cells in module `\Timer'. +Finding identical cells in module `\UartCtrl'. +Finding identical cells in module `\UartCtrlRx'. +Finding identical cells in module `\UartCtrlTx'. +Finding identical cells in module `\VexRiscv'. +Removed a total of 0 cells. + +3.13.13. Executing OPT_DFF pass (perform DFF optimizations). + +3.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Apb3Decoder.. +Finding unused cells or wires in module \Apb3Gpio.. +Finding unused cells or wires in module \Apb3Router.. +Finding unused cells or wires in module \Apb3UartCtrl.. +Finding unused cells or wires in module \BufferCC.. +Finding unused cells or wires in module \BufferCC_1.. +Finding unused cells or wires in module \BufferCC_2.. +Finding unused cells or wires in module \BufferCC_3.. +Finding unused cells or wires in module \FlowCCByToggle.. +Finding unused cells or wires in module \InterruptCtrl.. +Finding unused cells or wires in module \JtagBridge.. +Finding unused cells or wires in module \Murax.. +Finding unused cells or wires in module \MuraxApb3Timer.. +Finding unused cells or wires in module \MuraxMasterArbiter.. +Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam.. +Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge.. +Finding unused cells or wires in module \Prescaler.. +Finding unused cells or wires in module \StreamFifo.. +Finding unused cells or wires in module \StreamFifoLowLatency.. +Finding unused cells or wires in module \SystemDebugger.. +Finding unused cells or wires in module \Timer.. +Finding unused cells or wires in module \UartCtrl.. +Finding unused cells or wires in module \UartCtrlRx.. +Finding unused cells or wires in module \UartCtrlTx.. +Finding unused cells or wires in module \VexRiscv.. + +3.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module Apb3Decoder. +Optimizing module Apb3Gpio. +Optimizing module Apb3Router. +Optimizing module Apb3UartCtrl. +Optimizing module BufferCC. +Optimizing module BufferCC_1. +Optimizing module BufferCC_2. +Optimizing module BufferCC_3. +Optimizing module FlowCCByToggle. +Optimizing module InterruptCtrl. +Optimizing module JtagBridge. +Optimizing module Murax. +Optimizing module MuraxApb3Timer. +Optimizing module MuraxMasterArbiter. +Optimizing module MuraxPipelinedMemoryBusRam. +Optimizing module PipelinedMemoryBusToApbBridge. +Optimizing module Prescaler. +Optimizing module StreamFifo. +Optimizing module StreamFifoLowLatency. +Optimizing module SystemDebugger. +Optimizing module Timer. +Optimizing module UartCtrl. +Optimizing module UartCtrlRx. +Optimizing module UartCtrlTx. +Optimizing module VexRiscv. + +3.13.16. Finished OPT passes. (There is nothing left to do.) + +3.14. Executing MEMORY pass. + +3.14.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +3.14.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +3.14.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + Analyzing MuraxPipelinedMemoryBusRam.ram_symbol0 write port 0. + Analyzing MuraxPipelinedMemoryBusRam.ram_symbol1 write port 0. + Analyzing MuraxPipelinedMemoryBusRam.ram_symbol2 write port 0. + Analyzing MuraxPipelinedMemoryBusRam.ram_symbol3 write port 0. + Analyzing StreamFifo.logic_ram write port 0. + Analyzing VexRiscv.RegFilePlugin_regFile write port 0. + +3.14.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +Checking read port `\ram_symbol0'[0] in module `\MuraxPipelinedMemoryBusRam': merging output FF to cell. + Write port 0: non-transparent. +Checking read port `\ram_symbol1'[0] in module `\MuraxPipelinedMemoryBusRam': merging output FF to cell. + Write port 0: non-transparent. +Checking read port `\ram_symbol2'[0] in module `\MuraxPipelinedMemoryBusRam': merging output FF to cell. + Write port 0: non-transparent. +Checking read port `\ram_symbol3'[0] in module `\MuraxPipelinedMemoryBusRam': merging output FF to cell. + Write port 0: non-transparent. +Checking read port `\logic_ram'[0] in module `\StreamFifo': merging output FF to cell. + Write port 0: non-transparent. +Checking read port `\RegFilePlugin_regFile'[0] in module `\VexRiscv': merging output FF to cell. + Write port 0: non-transparent. +Checking read port `\RegFilePlugin_regFile'[1] in module `\VexRiscv': merging output FF to cell. + Write port 0: non-transparent. + +3.14.5. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Apb3Decoder.. +Finding unused cells or wires in module \Apb3Gpio.. +Finding unused cells or wires in module \Apb3Router.. +Finding unused cells or wires in module \Apb3UartCtrl.. +Finding unused cells or wires in module \BufferCC.. +Finding unused cells or wires in module \BufferCC_1.. +Finding unused cells or wires in module \BufferCC_2.. +Finding unused cells or wires in module \BufferCC_3.. +Finding unused cells or wires in module \FlowCCByToggle.. +Finding unused cells or wires in module \InterruptCtrl.. +Finding unused cells or wires in module \JtagBridge.. +Finding unused cells or wires in module \Murax.. +Finding unused cells or wires in module \MuraxApb3Timer.. +Finding unused cells or wires in module \MuraxMasterArbiter.. +Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam.. +Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge.. +Finding unused cells or wires in module \Prescaler.. +Finding unused cells or wires in module \StreamFifo.. +Finding unused cells or wires in module \StreamFifoLowLatency.. +Finding unused cells or wires in module \SystemDebugger.. +Finding unused cells or wires in module \Timer.. +Finding unused cells or wires in module \UartCtrl.. +Finding unused cells or wires in module \UartCtrlRx.. +Finding unused cells or wires in module \UartCtrlTx.. +Finding unused cells or wires in module \VexRiscv.. +Removed 7 unused cells and 111 unused wires. + + +3.14.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). +Consolidating read ports of memory VexRiscv.RegFilePlugin_regFile by address: + +3.14.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +3.14.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Apb3Decoder.. +Finding unused cells or wires in module \Apb3Gpio.. +Finding unused cells or wires in module \Apb3Router.. +Finding unused cells or wires in module \Apb3UartCtrl.. +Finding unused cells or wires in module \BufferCC.. +Finding unused cells or wires in module \BufferCC_1.. +Finding unused cells or wires in module \BufferCC_2.. +Finding unused cells or wires in module \BufferCC_3.. +Finding unused cells or wires in module \FlowCCByToggle.. +Finding unused cells or wires in module \InterruptCtrl.. +Finding unused cells or wires in module \JtagBridge.. +Finding unused cells or wires in module \Murax.. +Finding unused cells or wires in module \MuraxApb3Timer.. +Finding unused cells or wires in module \MuraxMasterArbiter.. +Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam.. +Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge.. +Finding unused cells or wires in module \Prescaler.. +Finding unused cells or wires in module \StreamFifo.. +Finding unused cells or wires in module \StreamFifoLowLatency.. +Finding unused cells or wires in module \SystemDebugger.. +Finding unused cells or wires in module \Timer.. +Finding unused cells or wires in module \UartCtrl.. +Finding unused cells or wires in module \UartCtrlRx.. +Finding unused cells or wires in module \UartCtrlTx.. +Finding unused cells or wires in module \VexRiscv.. + +3.14.9. Executing MEMORY_COLLECT pass (generating $mem cells). + +3.15. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Apb3Decoder.. +Finding unused cells or wires in module \Apb3Gpio.. +Finding unused cells or wires in module \Apb3Router.. +Finding unused cells or wires in module \Apb3UartCtrl.. +Finding unused cells or wires in module \BufferCC.. +Finding unused cells or wires in module \BufferCC_1.. +Finding unused cells or wires in module \BufferCC_2.. +Finding unused cells or wires in module \BufferCC_3.. +Finding unused cells or wires in module \FlowCCByToggle.. +Finding unused cells or wires in module \InterruptCtrl.. +Finding unused cells or wires in module \JtagBridge.. +Finding unused cells or wires in module \Murax.. +Finding unused cells or wires in module \MuraxApb3Timer.. +Finding unused cells or wires in module \MuraxMasterArbiter.. +Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam.. +Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge.. +Finding unused cells or wires in module \Prescaler.. +Finding unused cells or wires in module \StreamFifo.. +Finding unused cells or wires in module \StreamFifoLowLatency.. +Finding unused cells or wires in module \SystemDebugger.. +Finding unused cells or wires in module \Timer.. +Finding unused cells or wires in module \UartCtrl.. +Finding unused cells or wires in module \UartCtrlRx.. +Finding unused cells or wires in module \UartCtrlTx.. +Finding unused cells or wires in module \VexRiscv.. + +4. Executing OPT pass (performing simple optimizations). + +4.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module Apb3Decoder. + +Optimizing module Apb3Gpio. +Optimizing module Apb3Router. +Optimizing module Apb3UartCtrl. +Optimizing module BufferCC. +Optimizing module BufferCC_1. +Optimizing module BufferCC_2. +Optimizing module BufferCC_3. +Optimizing module FlowCCByToggle. +Optimizing module InterruptCtrl. +Optimizing module JtagBridge. +Optimizing module Murax. + +Optimizing module MuraxApb3Timer. + +Optimizing module MuraxMasterArbiter. +Optimizing module MuraxPipelinedMemoryBusRam. +Optimizing module PipelinedMemoryBusToApbBridge. +Optimizing module Prescaler. +Optimizing module StreamFifo. +Optimizing module StreamFifoLowLatency. +Optimizing module SystemDebugger. +Optimizing module Timer. +Optimizing module UartCtrl. +Optimizing module UartCtrlRx. +Optimizing module UartCtrlTx. +Optimizing module VexRiscv. + + +4.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Apb3Decoder'. +Finding identical cells in module `\Apb3Gpio'. +Finding identical cells in module `\Apb3Router'. +Finding identical cells in module `\Apb3UartCtrl'. +Finding identical cells in module `\BufferCC'. +Finding identical cells in module `\BufferCC_1'. +Finding identical cells in module `\BufferCC_2'. +Finding identical cells in module `\BufferCC_3'. +Finding identical cells in module `\FlowCCByToggle'. +Finding identical cells in module `\InterruptCtrl'. +Finding identical cells in module `\JtagBridge'. +Finding identical cells in module `\Murax'. +Finding identical cells in module `\MuraxApb3Timer'. +Finding identical cells in module `\MuraxMasterArbiter'. +Finding identical cells in module `\MuraxPipelinedMemoryBusRam'. +Finding identical cells in module `\PipelinedMemoryBusToApbBridge'. +Finding identical cells in module `\Prescaler'. +Finding identical cells in module `\StreamFifo'. +Finding identical cells in module `\StreamFifoLowLatency'. +Finding identical cells in module `\SystemDebugger'. +Finding identical cells in module `\Timer'. +Finding identical cells in module `\UartCtrl'. +Finding identical cells in module `\UartCtrlRx'. +Finding identical cells in module `\UartCtrlTx'. +Finding identical cells in module `\VexRiscv'. + +Removed a total of 1 cells. + +4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \Apb3Decoder.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Gpio.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Router.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \BufferCC.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_2.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_3.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \FlowCCByToggle.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \InterruptCtrl.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \JtagBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Murax.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxApb3Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxMasterArbiter.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Prescaler.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \StreamFifo.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \StreamFifoLowLatency.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \SystemDebugger.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlRx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlTx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \VexRiscv.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \Apb3Decoder. + Optimizing cells in module \Apb3Gpio. + Optimizing cells in module \Apb3Router. + Optimizing cells in module \Apb3UartCtrl. + Optimizing cells in module \BufferCC. + Optimizing cells in module \BufferCC_1. + Optimizing cells in module \BufferCC_2. + Optimizing cells in module \BufferCC_3. + Optimizing cells in module \FlowCCByToggle. + Optimizing cells in module \InterruptCtrl. + Optimizing cells in module \JtagBridge. + Optimizing cells in module \Murax. + Optimizing cells in module \MuraxApb3Timer. + Optimizing cells in module \MuraxMasterArbiter. + Consolidated identical input bits for $pmux cell $procmux$1408: + Old ports: A=4'1111, B=8'00010011, Y=\_zz_io_masterBus_cmd_payload_mask + New ports: A=2'11, B=4'0001, Y=\_zz_io_masterBus_cmd_payload_mask [2:1] + New connections: { \_zz_io_masterBus_cmd_payload_mask [3] \_zz_io_masterBus_cmd_payload_mask [0] } = { \_zz_io_masterBus_cmd_payload_mask [2] 1'1 } + Optimizing cells in module \MuraxMasterArbiter. + Optimizing cells in module \MuraxPipelinedMemoryBusRam. + Optimizing cells in module \PipelinedMemoryBusToApbBridge. + Optimizing cells in module \Prescaler. + Optimizing cells in module \StreamFifo. + Optimizing cells in module \StreamFifoLowLatency. + Optimizing cells in module \SystemDebugger. + Optimizing cells in module \Timer. + Optimizing cells in module \UartCtrl. + Optimizing cells in module \UartCtrlRx. + Optimizing cells in module \UartCtrlTx. + Optimizing cells in module \VexRiscv. + Consolidated identical input bits for $mux cell $procmux$1805: + Old ports: A=4'0000, B={ \CsrPlugin_mcause_exceptionCode [3:2] 2'11 }, Y=\_zz_CsrPlugin_csrMapping_readDataInit_3 [3:0] + New ports: A=3'000, B={ \CsrPlugin_mcause_exceptionCode [3:2] 1'1 }, Y={ \_zz_CsrPlugin_csrMapping_readDataInit_3 [3:2] \_zz_CsrPlugin_csrMapping_readDataInit_3 [0] } + New connections: \_zz_CsrPlugin_csrMapping_readDataInit_3 [1] = \_zz_CsrPlugin_csrMapping_readDataInit_3 [0] + Consolidated identical input bits for $pmux cell $procmux$1892: + Old ports: A={ \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [7] \decode_to_execute_INSTRUCTION [30:25] \decode_to_execute_INSTRUCTION [11:8] 1'0 }, B={ \decode_to_execute_INSTRUCTION [19:12] \decode_to_execute_INSTRUCTION [20] \decode_to_execute_INSTRUCTION [30:21] 1'0 \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31:20] }, Y=\execute_BranchPlugin_branch_src2 [19:0] + New ports: A={ \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [7] \decode_to_execute_INSTRUCTION [11:8] 1'0 }, B={ \decode_to_execute_INSTRUCTION [19:12] \decode_to_execute_INSTRUCTION [20] \decode_to_execute_INSTRUCTION [24:21] 1'0 \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [24:20] }, Y={ \execute_BranchPlugin_branch_src2 [19:11] \execute_BranchPlugin_branch_src2 [4:0] } + New connections: \execute_BranchPlugin_branch_src2 [10:5] = \decode_to_execute_INSTRUCTION [30:25] + Consolidated identical input bits for $pmux cell $procmux$2127: + Old ports: A={ \memory_to_writeBack_MEMORY_READ_DATA [31:16] \_zz_writeBack_DBusSimplePlugin_rspFormated_3 [15:8] \_zz_writeBack_DBusSimplePlugin_rspFormated_1 [7:0] }, B={ \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated_1 [7:0] \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_3 [15:8] \_zz_writeBack_DBusSimplePlugin_rspFormated_1 [7:0] }, Y=\writeBack_DBusSimplePlugin_rspFormated + New ports: A={ \memory_to_writeBack_MEMORY_READ_DATA [31:16] \_zz_writeBack_DBusSimplePlugin_rspFormated_3 [15:8] }, B={ \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_3 [15:8] }, Y=\writeBack_DBusSimplePlugin_rspFormated [31:8] + New connections: \writeBack_DBusSimplePlugin_rspFormated [7:0] = \_zz_writeBack_DBusSimplePlugin_rspFormated_1 [7:0] + Consolidated identical input bits for $pmux cell $procmux$2144: + Old ports: A=\decode_to_execute_RS2, B={ \decode_to_execute_RS2 [7:0] \decode_to_execute_RS2 [7:0] \decode_to_execute_RS2 [7:0] \decode_to_execute_RS2 [7:0] \decode_to_execute_RS2 [15:0] \decode_to_execute_RS2 [15:0] }, Y=\dBus_cmd_payload_data + New ports: A=\decode_to_execute_RS2 [31:8], B={ \decode_to_execute_RS2 [7:0] \decode_to_execute_RS2 [7:0] \decode_to_execute_RS2 [7:0] \decode_to_execute_RS2 [15:0] \decode_to_execute_RS2 [15:8] }, Y=\dBus_cmd_payload_data [31:8] + New connections: \dBus_cmd_payload_data [7:0] = \decode_to_execute_RS2 [7:0] + Consolidated identical input bits for $mux cell $procmux$2192: + Old ports: A=32'10000000000000000000000000100000, B={ \CsrPlugin_mepc [31:2] 2'00 }, Y=$3\CsrPlugin_jumpInterface_payload[31:0] + New ports: A=30'100000000000000000000000001000, B=\CsrPlugin_mepc [31:2], Y=$3\CsrPlugin_jumpInterface_payload[31:0] [31:2] + New connections: $3\CsrPlugin_jumpInterface_payload[31:0] [1:0] = 2'00 + Optimizing cells in module \VexRiscv. + Consolidated identical input bits for $mux cell $procmux$2197: + Old ports: A=32'10000000000000000000000000100000, B=$3\CsrPlugin_jumpInterface_payload[31:0], Y=\CsrPlugin_jumpInterface_payload + New ports: A=30'100000000000000000000000001000, B=$3\CsrPlugin_jumpInterface_payload[31:0] [31:2], Y=\CsrPlugin_jumpInterface_payload [31:2] + New connections: \CsrPlugin_jumpInterface_payload [1:0] = 2'00 + Optimizing cells in module \VexRiscv. + Consolidated identical input bits for $mux cell $ternary$../Murax.v:3997$427: + Old ports: A={ \execute_to_memory_BRANCH_CALC [31:1] 1'0 }, B=\CsrPlugin_jumpInterface_payload, Y=\IBusSimplePlugin_jump_pcLoad_payload + New ports: A=\execute_to_memory_BRANCH_CALC [31:1], B={ \CsrPlugin_jumpInterface_payload [31:2] 1'0 }, Y=\IBusSimplePlugin_jump_pcLoad_payload [31:1] + New connections: \IBusSimplePlugin_jump_pcLoad_payload [0] = 1'0 + Optimizing cells in module \VexRiscv. + Consolidated identical input bits for $mux cell $procmux$2170: + Old ports: A=$add$../Murax.v:4018$437_Y, B=\IBusSimplePlugin_jump_pcLoad_payload, Y={ \IBusSimplePlugin_fetchPc_pc [31:2] $1\IBusSimplePlugin_fetchPc_pc[31:0] [1:0] } + New ports: A={ $add$../Murax.v:4018$437_Y [31:2] 1'0 }, B=\IBusSimplePlugin_jump_pcLoad_payload [31:1], Y={ \IBusSimplePlugin_fetchPc_pc [31:2] $1\IBusSimplePlugin_fetchPc_pc[31:0] [1] } + New connections: $1\IBusSimplePlugin_fetchPc_pc[31:0] [0] = 1'0 + Optimizing cells in module \VexRiscv. +Performed a total of 9 changes. + +4.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Apb3Decoder'. +Finding identical cells in module `\Apb3Gpio'. +Finding identical cells in module `\Apb3Router'. +Finding identical cells in module `\Apb3UartCtrl'. +Finding identical cells in module `\BufferCC'. +Finding identical cells in module `\BufferCC_1'. +Finding identical cells in module `\BufferCC_2'. +Finding identical cells in module `\BufferCC_3'. +Finding identical cells in module `\FlowCCByToggle'. +Finding identical cells in module `\InterruptCtrl'. +Finding identical cells in module `\JtagBridge'. +Finding identical cells in module `\Murax'. +Finding identical cells in module `\MuraxApb3Timer'. +Finding identical cells in module `\MuraxMasterArbiter'. +Finding identical cells in module `\MuraxPipelinedMemoryBusRam'. +Finding identical cells in module `\PipelinedMemoryBusToApbBridge'. +Finding identical cells in module `\Prescaler'. +Finding identical cells in module `\StreamFifo'. +Finding identical cells in module `\StreamFifoLowLatency'. +Finding identical cells in module `\SystemDebugger'. +Finding identical cells in module `\Timer'. +Finding identical cells in module `\UartCtrl'. +Finding identical cells in module `\UartCtrlRx'. +Finding identical cells in module `\UartCtrlTx'. +Finding identical cells in module `\VexRiscv'. +Removed a total of 0 cells. + +4.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Apb3Decoder.. +Finding unused cells or wires in module \Apb3Gpio.. +Finding unused cells or wires in module \Apb3Router.. +Finding unused cells or wires in module \Apb3UartCtrl.. +Finding unused cells or wires in module \BufferCC.. +Finding unused cells or wires in module \BufferCC_1.. +Finding unused cells or wires in module \BufferCC_2.. +Finding unused cells or wires in module \BufferCC_3.. +Finding unused cells or wires in module \FlowCCByToggle.. +Finding unused cells or wires in module \InterruptCtrl.. +Finding unused cells or wires in module \JtagBridge.. +Finding unused cells or wires in module \Murax.. +Finding unused cells or wires in module \MuraxApb3Timer.. +Finding unused cells or wires in module \MuraxMasterArbiter.. +Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam.. +Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge.. +Finding unused cells or wires in module \Prescaler.. +Finding unused cells or wires in module \StreamFifo.. +Finding unused cells or wires in module \StreamFifoLowLatency.. +Finding unused cells or wires in module \SystemDebugger.. +Finding unused cells or wires in module \Timer.. +Finding unused cells or wires in module \UartCtrl.. +Finding unused cells or wires in module \UartCtrlRx.. +Finding unused cells or wires in module \UartCtrlTx.. +Finding unused cells or wires in module \VexRiscv.. +Removed 2 unused cells and 117 unused wires. + + +4.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module Apb3Decoder. +Optimizing module Apb3Gpio. +Optimizing module Apb3Router. +Optimizing module Apb3UartCtrl. +Optimizing module BufferCC. +Optimizing module BufferCC_1. +Optimizing module BufferCC_2. +Optimizing module BufferCC_3. +Optimizing module FlowCCByToggle. +Optimizing module InterruptCtrl. +Optimizing module JtagBridge. +Optimizing module Murax. +Optimizing module MuraxApb3Timer. +Optimizing module MuraxMasterArbiter. +Optimizing module MuraxPipelinedMemoryBusRam. +Optimizing module PipelinedMemoryBusToApbBridge. +Optimizing module Prescaler. +Optimizing module StreamFifo. +Optimizing module StreamFifoLowLatency. +Optimizing module SystemDebugger. +Optimizing module Timer. +Optimizing module UartCtrl. +Optimizing module UartCtrlRx. +Optimizing module UartCtrlTx. +Optimizing module VexRiscv. + + +4.9. Rerunning OPT passes. (Maybe there is more to do..) + +4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \Apb3Decoder.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Gpio.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3Router.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Apb3UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \BufferCC.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_1.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_2.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \BufferCC_3.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \FlowCCByToggle.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \InterruptCtrl.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \JtagBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Murax.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxApb3Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxMasterArbiter.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Prescaler.. + Creating internal representation of mux trees. + No muxes found in this module. +Running muxtree optimizer on module \StreamFifo.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \StreamFifoLowLatency.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \SystemDebugger.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \Timer.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrl.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlRx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \UartCtrlTx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \VexRiscv.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \Apb3Decoder. + Optimizing cells in module \Apb3Gpio. + Optimizing cells in module \Apb3Router. + Optimizing cells in module \Apb3UartCtrl. + Optimizing cells in module \BufferCC. + Optimizing cells in module \BufferCC_1. + Optimizing cells in module \BufferCC_2. + Optimizing cells in module \BufferCC_3. + Optimizing cells in module \FlowCCByToggle. + Optimizing cells in module \InterruptCtrl. + Optimizing cells in module \JtagBridge. + Optimizing cells in module \Murax. + Optimizing cells in module \MuraxApb3Timer. + Optimizing cells in module \MuraxMasterArbiter. + Optimizing cells in module \MuraxPipelinedMemoryBusRam. + Optimizing cells in module \PipelinedMemoryBusToApbBridge. + Optimizing cells in module \Prescaler. + Optimizing cells in module \StreamFifo. + Optimizing cells in module \StreamFifoLowLatency. + Optimizing cells in module \SystemDebugger. + Optimizing cells in module \Timer. + Optimizing cells in module \UartCtrl. + Optimizing cells in module \UartCtrlRx. + Optimizing cells in module \UartCtrlTx. + Optimizing cells in module \VexRiscv. +Performed a total of 0 changes. + +4.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Apb3Decoder'. +Finding identical cells in module `\Apb3Gpio'. +Finding identical cells in module `\Apb3Router'. +Finding identical cells in module `\Apb3UartCtrl'. +Finding identical cells in module `\BufferCC'. +Finding identical cells in module `\BufferCC_1'. +Finding identical cells in module `\BufferCC_2'. +Finding identical cells in module `\BufferCC_3'. +Finding identical cells in module `\FlowCCByToggle'. +Finding identical cells in module `\InterruptCtrl'. +Finding identical cells in module `\JtagBridge'. +Finding identical cells in module `\Murax'. +Finding identical cells in module `\MuraxApb3Timer'. +Finding identical cells in module `\MuraxMasterArbiter'. +Finding identical cells in module `\MuraxPipelinedMemoryBusRam'. +Finding identical cells in module `\PipelinedMemoryBusToApbBridge'. +Finding identical cells in module `\Prescaler'. +Finding identical cells in module `\StreamFifo'. +Finding identical cells in module `\StreamFifoLowLatency'. +Finding identical cells in module `\SystemDebugger'. +Finding identical cells in module `\Timer'. +Finding identical cells in module `\UartCtrl'. +Finding identical cells in module `\UartCtrlRx'. +Finding identical cells in module `\UartCtrlTx'. +Finding identical cells in module `\VexRiscv'. +Removed a total of 0 cells. + +4.13. Executing OPT_DFF pass (perform DFF optimizations). + +4.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Apb3Decoder.. +Finding unused cells or wires in module \Apb3Gpio.. +Finding unused cells or wires in module \Apb3Router.. +Finding unused cells or wires in module \Apb3UartCtrl.. +Finding unused cells or wires in module \BufferCC.. +Finding unused cells or wires in module \BufferCC_1.. +Finding unused cells or wires in module \BufferCC_2.. +Finding unused cells or wires in module \BufferCC_3.. +Finding unused cells or wires in module \FlowCCByToggle.. +Finding unused cells or wires in module \InterruptCtrl.. +Finding unused cells or wires in module \JtagBridge.. +Finding unused cells or wires in module \Murax.. +Finding unused cells or wires in module \MuraxApb3Timer.. +Finding unused cells or wires in module \MuraxMasterArbiter.. +Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam.. +Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge.. +Finding unused cells or wires in module \Prescaler.. +Finding unused cells or wires in module \StreamFifo.. +Finding unused cells or wires in module \StreamFifoLowLatency.. +Finding unused cells or wires in module \SystemDebugger.. +Finding unused cells or wires in module \Timer.. +Finding unused cells or wires in module \UartCtrl.. +Finding unused cells or wires in module \UartCtrlRx.. +Finding unused cells or wires in module \UartCtrlTx.. +Finding unused cells or wires in module \VexRiscv.. + +4.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module Apb3Decoder. +Optimizing module Apb3Gpio. +Optimizing module Apb3Router. +Optimizing module Apb3UartCtrl. +Optimizing module BufferCC. +Optimizing module BufferCC_1. +Optimizing module BufferCC_2. +Optimizing module BufferCC_3. +Optimizing module FlowCCByToggle. +Optimizing module InterruptCtrl. +Optimizing module JtagBridge. +Optimizing module Murax. +Optimizing module MuraxApb3Timer. +Optimizing module MuraxMasterArbiter. +Optimizing module MuraxPipelinedMemoryBusRam. +Optimizing module PipelinedMemoryBusToApbBridge. +Optimizing module Prescaler. +Optimizing module StreamFifo. +Optimizing module StreamFifoLowLatency. +Optimizing module SystemDebugger. +Optimizing module Timer. +Optimizing module UartCtrl. +Optimizing module UartCtrlRx. +Optimizing module UartCtrlTx. +Optimizing module VexRiscv. + +4.16. Finished OPT passes. (There is nothing left to do.) + +5. Executing Verilog backend. + +5.1. Executing BMUXMAP pass. + +5.2. Executing DEMUXMAP pass. +Dumping module `\Apb3Decoder'. +Dumping module `\Apb3Gpio'. +Dumping module `\Apb3Router'. +Dumping module `\Apb3UartCtrl'. +Dumping module `\BufferCC'. +Dumping module `\BufferCC_1'. +Dumping module `\BufferCC_2'. +Dumping module `\BufferCC_3'. +Dumping module `\FlowCCByToggle'. +Dumping module `\InterruptCtrl'. +Dumping module `\JtagBridge'. +Dumping module `\Murax'. +Dumping module `\MuraxApb3Timer'. +Dumping module `\MuraxMasterArbiter'. +Dumping module `\MuraxPipelinedMemoryBusRam'. +Dumping module `\PipelinedMemoryBusToApbBridge'. +Dumping module `\Prescaler'. +Dumping module `\StreamFifo'. +Dumping module `\StreamFifoLowLatency'. +Dumping module `\SystemDebugger'. +Dumping module `\Timer'. +Dumping module `\UartCtrl'. +Dumping module `\UartCtrlRx'. +Dumping module `\UartCtrlTx'. +Dumping module `\VexRiscv'. + +6. Executing SYNTH_ECP5 pass. + +6.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_sim.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_sim.v' to AST representation. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\$__ABC9_LUT5'. +Generating RTLIL representation for module `\$__ABC9_LUT6'. +Generating RTLIL representation for module `\$__ABC9_LUT7'. +Generating RTLIL representation for module `\L6MUX21'. +Generating RTLIL representation for module `\CCU2C'. +Generating RTLIL representation for module `\TRELLIS_RAM16X2'. +Generating RTLIL representation for module `\PFUMX'. +Generating RTLIL representation for module `\TRELLIS_DPR16X4'. +Generating RTLIL representation for module `\DPR16X4C'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\TRELLIS_FF'. +Generating RTLIL representation for module `\TRELLIS_IO'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\TRELLIS_SLICE'. +Generating RTLIL representation for module `\DP16KD'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +6.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_bb.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_bb.v' to AST representation. +Generating RTLIL representation for module `\MULT18X18D'. +Generating RTLIL representation for module `\ALU54B'. +Generating RTLIL representation for module `\EHXPLLL'. +Generating RTLIL representation for module `\DTR'. +Generating RTLIL representation for module `\OSCG'. +Generating RTLIL representation for module `\USRMCLK'. +Generating RTLIL representation for module `\JTAGG'. +Generating RTLIL representation for module `\DELAYF'. +Generating RTLIL representation for module `\DELAYG'. +Generating RTLIL representation for module `\IDDRX1F'. +Generating RTLIL representation for module `\IDDRX2F'. +Generating RTLIL representation for module `\IDDR71B'. +Generating RTLIL representation for module `\IDDRX2DQA'. +Generating RTLIL representation for module `\ODDRX1F'. +Generating RTLIL representation for module `\ODDRX2F'. +Generating RTLIL representation for module `\ODDR71B'. +Generating RTLIL representation for module `\OSHX2A'. +Generating RTLIL representation for module `\ODDRX2DQA'. +Generating RTLIL representation for module `\ODDRX2DQSB'. +Generating RTLIL representation for module `\TSHX2DQA'. +Generating RTLIL representation for module `\TSHX2DQSA'. +Generating RTLIL representation for module `\DQSBUFM'. +Generating RTLIL representation for module `\DDRDLLA'. +Generating RTLIL representation for module `\DLLDELD'. +Generating RTLIL representation for module `\CLKDIVF'. +Generating RTLIL representation for module `\ECLKSYNCB'. +Generating RTLIL representation for module `\ECLKBRIDGECS'. +Generating RTLIL representation for module `\DCCA'. +Generating RTLIL representation for module `\DCSC'. +Generating RTLIL representation for module `\DCUA'. +Generating RTLIL representation for module `\EXTREFB'. +Generating RTLIL representation for module `\PCSCLKDIV'. +Generating RTLIL representation for module `\PUR'. +Generating RTLIL representation for module `\GSR'. +Generating RTLIL representation for module `\SGSR'. +Generating RTLIL representation for module `\PDPW16KD'. +Successfully finished Verilog frontend. + +6.3. Executing HIERARCHY pass (managing design hierarchy). + +6.3.1. Analyzing design hierarchy.. +Top module: \Murax +Used module: \Apb3Router +Used module: \Apb3Decoder +Used module: \BufferCC_3 +Used module: \JtagBridge +Used module: \FlowCCByToggle +Used module: \BufferCC_1 +Used module: \SystemDebugger +Used module: \PipelinedMemoryBusToApbBridge +Used module: \VexRiscv +Used module: \StreamFifoLowLatency +Used module: \Apb3Gpio +Used module: \BufferCC_2 +Used module: \MuraxMasterArbiter +Used module: \MuraxPipelinedMemoryBusRam +Used module: \MuraxApb3Timer +Used module: \InterruptCtrl +Used module: \Prescaler +Used module: \Timer +Used module: \Apb3UartCtrl +Used module: \StreamFifo +Used module: \UartCtrl +Used module: \UartCtrlRx +Used module: \BufferCC +Used module: \UartCtrlTx + +6.3.2. Analyzing design hierarchy.. +Top module: \Murax +Used module: \Apb3Router +Used module: \Apb3Decoder +Used module: \BufferCC_3 +Used module: \JtagBridge +Used module: \FlowCCByToggle +Used module: \BufferCC_1 +Used module: \SystemDebugger +Used module: \PipelinedMemoryBusToApbBridge +Used module: \VexRiscv +Used module: \StreamFifoLowLatency +Used module: \Apb3Gpio +Used module: \BufferCC_2 +Used module: \MuraxMasterArbiter +Used module: \MuraxPipelinedMemoryBusRam +Used module: \MuraxApb3Timer +Used module: \InterruptCtrl +Used module: \Prescaler +Used module: \Timer +Used module: \Apb3UartCtrl +Used module: \StreamFifo +Used module: \UartCtrl +Used module: \UartCtrlRx +Used module: \BufferCC +Used module: \UartCtrlTx +Removed 0 unused modules. + +6.4. Executing PROC pass (convert processes to netlists). + +6.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$4173'. +Cleaned up 1 empty switch. + +6.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$4273 in module TRELLIS_FF. +Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$4232 in module DPR16X4C. +Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$4174 in module TRELLIS_DPR16X4. +Removed a total of 0 dead cases. + +6.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 42 assignments to connections. + +6.4.4. Executing PROC_INIT pass (extract init attributes). +Found init rule in `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4277'. + Set init value: \Q = 1'0 + +6.4.5. Executing PROC_ARST pass (detect async resets in processes). + +6.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4277'. +Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$4273'. + 1/1: $0\Q[0:0] +Creating decoders for process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'. +Creating decoders for process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$4232'. + 1/3: $1$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$4231_EN[3:0]$4238 + 2/3: $1$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$4231_DATA[3:0]$4237 + 3/3: $1$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$4231_ADDR[3:0]$4236 +Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'. +Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$4174'. + 1/3: $1$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$4172_EN[3:0]$4178 + 2/3: $1$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$4172_DATA[3:0]$4179 + 3/3: $1$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$4172_ADDR[3:0]$4180 +Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$4173'. + +6.4.7. Executing PROC_DLATCH pass (convert process syncs to latches). + +6.4.8. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$4273'. + created $dff cell `$procdff$4301' with positive edge clock. +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4218_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4220_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4223_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4221_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4217_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4219_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4222_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4216_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4224_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4225_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4226_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4227_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4228_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4229_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4230_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'. + created direct connection (no actual register cell created). +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$4231_ADDR' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$4232'. + created $dff cell `$procdff$4302' with positive edge clock. +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$4231_DATA' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$4232'. + created $dff cell `$procdff$4303' with positive edge clock. +Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$4231_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$4232'. + created $dff cell `$procdff$4304' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4171_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4170_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4156_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4157_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4158_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4159_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4160_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4161_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4162_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4167_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4166_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4165_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4164_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4163_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4169_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4168_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'. + created direct connection (no actual register cell created). +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$4172_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$4174'. + created $dff cell `$procdff$4305' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$4172_DATA' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$4174'. + created $dff cell `$procdff$4306' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$4172_ADDR' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$4174'. + created $dff cell `$procdff$4307' with positive edge clock. +Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$4173'. + created direct connection (no actual register cell created). + +6.4.9. Executing PROC_MEMWR pass (convert process memory writes to cells). + +6.4.10. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4277'. +Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$4273'. +Removing empty process `TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$4273'. +Removing empty process `DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'. +Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$4232'. +Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'. +Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$4174'. +Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$4173'. +Cleaned up 4 empty switches. + +6.4.11. Executing OPT_EXPR pass (perform const folding). +Optimizing module Apb3Decoder. +Optimizing module Apb3Gpio. +Optimizing module Apb3Router. +Optimizing module Apb3UartCtrl. +Optimizing module BufferCC. +Optimizing module BufferCC_1. +Optimizing module BufferCC_2. +Optimizing module BufferCC_3. +Optimizing module FlowCCByToggle. +Optimizing module InterruptCtrl. +Optimizing module JtagBridge. +Optimizing module Murax. +Optimizing module MuraxApb3Timer. +Optimizing module MuraxMasterArbiter. +Optimizing module MuraxPipelinedMemoryBusRam. +Optimizing module PipelinedMemoryBusToApbBridge. +Optimizing module Prescaler. +Optimizing module StreamFifo. +Optimizing module StreamFifoLowLatency. +Optimizing module SystemDebugger. +Optimizing module Timer. +Optimizing module UartCtrl. +Optimizing module UartCtrlRx. +Optimizing module UartCtrlTx. +Optimizing module VexRiscv. + +6.5. Executing FLATTEN pass (flatten design). +Deleting now unused module Apb3Decoder. +Deleting now unused module Apb3Gpio. +Deleting now unused module Apb3Router. +Deleting now unused module Apb3UartCtrl. +Deleting now unused module BufferCC. +Deleting now unused module BufferCC_1. +Deleting now unused module BufferCC_2. +Deleting now unused module BufferCC_3. +Deleting now unused module FlowCCByToggle. +Deleting now unused module InterruptCtrl. +Deleting now unused module JtagBridge. +Deleting now unused module MuraxApb3Timer. +Deleting now unused module MuraxMasterArbiter. +Deleting now unused module MuraxPipelinedMemoryBusRam. +Deleting now unused module PipelinedMemoryBusToApbBridge. +Deleting now unused module Prescaler. +Deleting now unused module StreamFifo. +Deleting now unused module StreamFifoLowLatency. +Deleting now unused module SystemDebugger. +Deleting now unused module Timer. +Deleting now unused module UartCtrl. +Deleting now unused module UartCtrlRx. +Deleting now unused module UartCtrlTx. +Deleting now unused module VexRiscv. + + +6.6. Executing TRIBUF pass. + +6.7. Executing DEMINOUT pass (demote inout ports to input or output). + +6.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module Murax. + + +6.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Murax.. +Removed 8 unused cells and 28 unused wires. + + +6.10. Executing CHECK pass (checking for obvious problems). +Checking module Murax... +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [31] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [30] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [29] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [28] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [27] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [26] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [25] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [24] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [23] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [22] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [21] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [20] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [19] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [18] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [17] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [16] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [15] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [14] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [13] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [12] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [11] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [10] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [9] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [8] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [7] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [6] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [5] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [4] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [3] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [2] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [1] is used but has no driver. +Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [0] is used but has no driver. +Found and reported 32 problems. + +6.11. Executing OPT pass (performing simple optimizations). + +6.11.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module Murax. + + +6.11.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Murax'. + +Removed a total of 8 cells. + +6.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \Murax.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +6.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \Murax. + Optimizing cells in module \Murax. +Performed a total of 2 changes. + +6.11.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Murax'. + +Removed a total of 3 cells. + +6.11.6. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 0-bit at position 0 on $flatten\jtagBridge_1.$auto$ff.cc:262:slice$3449 ($dffe) from module Murax. +Setting constant 0-bit at position 0 on $flatten\system_cpu.\IBusSimplePlugin_rspJoin_rspBuffer_c.$auto$ff.cc:262:slice$3525 ($dffe) from module Murax. + +6.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Murax.. +Removed 2 unused cells and 28 unused wires. + + +6.11.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module Murax. + + +6.11.9. Rerunning OPT passes. (Maybe there is more to do..) + +6.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \Murax.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +6.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \Murax. +Performed a total of 0 changes. + +6.11.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Murax'. +Removed a total of 0 cells. + +6.11.13. Executing OPT_DFF pass (perform DFF optimizations). + +6.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Murax.. +Removed 0 unused cells and 3 unused wires. + + +6.11.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module Murax. + +6.11.16. Rerunning OPT passes. (Maybe there is more to do..) + +6.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \Murax.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +6.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \Murax. +Performed a total of 0 changes. + +6.11.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Murax'. +Removed a total of 0 cells. + +6.11.20. Executing OPT_DFF pass (perform DFF optimizations). + +6.11.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Murax.. + +6.11.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module Murax. + +6.11.23. Finished OPT passes. (There is nothing left to do.) + +6.12. Executing FSM pass (extract and optimize FSM). + +6.12.1. Executing FSM_DETECT pass (finding FSMs in design). +Warning: Regarding the user-specified fsm_encoding attribute on Murax.system_cpu.CsrPlugin_interrupt_targetPrivilege: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +Not marking Murax.system_gpioACtrl.io_gpio_read_buffercc.buffers_0 as FSM state register: + Users of register don't seem to benefit from recoding. + +6.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). +Extracting FSM `\system_cpu.CsrPlugin_interrupt_targetPrivilege' from module `\Murax'. + root of input selection tree: 2'mm + fsm extraction failed: incomplete input selection tree root. + +6.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +6.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Murax.. + +6.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +6.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +6.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +6.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +6.13. Executing OPT pass (performing simple optimizations). + +6.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module Murax. + +6.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Murax'. +Removed a total of 0 cells. + +6.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \Murax.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +6.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \Murax. +Performed a total of 0 changes. + +6.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Murax'. +Removed a total of 0 cells. + +6.13.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $flatten\system_cpu.$procdff$2954 ($dff) from module Murax (D = \system_cpu.CsrPlugin_csrMapping_writeDataSignal [3], Q = \system_cpu.CsrPlugin_mip_MSIP, rval = 1'0). +Adding SRST signal on $flatten\system_apbBridge.$auto$ff.cc:262:slice$3516 ($dffe) from module Murax (D = \system_cpu_dBus_cmd_rData_address [1:0], Q = \system_apbBridge.io_pipelinedMemoryBus_cmd_rData_address [1:0], rval = 2'00). +Adding SRST signal on $flatten\jtagBridge_1.$auto$ff.cc:262:slice$3452 ($dffe) from module Murax (D = \jtagBridge_1.jtag_readArea_full_shifter [2], Q = \jtagBridge_1.jtag_readArea_full_shifter [1], rval = 1'0). + +6.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Murax.. +Removed 2 unused cells and 2 unused wires. + + +6.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module Murax. + +6.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +6.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \Murax.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +6.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \Murax. +Performed a total of 0 changes. + +6.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Murax'. +Removed a total of 0 cells. + +6.13.13. Executing OPT_DFF pass (perform DFF optimizations). + +6.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Murax.. + +6.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module Murax. + +6.13.16. Finished OPT passes. (There is nothing left to do.) + +6.14. Executing WREDUCE pass (reducing word size of cells). +Removed top 2 bits (of 6) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3012$284 ($eq). +Removed top 1 bits (of 5) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3013$287 ($eq). +Removed top 1 bits (of 3) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3013$288 ($eq). +Removed top 1 bits (of 2) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3025$300 ($eq). +Removed top 3 bits (of 5) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3035$312 ($eq). +Removed top 1 bits (of 3) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3037$317 ($eq). +Removed top 1 bits (of 3) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3058$337 ($eq). +Removed top 1 bits (of 2) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3066$345 ($eq). +Removed top 1 bits (of 3) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3081$359 ($eq). +Removed top 1 bits (of 2) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3086$367 ($eq). +Removed top 1 bits (of 2) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3088$369 ($eq). +Removed top 1 bits (of 3) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:4427$600 ($eq). +Removed top 1 bits (of 2) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:4430$606 ($eq). +Removed top 2 bits (of 3) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:4432$613 ($eq). +Removed top 3 bits (of 5) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:4432$616 ($eq). +Removed top 3 bits (of 8) from port B of cell Murax.$flatten\io_apb_decoder.$eq$../Murax.v:667$48 ($eq). +Removed top 2 bits (of 8) from port B of cell Murax.$flatten\io_apb_decoder.$eq$../Murax.v:668$51 ($eq). +Removed top 1 bits (of 2) from wire Murax.$flatten\system_cpu.$auto$wreduce.cc:454:run$3724. +Removed top 19 bits (of 32) from wire Murax.$flatten\system_cpu.$auto$wreduce.cc:454:run$3725. +Removed top 19 bits (of 32) from wire Murax.$flatten\system_cpu.$ternary$../Murax.v:4417$593_Y. +Removed top 15 bits (of 32) from wire Murax.system_timer_io_apb_PRDATA. +Removed top 3 bits (of 32) from wire Murax.system_uartCtrl_io_apb_PRDATA. + +6.15. Executing PEEPOPT pass (run peephole optimizers). + +6.16. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Murax.. +Removed 0 unused cells and 5 unused wires. + + +6.17. Executing SHARE pass (SAT-based resource sharing). + +6.18. Executing TECHMAP pass (map to technology primitives). + +6.18.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/cmp2lut.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +6.18.2. Continuing TECHMAP pass. +No more expansions possible. + + +6.19. Executing OPT_EXPR pass (perform const folding). +Optimizing module Murax. + +6.20. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Murax.. + +6.21. Executing TECHMAP pass (map to technology primitives). + +6.21.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +6.21.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/dsp_map.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/dsp_map.v' to AST representation. +Generating RTLIL representation for module `\$__MUL18X18'. +Successfully finished Verilog frontend. + +6.21.3. Continuing TECHMAP pass. +No more expansions possible. + + +6.22. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module Murax: + created 0 $alu and 0 $macc cells. + +6.23. Executing OPT pass (performing simple optimizations). + +6.23.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module Murax. + +6.23.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Murax'. +Removed a total of 0 cells. + +6.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \Murax.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +6.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \Murax. +Performed a total of 0 changes. + +6.23.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Murax'. +Removed a total of 0 cells. + +6.23.6. Executing OPT_DFF pass (perform DFF optimizations). + +6.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Murax.. + +6.23.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module Murax. + +6.23.9. Finished OPT passes. (There is nothing left to do.) + +6.24. Executing MEMORY pass. + +6.24.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +6.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +6.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + +6.24.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd). + +6.24.5. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Murax.. + +6.24.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). +Consolidating read ports of memory Murax.system_cpu.RegFilePlugin_regFile by address: + +6.24.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +6.24.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Murax.. + +6.24.9. Executing MEMORY_COLLECT pass (generating $mem cells). + +6.25. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Murax.. + +6.26. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). +Processing Murax.system_cpu.RegFilePlugin_regFile: + Properties: ports=3 bits=1024 rports=2 wports=1 dbits=32 abits=5 words=32 + Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5 + Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min bits 2048' not met. + Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5 + Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5 + Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2 + Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1 + Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2 + Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1 + Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2 + Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1 + Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met. + No acceptable bram resources found. +Processing Murax.system_ram.ram_symbol0: + Properties: ports=2 bits=16384 rports=1 wports=1 dbits=8 abits=11 words=2048 + Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted. + Mapping to bram type $__ECP5_PDPW16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=14336 efficiency=22 + Storing for later selection. + Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=10240 efficiency=44 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 2): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=2048 efficiency=88 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50 + Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 3): + Shuffle bit order to accommodate enable buckets of size 4.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=8192 efficiency=50 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25 + Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 4): + Shuffle bit order to accommodate enable buckets of size 2.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=12288 efficiency=25 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12 + Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 5): + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=14336 efficiency=12 + Storing for later selection. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50 + Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25 + Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12 + Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50 + Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25 + Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12 + Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met. + Selecting best of 6 rules: + Efficiency for rule 4.5: efficiency=12, cells=8, acells=1 + Efficiency for rule 4.4: efficiency=25, cells=4, acells=1 + Efficiency for rule 4.3: efficiency=50, cells=2, acells=1 + Efficiency for rule 4.2: efficiency=88, cells=1, acells=1 + Efficiency for rule 4.1: efficiency=44, cells=2, acells=2 + Efficiency for rule 1.1: efficiency=22, cells=4, acells=4 + Selected rule 4.2 with efficiency 88. + Mapping to bram type $__ECP5_DP16KD (variant 2): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Creating $__ECP5_DP16KD cell at grid position <0 0 0>: system_ram.ram_symbol0.0.0.0 +Processing Murax.system_ram.ram_symbol1: + Properties: ports=2 bits=16384 rports=1 wports=1 dbits=8 abits=11 words=2048 + Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted. + Mapping to bram type $__ECP5_PDPW16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=14336 efficiency=22 + Storing for later selection. + Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=10240 efficiency=44 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 2): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=2048 efficiency=88 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50 + Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 3): + Shuffle bit order to accommodate enable buckets of size 4.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=8192 efficiency=50 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25 + Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 4): + Shuffle bit order to accommodate enable buckets of size 2.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=12288 efficiency=25 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12 + Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 5): + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=14336 efficiency=12 + Storing for later selection. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50 + Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25 + Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12 + Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50 + Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25 + Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12 + Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met. + Selecting best of 6 rules: + Efficiency for rule 4.5: efficiency=12, cells=8, acells=1 + Efficiency for rule 4.4: efficiency=25, cells=4, acells=1 + Efficiency for rule 4.3: efficiency=50, cells=2, acells=1 + Efficiency for rule 4.2: efficiency=88, cells=1, acells=1 + Efficiency for rule 4.1: efficiency=44, cells=2, acells=2 + Efficiency for rule 1.1: efficiency=22, cells=4, acells=4 + Selected rule 4.2 with efficiency 88. + Mapping to bram type $__ECP5_DP16KD (variant 2): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Creating $__ECP5_DP16KD cell at grid position <0 0 0>: system_ram.ram_symbol1.0.0.0 +Processing Murax.system_ram.ram_symbol2: + Properties: ports=2 bits=16384 rports=1 wports=1 dbits=8 abits=11 words=2048 + Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted. + Mapping to bram type $__ECP5_PDPW16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=14336 efficiency=22 + Storing for later selection. + Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=10240 efficiency=44 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 2): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=2048 efficiency=88 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50 + Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 3): + Shuffle bit order to accommodate enable buckets of size 4.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=8192 efficiency=50 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25 + Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 4): + Shuffle bit order to accommodate enable buckets of size 2.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=12288 efficiency=25 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12 + Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 5): + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=14336 efficiency=12 + Storing for later selection. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50 + Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25 + Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12 + Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50 + Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25 + Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12 + Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met. + Selecting best of 6 rules: + Efficiency for rule 4.5: efficiency=12, cells=8, acells=1 + Efficiency for rule 4.4: efficiency=25, cells=4, acells=1 + Efficiency for rule 4.3: efficiency=50, cells=2, acells=1 + Efficiency for rule 4.2: efficiency=88, cells=1, acells=1 + Efficiency for rule 4.1: efficiency=44, cells=2, acells=2 + Efficiency for rule 1.1: efficiency=22, cells=4, acells=4 + Selected rule 4.2 with efficiency 88. + Mapping to bram type $__ECP5_DP16KD (variant 2): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Creating $__ECP5_DP16KD cell at grid position <0 0 0>: system_ram.ram_symbol2.0.0.0 +Processing Murax.system_ram.ram_symbol3: + Properties: ports=2 bits=16384 rports=1 wports=1 dbits=8 abits=11 words=2048 + Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted. + Mapping to bram type $__ECP5_PDPW16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=14336 efficiency=22 + Storing for later selection. + Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22 + Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=10240 efficiency=44 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 2): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=2048 efficiency=88 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50 + Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 3): + Shuffle bit order to accommodate enable buckets of size 4.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=8192 efficiency=50 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25 + Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 4): + Shuffle bit order to accommodate enable buckets of size 2.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=12288 efficiency=25 + Storing for later selection. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12 + Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted. + Mapping to bram type $__ECP5_DP16KD (variant 5): + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Updated properties: dups=1 waste=14336 efficiency=12 + Storing for later selection. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50 + Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25 + Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12 + Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44 + Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88 + Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50 + Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25 + Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12 + Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met. + Selecting best of 6 rules: + Efficiency for rule 4.5: efficiency=12, cells=8, acells=1 + Efficiency for rule 4.4: efficiency=25, cells=4, acells=1 + Efficiency for rule 4.3: efficiency=50, cells=2, acells=1 + Efficiency for rule 4.2: efficiency=88, cells=1, acells=1 + Efficiency for rule 4.1: efficiency=44, cells=2, acells=2 + Efficiency for rule 1.1: efficiency=22, cells=4, acells=4 + Selected rule 4.2 with efficiency 88. + Mapping to bram type $__ECP5_DP16KD (variant 2): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1 + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port A1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port B1.1. + Creating $__ECP5_DP16KD cell at grid position <0 0 0>: system_ram.ram_symbol3.0.0.0 +Processing Murax.system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram: + Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16 + Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0 + Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0 + Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0 + Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met. + No acceptable bram resources found. +Processing Murax.system_uartCtrl.uartCtrl_1_io_read_queueWithOccupancy.logic_ram: + Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16 + Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0 + Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0 + Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0 + Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0 + Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #5 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0 + Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met. + Checking rule #6 for bram type $__ECP5_DP16KD (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0 + Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met. + No acceptable bram resources found. + +6.27. Executing TECHMAP pass (map to technology primitives). + +6.27.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/brams_map.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/brams_map.v' to AST representation. +Generating RTLIL representation for module `\$__ECP5_DP16KD'. +Generating RTLIL representation for module `\$__ECP5_PDPW16KD'. +Successfully finished Verilog frontend. + +6.27.2. Continuing TECHMAP pass. +Using template $paramod$3be384f458d0537a27afbd79f48b29b3c25e4b9a\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD. +No more expansions possible. + + +6.28. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). +Processing Murax.system_cpu.RegFilePlugin_regFile: + Properties: ports=3 bits=1024 rports=2 wports=1 dbits=32 abits=5 words=32 + Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1): + Bram geometry: abits=4 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted. + Mapping to bram type $__TRELLIS_DPR16X4 (variant 1): + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port B1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port A1.1. + Read port #1 is in clock domain \io_mainClk. + Failed to map read port #1. + Growing more read ports by duplicating bram cells. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port A1.1. + Read port #1 is in clock domain \io_mainClk. + Mapped to bram port A1.2. + Updated properties: dups=2 waste=0 efficiency=50 +Extracted data FF from read port 0 of Murax.system_cpu.RegFilePlugin_regFile: $\system_cpu.RegFilePlugin_regFile$rdreg[0] +Extracted data FF from read port 1 of Murax.system_cpu.RegFilePlugin_regFile: $\system_cpu.RegFilePlugin_regFile$rdreg[1] + Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: system_cpu.RegFilePlugin_regFile.0.0.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 1>: system_cpu.RegFilePlugin_regFile.0.0.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <0 1 0>: system_cpu.RegFilePlugin_regFile.0.1.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <0 1 1>: system_cpu.RegFilePlugin_regFile.0.1.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: system_cpu.RegFilePlugin_regFile.1.0.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 1>: system_cpu.RegFilePlugin_regFile.1.0.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <1 1 0>: system_cpu.RegFilePlugin_regFile.1.1.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <1 1 1>: system_cpu.RegFilePlugin_regFile.1.1.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 0>: system_cpu.RegFilePlugin_regFile.2.0.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 1>: system_cpu.RegFilePlugin_regFile.2.0.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <2 1 0>: system_cpu.RegFilePlugin_regFile.2.1.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <2 1 1>: system_cpu.RegFilePlugin_regFile.2.1.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <3 0 0>: system_cpu.RegFilePlugin_regFile.3.0.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <3 0 1>: system_cpu.RegFilePlugin_regFile.3.0.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <3 1 0>: system_cpu.RegFilePlugin_regFile.3.1.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <3 1 1>: system_cpu.RegFilePlugin_regFile.3.1.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <4 0 0>: system_cpu.RegFilePlugin_regFile.4.0.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <4 0 1>: system_cpu.RegFilePlugin_regFile.4.0.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <4 1 0>: system_cpu.RegFilePlugin_regFile.4.1.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <4 1 1>: system_cpu.RegFilePlugin_regFile.4.1.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <5 0 0>: system_cpu.RegFilePlugin_regFile.5.0.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <5 0 1>: system_cpu.RegFilePlugin_regFile.5.0.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <5 1 0>: system_cpu.RegFilePlugin_regFile.5.1.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <5 1 1>: system_cpu.RegFilePlugin_regFile.5.1.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <6 0 0>: system_cpu.RegFilePlugin_regFile.6.0.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <6 0 1>: system_cpu.RegFilePlugin_regFile.6.0.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <6 1 0>: system_cpu.RegFilePlugin_regFile.6.1.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <6 1 1>: system_cpu.RegFilePlugin_regFile.6.1.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <7 0 0>: system_cpu.RegFilePlugin_regFile.7.0.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <7 0 1>: system_cpu.RegFilePlugin_regFile.7.0.1 + Creating $__TRELLIS_DPR16X4 cell at grid position <7 1 0>: system_cpu.RegFilePlugin_regFile.7.1.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <7 1 1>: system_cpu.RegFilePlugin_regFile.7.1.1 +Processing Murax.system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram: + Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16 + Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1): + Bram geometry: abits=4 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted. + Mapping to bram type $__TRELLIS_DPR16X4 (variant 1): + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port B1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=0 efficiency=100 +Extracted data FF from read port 0 of Murax.system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram: $\system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram$rdreg[0] + Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram.0.0.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram.1.0.0 +Processing Murax.system_uartCtrl.uartCtrl_1_io_read_queueWithOccupancy.logic_ram: + Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16 + Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1): + Bram geometry: abits=4 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 + Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted. + Mapping to bram type $__TRELLIS_DPR16X4 (variant 1): + Write port #0 is in clock domain \io_mainClk. + Mapped to bram port B1. + Read port #0 is in clock domain \io_mainClk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=0 efficiency=100 +Extracted data FF from read port 0 of Murax.system_uartCtrl.uartCtrl_1_io_read_queueWithOccupancy.logic_ram: $\system_uartCtrl.uartCtrl_1_io_read_queueWithOccupancy.logic_ram$rdreg[0] + Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: system_uartCtrl.uartCtrl_1_io_read_queueWithOccupancy.logic_ram.0.0.0 + Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: system_uartCtrl.uartCtrl_1_io_read_queueWithOccupancy.logic_ram.1.0.0 + +6.29. Executing TECHMAP pass (map to technology primitives). + +6.29.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/lutrams_map.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/lutrams_map.v' to AST representation. +Generating RTLIL representation for module `\$__TRELLIS_DPR16X4'. +Successfully finished Verilog frontend. + +6.29.2. Continuing TECHMAP pass. +Using template $paramod\$__TRELLIS_DPR16X4\CLKPOL2=32'00000000000000000000000000000001 for cells of type $__TRELLIS_DPR16X4. +No more expansions possible. + + +6.30. Executing OPT pass (performing simple optimizations). + +6.30.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module Murax. + + +6.30.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Murax'. + +Removed a total of 62 cells. + +6.30.3. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $flatten\jtagBridge_1.$auto$ff.cc:262:slice$3461 ($dffe) from module Murax (D = { \io_jtag_tdi \jtagBridge_1.jtag_tap_instructionShift [3:1] }, Q = \jtagBridge_1.jtag_tap_instructionShift, rval = 4'0001). +Setting constant 1-bit at position 0 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 1 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 2 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 3 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 4 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 5 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 6 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 7 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 8 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 9 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 10 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 11 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 12 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 13 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 14 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 15 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 16 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 17 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 18 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 19 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 20 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 21 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 22 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 23 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 24 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 25 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 26 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 27 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 28 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 29 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 30 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. +Setting constant 1-bit at position 31 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax. + +6.30.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Murax.. +Removed 4 unused cells and 392 unused wires. + + +6.30.5. Rerunning OPT passes. (Removed registers in this run.) + +6.30.6. Executing OPT_EXPR pass (perform const folding). +Optimizing module Murax. + +6.30.7. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Murax'. +Removed a total of 0 cells. + +6.30.8. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 1-bit at position 0 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 1 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 2 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 3 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 4 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 5 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 6 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 7 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 8 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 9 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 10 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 11 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 12 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 13 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 14 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 15 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 16 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 17 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 18 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 19 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 20 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 21 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 22 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 23 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 24 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 25 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 26 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 27 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 28 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 29 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 30 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. +Setting constant 1-bit at position 31 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax. + +6.30.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Murax.. + +6.30.10. Rerunning OPT passes. (Removed registers in this run.) + +6.30.11. Executing OPT_EXPR pass (perform const folding). +Optimizing module Murax. + + +6.30.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Murax'. +Removed a total of 0 cells. + +6.30.13. Executing OPT_DFF pass (perform DFF optimizations). + +6.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Murax.. +Removed 1 unused cells and 1 unused wires. + + +6.30.15. Finished fast OPT passes. + +6.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +6.32. Executing OPT pass (performing simple optimizations). + +6.32.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module Murax. + +6.32.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Murax'. +Removed a total of 0 cells. + +6.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \Murax.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +6.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \Murax. +Performed a total of 0 changes. + +6.32.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Murax'. +Removed a total of 0 cells. + +6.32.6. Executing OPT_DFF pass (perform DFF optimizations). + +6.32.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Murax.. + +6.32.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module Murax. + +6.32.9. Finished OPT passes. (There is nothing left to do.) + +6.33. Executing TECHMAP pass (map to technology primitives). + +6.33.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +6.33.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/arith_map.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/arith_map.v' to AST representation. +Generating RTLIL representation for module `\_80_ecp5_alu'. +Successfully finished Verilog frontend. + +6.33.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $ne. +Using extmapper simplemap for cells of type $logic_and. +Using extmapper simplemap for cells of type $eq. +Using extmapper simplemap for cells of type $reduce_bool. +Using extmapper simplemap for cells of type $logic_not. +Using extmapper simplemap for cells of type $logic_or. +Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu. +Using extmapper simplemap for cells of type $mux. +Using extmapper simplemap for cells of type $sdffce. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $sdff. +Using extmapper simplemap for cells of type $adff. +Using extmapper simplemap for cells of type $dffe. +Using extmapper simplemap for cells of type $adffe. +Using extmapper simplemap for cells of type $sdffe. +Using extmapper simplemap for cells of type $reduce_and. +Using template $paramod$740b056ede97228d3eae64ea2fdc81f0a33e0fe7\_90_alu for cells of type $alu. +Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. +Using template $paramod$d8458b3c47920e79a4e96c2be935e3ae586a4c76\_80_ecp5_alu for cells of type $alu. +Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $reduce_or. +Using extmapper simplemap for cells of type $not. +Using template $paramod$32e7c4d6f92ff4337599ece53082d2e88a82a9f2\_90_pmux for cells of type $pmux. +Using template $paramod$constmap:ee5af906ae0d3d414c6a0471604c553ef70c8e09$paramod$92adee9538f2381d8e5006822c900eb986d754e8\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$d629d85c8826a74239b9178d1930215a43b0ceb0\_90_pmux for cells of type $pmux. +Using template $paramod$103b4016182df467cceab67bcf3e18e6361ec0fd\_80_ecp5_alu for cells of type $alu. +Using template $paramod$b8c0a997bce700f23568a5ada79cc6781d1f5ca0\_90_alu for cells of type $alu. +Using extmapper simplemap for cells of type $or. +Using template $paramod$c5c783b17ab1d780abfad8cfe6563a0a7b47a3b0\_90_pmux for cells of type $pmux. +Using template $paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$3b3a66a7766bf28794ddcd35314b025da1fe57c8\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. +Analyzing pattern of constant bits for this cell: +Creating constmapped module `$paramod$constmap:f062eb9b59fe112e8a37f22ba8867a126e0dc845$paramod$3b3a66a7766bf28794ddcd35314b025da1fe57c8\_90_shift_ops_shr_shl_sshl_sshr'. + +6.33.38. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:f062eb9b59fe112e8a37f22ba8867a126e0dc845$paramod$3b3a66a7766bf28794ddcd35314b025da1fe57c8\_90_shift_ops_shr_shl_sshl_sshr.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + + +6.33.39. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:f062eb9b59fe112e8a37f22ba8867a126e0dc845$paramod$3b3a66a7766bf28794ddcd35314b025da1fe57c8\_90_shift_ops_shr_shl_sshl_sshr. + +Removed 0 unused cells and 8 unused wires. +Using template $paramod$constmap:f062eb9b59fe112e8a37f22ba8867a126e0dc845$paramod$3b3a66a7766bf28794ddcd35314b025da1fe57c8\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. +Using extmapper simplemap for cells of type $xor. +Using template $paramod$b18e16801adf491a64caa0542270798e5d4ac6b6\_80_ecp5_alu for cells of type $alu. +Using template $paramod$2af30114e9bd4ccb04dad757b3f0a8f6bf0615b0\_80_ecp5_alu for cells of type $alu. +Using template $paramod$5cf79906c00cc8f7a6c2d9b89d3bc7b92e33c859\_90_pmux for cells of type $pmux. +Using template $paramod$5982968ccccb55277ed45bb827df8f5e35c0a049\_90_pmux for cells of type $pmux. +Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux. +Using template $paramod$constmap:6e3026a439ed4a6e7983ca0e910890cc59b2f7b2$paramod$f244f79b7bd028e965812e6cbb9720dcefdc7dda\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshl. +Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux. +Using extmapper maccmap for cells of type $macc. + add \system_cpu.decode_to_execute_SRC1 (32 bits, signed) + add { 1'0 \system_cpu.decode_to_execute_SRC_USE_SUB_LESS } (2 bits, signed) + add \system_cpu._zz_execute_SrcPlugin_addSub_3 (32 bits, signed) + packed 1 (1) bits / 1 words into adder tree + add \system_cpu.IBusSimplePlugin_pending_value (3 bits, unsigned) + sub \system_cpu.IBusSimplePlugin_pending_dec (1 bits, unsigned) + add bits \system_cpu.IBusSimplePlugin_cmd_fire (1 bits) + packed 1 (1) bits / 1 words into adder tree +Using template $paramod$dc04b7d98e503a7bab16fce2df70e6e2c5ca34d6\_80_ecp5_alu for cells of type $alu. +Using template $paramod$44a13d10af618e7fbe7b9aad2f6151ffcee1e2fa\_80_ecp5_alu for cells of type $alu. +Using template $paramod$e978c189388a43a00e4e725f292dc6d7f2ae25b3\_90_pmux for cells of type $pmux. +Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu. +Using template $paramod$fc972a7a46956c1788f3cb5257b53c8f1df2d0cc\_90_alu for cells of type $alu. +Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux. +Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux. +Using template $paramod$cc1e387d9d5ac1d3f6e6bed180038d9c0ac48d0c\_90_pmux for cells of type $pmux. +Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux. +Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. +Using extmapper simplemap for cells of type $pos. +Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000011 for cells of type $fa. +Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. +Using template $paramod$78e969f2586efcf3a5b0b0440bcca0db83d5cca2\_90_alu for cells of type $alu. +Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000001 for cells of type $lcu. +No more expansions possible. + + +6.34. Executing OPT pass (performing simple optimizations). + +6.34.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module Murax. + + +6.34.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\Murax'. + +Removed a total of 507 cells. + +6.34.3. Executing OPT_DFF pass (perform DFF optimizations). + +6.34.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Murax.. +Removed 574 unused cells and 2881 unused wires. + + +6.34.5. Finished fast OPT passes. + +6.35. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Murax.. + +6.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +6.37. Executing TECHMAP pass (map to technology primitives). + +6.37.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_map.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFFE_NN_'. +Generating RTLIL representation for module `\$_DFFE_PN_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_SDFF_NP0_'. +Generating RTLIL representation for module `\$_SDFF_NP1_'. +Generating RTLIL representation for module `\$_SDFF_PP0_'. +Generating RTLIL representation for module `\$_SDFF_PP1_'. +Generating RTLIL representation for module `\$_DFFE_NP0P_'. +Generating RTLIL representation for module `\$_DFFE_NP1P_'. +Generating RTLIL representation for module `\$_DFFE_PP0P_'. +Generating RTLIL representation for module `\$_DFFE_PP1P_'. +Generating RTLIL representation for module `\$_DFFE_NP0N_'. +Generating RTLIL representation for module `\$_DFFE_NP1N_'. +Generating RTLIL representation for module `\$_DFFE_PP0N_'. +Generating RTLIL representation for module `\$_DFFE_PP1N_'. +Generating RTLIL representation for module `\$_SDFFE_NP0P_'. +Generating RTLIL representation for module `\$_SDFFE_NP1P_'. +Generating RTLIL representation for module `\$_SDFFE_PP0P_'. +Generating RTLIL representation for module `\$_SDFFE_PP1P_'. +Generating RTLIL representation for module `\$_SDFFE_NP0N_'. +Generating RTLIL representation for module `\$_SDFFE_NP1N_'. +Generating RTLIL representation for module `\$_SDFFE_PP0N_'. +Generating RTLIL representation for module `\$_SDFFE_PP1N_'. +Generating RTLIL representation for module `\$_ALDFF_NP_'. +Generating RTLIL representation for module `\$_ALDFF_PP_'. +Generating RTLIL representation for module `\$_ALDFFE_NPN_'. +Generating RTLIL representation for module `\$_ALDFFE_NPP_'. +Generating RTLIL representation for module `\$_ALDFFE_PPN_'. +Generating RTLIL representation for module `\$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +6.37.2. Continuing TECHMAP pass. +Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. +Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_. +Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. +Using template $paramod\$_DFFE_PN_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PN_. +Using template \$_DFF_PP0_ for cells of type $_DFF_PP0_. +Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. +Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. +Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. +Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. +Using template \$_DFF_PP1_ for cells of type $_DFF_PP1_. +Using template \$_DFFE_PP1P_ for cells of type $_DFFE_PP1P_. +Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_. +Using template $paramod\$_DFF_N_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_N_. +No more expansions possible. + + +6.38. Executing OPT_EXPR pass (perform const folding). +Optimizing module Murax. + + +6.39. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +6.40. Executing ECP5_GSR pass (implement FF init values). +Handling GSR in Murax. + +6.41. Executing ATTRMVCP pass (move or copy attributes). + +6.42. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \Murax.. +Removed 0 unused cells and 6768 unused wires. + + +6.43. Executing TECHMAP pass (map to technology primitives). + +6.43.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/latches_map.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/latches_map.v' to AST representation. +Generating RTLIL representation for module `\$_DLATCH_N_'. +Generating RTLIL representation for module `\$_DLATCH_P_'. +Successfully finished Verilog frontend. + +6.43.2. Continuing TECHMAP pass. +No more expansions possible. + + +6.44. Executing ABC pass (technology mapping using ABC). + +6.44.1. Extracting gate netlist of module `\Murax' to `/input.blif'.. +Extracted 3605 gates and 5015 wires to a netlist network with 1408 inputs and 833 outputs. + +6.44.1.1. Executing ABC. +Running ABC command: /yosys-abc -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_blif /input.blif +ABC: + read_lut /lutdefs.txt +ABC: + strash +ABC: + ifraig +ABC: + scorr +ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). +ABC: + dc2 +ABC: + dretime +ABC: + strash +ABC: + dch -f +ABC: + if +ABC: + mfs2 +ABC: + dress +ABC: Total number of equiv classes = 1275. +ABC: Participating nodes from both networks = 2770. +ABC: Participating nodes from the first network = 1284. ( 86.00 % of nodes) +ABC: Participating nodes from the second network = 1486. ( 99.53 % of nodes) +ABC: Node pairs (any polarity) = 1283. ( 85.93 % of names can be moved) +ABC: Node pairs (same polarity) = 958. ( 64.17 % of names can be moved) +ABC: Total runtime = 0.08 sec +ABC: + write_blif /output.blif + +6.44.1.2. Re-integrating ABC results. +ABC RESULTS: $lut cells: 1491 +ABC RESULTS: internal signals: 2774 +ABC RESULTS: input signals: 1408 +ABC RESULTS: output signals: 833 +Removing temp directory. +Removed 0 unused cells and 3191 unused wires. + +6.45. Executing TECHMAP pass (map to technology primitives). + +6.45.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_map.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFFE_NN_'. +Generating RTLIL representation for module `\$_DFFE_PN_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_SDFF_NP0_'. +Generating RTLIL representation for module `\$_SDFF_NP1_'. +Generating RTLIL representation for module `\$_SDFF_PP0_'. +Generating RTLIL representation for module `\$_SDFF_PP1_'. +Generating RTLIL representation for module `\$_DFFE_NP0P_'. +Generating RTLIL representation for module `\$_DFFE_NP1P_'. +Generating RTLIL representation for module `\$_DFFE_PP0P_'. +Generating RTLIL representation for module `\$_DFFE_PP1P_'. +Generating RTLIL representation for module `\$_DFFE_NP0N_'. +Generating RTLIL representation for module `\$_DFFE_NP1N_'. +Generating RTLIL representation for module `\$_DFFE_PP0N_'. +Generating RTLIL representation for module `\$_DFFE_PP1N_'. +Generating RTLIL representation for module `\$_SDFFE_NP0P_'. +Generating RTLIL representation for module `\$_SDFFE_NP1P_'. +Generating RTLIL representation for module `\$_SDFFE_PP0P_'. +Generating RTLIL representation for module `\$_SDFFE_PP1P_'. +Generating RTLIL representation for module `\$_SDFFE_NP0N_'. +Generating RTLIL representation for module `\$_SDFFE_NP1N_'. +Generating RTLIL representation for module `\$_SDFFE_PP0N_'. +Generating RTLIL representation for module `\$_SDFFE_PP1N_'. +Generating RTLIL representation for module `\$_ALDFF_NP_'. +Generating RTLIL representation for module `\$_ALDFF_PP_'. +Generating RTLIL representation for module `\$_ALDFFE_NPN_'. +Generating RTLIL representation for module `\$_ALDFFE_NPP_'. +Generating RTLIL representation for module `\$_ALDFFE_PPN_'. +Generating RTLIL representation for module `\$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `\$lut'. +Successfully finished Verilog frontend. + +6.45.2. Continuing TECHMAP pass. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. +Using template $paramod$04b674496422df8889c01c3744b94097628ccfbc\$lut for cells of type $lut. +Using template $paramod$3ab7a02e4f59b3797fed50685a40e5273a7f3af0\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. +Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. +Using template $paramod$77970d38e1d966d0c74631f307544f2efca4cbe7\$lut for cells of type $lut. +Using template $paramod$332a399730bfc61adea04021a76b1c4e4030f37d\$lut for cells of type $lut. +Using template $paramod$ad3a97108c9f4d10f8acfa309b668b9455d3d733\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000101 for cells of type $lut. +Using template $paramod$1076d5b96410dc32bbe68df15017559464728316\$lut for cells of type $lut. +Using template $paramod$243c00f5eb9faa1d5ce3478fdc389a56070781f8\$lut for cells of type $lut. +Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut. +Using template $paramod$c5b694ec89d7629b942ccf6a9be1d39e24f8edec\$lut for cells of type $lut. +Using template $paramod$ac0bc5d4f1e6dcfd192559e5535468fd2bd6a006\$lut for cells of type $lut. +Using template $paramod$238ce1c123ccd5620a61157a2c5350ee6fc4d4ff\$lut for cells of type $lut. +Using template $paramod$3cebaa2b1e3336884049aae719aefe5eeb22e095\$lut for cells of type $lut. +Using template $paramod$e2e4d79bec18c28fa313e8bd8f4df6f8a38115b2\$lut for cells of type $lut. +Using template $paramod$cc08dba3aac8677e797984bdf18a09dd37547dd3\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. +Using template $paramod$892f09c166ac66d081a83c58c4c973fa8f6776c4\$lut for cells of type $lut. +Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. +Using template $paramod$fe6b9140fa8badb9aa0c84263397a986020885c5\$lut for cells of type $lut. +Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut for cells of type $lut. +Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. +Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. +Using template $paramod$5a621b016c894274d07edef48c49b401a15fd796\$lut for cells of type $lut. +Using template $paramod$36d45b81a385db1288ea7fa1afc7f85ff749786d\$lut for cells of type $lut. +Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut. +Using template $paramod$dbe700c159e973016afb4c227ed7292dc8875f1d\$lut for cells of type $lut. +Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut. +Using template $paramod$8b09f347504cfc0d3d65fbb4601497936543b1b3\$lut for cells of type $lut. +Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. +Using template $paramod$70584433677bebb1f97d6827c9ba85513c8c682b\$lut for cells of type $lut. +Using template $paramod$1a6ea9151e749fe94446f4fb089a0baf2adde081\$lut for cells of type $lut. +Using template $paramod$ba05b8a1a425003df083aea0e69541f5cbdc68f2\$lut for cells of type $lut. +Using template $paramod$a710625e9e626ef5063a9eaeb20113d01f3592de\$lut for cells of type $lut. +Using template $paramod$63d28255a657ee32018d384f961c9cd429c82580\$lut for cells of type $lut. +Using template $paramod$f44e1eab45e047e709d5dfed32527eb1f7745488\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. +Using template $paramod$437f25da516337c16dc93de12e162d405a8f2fb2\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut. +Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. +Using template $paramod$5ef3e2a003d9029352faafd477743177813cd767\$lut for cells of type $lut. +Using template $paramod$aff3a645bb9f572421a4f0f49cf8987ceb4bcdc5\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. +Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. +Using template $paramod$cd6c4b4da6d8737b72fd2dc8f5d83d8967445809\$lut for cells of type $lut. +Using template $paramod$4685bd76b86e63a7673afc1b48c70bed06b8ddfb\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011100 for cells of type $lut. +Using template $paramod$a4404e742e43b8bf8bde71df8b64cbe0c6ba02bd\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. +Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. +Using template $paramod$fccccf8bb2add7667329c686feec7546eb9a3ae3\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. +Using template $paramod$516e0c30d66d0cb1c81ba299a22eaf236a4b303a\$lut for cells of type $lut. +Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. +Using template $paramod$ee4b98bad07bc0ced6d708127af2144fc9ba3e00\$lut for cells of type $lut. +Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut. +Using template $paramod$bb4fff1cc3b827238aa40993cafede1c5beecbe3\$lut for cells of type $lut. +Using template $paramod$a9b475774a27fd84fed6eecb5f25fc5601b59ec5\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. +Using template $paramod$7d2ffb1127b6d3bcd5c17f2724b343ab1bc3ea11\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut. +Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011100 for cells of type $lut. +Using template $paramod$001d9634602f00137f774620efde4c651c7a59ca\$lut for cells of type $lut. +Using template $paramod$f63fe32f78d5f3c5de711945c592c8c5ec2303ae\$lut for cells of type $lut. +Using template $paramod$126c776b0f5e5eef0fff11eb6abcf95b4d1189d2\$lut for cells of type $lut. +Using template $paramod$0f52647588235a7349ddd3f3432c9ac1e33ad9e1\$lut for cells of type $lut. +Using template $paramod$4e1cecab63d8e9cc19cb0241724b1211fb7856cb\$lut for cells of type $lut. +Using template $paramod$1a73a09a6e092620145558f2f06f2243b658a28f\$lut for cells of type $lut. +Using template $paramod$50666a8f9d622ca1f027a4587dfd5f2a7d8810c9\$lut for cells of type $lut. +Using template $paramod$b4f15f202f50520dbc381cd0880ac94f830f05a8\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. +Using template $paramod$5bb4dad2090b93ea18c2a5cf3364462e38b08d14\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. +Using template $paramod$979794232a1b12010187e90e68ca43f80b43cf7f\$lut for cells of type $lut. +Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f\$lut for cells of type $lut. +Using template $paramod$6961918e3564ac9ead822ba7e0287e436372f86a\$lut for cells of type $lut. +Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut. +Using template $paramod$f54c0ffd7b041ca43eac7710ab19c0666d826c22\$lut for cells of type $lut. +Using template $paramod$6d494330fd261ad16788e47f8e3f9eccfab42476\$lut for cells of type $lut. +Using template $paramod$af763bca85949884aefa417266a961f9c91132de\$lut for cells of type $lut. +Using template $paramod$b4d59a169df3392cc49f75ff3f36786eb368b5e7\$lut for cells of type $lut. +Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut. +Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730\$lut for cells of type $lut. +Using template $paramod$38742bbf7987158b879a68af2ec5225dead39592\$lut for cells of type $lut. +Using template $paramod$d0bf26260eea0e8530fb2e72eb38c60e28a47da8\$lut for cells of type $lut. +Using template $paramod$d53578aacfd93124244778d88be0e90eb09c1b1b\$lut for cells of type $lut. +Using template $paramod$987ba47d9f22b1c8fde8a2d7a2abff4be5df6ab8\$lut for cells of type $lut. +Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut. +Using template $paramod$6d7cc275871d0ceead401cadfae2ff1124665ec4\$lut for cells of type $lut. +Using template $paramod$e3d1f7a5be70c549b567cce08ebf28da10c48aca\$lut for cells of type $lut. +Using template $paramod$a15fd389a2f54cb7b94707b25934d226e68d9e2e\$lut for cells of type $lut. +Using template $paramod$c35ad3063d5038410210ddc72c1fd5fed46413b4\$lut for cells of type $lut. +Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75\$lut for cells of type $lut. +Using template $paramod$12879138d1e376f344e47ea40be66b776233be75\$lut for cells of type $lut. +Using template $paramod$503f1caa2d36bf95454dec35a3ec553941806716\$lut for cells of type $lut. +Using template $paramod$4b23d751b3e1d7cde9cd1766bf20ceee12e38a3d\$lut for cells of type $lut. +Using template $paramod$21258e4f137fd0b5b0eaf41c5b0d170364c0ec37\$lut for cells of type $lut. +Using template $paramod$69f20e0703606f2ffd2ee27cd26f815bd5eeb6e9\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. +Using template $paramod$9a07e85e0c43955880b8d4f336046932e83335ec\$lut for cells of type $lut. +Using template $paramod$bb59fc9d73f3ced261e3a74efef030fd29d37b76\$lut for cells of type $lut. +Using template $paramod$ecf9cac817e9cbb222dc9e58a122faf05f34c860\$lut for cells of type $lut. +Using template $paramod$ad823946862e656cf7f96d606b18b8f972dc6d6c\$lut for cells of type $lut. +Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut. +Using template $paramod$67cf9e9d1d7679c6328496357baf58f31796fe98\$lut for cells of type $lut. +Using template $paramod$f2c2253739da195f4801437496b091d4b39d9051\$lut for cells of type $lut. +Using template $paramod$b297295e19b03521716155b85537bbe86d6a9ae6\$lut for cells of type $lut. +Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut. +Using template $paramod$cd05f04889088c47a0a5abae8c2d644fd314805e\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001111 for cells of type $lut. +Using template $paramod$e08323ae5c39c98bbab150aa28bb73956c0bc47f\$lut for cells of type $lut. +Using template $paramod$054ad6ae20dc6b77853fd02d05a30f66c95c29fb\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut. +Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut. +Using template $paramod$575b200168b9e109c2ed99df4359056f2c6696ac\$lut for cells of type $lut. +Using template $paramod$d4fae2c0d9ad2966369cd4e39b81c71bcd1327c9\$lut for cells of type $lut. +Using template $paramod$85b779ce5ab505dbf25e5e046fb43ca2b76b878b\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut. +Using template $paramod$774861bf9b1885d60265e6ddea1c95a32f095489\$lut for cells of type $lut. +Using template $paramod$16985e1706243a019d93daf9cca618b30aa25f6c\$lut for cells of type $lut. +Using template $paramod$21672ccedebaf14674b9405dc8e596f04707c4db\$lut for cells of type $lut. +Using template $paramod$c6932d0419018208e5384761d78f0ead9bcc772f\$lut for cells of type $lut. +Using template $paramod$16773ebb5e5d8dbce266b8a86bb4af4574d61ffd\$lut for cells of type $lut. +Using template $paramod$27ecdd7cfe22d19cb765e27291229c9275d4bc83\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001011 for cells of type $lut. +Using template $paramod$70ebb6cf5bc7d63c5c1a98ccefefa2af79e8f2a9\$lut for cells of type $lut. +Using template $paramod$baa88887c4630803f83ac99e16ebe1294bd45a7a\$lut for cells of type $lut. +Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101000 for cells of type $lut. +Using template $paramod$868427562418b5dc988caeac6a54689ec9c9025e\$lut for cells of type $lut. +Using template $paramod$09194da5f2c8e08bed8f609fd0e254d8629b24b3\$lut for cells of type $lut. +Using template $paramod$f644023398ad1e2b0531ae68cdf65167cac9a042\$lut for cells of type $lut. +Using template $paramod$c59b53d80ea96d8b5203dc76db438edcc4ac492b\$lut for cells of type $lut. +Using template $paramod$a3cdc1eb771a2c6a16f64da161e11100ac409d2b\$lut for cells of type $lut. +Using template $paramod$376b64e1b363367ba758e2d4a9f90bb42b7b6248\$lut for cells of type $lut. +Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100011 for cells of type $lut. +Using template $paramod$ef26adabe6060e01077b576cfe34e95e55a26aef\$lut for cells of type $lut. +Using template $paramod$affcf0f154430e5f24240efdee5f7d379dca7dd1\$lut for cells of type $lut. +Using template $paramod$4fd7b1305bda889fb7cf3da75b130d5c046d290a\$lut for cells of type $lut. +Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. +Using template $paramod$ca13f43e42317a8affa4fd1d71c27d091bcacc68\$lut for cells of type $lut. +Using template $paramod$1bf62ab10e48d71d6497bccacf5c70420c470fe9\$lut for cells of type $lut. +Using template $paramod$21467c203c389a4feadb8ce2044a20839fad01b3\$lut for cells of type $lut. +Using template $paramod$4b2297966ddb718657b80566604f97685ffc0120\$lut for cells of type $lut. +Using template $paramod$12e9049d8709286a770fe60b59ec4d94c39ce3c9\$lut for cells of type $lut. +Using template $paramod$ad66ff31645a1d4356de5b37218dbb8f3a4598ee\$lut for cells of type $lut. +Using template $paramod$3acbcfda92c30d4c719d6131dda3cd813f60e2b4\$lut for cells of type $lut. +Using template $paramod$53547ba0de08bbaa2219d0f5c1dbf5425d76a290\$lut for cells of type $lut. +Using template $paramod$a20b0c093af372402eecf32644de5f0208303079\$lut for cells of type $lut. +Using template $paramod$43c661319c94b3a52ddfa5a880539d205f6bbd5a\$lut for cells of type $lut. +Using template $paramod$79e7cf60c5406fc1d03111fae9bde1471166818b\$lut for cells of type $lut. +Using template $paramod$7e81a8ad8f27fccecc6e805c0ccf27dd70f2d2c2\$lut for cells of type $lut. +Using template $paramod$63e339ea2883ee008caae375935d0922a0b97d1f\$lut for cells of type $lut. +Using template $paramod$33e5359b2ffed03da55edf41d9bc4006935f2f69\$lut for cells of type $lut. +Using template $paramod$f9d599805186f77d6ad04b255d14441f83286ec8\$lut for cells of type $lut. +Using template $paramod$c299bfea24ff1990a23b453be488cdb6a5d0581c\$lut for cells of type $lut. +Using template $paramod$d9b052694296e7084bef89296751fcdab051f8df\$lut for cells of type $lut. +Using template $paramod$8c5b7259c9d9cd17395950154a06a8b3c48fdd5f\$lut for cells of type $lut. +Using template $paramod$02a202a1a635c330b20598d3bac3a9b6e5608208\$lut for cells of type $lut. +Using template $paramod$7a9d9396461df152f697894fa3b294ad1b285e08\$lut for cells of type $lut. +Using template $paramod$703a13a751e631ef123f38f7d2125aeabec0f94c\$lut for cells of type $lut. +Using template $paramod$680fd8d179aaa2b94b3b7c0dab400ac18bb55c38\$lut for cells of type $lut. +Using template $paramod$68036a40c5a685bb357be70d1f585fbcff135b53\$lut for cells of type $lut. +Using template $paramod$f85118f727cbfc385385a0fcb2d977c74c137bb0\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111000 for cells of type $lut. +Using template $paramod$7d791c2363f4f019348f93a148b2a44b4ba6b5b3\$lut for cells of type $lut. +Using template $paramod$bfc5ec0efb7a7554a714fba569e000275a25c525\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100001 for cells of type $lut. +Using template $paramod$5b13d2ee598c87cdbe912286a35c6fd102e2087c\$lut for cells of type $lut. +Using template $paramod$ad7246a24b6e56b3b67deb6ce92da7632476b727\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. +Using template $paramod$e5e9da8fed769f971686eed8c5eea50e61f73aaa\$lut for cells of type $lut. +Using template $paramod$965f8f2fa1a796a6c51222eabb50fbd26e97d98b\$lut for cells of type $lut. +Using template $paramod$dfe991354c46989496cb28816eb528b52a03f85c\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010110 for cells of type $lut. +Using template $paramod$8c24dc0cdd336b7fb88bbf7eed45cec5cbae862b\$lut for cells of type $lut. +Using template $paramod$0e12ea2d93e07ffd38b30c47251a5243bc5dc262\$lut for cells of type $lut. +Using template $paramod$bff35d97b07dddb273c72678bf847e2b78003681\$lut for cells of type $lut. +Using template $paramod$415b9dd3a15783ae56c103f189fd8e182f997441\$lut for cells of type $lut. +Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec\$lut for cells of type $lut. +Using template $paramod$987d4c6b9265ec278a119d59a96dbc9e6ffc65bc\$lut for cells of type $lut. +Using template $paramod$d184020c951bc948452f5dea6b3f065c16694086\$lut for cells of type $lut. +Using template $paramod$172d96dd42ce7449cb4e1d402244099ce11a0b1c\$lut for cells of type $lut. +Using template $paramod$c24ed72ebb67e9ead6029e42e909ef7fc0abbb11\$lut for cells of type $lut. +Using template $paramod$92d606332f1ee29cf1de0bfa0bc5c21b77f4493e\$lut for cells of type $lut. +Using template $paramod$933f4f3e373a784da64d137def3625bdd36d1695\$lut for cells of type $lut. +Using template $paramod$d94f7d3127937b5dc7a66ea8cc409d7cf91bc488\$lut for cells of type $lut. +Using template $paramod$cd0c2a3d5302372e3760f1a1037771a8cae61f4b\$lut for cells of type $lut. +Using template $paramod$9747e27d592a5de65fe94778f9dc8ad338a6e3d4\$lut for cells of type $lut. +No more expansions possible. + + +6.46. Executing OPT_LUT_INS pass (discard unused LUT inputs). +Optimizing LUTs in Murax. + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17364.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17171.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17181.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17186.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17191.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17188.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17179.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17193.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17189.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17183.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16641.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16636.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17117.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16649.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17132.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17138.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16128.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16127.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16644.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16648.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16647.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16630.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16638.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16635.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16643.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16634.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16123.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16139.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16165.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16181.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16245.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16253.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16309.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16317.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17344.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16371.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16378.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16395.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16393.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16474.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16220.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17169.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16519.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16567.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17174.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16580.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16642.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16567.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16640.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16651.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17108.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16637.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16737.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17184.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16645.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16739.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16735.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16736.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16740.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16738.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16746.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16847.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16421.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16812.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16833.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16832.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16847.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16861.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16871.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16887.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16519.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16639.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17177.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17165.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17017.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17061.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16740.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16736.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16735.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17123.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17069.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17072.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17070.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17069.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16741.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16742.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17098.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17101.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17105.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17105.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17111.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17101.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17117.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17126.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17120.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17135.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17141.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17141.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17129.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17147.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16632.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17175.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17165.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17181.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17189.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17201.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17197.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17194.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17173.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17219.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17200.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17248.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17135.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17144.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17147.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17167.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17180.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17185.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17359.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17385.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17405.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17406.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17594.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) +Removed 0 unused cells and 3274 unused wires. + +6.47. Executing AUTONAME pass. +Renamed 21428 objects in module Murax (46 iterations). + + +6.48. Executing HIERARCHY pass (managing design hierarchy). + +6.48.1. Analyzing design hierarchy.. +Top module: \Murax + +6.48.2. Analyzing design hierarchy.. +Top module: \Murax +Removed 0 unused modules. + +6.49. Printing statistics. + +=== Murax === + + Number of wires: 2397 + Number of wire bits: 13510 + Number of public wires: 2397 + Number of public wire bits: 13510 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 3455 + CCU2C 94 + DP16KD 4 + L6MUX21 27 + LUT4 1722 + PFUMX 209 + TRELLIS_DPR16X4 36 + TRELLIS_FF 1363 + +6.50. Executing CHECK pass (checking for obvious problems). +Checking module Murax... +Found and reported 0 problems. + +6.51. Executing JSON backend. + +Warnings: 65 unique messages, 65 total +End of script. Logfile hash: 18aae72bca, CPU: user 6.26s system 0.08s, MEM: 330.91 MB peak +Yosys 0.13+28 (git sha1 fc40df091, gcc 11.2.0-7ubuntu2 -fPIC -Os) +Time spent: 17% 42x opt_clean (1 sec), 16% 51x opt_expr (1 sec), ... diff --git a/VexRiscv/fpga/gen/synth.v b/VexRiscv/fpga/gen/synth.v new file mode 100644 index 0000000..3be526a --- /dev/null +++ b/VexRiscv/fpga/gen/synth.v @@ -0,0 +1,14036 @@ +/* Generated by Yosys 0.13+28 (git sha1 fc40df091, gcc 11.2.0-7ubuntu2 -fPIC -Os) */ + +module Apb3Decoder(io_input_PADDR, io_input_PSEL, io_input_PENABLE, io_input_PREADY, io_input_PWRITE, io_input_PWDATA, io_input_PRDATA, io_input_PSLVERROR, io_output_PADDR, io_output_PSEL, io_output_PENABLE, io_output_PREADY, io_output_PWRITE, io_output_PWDATA, io_output_PRDATA, io_output_PSLVERROR); + wire _00_; + wire _01_; + wire _02_; + wire _03_; + input [19:0] io_input_PADDR; + wire [19:0] io_input_PADDR; + input io_input_PENABLE; + wire io_input_PENABLE; + output [31:0] io_input_PRDATA; + wire [31:0] io_input_PRDATA; + output io_input_PREADY; + wire io_input_PREADY; + input io_input_PSEL; + wire io_input_PSEL; + output io_input_PSLVERROR; + wire io_input_PSLVERROR; + input [31:0] io_input_PWDATA; + wire [31:0] io_input_PWDATA; + input io_input_PWRITE; + wire io_input_PWRITE; + output [19:0] io_output_PADDR; + wire [19:0] io_output_PADDR; + output io_output_PENABLE; + wire io_output_PENABLE; + input [31:0] io_output_PRDATA; + wire [31:0] io_output_PRDATA; + input io_output_PREADY; + wire io_output_PREADY; + output [2:0] io_output_PSEL; + wire [2:0] io_output_PSEL; + input io_output_PSLVERROR; + wire io_output_PSLVERROR; + output [31:0] io_output_PWDATA; + wire [31:0] io_output_PWDATA; + output io_output_PWRITE; + wire io_output_PWRITE; + wire when_Apb3Decoder_l88; + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd8), + .Y_WIDTH(32'd1) + ) _04_ ( + .A(io_input_PADDR[19:12]), + .Y(_00_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd8), + .B_SIGNED(32'd0), + .B_WIDTH(32'd8), + .Y_WIDTH(32'd1) + ) _05_ ( + .A(io_input_PADDR[19:12]), + .B(8'h10), + .Y(_01_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd8), + .B_SIGNED(32'd0), + .B_WIDTH(32'd8), + .Y_WIDTH(32'd1) + ) _06_ ( + .A(io_input_PADDR[19:12]), + .B(8'h20), + .Y(_02_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _07_ ( + .A(io_output_PSEL), + .Y(_03_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _08_ ( + .A(_00_), + .B(io_input_PSEL), + .Y(io_output_PSEL[0]) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _09_ ( + .A(_01_), + .B(io_input_PSEL), + .Y(io_output_PSEL[1]) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _10_ ( + .A(_02_), + .B(io_input_PSEL), + .Y(io_output_PSEL[2]) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _11_ ( + .A(io_input_PSEL), + .B(_03_), + .Y(when_Apb3Decoder_l88) + ); + \$mux #( + .WIDTH(32'd1) + ) _12_ ( + .A(io_output_PSLVERROR), + .B(1'h1), + .S(when_Apb3Decoder_l88), + .Y(io_input_PSLVERROR) + ); + \$mux #( + .WIDTH(32'd1) + ) _13_ ( + .A(io_output_PREADY), + .B(1'h1), + .S(when_Apb3Decoder_l88), + .Y(io_input_PREADY) + ); + assign io_input_PRDATA = io_output_PRDATA; + assign io_output_PADDR = io_input_PADDR; + assign io_output_PENABLE = io_input_PENABLE; + assign io_output_PWDATA = io_input_PWDATA; + assign io_output_PWRITE = io_input_PWRITE; +endmodule + +module Apb3Gpio(io_apb_PADDR, io_apb_PSEL, io_apb_PENABLE, io_apb_PREADY, io_apb_PWRITE, io_apb_PWDATA, io_apb_PRDATA, io_apb_PSLVERROR, io_gpio_read, io_gpio_write, io_gpio_writeEnable, io_value, io_mainClk, resetCtrl_systemReset); + wire _00_; + wire _01_; + wire _02_; + wire _03_; + wire _04_; + wire _05_; + wire ctrl_doWrite; + input [3:0] io_apb_PADDR; + wire [3:0] io_apb_PADDR; + input io_apb_PENABLE; + wire io_apb_PENABLE; + output [31:0] io_apb_PRDATA; + wire [31:0] io_apb_PRDATA; + output io_apb_PREADY; + wire io_apb_PREADY; + input io_apb_PSEL; + wire io_apb_PSEL; + output io_apb_PSLVERROR; + wire io_apb_PSLVERROR; + input [31:0] io_apb_PWDATA; + wire [31:0] io_apb_PWDATA; + input io_apb_PWRITE; + wire io_apb_PWRITE; + input [31:0] io_gpio_read; + wire [31:0] io_gpio_read; + wire [31:0] io_gpio_read_buffercc_io_dataOut; + output [31:0] io_gpio_write; + wire [31:0] io_gpio_write; + output [31:0] io_gpio_writeEnable; + wire [31:0] io_gpio_writeEnable; + wire [31:0] io_gpio_writeEnable_driver; + wire [31:0] io_gpio_write_driver; + input io_mainClk; + wire io_mainClk; + output [31:0] io_value; + wire [31:0] io_value; + input resetCtrl_systemReset; + wire resetCtrl_systemReset; + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(32'd0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd32) + ) _06_ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(io_apb_PWDATA), + .EN(_00_), + .Q(io_gpio_writeEnable_driver) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd32) + ) _07_ ( + .CLK(io_mainClk), + .D(io_apb_PWDATA), + .EN(_01_), + .Q(io_gpio_write_driver) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _08_ ( + .A({ _04_, ctrl_doWrite }), + .Y(_00_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _09_ ( + .A({ _03_, ctrl_doWrite }), + .Y(_01_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _10_ ( + .A(io_apb_PSEL), + .B(io_apb_PENABLE), + .Y(_02_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _11_ ( + .A(_02_), + .B(io_apb_PWRITE), + .Y(ctrl_doWrite) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd4), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _12_ ( + .A(io_apb_PADDR), + .B(3'h4), + .Y(_03_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd4), + .B_SIGNED(32'd0), + .B_WIDTH(32'd4), + .Y_WIDTH(32'd1) + ) _13_ ( + .A(io_apb_PADDR), + .B(4'h8), + .Y(_04_) + ); + \$pmux #( + .S_WIDTH(32'd3), + .WIDTH(32'd32) + ) _14_ ( + .A(32'd0), + .B({ io_gpio_read_buffercc_io_dataOut, io_gpio_write_driver, io_gpio_writeEnable_driver }), + .S({ _05_, _03_, _04_ }), + .Y(io_apb_PRDATA) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd4), + .Y_WIDTH(32'd1) + ) _15_ ( + .A(io_apb_PADDR), + .Y(_05_) + ); + BufferCC_2 io_gpio_read_buffercc ( + .io_dataIn(io_gpio_read), + .io_dataOut(io_gpio_read_buffercc_io_dataOut), + .io_mainClk(io_mainClk), + .resetCtrl_systemReset(resetCtrl_systemReset) + ); + assign io_apb_PREADY = 1'h1; + assign io_apb_PSLVERROR = 1'h0; + assign io_gpio_write = io_gpio_write_driver; + assign io_gpio_writeEnable = io_gpio_writeEnable_driver; + assign io_value = io_gpio_read_buffercc_io_dataOut; +endmodule + +module Apb3Router(io_input_PADDR, io_input_PSEL, io_input_PENABLE, io_input_PREADY, io_input_PWRITE, io_input_PWDATA, io_input_PRDATA, io_input_PSLVERROR, io_outputs_0_PADDR, io_outputs_0_PSEL, io_outputs_0_PENABLE, io_outputs_0_PREADY, io_outputs_0_PWRITE, io_outputs_0_PWDATA, io_outputs_0_PRDATA, io_outputs_0_PSLVERROR, io_outputs_1_PADDR, io_outputs_1_PSEL, io_outputs_1_PENABLE, io_outputs_1_PREADY, io_outputs_1_PWRITE +, io_outputs_1_PWDATA, io_outputs_1_PRDATA, io_outputs_1_PSLVERROR, io_outputs_2_PADDR, io_outputs_2_PSEL, io_outputs_2_PENABLE, io_outputs_2_PREADY, io_outputs_2_PWRITE, io_outputs_2_PWDATA, io_outputs_2_PRDATA, io_outputs_2_PSLVERROR, io_mainClk, resetCtrl_systemReset); + wire _0_; + wire _1_; + wire [31:0] _zz_io_input_PRDATA; + wire _zz_io_input_PREADY; + wire _zz_io_input_PSLVERROR; + wire _zz_selIndex; + wire _zz_selIndex_1; + input [19:0] io_input_PADDR; + wire [19:0] io_input_PADDR; + input io_input_PENABLE; + wire io_input_PENABLE; + output [31:0] io_input_PRDATA; + wire [31:0] io_input_PRDATA; + output io_input_PREADY; + wire io_input_PREADY; + input [2:0] io_input_PSEL; + wire [2:0] io_input_PSEL; + output io_input_PSLVERROR; + wire io_input_PSLVERROR; + input [31:0] io_input_PWDATA; + wire [31:0] io_input_PWDATA; + input io_input_PWRITE; + wire io_input_PWRITE; + input io_mainClk; + wire io_mainClk; + output [19:0] io_outputs_0_PADDR; + wire [19:0] io_outputs_0_PADDR; + output io_outputs_0_PENABLE; + wire io_outputs_0_PENABLE; + input [31:0] io_outputs_0_PRDATA; + wire [31:0] io_outputs_0_PRDATA; + input io_outputs_0_PREADY; + wire io_outputs_0_PREADY; + output io_outputs_0_PSEL; + wire io_outputs_0_PSEL; + input io_outputs_0_PSLVERROR; + wire io_outputs_0_PSLVERROR; + output [31:0] io_outputs_0_PWDATA; + wire [31:0] io_outputs_0_PWDATA; + output io_outputs_0_PWRITE; + wire io_outputs_0_PWRITE; + output [19:0] io_outputs_1_PADDR; + wire [19:0] io_outputs_1_PADDR; + output io_outputs_1_PENABLE; + wire io_outputs_1_PENABLE; + input [31:0] io_outputs_1_PRDATA; + wire [31:0] io_outputs_1_PRDATA; + input io_outputs_1_PREADY; + wire io_outputs_1_PREADY; + output io_outputs_1_PSEL; + wire io_outputs_1_PSEL; + input io_outputs_1_PSLVERROR; + wire io_outputs_1_PSLVERROR; + output [31:0] io_outputs_1_PWDATA; + wire [31:0] io_outputs_1_PWDATA; + output io_outputs_1_PWRITE; + wire io_outputs_1_PWRITE; + output [19:0] io_outputs_2_PADDR; + wire [19:0] io_outputs_2_PADDR; + output io_outputs_2_PENABLE; + wire io_outputs_2_PENABLE; + input [31:0] io_outputs_2_PRDATA; + wire [31:0] io_outputs_2_PRDATA; + input io_outputs_2_PREADY; + wire io_outputs_2_PREADY; + output io_outputs_2_PSEL; + wire io_outputs_2_PSEL; + input io_outputs_2_PSLVERROR; + wire io_outputs_2_PSLVERROR; + output [31:0] io_outputs_2_PWDATA; + wire [31:0] io_outputs_2_PWDATA; + output io_outputs_2_PWRITE; + wire io_outputs_2_PWRITE; + input resetCtrl_systemReset; + wire resetCtrl_systemReset; + wire [1:0] selIndex; + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd2) + ) _2_ ( + .CLK(io_mainClk), + .D(io_input_PSEL[2:1]), + .Q(selIndex) + ); + \$pmux #( + .S_WIDTH(32'd2), + .WIDTH(32'd1) + ) _3_ ( + .A(io_outputs_2_PSLVERROR), + .B({ io_outputs_0_PSLVERROR, io_outputs_1_PSLVERROR }), + .S({ _1_, _0_ }), + .Y(io_input_PSLVERROR) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _4_ ( + .A(selIndex), + .B(1'h1), + .Y(_0_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _5_ ( + .A(selIndex), + .Y(_1_) + ); + \$pmux #( + .S_WIDTH(32'd2), + .WIDTH(32'd32) + ) _6_ ( + .A(io_outputs_2_PRDATA), + .B({ io_outputs_0_PRDATA, io_outputs_1_PRDATA }), + .S({ _1_, _0_ }), + .Y(io_input_PRDATA) + ); + \$pmux #( + .S_WIDTH(32'd2), + .WIDTH(32'd1) + ) _7_ ( + .A(io_outputs_2_PREADY), + .B({ io_outputs_0_PREADY, io_outputs_1_PREADY }), + .S({ _1_, _0_ }), + .Y(io_input_PREADY) + ); + assign _zz_io_input_PRDATA = io_input_PRDATA; + assign _zz_io_input_PREADY = io_input_PREADY; + assign _zz_io_input_PSLVERROR = io_input_PSLVERROR; + assign _zz_selIndex = io_input_PSEL[1]; + assign _zz_selIndex_1 = io_input_PSEL[2]; + assign io_outputs_0_PADDR = io_input_PADDR; + assign io_outputs_0_PENABLE = io_input_PENABLE; + assign io_outputs_0_PSEL = io_input_PSEL[0]; + assign io_outputs_0_PWDATA = io_input_PWDATA; + assign io_outputs_0_PWRITE = io_input_PWRITE; + assign io_outputs_1_PADDR = io_input_PADDR; + assign io_outputs_1_PENABLE = io_input_PENABLE; + assign io_outputs_1_PSEL = io_input_PSEL[1]; + assign io_outputs_1_PWDATA = io_input_PWDATA; + assign io_outputs_1_PWRITE = io_input_PWRITE; + assign io_outputs_2_PADDR = io_input_PADDR; + assign io_outputs_2_PENABLE = io_input_PENABLE; + assign io_outputs_2_PSEL = io_input_PSEL[2]; + assign io_outputs_2_PWDATA = io_input_PWDATA; + assign io_outputs_2_PWRITE = io_input_PWRITE; +endmodule + +module Apb3UartCtrl(io_apb_PADDR, io_apb_PSEL, io_apb_PENABLE, io_apb_PREADY, io_apb_PWRITE, io_apb_PWDATA, io_apb_PRDATA, io_uart_txd, io_uart_rxd, io_interrupt, io_mainClk, resetCtrl_systemReset); + wire _00_; + wire _01_; + wire _02_; + wire _03_; + wire _04_; + wire _05_; + wire [4:0] _06_; + wire [4:0] _07_; + wire _08_; + wire _09_; + wire _10_; + wire _11_; + wire _12_; + wire _13_; + wire _14_; + wire _15_; + wire _16_; + wire _17_; + wire _18_; + wire _19_; + wire _20_; + wire _21_; + wire _22_; + wire _23_; + wire _24_; + wire _25_; + wire _26_; + wire _27_; + wire [19:0] _zz_1; + wire _zz_bridge_misc_breakDetected; + wire _zz_bridge_misc_doBreak; + wire _zz_bridge_misc_doBreak_1; + wire _zz_bridge_misc_readError; + wire _zz_bridge_misc_readOverflowError; + wire _zz_bridge_write_streamUnbuffered_valid; + wire [4:0] _zz_io_apb_PRDATA; + wire bridge_interruptCtrl_interrupt; + wire bridge_interruptCtrl_readInt; + wire bridge_interruptCtrl_readIntEnable; + wire bridge_interruptCtrl_writeInt; + wire bridge_interruptCtrl_writeIntEnable; + wire bridge_misc_breakDetected; + wire bridge_misc_doBreak; + wire bridge_misc_readError; + wire bridge_misc_readOverflowError; + wire [7:0] bridge_read_streamBreaked_payload; + wire bridge_read_streamBreaked_ready; + wire bridge_read_streamBreaked_valid; + wire [19:0] bridge_uartConfigReg_clockDivider; + wire [2:0] bridge_uartConfigReg_frame_dataLength; + wire [1:0] bridge_uartConfigReg_frame_parity; + wire bridge_uartConfigReg_frame_stop; + wire [7:0] bridge_write_streamUnbuffered_payload; + wire [4:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_availability; + wire [4:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + wire bridge_write_streamUnbuffered_ready; + wire bridge_write_streamUnbuffered_valid; + wire busCtrl_doRead; + wire busCtrl_doWrite; + input [4:0] io_apb_PADDR; + wire [4:0] io_apb_PADDR; + input io_apb_PENABLE; + wire io_apb_PENABLE; + output [31:0] io_apb_PRDATA; + wire [31:0] io_apb_PRDATA; + output io_apb_PREADY; + wire io_apb_PREADY; + input io_apb_PSEL; + wire io_apb_PSEL; + input [31:0] io_apb_PWDATA; + wire [31:0] io_apb_PWDATA; + input io_apb_PWRITE; + wire io_apb_PWRITE; + output io_interrupt; + wire io_interrupt; + input io_mainClk; + wire io_mainClk; + input io_uart_rxd; + wire io_uart_rxd; + output io_uart_txd; + wire io_uart_txd; + input resetCtrl_systemReset; + wire resetCtrl_systemReset; + wire uartCtrl_1_io_readBreak; + wire uartCtrl_1_io_readBreak_regNext; + wire uartCtrl_1_io_readError; + wire uartCtrl_1_io_read_isStall; + wire [7:0] uartCtrl_1_io_read_payload; + wire [4:0] uartCtrl_1_io_read_queueWithOccupancy_io_availability; + wire [4:0] uartCtrl_1_io_read_queueWithOccupancy_io_occupancy; + wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload; + wire uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready; + wire uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid; + wire uartCtrl_1_io_read_queueWithOccupancy_io_push_ready; + wire uartCtrl_1_io_read_valid; + wire uartCtrl_1_io_uart_txd; + wire uartCtrl_1_io_write_ready; + wire when_BusSlaveFactory_l335; + wire when_BusSlaveFactory_l335_1; + wire when_BusSlaveFactory_l335_2; + wire when_BusSlaveFactory_l335_3; + wire when_BusSlaveFactory_l337; + wire when_BusSlaveFactory_l337_1; + wire when_BusSlaveFactory_l337_2; + wire when_BusSlaveFactory_l337_3; + wire when_BusSlaveFactory_l366; + wire when_BusSlaveFactory_l368; + wire when_UartCtrl_l155; + \$alu #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .B_SIGNED(32'd0), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd5) + ) _28_ ( + .A(5'h10), + .B(bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy), + .BI(1'h1), + .CI(1'h1), + .CO(_07_), + .X(_06_), + .Y(_zz_io_apb_PRDATA) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) bridge_misc_readOverflowError_reg /* _29_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_03_), + .EN(_12_), + .Q(bridge_misc_readOverflowError) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) bridge_misc_readError_reg /* _30_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_02_), + .EN(_13_), + .Q(bridge_misc_readError) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) bridge_interruptCtrl_readIntEnable_reg /* _31_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(io_apb_PWDATA[1]), + .EN(_14_), + .Q(bridge_interruptCtrl_readIntEnable) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) bridge_interruptCtrl_writeIntEnable_reg /* _32_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(io_apb_PWDATA[0]), + .EN(_14_), + .Q(bridge_interruptCtrl_writeIntEnable) + ); + \$ne #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _33_ ( + .A({ uartCtrl_1_io_read_isStall, when_BusSlaveFactory_l335, io_apb_PWDATA[1] }), + .B(2'h2), + .Y(_08_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _34_ ( + .A({ uartCtrl_1_io_read_isStall, when_BusSlaveFactory_l335 }), + .Y(_09_) + ); + \$ne #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _35_ ( + .A({ when_BusSlaveFactory_l335, uartCtrl_1_io_readError, io_apb_PWDATA[0] }), + .B(3'h4), + .Y(_10_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _36_ ( + .A({ when_BusSlaveFactory_l335, uartCtrl_1_io_readError }), + .Y(_11_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _37_ ( + .A({ _08_, _09_ }), + .Y(_12_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _38_ ( + .A({ _11_, _10_ }), + .Y(_13_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _39_ ( + .A({ _25_, busCtrl_doWrite }), + .Y(_14_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _40_ ( + .A(io_apb_PSEL), + .B(io_apb_PENABLE), + .Y(_15_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _41_ ( + .A(_15_), + .B(io_apb_PWRITE), + .Y(busCtrl_doWrite) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _42_ ( + .A(_15_), + .B(_16_), + .Y(busCtrl_doRead) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _43_ ( + .A(bridge_interruptCtrl_readIntEnable), + .B(bridge_read_streamBreaked_valid), + .Y(bridge_interruptCtrl_readInt) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _44_ ( + .A(bridge_interruptCtrl_writeIntEnable), + .B(_17_), + .Y(bridge_interruptCtrl_writeInt) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _45_ ( + .A(uartCtrl_1_io_read_valid), + .B(_18_), + .Y(uartCtrl_1_io_read_isStall) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _46_ ( + .A(uartCtrl_1_io_readBreak), + .B(_19_), + .Y(when_UartCtrl_l155) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _47_ ( + .A(io_apb_PWRITE), + .Y(_16_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _48_ ( + .A(bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid), + .Y(_17_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _49_ ( + .A(uartCtrl_1_io_read_queueWithOccupancy_io_push_ready), + .Y(_18_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _50_ ( + .A(uartCtrl_1_io_readBreak_regNext), + .Y(_19_) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _51_ ( + .A(bridge_interruptCtrl_readInt), + .B(bridge_interruptCtrl_writeInt), + .Y(io_interrupt) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) uartCtrl_1_io_readBreak_regNext_reg /* _52_ */ ( + .CLK(io_mainClk), + .D(uartCtrl_1_io_readBreak), + .Q(uartCtrl_1_io_readBreak_regNext) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) bridge_misc_breakDetected_reg /* _53_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_00_), + .Q(bridge_misc_breakDetected) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) bridge_misc_doBreak_reg /* _54_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_01_), + .Q(bridge_misc_doBreak) + ); + \$mux #( + .WIDTH(32'd1) + ) _55_ ( + .A(bridge_misc_doBreak), + .B(1'h1), + .S(io_apb_PWDATA[10]), + .Y(_20_) + ); + \$mux #( + .WIDTH(32'd1) + ) _56_ ( + .A(bridge_misc_doBreak), + .B(_20_), + .S(when_BusSlaveFactory_l335), + .Y(_21_) + ); + \$mux #( + .WIDTH(32'd1) + ) _57_ ( + .A(_21_), + .B(1'h0), + .S(io_apb_PWDATA[11]), + .Y(_22_) + ); + \$mux #( + .WIDTH(32'd1) + ) _58_ ( + .A(_21_), + .B(_22_), + .S(when_BusSlaveFactory_l335), + .Y(_01_) + ); + \$mux #( + .WIDTH(32'd1) + ) _59_ ( + .A(bridge_misc_breakDetected), + .B(1'h1), + .S(when_UartCtrl_l155), + .Y(_23_) + ); + \$mux #( + .WIDTH(32'd1) + ) _60_ ( + .A(_23_), + .B(1'h0), + .S(io_apb_PWDATA[9]), + .Y(_24_) + ); + \$mux #( + .WIDTH(32'd1) + ) _61_ ( + .A(_23_), + .B(_24_), + .S(when_BusSlaveFactory_l335), + .Y(_00_) + ); + \$mux #( + .WIDTH(32'd1) + ) _62_ ( + .A(1'h0), + .B(1'h1), + .S(uartCtrl_1_io_read_isStall), + .Y(_03_) + ); + \$mux #( + .WIDTH(32'd1) + ) _63_ ( + .A(1'h0), + .B(1'h1), + .S(uartCtrl_1_io_readError), + .Y(_02_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _64_ ( + .A(io_apb_PADDR), + .B(3'h4), + .Y(_25_) + ); + \$mux #( + .WIDTH(32'd1) + ) _65_ ( + .A(1'h0), + .B(1'h1), + .S(busCtrl_doWrite), + .Y(_04_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .B_SIGNED(32'd0), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd1) + ) _66_ ( + .A(io_apb_PADDR), + .B(5'h10), + .Y(_26_) + ); + \$mux #( + .WIDTH(32'd1) + ) _67_ ( + .A(1'h0), + .B(_04_), + .S(_26_), + .Y(when_BusSlaveFactory_l335) + ); + \$mux #( + .WIDTH(32'd1) + ) _68_ ( + .A(1'h0), + .B(1'h1), + .S(busCtrl_doRead), + .Y(_05_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .Y_WIDTH(32'd1) + ) _69_ ( + .A(io_apb_PADDR), + .Y(_27_) + ); + \$mux #( + .WIDTH(32'd1) + ) _70_ ( + .A(1'h0), + .B(_05_), + .S(_27_), + .Y(bridge_read_streamBreaked_ready) + ); + \$mux #( + .WIDTH(32'd1) + ) _71_ ( + .A(bridge_read_streamBreaked_ready), + .B(1'h1), + .S(uartCtrl_1_io_readBreak), + .Y(uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready) + ); + \$mux #( + .WIDTH(32'd1) + ) _72_ ( + .A(uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid), + .B(1'h0), + .S(uartCtrl_1_io_readBreak), + .Y(bridge_read_streamBreaked_valid) + ); + \$mux #( + .WIDTH(32'd1) + ) _73_ ( + .A(1'h0), + .B(_04_), + .S(_27_), + .Y(bridge_write_streamUnbuffered_valid) + ); + \$mux #( + .WIDTH(32'd4) + ) _74_ ( + .A(4'h0), + .B(_zz_io_apb_PRDATA[4:1]), + .S(_25_), + .Y(io_apb_PRDATA[20:17]) + ); + \$mux #( + .WIDTH(32'd6) + ) _75_ ( + .A(6'h00), + .B(uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload[7:2]), + .S(_27_), + .Y(io_apb_PRDATA[7:2]) + ); + \$pmux #( + .S_WIDTH(32'd2), + .WIDTH(32'd1) + ) _76_ ( + .A(1'h0), + .B({ bridge_read_streamBreaked_valid, _zz_io_apb_PRDATA[0] }), + .S({ _27_, _25_ }), + .Y(io_apb_PRDATA[16]) + ); + \$pmux #( + .S_WIDTH(32'd2), + .WIDTH(32'd1) + ) _77_ ( + .A(1'h0), + .B({ bridge_interruptCtrl_writeInt, uartCtrl_1_io_readBreak }), + .S({ _25_, _26_ }), + .Y(io_apb_PRDATA[8]) + ); + \$mux #( + .WIDTH(32'd1) + ) _78_ ( + .A(1'h0), + .B(bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid), + .S(_25_), + .Y(io_apb_PRDATA[15]) + ); + \$pmux #( + .S_WIDTH(32'd3), + .WIDTH(32'd1) + ) _79_ ( + .A(1'h0), + .B({ uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload[1], bridge_interruptCtrl_readIntEnable, bridge_misc_readOverflowError }), + .S({ _27_, _25_, _26_ }), + .Y(io_apb_PRDATA[1]) + ); + \$mux #( + .WIDTH(32'd5) + ) _80_ ( + .A(5'h00), + .B(uartCtrl_1_io_read_queueWithOccupancy_io_occupancy), + .S(_25_), + .Y(io_apb_PRDATA[28:24]) + ); + \$pmux #( + .S_WIDTH(32'd2), + .WIDTH(32'd1) + ) _81_ ( + .A(1'h0), + .B({ bridge_interruptCtrl_readInt, bridge_misc_breakDetected }), + .S({ _25_, _26_ }), + .Y(io_apb_PRDATA[9]) + ); + \$pmux #( + .S_WIDTH(32'd3), + .WIDTH(32'd1) + ) _82_ ( + .A(1'h0), + .B({ uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload[0], bridge_interruptCtrl_writeIntEnable, bridge_misc_readError }), + .S({ _27_, _25_, _26_ }), + .Y(io_apb_PRDATA[0]) + ); + StreamFifo bridge_write_streamUnbuffered_queueWithOccupancy ( + .io_availability(bridge_write_streamUnbuffered_queueWithOccupancy_io_availability), + .io_flush(1'h0), + .io_mainClk(io_mainClk), + .io_occupancy(bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy), + .io_pop_payload(bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload), + .io_pop_ready(uartCtrl_1_io_write_ready), + .io_pop_valid(bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid), + .io_push_payload(io_apb_PWDATA[7:0]), + .io_push_ready(bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready), + .io_push_valid(bridge_write_streamUnbuffered_valid), + .resetCtrl_systemReset(resetCtrl_systemReset) + ); + UartCtrl uartCtrl_1 ( + .io_config_clockDivider(20'h00013), + .io_config_frame_dataLength(3'h7), + .io_config_frame_parity(2'h0), + .io_config_frame_stop(1'h0), + .io_mainClk(io_mainClk), + .io_readBreak(uartCtrl_1_io_readBreak), + .io_readError(uartCtrl_1_io_readError), + .io_read_payload(uartCtrl_1_io_read_payload), + .io_read_ready(uartCtrl_1_io_read_queueWithOccupancy_io_push_ready), + .io_read_valid(uartCtrl_1_io_read_valid), + .io_uart_rxd(io_uart_rxd), + .io_uart_txd(uartCtrl_1_io_uart_txd), + .io_writeBreak(bridge_misc_doBreak), + .io_write_payload(bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload), + .io_write_ready(uartCtrl_1_io_write_ready), + .io_write_valid(bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid), + .resetCtrl_systemReset(resetCtrl_systemReset) + ); + StreamFifo uartCtrl_1_io_read_queueWithOccupancy ( + .io_availability(uartCtrl_1_io_read_queueWithOccupancy_io_availability), + .io_flush(1'h0), + .io_mainClk(io_mainClk), + .io_occupancy(uartCtrl_1_io_read_queueWithOccupancy_io_occupancy), + .io_pop_payload(uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload), + .io_pop_ready(uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready), + .io_pop_valid(uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid), + .io_push_payload(uartCtrl_1_io_read_payload), + .io_push_ready(uartCtrl_1_io_read_queueWithOccupancy_io_push_ready), + .io_push_valid(uartCtrl_1_io_read_valid), + .resetCtrl_systemReset(resetCtrl_systemReset) + ); + assign _zz_1 = 20'h00013; + assign _zz_bridge_misc_breakDetected = 1'h0; + assign _zz_bridge_misc_doBreak = 1'h1; + assign _zz_bridge_misc_doBreak_1 = 1'h0; + assign _zz_bridge_misc_readError = 1'h0; + assign _zz_bridge_misc_readOverflowError = 1'h0; + assign _zz_bridge_write_streamUnbuffered_valid = bridge_write_streamUnbuffered_valid; + assign bridge_interruptCtrl_interrupt = io_interrupt; + assign bridge_read_streamBreaked_payload = uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload; + assign bridge_uartConfigReg_clockDivider = 20'h00013; + assign bridge_uartConfigReg_frame_dataLength = 3'h7; + assign bridge_uartConfigReg_frame_parity = 2'h0; + assign bridge_uartConfigReg_frame_stop = 1'h0; + assign bridge_write_streamUnbuffered_payload = io_apb_PWDATA[7:0]; + assign bridge_write_streamUnbuffered_ready = bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + assign { io_apb_PRDATA[31:29], io_apb_PRDATA[23:21], io_apb_PRDATA[14:10] } = 11'h000; + assign io_apb_PREADY = 1'h1; + assign io_uart_txd = uartCtrl_1_io_uart_txd; + assign when_BusSlaveFactory_l335_1 = when_BusSlaveFactory_l335; + assign when_BusSlaveFactory_l335_2 = when_BusSlaveFactory_l335; + assign when_BusSlaveFactory_l335_3 = when_BusSlaveFactory_l335; + assign when_BusSlaveFactory_l337 = io_apb_PWDATA[0]; + assign when_BusSlaveFactory_l337_1 = io_apb_PWDATA[1]; + assign when_BusSlaveFactory_l337_2 = io_apb_PWDATA[9]; + assign when_BusSlaveFactory_l337_3 = io_apb_PWDATA[11]; + assign when_BusSlaveFactory_l366 = when_BusSlaveFactory_l335; + assign when_BusSlaveFactory_l368 = io_apb_PWDATA[10]; +endmodule + +module BufferCC(io_dataIn, io_dataOut, io_mainClk, resetCtrl_systemReset); + wire buffers_0; + wire buffers_1; + input io_dataIn; + wire io_dataIn; + output io_dataOut; + wire io_dataOut; + input io_mainClk; + wire io_mainClk; + input resetCtrl_systemReset; + wire resetCtrl_systemReset; + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) buffers_0_reg /* _0_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(io_dataIn), + .Q(buffers_0) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) buffers_1_reg /* _1_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(buffers_0), + .Q(buffers_1) + ); + assign io_dataOut = buffers_1; +endmodule + +module BufferCC_1(io_dataIn, io_dataOut, io_mainClk, resetCtrl_mainClkReset); + wire buffers_0; + wire buffers_1; + input io_dataIn; + wire io_dataIn; + output io_dataOut; + wire io_dataOut; + input io_mainClk; + wire io_mainClk; + input resetCtrl_mainClkReset; + wire resetCtrl_mainClkReset; + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) buffers_0_reg /* _0_ */ ( + .CLK(io_mainClk), + .D(io_dataIn), + .Q(buffers_0) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) buffers_1_reg /* _1_ */ ( + .CLK(io_mainClk), + .D(buffers_0), + .Q(buffers_1) + ); + assign io_dataOut = buffers_1; +endmodule + +module BufferCC_2(io_dataIn, io_dataOut, io_mainClk, resetCtrl_systemReset); + wire [31:0] buffers_0; + wire [31:0] buffers_1; + input [31:0] io_dataIn; + wire [31:0] io_dataIn; + output [31:0] io_dataOut; + wire [31:0] io_dataOut; + input io_mainClk; + wire io_mainClk; + input resetCtrl_systemReset; + wire resetCtrl_systemReset; + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd32) + ) _0_ ( + .CLK(io_mainClk), + .D(io_dataIn), + .Q(buffers_0) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd32) + ) _1_ ( + .CLK(io_mainClk), + .D(buffers_0), + .Q(buffers_1) + ); + assign io_dataOut = buffers_1; +endmodule + +module BufferCC_3(io_dataIn, io_dataOut, io_mainClk); + wire buffers_0; + wire buffers_1; + input io_dataIn; + wire io_dataIn; + output io_dataOut; + wire io_dataOut; + input io_mainClk; + wire io_mainClk; + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) buffers_0_reg /* _0_ */ ( + .CLK(io_mainClk), + .D(io_dataIn), + .Q(buffers_0) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) buffers_1_reg /* _1_ */ ( + .CLK(io_mainClk), + .D(buffers_0), + .Q(buffers_1) + ); + assign io_dataOut = buffers_1; +endmodule + +module FlowCCByToggle(io_input_valid, io_input_payload_last, io_input_payload_fragment, io_output_valid, io_output_payload_last, io_output_payload_fragment, io_jtag_tck, io_mainClk, resetCtrl_mainClkReset); + wire _0_; + wire inputArea_data_fragment; + wire inputArea_data_last; + wire inputArea_target; + wire inputArea_target_buffercc_io_dataOut; + input io_input_payload_fragment; + wire io_input_payload_fragment; + input io_input_payload_last; + wire io_input_payload_last; + input io_input_valid; + wire io_input_valid; + input io_jtag_tck; + wire io_jtag_tck; + input io_mainClk; + wire io_mainClk; + output io_output_payload_fragment; + wire io_output_payload_fragment; + output io_output_payload_last; + wire io_output_payload_last; + output io_output_valid; + wire io_output_valid; + wire outputArea_flow_m2sPipe_payload_fragment; + wire outputArea_flow_m2sPipe_payload_last; + wire outputArea_flow_m2sPipe_valid; + wire outputArea_flow_payload_fragment; + wire outputArea_flow_payload_last; + wire outputArea_flow_valid; + wire outputArea_hit; + wire outputArea_target; + input resetCtrl_mainClkReset; + wire resetCtrl_mainClkReset; + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) inputArea_data_fragment_reg /* _1_ */ ( + .CLK(io_jtag_tck), + .D(io_input_payload_fragment), + .EN(io_input_valid), + .Q(inputArea_data_fragment) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) inputArea_data_last_reg /* _2_ */ ( + .CLK(io_jtag_tck), + .D(io_input_payload_last), + .EN(io_input_valid), + .Q(inputArea_data_last) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) inputArea_target_reg /* _3_ */ ( + .CLK(io_jtag_tck), + .D(_0_), + .EN(io_input_valid), + .Q(inputArea_target) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) outputArea_flow_m2sPipe_payload_fragment_reg /* _4_ */ ( + .CLK(io_mainClk), + .D(inputArea_data_fragment), + .EN(outputArea_flow_valid), + .Q(outputArea_flow_m2sPipe_payload_fragment) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) outputArea_flow_m2sPipe_payload_last_reg /* _5_ */ ( + .CLK(io_mainClk), + .D(inputArea_data_last), + .EN(outputArea_flow_valid), + .Q(outputArea_flow_m2sPipe_payload_last) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _6_ ( + .A(inputArea_target), + .Y(_0_) + ); + \$ne #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _7_ ( + .A(inputArea_target_buffercc_io_dataOut), + .B(outputArea_hit), + .Y(outputArea_flow_valid) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) outputArea_flow_m2sPipe_valid_reg /* _8_ */ ( + .ARST(resetCtrl_mainClkReset), + .CLK(io_mainClk), + .D(outputArea_flow_valid), + .Q(outputArea_flow_m2sPipe_valid) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) outputArea_hit_reg /* _9_ */ ( + .CLK(io_mainClk), + .D(inputArea_target_buffercc_io_dataOut), + .Q(outputArea_hit) + ); + BufferCC_1 inputArea_target_buffercc ( + .io_dataIn(inputArea_target), + .io_dataOut(inputArea_target_buffercc_io_dataOut), + .io_mainClk(io_mainClk), + .resetCtrl_mainClkReset(resetCtrl_mainClkReset) + ); + assign io_output_payload_fragment = outputArea_flow_m2sPipe_payload_fragment; + assign io_output_payload_last = outputArea_flow_m2sPipe_payload_last; + assign io_output_valid = outputArea_flow_m2sPipe_valid; + assign outputArea_flow_payload_fragment = inputArea_data_fragment; + assign outputArea_flow_payload_last = inputArea_data_last; + assign outputArea_target = inputArea_target_buffercc_io_dataOut; +endmodule + +module InterruptCtrl(io_inputs, io_clears, io_masks, io_pendings, io_mainClk, resetCtrl_systemReset); + wire [1:0] _0_; + wire [1:0] _1_; + wire [1:0] _2_; + input [1:0] io_clears; + wire [1:0] io_clears; + input [1:0] io_inputs; + wire [1:0] io_inputs; + input io_mainClk; + wire io_mainClk; + input [1:0] io_masks; + wire [1:0] io_masks; + output [1:0] io_pendings; + wire [1:0] io_pendings; + wire [1:0] pendings; + input resetCtrl_systemReset; + wire resetCtrl_systemReset; + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd2) + ) _3_ ( + .A(pendings), + .B(io_masks), + .Y(io_pendings) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd2) + ) _4_ ( + .A(pendings), + .B(_2_), + .Y(_1_) + ); + \$not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd2) + ) _5_ ( + .A(io_clears), + .Y(_2_) + ); + \$or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd2) + ) _6_ ( + .A(_1_), + .B(io_inputs), + .Y(_0_) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(2'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd2) + ) _7_ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_0_), + .Q(pendings) + ); +endmodule + +module JtagBridge(io_jtag_tms, io_jtag_tdi, io_jtag_tdo, io_jtag_tck, io_remote_cmd_valid, io_remote_cmd_ready, io_remote_cmd_payload_last, io_remote_cmd_payload_fragment, io_remote_rsp_valid, io_remote_rsp_ready, io_remote_rsp_payload_error, io_remote_rsp_payload_data, io_mainClk, resetCtrl_mainClkReset); + wire [3:0] _000_; + wire _001_; + wire _002_; + wire _003_; + wire _004_; + wire _005_; + wire _006_; + wire _007_; + wire _008_; + wire _009_; + wire _010_; + wire _011_; + wire _012_; + wire _013_; + wire _014_; + wire _015_; + wire _016_; + wire _017_; + wire _018_; + wire _019_; + wire _020_; + wire _021_; + wire _022_; + wire _023_; + wire _024_; + wire _025_; + wire _026_; + wire _027_; + wire _028_; + wire _029_; + wire _030_; + wire _031_; + wire [15:0] _032_; + wire _033_; + wire _034_; + wire _035_; + wire _036_; + wire _037_; + wire _038_; + wire _039_; + wire _040_; + wire _041_; + wire _042_; + wire [33:0] _043_; + wire [1:0] _zz_jtag_tap_instructionShift; + wire [3:0] _zz_jtag_tap_isBypass; + wire [3:0] _zz_jtag_tap_isBypass_1; + wire flowCCByToggle_1_io_output_payload_fragment; + wire flowCCByToggle_1_io_output_payload_last; + wire flowCCByToggle_1_io_output_valid; + input io_jtag_tck; + wire io_jtag_tck; + input io_jtag_tdi; + wire io_jtag_tdi; + output io_jtag_tdo; + wire io_jtag_tdo; + input io_jtag_tms; + wire io_jtag_tms; + input io_mainClk; + wire io_mainClk; + output io_remote_cmd_payload_fragment; + wire io_remote_cmd_payload_fragment; + output io_remote_cmd_payload_last; + wire io_remote_cmd_payload_last; + input io_remote_cmd_ready; + wire io_remote_cmd_ready; + output io_remote_cmd_valid; + wire io_remote_cmd_valid; + wire io_remote_rsp_fire; + input [31:0] io_remote_rsp_payload_data; + wire [31:0] io_remote_rsp_payload_data; + input io_remote_rsp_payload_error; + wire io_remote_rsp_payload_error; + output io_remote_rsp_ready; + wire io_remote_rsp_ready; + input io_remote_rsp_valid; + wire io_remote_rsp_valid; + wire jtag_idcodeArea_ctrl_capture; + wire jtag_idcodeArea_ctrl_enable; + wire jtag_idcodeArea_ctrl_shift; + wire jtag_idcodeArea_ctrl_tdi; + wire jtag_idcodeArea_ctrl_tdo; + wire [31:0] jtag_idcodeArea_shifter; + wire jtag_readArea_ctrl_capture; + wire jtag_readArea_ctrl_enable; + wire jtag_readArea_ctrl_shift; + wire jtag_readArea_ctrl_tdi; + wire jtag_readArea_ctrl_tdo; + wire [33:0] jtag_readArea_full_shifter; + wire jtag_tap_bypass; + wire [15:0] jtag_tap_fsm_state; + wire [3:0] jtag_tap_instruction; + wire [3:0] jtag_tap_instructionShift; + wire jtag_tap_isBypass; + wire jtag_tap_tdoDr; + wire jtag_tap_tdoIr; + wire jtag_tap_tdoUnbufferd; + wire jtag_tap_tdoUnbufferd_regNext; + wire jtag_writeArea_ctrl_enable; + wire jtag_writeArea_ctrl_shift; + wire jtag_writeArea_ctrl_tdi; + wire jtag_writeArea_ctrl_tdo; + wire jtag_writeArea_data; + wire jtag_writeArea_source_payload_fragment; + wire jtag_writeArea_source_payload_last; + wire jtag_writeArea_source_valid; + wire jtag_writeArea_valid; + input resetCtrl_mainClkReset; + wire resetCtrl_mainClkReset; + wire system_cmd_payload_fragment; + wire system_cmd_payload_last; + wire system_cmd_toStream_payload_fragment; + wire system_cmd_toStream_payload_last; + wire system_cmd_toStream_ready; + wire system_cmd_toStream_valid; + wire system_cmd_valid; + wire [31:0] system_rsp_payload_data; + wire system_rsp_payload_error; + wire system_rsp_valid; + wire when_JtagTap_l120; + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd32) + ) _044_ ( + .CLK(io_mainClk), + .D(io_remote_rsp_payload_data), + .EN(io_remote_rsp_valid), + .Q(system_rsp_payload_data) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) system_rsp_payload_error_reg /* _045_ */ ( + .CLK(io_mainClk), + .D(io_remote_rsp_payload_error), + .EN(io_remote_rsp_valid), + .Q(system_rsp_payload_error) + ); + \$sdffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .SRST_POLARITY(32'd1), + .SRST_VALUE(1'h1), + .WIDTH(32'd1) + ) system_rsp_valid_reg /* _046_ */ ( + .CLK(io_mainClk), + .D(1'h0), + .EN(flowCCByToggle_1_io_output_valid), + .Q(system_rsp_valid), + .SRST(io_remote_rsp_valid) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd34) + ) _047_ ( + .CLK(io_jtag_tck), + .D(_043_), + .EN(_040_), + .Q(jtag_readArea_full_shifter) + ); + \$sdffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .SRST_POLARITY(32'd1), + .SRST_VALUE(32'd268443647), + .WIDTH(32'd32) + ) _048_ ( + .CLK(io_jtag_tck), + .D({ io_jtag_tdi, jtag_idcodeArea_shifter[31:1] }), + .EN(_041_), + .Q(jtag_idcodeArea_shifter), + .SRST(jtag_tap_fsm_state[5]) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd4) + ) _049_ ( + .CLK(io_jtag_tck), + .D(_000_), + .EN(_039_), + .Q(jtag_tap_instructionShift) + ); + \$sdffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .SRST_POLARITY(32'd1), + .SRST_VALUE(4'h1), + .WIDTH(32'd4) + ) _050_ ( + .CLK(io_jtag_tck), + .D(jtag_tap_instructionShift), + .EN(jtag_tap_fsm_state[1]), + .Q(jtag_tap_instruction), + .SRST(jtag_tap_fsm_state[0]) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _051_ ( + .A({ jtag_tap_fsm_state[4], jtag_tap_fsm_state[0] }), + .Y(_005_) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _052_ ( + .A({ jtag_tap_fsm_state[14], jtag_tap_fsm_state[10] }), + .Y(_006_) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _053_ ( + .A({ jtag_tap_fsm_state[14], jtag_tap_fsm_state[12], jtag_tap_fsm_state[2] }), + .Y(_007_) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _054_ ( + .A({ jtag_tap_fsm_state[10], jtag_tap_fsm_state[6] }), + .Y(_009_) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _055_ ( + .A({ jtag_tap_fsm_state[15], jtag_tap_fsm_state[8], jtag_tap_fsm_state[1] }), + .Y(_010_) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _056_ ( + .A({ jtag_tap_fsm_state[12], jtag_tap_fsm_state[2] }), + .Y(_011_) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _057_ ( + .A({ jtag_tap_fsm_state[11], jtag_tap_fsm_state[3] }), + .Y(_012_) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _058_ ( + .A({ jtag_tap_fsm_state[13], jtag_tap_fsm_state[5] }), + .Y(_008_) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _059_ ( + .A({ jtag_tap_fsm_state[7], jtag_tap_fsm_state[3] }), + .Y(_013_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _060_ ( + .A(io_jtag_tms), + .B(_005_), + .Y(_014_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _061_ ( + .A(io_jtag_tms), + .B(_006_), + .Y(_015_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _062_ ( + .A(_033_), + .B(_007_), + .Y(_016_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _063_ ( + .A(_034_), + .B(_008_), + .Y(_017_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _064_ ( + .A(io_jtag_tms), + .B(jtag_tap_fsm_state[9]), + .Y(_018_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _065_ ( + .A(_033_), + .B(jtag_tap_fsm_state[9]), + .Y(_019_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _066_ ( + .A(_033_), + .B(_009_), + .Y(_020_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _067_ ( + .A(io_jtag_tms), + .B(jtag_tap_fsm_state[11]), + .Y(_021_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _068_ ( + .A(_035_), + .B(_010_), + .Y(_022_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _069_ ( + .A(_033_), + .B(jtag_tap_fsm_state[0]), + .Y(_023_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _070_ ( + .A(_036_), + .B(_010_), + .Y(_024_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _071_ ( + .A(io_jtag_tms), + .B(_011_), + .Y(_025_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _072_ ( + .A(_033_), + .B(_012_), + .Y(_026_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _073_ ( + .A(_033_), + .B(jtag_tap_fsm_state[4]), + .Y(_027_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _074_ ( + .A(_037_), + .B(_008_), + .Y(_028_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _075_ ( + .A(_033_), + .B(jtag_tap_fsm_state[7]), + .Y(_029_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _076_ ( + .A(io_jtag_tms), + .B(jtag_tap_fsm_state[6]), + .Y(_030_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _077_ ( + .A(io_jtag_tms), + .B(_013_), + .Y(_031_) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _078_ ( + .A({ _022_, _023_ }), + .Y(_032_[8]) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _079_ ( + .A({ _029_, _028_ }), + .Y(_032_[13]) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd16) + ) _080_ ( + .CLK(io_jtag_tck), + .D({ _031_, _030_, _032_[13], _027_, _026_, _025_, _024_, _032_[8], _021_, _020_, _019_, _018_, _017_, _016_, _015_, _014_ }), + .Q(jtag_tap_fsm_state) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _081_ ( + .A({ _011_, io_jtag_tms }), + .B(1'h1), + .Y(_034_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _082_ ( + .A({ _011_, _008_, io_jtag_tms }), + .Y(_035_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _083_ ( + .A({ _011_, _008_, io_jtag_tms }), + .B(1'h1), + .Y(_036_) + ); + \$not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _084_ ( + .A(io_jtag_tms), + .Y(_033_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _085_ ( + .A({ _011_, io_jtag_tms }), + .Y(_037_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _086_ ( + .A({ jtag_tap_fsm_state[13], jtag_tap_fsm_state[5] }), + .Y(_038_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _087_ ( + .A({ _042_, jtag_tap_fsm_state[12] }), + .Y(_039_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _088_ ( + .A({ _038_, jtag_readArea_ctrl_enable }), + .Y(_040_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _089_ ( + .A({ jtag_tap_fsm_state[13], jtag_idcodeArea_ctrl_enable }), + .Y(_041_) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _090_ ( + .A({ jtag_tap_fsm_state[13], jtag_tap_fsm_state[2] }), + .Y(_042_) + ); + \$eq #( + .A_SIGNED(32'd1), + .A_WIDTH(32'd4), + .B_SIGNED(32'd1), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _091_ ( + .A(jtag_tap_instruction), + .B(1'h1), + .Y(jtag_tap_isBypass) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd4), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _092_ ( + .A(jtag_tap_instruction), + .B(1'h1), + .Y(jtag_idcodeArea_ctrl_enable) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd4), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _093_ ( + .A(jtag_tap_instruction), + .B(2'h2), + .Y(jtag_writeArea_ctrl_enable) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd4), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _094_ ( + .A(jtag_tap_instruction), + .B(2'h3), + .Y(jtag_readArea_ctrl_enable) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _095_ ( + .A(jtag_writeArea_ctrl_enable), + .B(jtag_tap_fsm_state[13]), + .Y(_001_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _096_ ( + .A(_001_), + .Y(jtag_writeArea_source_payload_last) + ); + \$dff #( + .CLK_POLARITY(1'h0), + .WIDTH(32'd1) + ) jtag_tap_tdoUnbufferd_regNext_reg /* _097_ */ ( + .CLK(io_jtag_tck), + .D(jtag_tap_tdoUnbufferd), + .Q(jtag_tap_tdoUnbufferd_regNext) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) jtag_tap_bypass_reg /* _098_ */ ( + .CLK(io_jtag_tck), + .D(io_jtag_tdi), + .Q(jtag_tap_bypass) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) jtag_writeArea_valid_reg /* _099_ */ ( + .CLK(io_jtag_tck), + .D(_001_), + .Q(jtag_writeArea_valid) + ); + \$mux #( + .WIDTH(32'd34) + ) _100_ ( + .A({ system_rsp_payload_data, system_rsp_payload_error, system_rsp_valid }), + .B({ io_jtag_tdi, jtag_readArea_full_shifter[33:1] }), + .S(jtag_tap_fsm_state[13]), + .Y(_043_) + ); + \$pmux #( + .S_WIDTH(32'd2), + .WIDTH(32'd4) + ) _101_ ( + .A(4'hx), + .B({ 4'h1, io_jtag_tdi, jtag_tap_instructionShift[3:1] }), + .S({ jtag_tap_fsm_state[12], _042_ }), + .Y(_000_) + ); + \$mux #( + .WIDTH(32'd1) + ) _102_ ( + .A(_003_), + .B(jtag_readArea_full_shifter[0]), + .S(jtag_readArea_ctrl_enable), + .Y(jtag_tap_tdoDr) + ); + \$mux #( + .WIDTH(32'd1) + ) _103_ ( + .A(_002_), + .B(1'h0), + .S(jtag_writeArea_ctrl_enable), + .Y(_003_) + ); + \$mux #( + .WIDTH(32'd1) + ) _104_ ( + .A(1'h0), + .B(jtag_idcodeArea_shifter[0]), + .S(jtag_idcodeArea_ctrl_enable), + .Y(_002_) + ); + \$mux #( + .WIDTH(32'd1) + ) _105_ ( + .A(jtag_tap_tdoDr), + .B(jtag_tap_bypass), + .S(jtag_tap_isBypass), + .Y(_004_) + ); + \$pmux #( + .S_WIDTH(32'd2), + .WIDTH(32'd1) + ) _106_ ( + .A(jtag_tap_bypass), + .B({ jtag_tap_instructionShift[0], _004_ }), + .S({ jtag_tap_fsm_state[2], jtag_tap_fsm_state[13] }), + .Y(jtag_tap_tdoUnbufferd) + ); + FlowCCByToggle flowCCByToggle_1 ( + .io_input_payload_fragment(jtag_tap_bypass), + .io_input_payload_last(jtag_writeArea_source_payload_last), + .io_input_valid(jtag_writeArea_valid), + .io_jtag_tck(io_jtag_tck), + .io_mainClk(io_mainClk), + .io_output_payload_fragment(flowCCByToggle_1_io_output_payload_fragment), + .io_output_payload_last(flowCCByToggle_1_io_output_payload_last), + .io_output_valid(flowCCByToggle_1_io_output_valid), + .resetCtrl_mainClkReset(resetCtrl_mainClkReset) + ); + assign { _032_[15:14], _032_[12:9], _032_[7:0] } = { _031_, _030_, _027_, _026_, _025_, _024_, _021_, _020_, _019_, _018_, _017_, _016_, _015_, _014_ }; + assign _zz_jtag_tap_instructionShift = 2'h1; + assign _zz_jtag_tap_isBypass = jtag_tap_instruction; + assign _zz_jtag_tap_isBypass_1 = 4'hf; + assign io_jtag_tdo = jtag_tap_tdoUnbufferd_regNext; + assign io_remote_cmd_payload_fragment = flowCCByToggle_1_io_output_payload_fragment; + assign io_remote_cmd_payload_last = flowCCByToggle_1_io_output_payload_last; + assign io_remote_cmd_valid = flowCCByToggle_1_io_output_valid; + assign io_remote_rsp_fire = io_remote_rsp_valid; + assign io_remote_rsp_ready = 1'h1; + assign jtag_idcodeArea_ctrl_capture = jtag_tap_fsm_state[5]; + assign jtag_idcodeArea_ctrl_shift = jtag_tap_fsm_state[13]; + assign jtag_idcodeArea_ctrl_tdi = io_jtag_tdi; + assign jtag_idcodeArea_ctrl_tdo = jtag_idcodeArea_shifter[0]; + assign jtag_readArea_ctrl_capture = jtag_tap_fsm_state[5]; + assign jtag_readArea_ctrl_shift = jtag_tap_fsm_state[13]; + assign jtag_readArea_ctrl_tdi = io_jtag_tdi; + assign jtag_readArea_ctrl_tdo = jtag_readArea_full_shifter[0]; + assign jtag_tap_tdoIr = jtag_tap_instructionShift[0]; + assign jtag_writeArea_ctrl_shift = jtag_tap_fsm_state[13]; + assign jtag_writeArea_ctrl_tdi = io_jtag_tdi; + assign jtag_writeArea_ctrl_tdo = 1'h0; + assign jtag_writeArea_data = jtag_tap_bypass; + assign jtag_writeArea_source_payload_fragment = jtag_tap_bypass; + assign jtag_writeArea_source_valid = jtag_writeArea_valid; + assign system_cmd_payload_fragment = flowCCByToggle_1_io_output_payload_fragment; + assign system_cmd_payload_last = flowCCByToggle_1_io_output_payload_last; + assign system_cmd_toStream_payload_fragment = flowCCByToggle_1_io_output_payload_fragment; + assign system_cmd_toStream_payload_last = flowCCByToggle_1_io_output_payload_last; + assign system_cmd_toStream_ready = io_remote_cmd_ready; + assign system_cmd_toStream_valid = flowCCByToggle_1_io_output_valid; + assign system_cmd_valid = flowCCByToggle_1_io_output_valid; + assign when_JtagTap_l120 = jtag_tap_fsm_state[0]; +endmodule + +module Murax(io_asyncReset, io_mainClk, io_jtag_tms, io_jtag_tdi, io_jtag_tdo, io_jtag_tck, io_uart_txd, io_uart_rxd); + wire _00_; + wire _01_; + wire _02_; + wire [5:0] _03_; + wire [5:0] _04_; + wire [5:0] _05_; + wire _06_; + wire _07_; + wire _08_; + wire _09_; + wire _10_; + wire _11_; + wire _12_; + wire _13_; + wire _14_; + wire _15_; + wire _16_; + wire _17_; + wire _18_; + wire _zz_io_bus_cmd_payload_write; + wire _zz_io_pipelinedMemoryBus_cmd_payload_write; + wire [31:0] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data; + wire [5:0] _zz_when_Murax_l188; + wire [31:0] apb3Router_1_io_input_PRDATA; + wire apb3Router_1_io_input_PREADY; + wire apb3Router_1_io_input_PSLVERROR; + wire [19:0] apb3Router_1_io_outputs_0_PADDR; + wire apb3Router_1_io_outputs_0_PENABLE; + wire apb3Router_1_io_outputs_0_PSEL; + wire [31:0] apb3Router_1_io_outputs_0_PWDATA; + wire apb3Router_1_io_outputs_0_PWRITE; + wire [19:0] apb3Router_1_io_outputs_1_PADDR; + wire apb3Router_1_io_outputs_1_PENABLE; + wire apb3Router_1_io_outputs_1_PSEL; + wire [31:0] apb3Router_1_io_outputs_1_PWDATA; + wire apb3Router_1_io_outputs_1_PWRITE; + wire [19:0] apb3Router_1_io_outputs_2_PADDR; + wire apb3Router_1_io_outputs_2_PENABLE; + wire apb3Router_1_io_outputs_2_PSEL; + wire [31:0] apb3Router_1_io_outputs_2_PWDATA; + wire apb3Router_1_io_outputs_2_PWRITE; + wire [31:0] io_apb_decoder_io_input_PRDATA; + wire io_apb_decoder_io_input_PREADY; + wire io_apb_decoder_io_input_PSLVERROR; + wire [19:0] io_apb_decoder_io_output_PADDR; + wire io_apb_decoder_io_output_PENABLE; + wire [2:0] io_apb_decoder_io_output_PSEL; + wire [31:0] io_apb_decoder_io_output_PWDATA; + wire io_apb_decoder_io_output_PWRITE; + input io_asyncReset; + wire io_asyncReset; + wire io_asyncReset_buffercc_io_dataOut; + wire [31:0] io_gpioA_read; + wire [31:0] io_gpioA_write; + wire [31:0] io_gpioA_writeEnable; + input io_jtag_tck; + wire io_jtag_tck; + input io_jtag_tdi; + wire io_jtag_tdi; + output io_jtag_tdo; + wire io_jtag_tdo; + input io_jtag_tms; + wire io_jtag_tms; + input io_mainClk; + wire io_mainClk; + input io_uart_rxd; + wire io_uart_rxd; + output io_uart_txd; + wire io_uart_txd; + wire jtagBridge_1_io_jtag_tdo; + wire jtagBridge_1_io_remote_cmd_payload_fragment; + wire jtagBridge_1_io_remote_cmd_payload_last; + wire jtagBridge_1_io_remote_cmd_valid; + wire jtagBridge_1_io_remote_rsp_ready; + wire resetCtrl_mainClkReset; + wire resetCtrl_mainClkResetUnbuffered; + wire [5:0] resetCtrl_systemClkResetCounter; + wire resetCtrl_systemReset; + wire [31:0] systemDebugger_1_io_mem_cmd_payload_address; + wire [31:0] systemDebugger_1_io_mem_cmd_payload_data; + wire [1:0] systemDebugger_1_io_mem_cmd_payload_size; + wire systemDebugger_1_io_mem_cmd_payload_wr; + wire systemDebugger_1_io_mem_cmd_valid; + wire systemDebugger_1_io_remote_cmd_ready; + wire [31:0] systemDebugger_1_io_remote_rsp_payload_data; + wire systemDebugger_1_io_remote_rsp_payload_error; + wire systemDebugger_1_io_remote_rsp_valid; + wire [19:0] system_apbBridge_io_apb_PADDR; + wire system_apbBridge_io_apb_PENABLE; + wire system_apbBridge_io_apb_PSEL; + wire [31:0] system_apbBridge_io_apb_PWDATA; + wire system_apbBridge_io_apb_PWRITE; + wire system_apbBridge_io_pipelinedMemoryBus_cmd_ready; + wire system_apbBridge_io_pipelinedMemoryBus_cmd_valid; + wire [31:0] system_apbBridge_io_pipelinedMemoryBus_rsp_payload_data; + wire system_apbBridge_io_pipelinedMemoryBus_rsp_valid; + wire system_cpu_dBus_cmd_halfPipe_fire; + wire [31:0] system_cpu_dBus_cmd_halfPipe_payload_address; + wire [31:0] system_cpu_dBus_cmd_halfPipe_payload_data; + wire [1:0] system_cpu_dBus_cmd_halfPipe_payload_size; + wire system_cpu_dBus_cmd_halfPipe_payload_wr; + wire system_cpu_dBus_cmd_halfPipe_ready; + wire system_cpu_dBus_cmd_halfPipe_valid; + wire [31:0] system_cpu_dBus_cmd_payload_address; + wire [31:0] system_cpu_dBus_cmd_payload_data; + wire [1:0] system_cpu_dBus_cmd_payload_size; + wire system_cpu_dBus_cmd_payload_wr; + wire [31:0] system_cpu_dBus_cmd_rData_address; + wire [31:0] system_cpu_dBus_cmd_rData_data; + wire [1:0] system_cpu_dBus_cmd_rData_size; + wire system_cpu_dBus_cmd_rData_wr; + wire system_cpu_dBus_cmd_rValid; + wire system_cpu_dBus_cmd_ready; + wire system_cpu_dBus_cmd_valid; + wire system_cpu_debug_bus_cmd_fire; + wire system_cpu_debug_bus_cmd_fire_regNext; + wire [7:0] system_cpu_debug_bus_cmd_payload_address; + wire system_cpu_debug_bus_cmd_ready; + wire [31:0] system_cpu_debug_bus_rsp_data; + wire system_cpu_debug_resetOut; + wire system_cpu_debug_resetOut_regNext; + wire [31:0] system_cpu_iBus_cmd_payload_pc; + wire system_cpu_iBus_cmd_valid; + wire system_externalInterrupt; + wire [3:0] system_gpioACtrl_io_apb_PADDR; + wire [31:0] system_gpioACtrl_io_apb_PRDATA; + wire system_gpioACtrl_io_apb_PREADY; + wire system_gpioACtrl_io_apb_PSLVERROR; + wire [31:0] system_gpioACtrl_io_gpio_write; + wire [31:0] system_gpioACtrl_io_gpio_writeEnable; + wire [31:0] system_gpioACtrl_io_value; + wire system_mainBusArbiter_io_dBus_cmd_ready; + wire [31:0] system_mainBusArbiter_io_dBus_rsp_data; + wire system_mainBusArbiter_io_dBus_rsp_error; + wire system_mainBusArbiter_io_dBus_rsp_ready; + wire system_mainBusArbiter_io_iBus_cmd_ready; + wire system_mainBusArbiter_io_iBus_rsp_payload_error; + wire [31:0] system_mainBusArbiter_io_iBus_rsp_payload_inst; + wire system_mainBusArbiter_io_iBus_rsp_valid; + wire [31:0] system_mainBusArbiter_io_masterBus_cmd_payload_address; + wire [31:0] system_mainBusArbiter_io_masterBus_cmd_payload_data; + wire [3:0] system_mainBusArbiter_io_masterBus_cmd_payload_mask; + wire system_mainBusArbiter_io_masterBus_cmd_payload_write; + wire system_mainBusArbiter_io_masterBus_cmd_valid; + wire system_mainBusDecoder_logic_hits_0; + wire system_mainBusDecoder_logic_hits_1; + wire system_mainBusDecoder_logic_masterPipelined_cmd_fire; + wire system_mainBusDecoder_logic_masterPipelined_cmd_fire_1; + wire [31:0] system_mainBusDecoder_logic_masterPipelined_cmd_payload_address; + wire [31:0] system_mainBusDecoder_logic_masterPipelined_cmd_payload_data; + wire [3:0] system_mainBusDecoder_logic_masterPipelined_cmd_payload_mask; + wire system_mainBusDecoder_logic_masterPipelined_cmd_payload_write; + wire system_mainBusDecoder_logic_masterPipelined_cmd_ready; + wire system_mainBusDecoder_logic_masterPipelined_cmd_valid; + wire [31:0] system_mainBusDecoder_logic_masterPipelined_rsp_payload_data; + wire system_mainBusDecoder_logic_masterPipelined_rsp_valid; + wire system_mainBusDecoder_logic_noHit; + wire system_mainBusDecoder_logic_rspNoHit; + wire system_mainBusDecoder_logic_rspPending; + wire system_mainBusDecoder_logic_rspSourceId; + wire system_ram_io_bus_cmd_ready; + wire system_ram_io_bus_cmd_valid; + wire [31:0] system_ram_io_bus_rsp_payload_data; + wire system_ram_io_bus_rsp_valid; + wire system_timerInterrupt; + wire [7:0] system_timer_io_apb_PADDR; + wire [31:0] system_timer_io_apb_PRDATA; + wire system_timer_io_apb_PREADY; + wire system_timer_io_apb_PSLVERROR; + wire system_timer_io_interrupt; + wire [4:0] system_uartCtrl_io_apb_PADDR; + wire [31:0] system_uartCtrl_io_apb_PRDATA; + wire system_uartCtrl_io_apb_PREADY; + wire system_uartCtrl_io_interrupt; + wire system_uartCtrl_io_uart_txd; + wire when_MuraxUtiles_l127; + wire when_MuraxUtiles_l133; + wire when_Murax_l188; + wire when_Murax_l192; + \$alu #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd6), + .Y_WIDTH(32'd6) + ) _19_ ( + .A(1'h1), + .B(resetCtrl_systemClkResetCounter), + .BI(1'h0), + .CI(1'h0), + .CO(_05_), + .X(_04_), + .Y(_03_) + ); + \$sdffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .SRST_POLARITY(32'd1), + .SRST_VALUE(6'h00), + .WIDTH(32'd6) + ) _20_ ( + .CLK(io_mainClk), + .D(_03_), + .EN(when_Murax_l188), + .Q(resetCtrl_systemClkResetCounter), + .SRST(io_asyncReset_buffercc_io_dataOut) + ); + \$sdff #( + .CLK_POLARITY(32'd1), + .SRST_POLARITY(32'd1), + .SRST_VALUE(1'h1), + .WIDTH(32'd1) + ) resetCtrl_systemReset_reg /* _21_ */ ( + .CLK(io_mainClk), + .D(resetCtrl_mainClkResetUnbuffered), + .Q(resetCtrl_systemReset), + .SRST(system_cpu_debug_resetOut_regNext) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) system_mainBusDecoder_logic_rspPending_reg /* _22_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_02_), + .EN(_06_), + .Q(system_mainBusDecoder_logic_rspPending) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) system_cpu_dBus_cmd_rValid_reg /* _23_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_00_), + .EN(_07_), + .Q(system_cpu_dBus_cmd_rValid) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) system_mainBusDecoder_logic_rspSourceId_reg /* _24_ */ ( + .CLK(io_mainClk), + .D(system_mainBusDecoder_logic_hits_1), + .EN(system_mainBusDecoder_logic_masterPipelined_cmd_fire), + .Q(system_mainBusDecoder_logic_rspSourceId) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd2) + ) _25_ ( + .CLK(io_mainClk), + .D(system_cpu_dBus_cmd_payload_size), + .EN(system_cpu_dBus_cmd_rValid), + .Q(system_cpu_dBus_cmd_rData_size) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd32) + ) _26_ ( + .CLK(io_mainClk), + .D(system_cpu_dBus_cmd_payload_data), + .EN(system_cpu_dBus_cmd_rValid), + .Q(system_cpu_dBus_cmd_rData_data) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd32) + ) _27_ ( + .CLK(io_mainClk), + .D(system_cpu_dBus_cmd_payload_address), + .EN(system_cpu_dBus_cmd_rValid), + .Q(system_cpu_dBus_cmd_rData_address) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd1) + ) system_cpu_dBus_cmd_rData_wr_reg /* _28_ */ ( + .CLK(io_mainClk), + .D(system_cpu_dBus_cmd_payload_wr), + .EN(system_cpu_dBus_cmd_rValid), + .Q(system_cpu_dBus_cmd_rData_wr) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _29_ ( + .A({ when_MuraxUtiles_l127, system_mainBusDecoder_logic_masterPipelined_rsp_valid }), + .Y(_06_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _30_ ( + .A({ system_cpu_dBus_cmd_halfPipe_fire, system_cpu_dBus_cmd_valid }), + .Y(_07_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd19), + .B_SIGNED(32'd0), + .B_WIDTH(32'd19), + .Y_WIDTH(32'd1) + ) _31_ ( + .A(system_mainBusArbiter_io_masterBus_cmd_payload_address[31:13]), + .B(19'h40000), + .Y(system_mainBusDecoder_logic_hits_0) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd12), + .B_SIGNED(32'd0), + .B_WIDTH(32'd12), + .Y_WIDTH(32'd1) + ) _32_ ( + .A(system_mainBusArbiter_io_masterBus_cmd_payload_address[31:20]), + .B(12'hf00), + .Y(system_mainBusDecoder_logic_hits_1) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _33_ ( + .A(system_cpu_dBus_cmd_rValid), + .B(system_cpu_dBus_cmd_halfPipe_ready), + .Y(system_cpu_dBus_cmd_halfPipe_fire) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _34_ ( + .A(systemDebugger_1_io_mem_cmd_valid), + .B(system_cpu_debug_bus_cmd_ready), + .Y(system_cpu_debug_bus_cmd_fire) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _35_ ( + .A(system_mainBusArbiter_io_masterBus_cmd_valid), + .B(system_mainBusDecoder_logic_hits_0), + .Y(_08_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _36_ ( + .A(system_mainBusArbiter_io_masterBus_cmd_valid), + .B(system_mainBusDecoder_logic_hits_1), + .Y(_09_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _37_ ( + .A(system_mainBusDecoder_logic_hits_0), + .B(system_ram_io_bus_cmd_ready), + .Y(_10_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _38_ ( + .A(system_mainBusDecoder_logic_hits_1), + .B(system_apbBridge_io_pipelinedMemoryBus_cmd_ready), + .Y(_11_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _39_ ( + .A(system_mainBusArbiter_io_masterBus_cmd_valid), + .B(system_mainBusDecoder_logic_masterPipelined_cmd_ready), + .Y(system_mainBusDecoder_logic_masterPipelined_cmd_fire) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _40_ ( + .A(system_mainBusDecoder_logic_masterPipelined_cmd_fire), + .B(_13_), + .Y(when_MuraxUtiles_l127) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _41_ ( + .A(system_mainBusDecoder_logic_rspPending), + .B(system_mainBusDecoder_logic_rspNoHit), + .Y(_12_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _42_ ( + .A(system_mainBusDecoder_logic_rspPending), + .B(_14_), + .Y(when_MuraxUtiles_l133) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _43_ ( + .A(system_cpu_dBus_cmd_rValid), + .Y(system_cpu_dBus_cmd_ready) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _44_ ( + .A(_16_), + .Y(system_mainBusDecoder_logic_noHit) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _45_ ( + .A(_zz_io_bus_cmd_payload_write), + .Y(_13_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _46_ ( + .A(system_mainBusDecoder_logic_masterPipelined_rsp_valid), + .Y(_14_) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _47_ ( + .A(_17_), + .B(system_mainBusDecoder_logic_noHit), + .Y(_15_) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _48_ ( + .A(_18_), + .B(_12_), + .Y(system_mainBusDecoder_logic_masterPipelined_rsp_valid) + ); + \$ne #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd6), + .B_SIGNED(32'd0), + .B_WIDTH(32'd6), + .Y_WIDTH(32'd1) + ) _49_ ( + .A(resetCtrl_systemClkResetCounter), + .B(6'h3f), + .Y(when_Murax_l188) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _50_ ( + .A({ system_mainBusDecoder_logic_hits_1, system_mainBusDecoder_logic_hits_0 }), + .Y(_16_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _51_ ( + .A({ _11_, _10_ }), + .Y(_17_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _52_ ( + .A({ system_apbBridge_io_pipelinedMemoryBus_rsp_valid, system_ram_io_bus_rsp_valid }), + .Y(_18_) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) system_cpu_debug_bus_cmd_fire_regNext_reg /* _53_ */ ( + .ARST(resetCtrl_mainClkReset), + .CLK(io_mainClk), + .D(system_cpu_debug_bus_cmd_fire), + .Q(system_cpu_debug_bus_cmd_fire_regNext) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) system_cpu_debug_resetOut_regNext_reg /* _54_ */ ( + .CLK(io_mainClk), + .D(system_cpu_debug_resetOut), + .Q(system_cpu_debug_resetOut_regNext) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) system_mainBusDecoder_logic_rspNoHit_reg /* _55_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_01_), + .Q(system_mainBusDecoder_logic_rspNoHit) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) resetCtrl_mainClkReset_reg /* _56_ */ ( + .CLK(io_mainClk), + .D(resetCtrl_mainClkResetUnbuffered), + .Q(resetCtrl_mainClkReset) + ); + \$mux #( + .WIDTH(32'd1) + ) _57_ ( + .A(1'h1), + .B(1'h0), + .S(_16_), + .Y(_01_) + ); + \$mux #( + .WIDTH(32'd1) + ) _58_ ( + .A(1'h0), + .B(1'h1), + .S(when_MuraxUtiles_l127), + .Y(_02_) + ); + \$mux #( + .WIDTH(32'd1) + ) _59_ ( + .A(1'h1), + .B(1'h0), + .S(system_cpu_dBus_cmd_halfPipe_fire), + .Y(_00_) + ); + \$mux #( + .WIDTH(32'd1) + ) _60_ ( + .A(_15_), + .B(1'h0), + .S(when_MuraxUtiles_l133), + .Y(system_mainBusDecoder_logic_masterPipelined_cmd_ready) + ); + \$mux #( + .WIDTH(32'd1) + ) _61_ ( + .A(_09_), + .B(1'h0), + .S(when_MuraxUtiles_l133), + .Y(system_apbBridge_io_pipelinedMemoryBus_cmd_valid) + ); + \$mux #( + .WIDTH(32'd1) + ) _62_ ( + .A(_08_), + .B(1'h0), + .S(when_MuraxUtiles_l133), + .Y(system_ram_io_bus_cmd_valid) + ); + \$mux #( + .WIDTH(32'd1) + ) _63_ ( + .A(1'h0), + .B(1'h1), + .S(system_uartCtrl_io_interrupt), + .Y(system_externalInterrupt) + ); + \$mux #( + .WIDTH(32'd1) + ) _64_ ( + .A(1'h0), + .B(1'h1), + .S(system_timer_io_interrupt), + .Y(system_timerInterrupt) + ); + \$mux #( + .WIDTH(32'd1) + ) _65_ ( + .A(1'h0), + .B(1'h1), + .S(when_Murax_l188), + .Y(resetCtrl_mainClkResetUnbuffered) + ); + \$mux #( + .WIDTH(32'd32) + ) _66_ ( + .A(system_ram_io_bus_rsp_payload_data), + .B(system_apbBridge_io_pipelinedMemoryBus_rsp_payload_data), + .S(system_mainBusDecoder_logic_rspSourceId), + .Y(system_mainBusDecoder_logic_masterPipelined_rsp_payload_data) + ); + Apb3Router apb3Router_1 ( + .io_input_PADDR(io_apb_decoder_io_output_PADDR), + .io_input_PENABLE(io_apb_decoder_io_output_PENABLE), + .io_input_PRDATA(apb3Router_1_io_input_PRDATA), + .io_input_PREADY(apb3Router_1_io_input_PREADY), + .io_input_PSEL(io_apb_decoder_io_output_PSEL), + .io_input_PSLVERROR(apb3Router_1_io_input_PSLVERROR), + .io_input_PWDATA(io_apb_decoder_io_output_PWDATA), + .io_input_PWRITE(io_apb_decoder_io_output_PWRITE), + .io_mainClk(io_mainClk), + .io_outputs_0_PADDR(apb3Router_1_io_outputs_0_PADDR), + .io_outputs_0_PENABLE(apb3Router_1_io_outputs_0_PENABLE), + .io_outputs_0_PRDATA(system_gpioACtrl_io_apb_PRDATA), + .io_outputs_0_PREADY(system_gpioACtrl_io_apb_PREADY), + .io_outputs_0_PSEL(apb3Router_1_io_outputs_0_PSEL), + .io_outputs_0_PSLVERROR(system_gpioACtrl_io_apb_PSLVERROR), + .io_outputs_0_PWDATA(apb3Router_1_io_outputs_0_PWDATA), + .io_outputs_0_PWRITE(apb3Router_1_io_outputs_0_PWRITE), + .io_outputs_1_PADDR(apb3Router_1_io_outputs_1_PADDR), + .io_outputs_1_PENABLE(apb3Router_1_io_outputs_1_PENABLE), + .io_outputs_1_PRDATA(system_uartCtrl_io_apb_PRDATA), + .io_outputs_1_PREADY(system_uartCtrl_io_apb_PREADY), + .io_outputs_1_PSEL(apb3Router_1_io_outputs_1_PSEL), + .io_outputs_1_PSLVERROR(1'h0), + .io_outputs_1_PWDATA(apb3Router_1_io_outputs_1_PWDATA), + .io_outputs_1_PWRITE(apb3Router_1_io_outputs_1_PWRITE), + .io_outputs_2_PADDR(apb3Router_1_io_outputs_2_PADDR), + .io_outputs_2_PENABLE(apb3Router_1_io_outputs_2_PENABLE), + .io_outputs_2_PRDATA(system_timer_io_apb_PRDATA), + .io_outputs_2_PREADY(system_timer_io_apb_PREADY), + .io_outputs_2_PSEL(apb3Router_1_io_outputs_2_PSEL), + .io_outputs_2_PSLVERROR(system_timer_io_apb_PSLVERROR), + .io_outputs_2_PWDATA(apb3Router_1_io_outputs_2_PWDATA), + .io_outputs_2_PWRITE(apb3Router_1_io_outputs_2_PWRITE), + .resetCtrl_systemReset(resetCtrl_systemReset) + ); + Apb3Decoder io_apb_decoder ( + .io_input_PADDR(system_apbBridge_io_apb_PADDR), + .io_input_PENABLE(system_apbBridge_io_apb_PENABLE), + .io_input_PRDATA(io_apb_decoder_io_input_PRDATA), + .io_input_PREADY(io_apb_decoder_io_input_PREADY), + .io_input_PSEL(system_apbBridge_io_apb_PSEL), + .io_input_PSLVERROR(io_apb_decoder_io_input_PSLVERROR), + .io_input_PWDATA(system_apbBridge_io_apb_PWDATA), + .io_input_PWRITE(system_apbBridge_io_apb_PWRITE), + .io_output_PADDR(io_apb_decoder_io_output_PADDR), + .io_output_PENABLE(io_apb_decoder_io_output_PENABLE), + .io_output_PRDATA(apb3Router_1_io_input_PRDATA), + .io_output_PREADY(apb3Router_1_io_input_PREADY), + .io_output_PSEL(io_apb_decoder_io_output_PSEL), + .io_output_PSLVERROR(apb3Router_1_io_input_PSLVERROR), + .io_output_PWDATA(io_apb_decoder_io_output_PWDATA), + .io_output_PWRITE(io_apb_decoder_io_output_PWRITE) + ); + BufferCC_3 io_asyncReset_buffercc ( + .io_dataIn(io_asyncReset), + .io_dataOut(io_asyncReset_buffercc_io_dataOut), + .io_mainClk(io_mainClk) + ); + JtagBridge jtagBridge_1 ( + .io_jtag_tck(io_jtag_tck), + .io_jtag_tdi(io_jtag_tdi), + .io_jtag_tdo(jtagBridge_1_io_jtag_tdo), + .io_jtag_tms(io_jtag_tms), + .io_mainClk(io_mainClk), + .io_remote_cmd_payload_fragment(jtagBridge_1_io_remote_cmd_payload_fragment), + .io_remote_cmd_payload_last(jtagBridge_1_io_remote_cmd_payload_last), + .io_remote_cmd_ready(systemDebugger_1_io_remote_cmd_ready), + .io_remote_cmd_valid(jtagBridge_1_io_remote_cmd_valid), + .io_remote_rsp_payload_data(systemDebugger_1_io_remote_rsp_payload_data), + .io_remote_rsp_payload_error(systemDebugger_1_io_remote_rsp_payload_error), + .io_remote_rsp_ready(jtagBridge_1_io_remote_rsp_ready), + .io_remote_rsp_valid(systemDebugger_1_io_remote_rsp_valid), + .resetCtrl_mainClkReset(resetCtrl_mainClkReset) + ); + SystemDebugger systemDebugger_1 ( + .io_mainClk(io_mainClk), + .io_mem_cmd_payload_address(systemDebugger_1_io_mem_cmd_payload_address), + .io_mem_cmd_payload_data(systemDebugger_1_io_mem_cmd_payload_data), + .io_mem_cmd_payload_size(systemDebugger_1_io_mem_cmd_payload_size), + .io_mem_cmd_payload_wr(systemDebugger_1_io_mem_cmd_payload_wr), + .io_mem_cmd_ready(system_cpu_debug_bus_cmd_ready), + .io_mem_cmd_valid(systemDebugger_1_io_mem_cmd_valid), + .io_mem_rsp_payload(system_cpu_debug_bus_rsp_data), + .io_mem_rsp_valid(system_cpu_debug_bus_cmd_fire_regNext), + .io_remote_cmd_payload_fragment(jtagBridge_1_io_remote_cmd_payload_fragment), + .io_remote_cmd_payload_last(jtagBridge_1_io_remote_cmd_payload_last), + .io_remote_cmd_ready(systemDebugger_1_io_remote_cmd_ready), + .io_remote_cmd_valid(jtagBridge_1_io_remote_cmd_valid), + .io_remote_rsp_payload_data(systemDebugger_1_io_remote_rsp_payload_data), + .io_remote_rsp_payload_error(systemDebugger_1_io_remote_rsp_payload_error), + .io_remote_rsp_ready(jtagBridge_1_io_remote_rsp_ready), + .io_remote_rsp_valid(systemDebugger_1_io_remote_rsp_valid), + .resetCtrl_mainClkReset(resetCtrl_mainClkReset) + ); + PipelinedMemoryBusToApbBridge system_apbBridge ( + .io_apb_PADDR(system_apbBridge_io_apb_PADDR), + .io_apb_PENABLE(system_apbBridge_io_apb_PENABLE), + .io_apb_PRDATA(io_apb_decoder_io_input_PRDATA), + .io_apb_PREADY(io_apb_decoder_io_input_PREADY), + .io_apb_PSEL(system_apbBridge_io_apb_PSEL), + .io_apb_PSLVERROR(io_apb_decoder_io_input_PSLVERROR), + .io_apb_PWDATA(system_apbBridge_io_apb_PWDATA), + .io_apb_PWRITE(system_apbBridge_io_apb_PWRITE), + .io_mainClk(io_mainClk), + .io_pipelinedMemoryBus_cmd_payload_address(system_mainBusArbiter_io_masterBus_cmd_payload_address), + .io_pipelinedMemoryBus_cmd_payload_data(system_mainBusArbiter_io_masterBus_cmd_payload_data), + .io_pipelinedMemoryBus_cmd_payload_mask(system_mainBusArbiter_io_masterBus_cmd_payload_mask), + .io_pipelinedMemoryBus_cmd_payload_write(_zz_io_bus_cmd_payload_write), + .io_pipelinedMemoryBus_cmd_ready(system_apbBridge_io_pipelinedMemoryBus_cmd_ready), + .io_pipelinedMemoryBus_cmd_valid(system_apbBridge_io_pipelinedMemoryBus_cmd_valid), + .io_pipelinedMemoryBus_rsp_payload_data(system_apbBridge_io_pipelinedMemoryBus_rsp_payload_data), + .io_pipelinedMemoryBus_rsp_valid(system_apbBridge_io_pipelinedMemoryBus_rsp_valid), + .resetCtrl_systemReset(resetCtrl_systemReset) + ); + VexRiscv system_cpu ( + .dBus_cmd_payload_address(system_cpu_dBus_cmd_payload_address), + .dBus_cmd_payload_data(system_cpu_dBus_cmd_payload_data), + .dBus_cmd_payload_size(system_cpu_dBus_cmd_payload_size), + .dBus_cmd_payload_wr(system_cpu_dBus_cmd_payload_wr), + .dBus_cmd_ready(system_cpu_dBus_cmd_ready), + .dBus_cmd_valid(system_cpu_dBus_cmd_valid), + .dBus_rsp_data(system_mainBusArbiter_io_dBus_rsp_data), + .dBus_rsp_error(system_mainBusArbiter_io_dBus_rsp_error), + .dBus_rsp_ready(system_mainBusArbiter_io_dBus_rsp_ready), + .debug_bus_cmd_payload_address(systemDebugger_1_io_mem_cmd_payload_address[7:0]), + .debug_bus_cmd_payload_data(systemDebugger_1_io_mem_cmd_payload_data), + .debug_bus_cmd_payload_wr(systemDebugger_1_io_mem_cmd_payload_wr), + .debug_bus_cmd_ready(system_cpu_debug_bus_cmd_ready), + .debug_bus_cmd_valid(systemDebugger_1_io_mem_cmd_valid), + .debug_bus_rsp_data(system_cpu_debug_bus_rsp_data), + .debug_resetOut(system_cpu_debug_resetOut), + .externalInterrupt(system_externalInterrupt), + .iBus_cmd_payload_pc(system_cpu_iBus_cmd_payload_pc), + .iBus_cmd_ready(system_mainBusArbiter_io_iBus_cmd_ready), + .iBus_cmd_valid(system_cpu_iBus_cmd_valid), + .iBus_rsp_payload_error(system_mainBusArbiter_io_iBus_rsp_payload_error), + .iBus_rsp_payload_inst(system_mainBusArbiter_io_iBus_rsp_payload_inst), + .iBus_rsp_valid(system_mainBusArbiter_io_iBus_rsp_valid), + .io_mainClk(io_mainClk), + .resetCtrl_mainClkReset(resetCtrl_mainClkReset), + .resetCtrl_systemReset(resetCtrl_systemReset), + .softwareInterrupt(1'h0), + .timerInterrupt(system_timerInterrupt) + ); + Apb3Gpio system_gpioACtrl ( + .io_apb_PADDR(apb3Router_1_io_outputs_0_PADDR[3:0]), + .io_apb_PENABLE(apb3Router_1_io_outputs_0_PENABLE), + .io_apb_PRDATA(system_gpioACtrl_io_apb_PRDATA), + .io_apb_PREADY(system_gpioACtrl_io_apb_PREADY), + .io_apb_PSEL(apb3Router_1_io_outputs_0_PSEL), + .io_apb_PSLVERROR(system_gpioACtrl_io_apb_PSLVERROR), + .io_apb_PWDATA(apb3Router_1_io_outputs_0_PWDATA), + .io_apb_PWRITE(apb3Router_1_io_outputs_0_PWRITE), + .io_gpio_read(io_gpioA_read), + .io_gpio_write(system_gpioACtrl_io_gpio_write), + .io_gpio_writeEnable(system_gpioACtrl_io_gpio_writeEnable), + .io_mainClk(io_mainClk), + .io_value(system_gpioACtrl_io_value), + .resetCtrl_systemReset(resetCtrl_systemReset) + ); + MuraxMasterArbiter system_mainBusArbiter ( + .io_dBus_cmd_payload_address(system_cpu_dBus_cmd_rData_address), + .io_dBus_cmd_payload_data(system_cpu_dBus_cmd_rData_data), + .io_dBus_cmd_payload_size(system_cpu_dBus_cmd_rData_size), + .io_dBus_cmd_payload_wr(system_cpu_dBus_cmd_rData_wr), + .io_dBus_cmd_ready(system_cpu_dBus_cmd_halfPipe_ready), + .io_dBus_cmd_valid(system_cpu_dBus_cmd_rValid), + .io_dBus_rsp_data(system_mainBusArbiter_io_dBus_rsp_data), + .io_dBus_rsp_error(system_mainBusArbiter_io_dBus_rsp_error), + .io_dBus_rsp_ready(system_mainBusArbiter_io_dBus_rsp_ready), + .io_iBus_cmd_payload_pc(system_cpu_iBus_cmd_payload_pc), + .io_iBus_cmd_ready(system_mainBusArbiter_io_iBus_cmd_ready), + .io_iBus_cmd_valid(system_cpu_iBus_cmd_valid), + .io_iBus_rsp_payload_error(system_mainBusArbiter_io_iBus_rsp_payload_error), + .io_iBus_rsp_payload_inst(system_mainBusArbiter_io_iBus_rsp_payload_inst), + .io_iBus_rsp_valid(system_mainBusArbiter_io_iBus_rsp_valid), + .io_mainClk(io_mainClk), + .io_masterBus_cmd_payload_address(system_mainBusArbiter_io_masterBus_cmd_payload_address), + .io_masterBus_cmd_payload_data(system_mainBusArbiter_io_masterBus_cmd_payload_data), + .io_masterBus_cmd_payload_mask(system_mainBusArbiter_io_masterBus_cmd_payload_mask), + .io_masterBus_cmd_payload_write(_zz_io_bus_cmd_payload_write), + .io_masterBus_cmd_ready(system_mainBusDecoder_logic_masterPipelined_cmd_ready), + .io_masterBus_cmd_valid(system_mainBusArbiter_io_masterBus_cmd_valid), + .io_masterBus_rsp_payload_data(system_mainBusDecoder_logic_masterPipelined_rsp_payload_data), + .io_masterBus_rsp_valid(system_mainBusDecoder_logic_masterPipelined_rsp_valid), + .resetCtrl_systemReset(resetCtrl_systemReset) + ); + MuraxPipelinedMemoryBusRam system_ram ( + .io_bus_cmd_payload_address(system_mainBusArbiter_io_masterBus_cmd_payload_address), + .io_bus_cmd_payload_data(system_mainBusArbiter_io_masterBus_cmd_payload_data), + .io_bus_cmd_payload_mask(system_mainBusArbiter_io_masterBus_cmd_payload_mask), + .io_bus_cmd_payload_write(_zz_io_bus_cmd_payload_write), + .io_bus_cmd_ready(system_ram_io_bus_cmd_ready), + .io_bus_cmd_valid(system_ram_io_bus_cmd_valid), + .io_bus_rsp_payload_data(system_ram_io_bus_rsp_payload_data), + .io_bus_rsp_valid(system_ram_io_bus_rsp_valid), + .io_mainClk(io_mainClk), + .resetCtrl_systemReset(resetCtrl_systemReset) + ); + MuraxApb3Timer system_timer ( + .io_apb_PADDR(apb3Router_1_io_outputs_2_PADDR[7:0]), + .io_apb_PENABLE(apb3Router_1_io_outputs_2_PENABLE), + .io_apb_PRDATA(system_timer_io_apb_PRDATA), + .io_apb_PREADY(system_timer_io_apb_PREADY), + .io_apb_PSEL(apb3Router_1_io_outputs_2_PSEL), + .io_apb_PSLVERROR(system_timer_io_apb_PSLVERROR), + .io_apb_PWDATA(apb3Router_1_io_outputs_2_PWDATA), + .io_apb_PWRITE(apb3Router_1_io_outputs_2_PWRITE), + .io_interrupt(system_timer_io_interrupt), + .io_mainClk(io_mainClk), + .resetCtrl_systemReset(resetCtrl_systemReset) + ); + Apb3UartCtrl system_uartCtrl ( + .io_apb_PADDR(apb3Router_1_io_outputs_1_PADDR[4:0]), + .io_apb_PENABLE(apb3Router_1_io_outputs_1_PENABLE), + .io_apb_PRDATA(system_uartCtrl_io_apb_PRDATA), + .io_apb_PREADY(system_uartCtrl_io_apb_PREADY), + .io_apb_PSEL(apb3Router_1_io_outputs_1_PSEL), + .io_apb_PWDATA(apb3Router_1_io_outputs_1_PWDATA), + .io_apb_PWRITE(apb3Router_1_io_outputs_1_PWRITE), + .io_interrupt(system_uartCtrl_io_interrupt), + .io_mainClk(io_mainClk), + .io_uart_rxd(io_uart_rxd), + .io_uart_txd(system_uartCtrl_io_uart_txd), + .resetCtrl_systemReset(resetCtrl_systemReset) + ); + assign _zz_io_pipelinedMemoryBus_cmd_payload_write = _zz_io_bus_cmd_payload_write; + assign _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data = system_mainBusDecoder_logic_masterPipelined_rsp_payload_data; + assign _zz_when_Murax_l188 = 6'h3f; + assign io_gpioA_write = system_gpioACtrl_io_gpio_write; + assign io_gpioA_writeEnable = system_gpioACtrl_io_gpio_writeEnable; + assign io_jtag_tdo = jtagBridge_1_io_jtag_tdo; + assign io_uart_txd = system_uartCtrl_io_uart_txd; + assign system_cpu_dBus_cmd_halfPipe_payload_address = system_cpu_dBus_cmd_rData_address; + assign system_cpu_dBus_cmd_halfPipe_payload_data = system_cpu_dBus_cmd_rData_data; + assign system_cpu_dBus_cmd_halfPipe_payload_size = system_cpu_dBus_cmd_rData_size; + assign system_cpu_dBus_cmd_halfPipe_payload_wr = system_cpu_dBus_cmd_rData_wr; + assign system_cpu_dBus_cmd_halfPipe_valid = system_cpu_dBus_cmd_rValid; + assign system_cpu_debug_bus_cmd_payload_address = systemDebugger_1_io_mem_cmd_payload_address[7:0]; + assign system_gpioACtrl_io_apb_PADDR = apb3Router_1_io_outputs_0_PADDR[3:0]; + assign system_mainBusArbiter_io_dBus_cmd_ready = system_cpu_dBus_cmd_halfPipe_ready; + assign system_mainBusArbiter_io_masterBus_cmd_payload_write = _zz_io_bus_cmd_payload_write; + assign system_mainBusDecoder_logic_masterPipelined_cmd_fire_1 = system_mainBusDecoder_logic_masterPipelined_cmd_fire; + assign system_mainBusDecoder_logic_masterPipelined_cmd_payload_address = system_mainBusArbiter_io_masterBus_cmd_payload_address; + assign system_mainBusDecoder_logic_masterPipelined_cmd_payload_data = system_mainBusArbiter_io_masterBus_cmd_payload_data; + assign system_mainBusDecoder_logic_masterPipelined_cmd_payload_mask = system_mainBusArbiter_io_masterBus_cmd_payload_mask; + assign system_mainBusDecoder_logic_masterPipelined_cmd_payload_write = _zz_io_bus_cmd_payload_write; + assign system_mainBusDecoder_logic_masterPipelined_cmd_valid = system_mainBusArbiter_io_masterBus_cmd_valid; + assign system_timer_io_apb_PADDR = apb3Router_1_io_outputs_2_PADDR[7:0]; + assign system_uartCtrl_io_apb_PADDR = apb3Router_1_io_outputs_1_PADDR[4:0]; + assign when_Murax_l192 = io_asyncReset_buffercc_io_dataOut; +endmodule + +module MuraxApb3Timer(io_apb_PADDR, io_apb_PSEL, io_apb_PENABLE, io_apb_PREADY, io_apb_PWRITE, io_apb_PWDATA, io_apb_PRDATA, io_apb_PSLVERROR, io_interrupt, io_mainClk, resetCtrl_systemReset); + wire _00_; + wire _01_; + wire _02_; + wire [1:0] _03_; + wire _04_; + wire [1:0] _05_; + wire _06_; + wire [1:0] _07_; + wire _08_; + wire _09_; + wire _10_; + wire _11_; + wire _12_; + wire _13_; + wire _14_; + wire _15_; + wire _16_; + wire _17_; + wire _18_; + wire _19_; + wire _20_; + wire _21_; + wire _22_; + wire _23_; + wire _zz_io_clear; + wire [15:0] _zz_io_limit; + wire busCtrl_doWrite; + wire [1:0] interruptCtrl_1_io_clears; + wire [1:0] interruptCtrl_1_io_inputs; + wire [1:0] interruptCtrl_1_io_masks_driver; + wire [1:0] interruptCtrl_1_io_pendings; + input [7:0] io_apb_PADDR; + wire [7:0] io_apb_PADDR; + input io_apb_PENABLE; + wire io_apb_PENABLE; + output [31:0] io_apb_PRDATA; + wire [31:0] io_apb_PRDATA; + output io_apb_PREADY; + wire io_apb_PREADY; + input io_apb_PSEL; + wire io_apb_PSEL; + output io_apb_PSLVERROR; + wire io_apb_PSLVERROR; + input [31:0] io_apb_PWDATA; + wire [31:0] io_apb_PWDATA; + input io_apb_PWRITE; + wire io_apb_PWRITE; + output io_interrupt; + wire io_interrupt; + input io_mainClk; + wire io_mainClk; + wire prescaler_1_io_overflow; + input resetCtrl_systemReset; + wire resetCtrl_systemReset; + wire timerABridge_busClearing; + wire timerABridge_clearsEnable; + wire [1:0] timerABridge_ticksEnable; + wire timerA_io_clear; + wire timerA_io_full; + wire [15:0] timerA_io_limit_driver; + wire timerA_io_tick; + wire [15:0] timerA_io_value; + wire timerBBridge_busClearing; + wire timerBBridge_clearsEnable; + wire [1:0] timerBBridge_ticksEnable; + wire timerB_io_clear; + wire timerB_io_full; + wire [15:0] timerB_io_limit_driver; + wire timerB_io_tick; + wire [15:0] timerB_io_value; + wire when_Timer_l40; + wire when_Timer_l40_1; + wire when_Timer_l44; + wire when_Timer_l44_1; + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _24_ ( + .A(timerABridge_clearsEnable), + .B(timerA_io_full), + .Y(_04_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _25_ ( + .A(timerBBridge_clearsEnable), + .B(timerB_io_full), + .Y(_06_) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(2'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd2) + ) _26_ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(io_apb_PWDATA[1:0]), + .EN(_08_), + .Q(interruptCtrl_1_io_masks_driver) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) timerBBridge_clearsEnable_reg /* _27_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(io_apb_PWDATA[16]), + .EN(_09_), + .Q(timerBBridge_clearsEnable) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(2'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd2) + ) _28_ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(io_apb_PWDATA[1:0]), + .EN(_09_), + .Q(timerBBridge_ticksEnable) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) timerABridge_clearsEnable_reg /* _29_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(io_apb_PWDATA[16]), + .EN(_10_), + .Q(timerABridge_clearsEnable) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(2'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd2) + ) _30_ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(io_apb_PWDATA[1:0]), + .EN(_10_), + .Q(timerABridge_ticksEnable) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd16) + ) _31_ ( + .CLK(io_mainClk), + .D(io_apb_PWDATA[15:0]), + .EN(_11_), + .Q(timerB_io_limit_driver) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd16) + ) _32_ ( + .CLK(io_mainClk), + .D(io_apb_PWDATA[15:0]), + .EN(_12_), + .Q(timerA_io_limit_driver) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd16) + ) _33_ ( + .CLK(io_mainClk), + .D(io_apb_PWDATA[15:0]), + .EN(_13_), + .Q(_zz_io_limit) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _34_ ( + .A({ _18_, busCtrl_doWrite }), + .Y(_08_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _35_ ( + .A({ _19_, busCtrl_doWrite }), + .Y(_09_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _36_ ( + .A({ _20_, busCtrl_doWrite }), + .Y(_10_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _37_ ( + .A({ _15_, busCtrl_doWrite }), + .Y(_11_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _38_ ( + .A({ _16_, busCtrl_doWrite }), + .Y(_12_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _39_ ( + .A({ _17_, busCtrl_doWrite }), + .Y(_13_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _40_ ( + .A(timerABridge_ticksEnable[1]), + .B(prescaler_1_io_overflow), + .Y(_05_[1]) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _41_ ( + .A(timerBBridge_ticksEnable[1]), + .B(prescaler_1_io_overflow), + .Y(_07_[1]) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _42_ ( + .A(io_apb_PSEL), + .B(io_apb_PENABLE), + .Y(_14_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _43_ ( + .A(_14_), + .B(io_apb_PWRITE), + .Y(busCtrl_doWrite) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _44_ ( + .A(_04_), + .B(timerABridge_busClearing), + .Y(timerA_io_clear) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _45_ ( + .A(_06_), + .B(timerBBridge_busClearing), + .Y(timerB_io_clear) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd8), + .B_SIGNED(32'd0), + .B_WIDTH(32'd7), + .Y_WIDTH(32'd1) + ) _46_ ( + .A(io_apb_PADDR), + .B(7'h54), + .Y(_15_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd8), + .B_SIGNED(32'd0), + .B_WIDTH(32'd7), + .Y_WIDTH(32'd1) + ) _47_ ( + .A(io_apb_PADDR), + .B(7'h44), + .Y(_16_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd8), + .Y_WIDTH(32'd1) + ) _48_ ( + .A(io_apb_PADDR), + .Y(_17_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd8), + .B_SIGNED(32'd0), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd1) + ) _49_ ( + .A(io_apb_PADDR), + .B(5'h14), + .Y(_18_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd8), + .B_SIGNED(32'd0), + .B_WIDTH(32'd7), + .Y_WIDTH(32'd1) + ) _50_ ( + .A(io_apb_PADDR), + .B(7'h50), + .Y(_19_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd8), + .B_SIGNED(32'd0), + .B_WIDTH(32'd7), + .Y_WIDTH(32'd1) + ) _51_ ( + .A(io_apb_PADDR), + .B(7'h40), + .Y(_20_) + ); + \$mux #( + .WIDTH(32'd2) + ) _52_ ( + .A(2'h0), + .B(io_apb_PWDATA[1:0]), + .S(busCtrl_doWrite), + .Y(_03_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd8), + .B_SIGNED(32'd0), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd1) + ) _53_ ( + .A(io_apb_PADDR), + .B(5'h10), + .Y(_21_) + ); + \$mux #( + .WIDTH(32'd2) + ) _54_ ( + .A(2'h0), + .B(_03_), + .S(_21_), + .Y(interruptCtrl_1_io_clears) + ); + \$mux #( + .WIDTH(32'd1) + ) _55_ ( + .A(1'h0), + .B(1'h1), + .S(busCtrl_doWrite), + .Y(_02_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd8), + .B_SIGNED(32'd0), + .B_WIDTH(32'd7), + .Y_WIDTH(32'd1) + ) _56_ ( + .A(io_apb_PADDR), + .B(7'h58), + .Y(_22_) + ); + \$mux #( + .WIDTH(32'd1) + ) _57_ ( + .A(1'h0), + .B(_02_), + .S(_22_), + .Y(when_Timer_l44_1) + ); + \$mux #( + .WIDTH(32'd1) + ) _58_ ( + .A(1'h0), + .B(_02_), + .S(_15_), + .Y(when_Timer_l40_1) + ); + \$mux #( + .WIDTH(32'd1) + ) _59_ ( + .A(_01_), + .B(1'h1), + .S(when_Timer_l44_1), + .Y(timerBBridge_busClearing) + ); + \$mux #( + .WIDTH(32'd1) + ) _60_ ( + .A(1'h0), + .B(1'h1), + .S(when_Timer_l40_1), + .Y(_01_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd8), + .B_SIGNED(32'd0), + .B_WIDTH(32'd7), + .Y_WIDTH(32'd1) + ) _61_ ( + .A(io_apb_PADDR), + .B(7'h48), + .Y(_23_) + ); + \$mux #( + .WIDTH(32'd1) + ) _62_ ( + .A(1'h0), + .B(_02_), + .S(_23_), + .Y(when_Timer_l44) + ); + \$mux #( + .WIDTH(32'd1) + ) _63_ ( + .A(1'h0), + .B(_02_), + .S(_16_), + .Y(when_Timer_l40) + ); + \$mux #( + .WIDTH(32'd1) + ) _64_ ( + .A(_00_), + .B(1'h1), + .S(when_Timer_l44), + .Y(timerABridge_busClearing) + ); + \$mux #( + .WIDTH(32'd1) + ) _65_ ( + .A(1'h0), + .B(1'h1), + .S(when_Timer_l40), + .Y(_00_) + ); + \$mux #( + .WIDTH(32'd1) + ) _66_ ( + .A(1'h0), + .B(_02_), + .S(_17_), + .Y(_zz_io_clear) + ); + \$pmux #( + .S_WIDTH(32'd2), + .WIDTH(32'd1) + ) _67_ ( + .A(1'h0), + .B({ timerABridge_clearsEnable, timerBBridge_clearsEnable }), + .S({ _20_, _19_ }), + .Y(io_apb_PRDATA[16]) + ); + \$pmux #( + .S_WIDTH(32'd5), + .WIDTH(32'd14) + ) _68_ ( + .A(14'h0000), + .B({ _zz_io_limit[15:2], timerA_io_limit_driver[15:2], timerA_io_value[15:2], timerB_io_limit_driver[15:2], timerB_io_value[15:2] }), + .S({ _17_, _16_, _23_, _15_, _22_ }), + .Y(io_apb_PRDATA[15:2]) + ); + \$pmux #( + .S_WIDTH(32'd9), + .WIDTH(32'd2) + ) _69_ ( + .A(2'h0), + .B({ _zz_io_limit[1:0], timerABridge_ticksEnable, timerA_io_limit_driver[1:0], timerA_io_value[1:0], timerBBridge_ticksEnable, timerB_io_limit_driver[1:0], timerB_io_value[1:0], interruptCtrl_1_io_pendings, interruptCtrl_1_io_masks_driver }), + .S({ _17_, _20_, _16_, _23_, _19_, _15_, _22_, _21_, _18_ }), + .Y(io_apb_PRDATA[1:0]) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _70_ ( + .A({ _05_[1], timerABridge_ticksEnable[0] }), + .Y(timerA_io_tick) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _71_ ( + .A({ _07_[1], timerBBridge_ticksEnable[0] }), + .Y(timerB_io_tick) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _72_ ( + .A(interruptCtrl_1_io_pendings), + .Y(io_interrupt) + ); + InterruptCtrl interruptCtrl_1 ( + .io_clears(interruptCtrl_1_io_clears), + .io_inputs({ timerB_io_full, timerA_io_full }), + .io_mainClk(io_mainClk), + .io_masks(interruptCtrl_1_io_masks_driver), + .io_pendings(interruptCtrl_1_io_pendings), + .resetCtrl_systemReset(resetCtrl_systemReset) + ); + Prescaler prescaler_1 ( + .io_clear(_zz_io_clear), + .io_limit(_zz_io_limit), + .io_mainClk(io_mainClk), + .io_overflow(prescaler_1_io_overflow), + .resetCtrl_systemReset(resetCtrl_systemReset) + ); + Timer timerA ( + .io_clear(timerA_io_clear), + .io_full(timerA_io_full), + .io_limit(timerA_io_limit_driver), + .io_mainClk(io_mainClk), + .io_tick(timerA_io_tick), + .io_value(timerA_io_value), + .resetCtrl_systemReset(resetCtrl_systemReset) + ); + Timer timerB ( + .io_clear(timerB_io_clear), + .io_full(timerB_io_full), + .io_limit(timerB_io_limit_driver), + .io_mainClk(io_mainClk), + .io_tick(timerB_io_tick), + .io_value(timerB_io_value), + .resetCtrl_systemReset(resetCtrl_systemReset) + ); + assign _05_[0] = timerABridge_ticksEnable[0]; + assign _07_[0] = timerBBridge_ticksEnable[0]; + assign interruptCtrl_1_io_inputs = { timerB_io_full, timerA_io_full }; + assign io_apb_PRDATA[31:17] = 15'h0000; + assign io_apb_PREADY = 1'h1; + assign io_apb_PSLVERROR = 1'h0; +endmodule + +module MuraxMasterArbiter(io_iBus_cmd_valid, io_iBus_cmd_ready, io_iBus_cmd_payload_pc, io_iBus_rsp_valid, io_iBus_rsp_payload_error, io_iBus_rsp_payload_inst, io_dBus_cmd_valid, io_dBus_cmd_ready, io_dBus_cmd_payload_wr, io_dBus_cmd_payload_address, io_dBus_cmd_payload_data, io_dBus_cmd_payload_size, io_dBus_rsp_ready, io_dBus_rsp_error, io_dBus_rsp_data, io_masterBus_cmd_valid, io_masterBus_cmd_ready, io_masterBus_cmd_payload_write, io_masterBus_cmd_payload_address, io_masterBus_cmd_payload_data, io_masterBus_cmd_payload_mask +, io_masterBus_rsp_valid, io_masterBus_rsp_payload_data, io_mainClk, resetCtrl_systemReset); + wire _00_; + wire _01_; + wire _02_; + wire _03_; + wire _04_; + wire _05_; + wire _06_; + wire _07_; + wire _08_; + wire _09_; + wire [3:0] _zz_io_masterBus_cmd_payload_mask; + input [31:0] io_dBus_cmd_payload_address; + wire [31:0] io_dBus_cmd_payload_address; + input [31:0] io_dBus_cmd_payload_data; + wire [31:0] io_dBus_cmd_payload_data; + input [1:0] io_dBus_cmd_payload_size; + wire [1:0] io_dBus_cmd_payload_size; + input io_dBus_cmd_payload_wr; + wire io_dBus_cmd_payload_wr; + output io_dBus_cmd_ready; + wire io_dBus_cmd_ready; + input io_dBus_cmd_valid; + wire io_dBus_cmd_valid; + output [31:0] io_dBus_rsp_data; + wire [31:0] io_dBus_rsp_data; + output io_dBus_rsp_error; + wire io_dBus_rsp_error; + output io_dBus_rsp_ready; + wire io_dBus_rsp_ready; + input [31:0] io_iBus_cmd_payload_pc; + wire [31:0] io_iBus_cmd_payload_pc; + output io_iBus_cmd_ready; + wire io_iBus_cmd_ready; + input io_iBus_cmd_valid; + wire io_iBus_cmd_valid; + output io_iBus_rsp_payload_error; + wire io_iBus_rsp_payload_error; + output [31:0] io_iBus_rsp_payload_inst; + wire [31:0] io_iBus_rsp_payload_inst; + output io_iBus_rsp_valid; + wire io_iBus_rsp_valid; + input io_mainClk; + wire io_mainClk; + wire io_masterBus_cmd_fire; + output [31:0] io_masterBus_cmd_payload_address; + wire [31:0] io_masterBus_cmd_payload_address; + output [31:0] io_masterBus_cmd_payload_data; + wire [31:0] io_masterBus_cmd_payload_data; + output [3:0] io_masterBus_cmd_payload_mask; + wire [3:0] io_masterBus_cmd_payload_mask; + output io_masterBus_cmd_payload_write; + wire io_masterBus_cmd_payload_write; + input io_masterBus_cmd_ready; + wire io_masterBus_cmd_ready; + output io_masterBus_cmd_valid; + wire io_masterBus_cmd_valid; + input [31:0] io_masterBus_rsp_payload_data; + wire [31:0] io_masterBus_rsp_payload_data; + input io_masterBus_rsp_valid; + wire io_masterBus_rsp_valid; + input resetCtrl_systemReset; + wire resetCtrl_systemReset; + wire rspPending; + wire rspTarget; + wire when_MuraxUtiles_l31; + wire when_MuraxUtiles_l36; + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) rspTarget_reg /* _10_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(io_dBus_cmd_valid), + .EN(when_MuraxUtiles_l31), + .Q(rspTarget) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) rspPending_reg /* _11_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_00_), + .EN(_01_), + .Q(rspPending) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _12_ ( + .A({ when_MuraxUtiles_l31, io_masterBus_rsp_valid }), + .Y(_01_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _13_ ( + .A(io_dBus_cmd_valid), + .B(io_dBus_cmd_payload_wr), + .Y(io_masterBus_cmd_payload_write) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _14_ ( + .A(io_masterBus_cmd_ready), + .B(_03_), + .Y(_02_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _15_ ( + .A(io_masterBus_cmd_valid), + .B(io_masterBus_cmd_ready), + .Y(io_masterBus_cmd_fire) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _16_ ( + .A(io_masterBus_cmd_fire), + .B(_04_), + .Y(when_MuraxUtiles_l31) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _17_ ( + .A(rspPending), + .B(_05_), + .Y(when_MuraxUtiles_l36) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _18_ ( + .A(io_masterBus_rsp_valid), + .B(_06_), + .Y(io_iBus_rsp_valid) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _19_ ( + .A(io_masterBus_rsp_valid), + .B(rspTarget), + .Y(io_dBus_rsp_ready) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _20_ ( + .A(io_dBus_cmd_valid), + .Y(_03_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _21_ ( + .A(io_masterBus_cmd_payload_write), + .Y(_04_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _22_ ( + .A(io_masterBus_rsp_valid), + .Y(_05_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _23_ ( + .A(rspTarget), + .Y(_06_) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _24_ ( + .A(io_iBus_cmd_valid), + .B(io_dBus_cmd_valid), + .Y(_07_) + ); + \$mux #( + .WIDTH(32'd1) + ) _25_ ( + .A(1'h0), + .B(1'h1), + .S(when_MuraxUtiles_l31), + .Y(_00_) + ); + \$mux #( + .WIDTH(32'd1) + ) _26_ ( + .A(io_masterBus_cmd_ready), + .B(1'h0), + .S(when_MuraxUtiles_l36), + .Y(io_dBus_cmd_ready) + ); + \$mux #( + .WIDTH(32'd1) + ) _27_ ( + .A(_02_), + .B(1'h0), + .S(when_MuraxUtiles_l36), + .Y(io_iBus_cmd_ready) + ); + \$pmux #( + .S_WIDTH(32'd2), + .WIDTH(32'd2) + ) _28_ ( + .A(2'h3), + .B(4'h1), + .S({ _09_, _08_ }), + .Y({ _zz_io_masterBus_cmd_payload_mask[3], _zz_io_masterBus_cmd_payload_mask[1] }) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _29_ ( + .A(io_dBus_cmd_payload_size), + .B(1'h1), + .Y(_08_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _30_ ( + .A(io_dBus_cmd_payload_size), + .Y(_09_) + ); + \$mux #( + .WIDTH(32'd1) + ) _31_ ( + .A(_07_), + .B(1'h0), + .S(when_MuraxUtiles_l36), + .Y(io_masterBus_cmd_valid) + ); + \$sshl #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd4), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd4) + ) _32_ ( + .A({ _zz_io_masterBus_cmd_payload_mask[3], _zz_io_masterBus_cmd_payload_mask[3], _zz_io_masterBus_cmd_payload_mask[1], 1'h1 }), + .B(io_dBus_cmd_payload_address[1:0]), + .Y(io_masterBus_cmd_payload_mask) + ); + \$mux #( + .WIDTH(32'd32) + ) _33_ ( + .A(io_iBus_cmd_payload_pc), + .B(io_dBus_cmd_payload_address), + .S(io_dBus_cmd_valid), + .Y(io_masterBus_cmd_payload_address) + ); + assign { _zz_io_masterBus_cmd_payload_mask[2], _zz_io_masterBus_cmd_payload_mask[0] } = { _zz_io_masterBus_cmd_payload_mask[3], 1'h1 }; + assign io_dBus_rsp_data = io_masterBus_rsp_payload_data; + assign io_dBus_rsp_error = 1'h0; + assign io_iBus_rsp_payload_error = 1'h0; + assign io_iBus_rsp_payload_inst = io_masterBus_rsp_payload_data; + assign io_masterBus_cmd_payload_data = io_dBus_cmd_payload_data; +endmodule + +module MuraxPipelinedMemoryBusRam(io_bus_cmd_valid, io_bus_cmd_ready, io_bus_cmd_payload_write, io_bus_cmd_payload_address, io_bus_cmd_payload_data, io_bus_cmd_payload_mask, io_bus_rsp_valid, io_bus_rsp_payload_data, io_mainClk, resetCtrl_systemReset); + wire [7:0] _00_; + wire [7:0] _01_; + wire [7:0] _02_; + wire [7:0] _03_; + wire _04_; + wire _05_; + wire _06_; + wire _07_; + wire _08_; + wire _09_; + wire _10_; + wire _11_; + wire _12_; + wire _13_; + wire [29:0] _zz_io_bus_rsp_payload_data; + wire [31:0] _zz_io_bus_rsp_payload_data_1; + wire [10:0] _zz_io_bus_rsp_payload_data_2; + wire _zz_io_bus_rsp_valid; + wire [31:0] _zz_ram_port0; + wire [7:0] _zz_ramsymbol_read; + wire [7:0] _zz_ramsymbol_read_1; + wire [7:0] _zz_ramsymbol_read_2; + wire [7:0] _zz_ramsymbol_read_3; + wire io_bus_cmd_fire; + input [31:0] io_bus_cmd_payload_address; + wire [31:0] io_bus_cmd_payload_address; + input [31:0] io_bus_cmd_payload_data; + wire [31:0] io_bus_cmd_payload_data; + input [3:0] io_bus_cmd_payload_mask; + wire [3:0] io_bus_cmd_payload_mask; + input io_bus_cmd_payload_write; + wire io_bus_cmd_payload_write; + output io_bus_cmd_ready; + wire io_bus_cmd_ready; + input io_bus_cmd_valid; + wire io_bus_cmd_valid; + output [31:0] io_bus_rsp_payload_data; + wire [31:0] io_bus_rsp_payload_data; + output io_bus_rsp_valid; + wire io_bus_rsp_valid; + input io_mainClk; + wire io_mainClk; + input resetCtrl_systemReset; + wire resetCtrl_systemReset; + reg [7:0] ram_symbol0 [2047:0]; + always @(posedge io_mainClk) begin + if (_00_[7]) + ram_symbol0[io_bus_cmd_payload_address[12:2]] <= io_bus_cmd_payload_data[7:0]; + end + reg [7:0] _29_; + always @(posedge io_mainClk) begin + if (io_bus_cmd_valid) begin + _29_ <= ram_symbol0[io_bus_cmd_payload_address[12:2]]; + end + end + assign _zz_ramsymbol_read = _29_; + reg [7:0] ram_symbol1 [2047:0]; + always @(posedge io_mainClk) begin + if (_01_[7]) + ram_symbol1[io_bus_cmd_payload_address[12:2]] <= io_bus_cmd_payload_data[15:8]; + end + reg [7:0] _30_; + always @(posedge io_mainClk) begin + if (io_bus_cmd_valid) begin + _30_ <= ram_symbol1[io_bus_cmd_payload_address[12:2]]; + end + end + assign _zz_ramsymbol_read_1 = _30_; + reg [7:0] ram_symbol2 [2047:0]; + always @(posedge io_mainClk) begin + if (_02_[7]) + ram_symbol2[io_bus_cmd_payload_address[12:2]] <= io_bus_cmd_payload_data[23:16]; + end + reg [7:0] _31_; + always @(posedge io_mainClk) begin + if (io_bus_cmd_valid) begin + _31_ <= ram_symbol2[io_bus_cmd_payload_address[12:2]]; + end + end + assign _zz_ramsymbol_read_2 = _31_; + reg [7:0] ram_symbol3 [2047:0]; + always @(posedge io_mainClk) begin + if (_03_[7]) + ram_symbol3[io_bus_cmd_payload_address[12:2]] <= io_bus_cmd_payload_data[31:24]; + end + reg [7:0] _32_; + always @(posedge io_mainClk) begin + if (io_bus_cmd_valid) begin + _32_ <= ram_symbol3[io_bus_cmd_payload_address[12:2]]; + end + end + assign _zz_ramsymbol_read_3 = _32_; + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _14_ ( + .A(io_bus_cmd_payload_mask[0]), + .B(io_bus_cmd_valid), + .Y(_05_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _15_ ( + .A(_05_), + .B(io_bus_cmd_payload_write), + .Y(_06_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _16_ ( + .A(io_bus_cmd_payload_mask[1]), + .B(io_bus_cmd_valid), + .Y(_07_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _17_ ( + .A(_07_), + .B(io_bus_cmd_payload_write), + .Y(_08_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _18_ ( + .A(io_bus_cmd_payload_mask[2]), + .B(io_bus_cmd_valid), + .Y(_09_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _19_ ( + .A(_09_), + .B(io_bus_cmd_payload_write), + .Y(_10_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _20_ ( + .A(io_bus_cmd_payload_mask[3]), + .B(io_bus_cmd_valid), + .Y(_11_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _21_ ( + .A(_11_), + .B(io_bus_cmd_payload_write), + .Y(_12_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _22_ ( + .A(io_bus_cmd_valid), + .B(_13_), + .Y(_04_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _23_ ( + .A(io_bus_cmd_payload_write), + .Y(_13_) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) _zz_io_bus_rsp_valid_reg /* _24_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_04_), + .Q(_zz_io_bus_rsp_valid) + ); + \$mux #( + .WIDTH(32'd1) + ) _25_ ( + .A(1'h0), + .B(1'h1), + .S(_12_), + .Y(_03_[7]) + ); + \$mux #( + .WIDTH(32'd1) + ) _26_ ( + .A(1'h0), + .B(1'h1), + .S(_10_), + .Y(_02_[7]) + ); + \$mux #( + .WIDTH(32'd1) + ) _27_ ( + .A(1'h0), + .B(1'h1), + .S(_08_), + .Y(_01_[7]) + ); + \$mux #( + .WIDTH(32'd1) + ) _28_ ( + .A(1'h0), + .B(1'h1), + .S(_06_), + .Y(_00_[7]) + ); + assign _00_[6:0] = { _00_[7], _00_[7], _00_[7], _00_[7], _00_[7], _00_[7], _00_[7] }; + assign _01_[6:0] = { _01_[7], _01_[7], _01_[7], _01_[7], _01_[7], _01_[7], _01_[7] }; + assign _02_[6:0] = { _02_[7], _02_[7], _02_[7], _02_[7], _02_[7], _02_[7], _02_[7] }; + assign _03_[6:0] = { _03_[7], _03_[7], _03_[7], _03_[7], _03_[7], _03_[7], _03_[7] }; + assign _zz_io_bus_rsp_payload_data = io_bus_cmd_payload_address[31:2]; + assign _zz_io_bus_rsp_payload_data_1 = io_bus_cmd_payload_data; + assign _zz_io_bus_rsp_payload_data_2 = io_bus_cmd_payload_address[12:2]; + assign _zz_ram_port0 = { _zz_ramsymbol_read_3, _zz_ramsymbol_read_2, _zz_ramsymbol_read_1, _zz_ramsymbol_read }; + assign io_bus_cmd_fire = io_bus_cmd_valid; + assign io_bus_cmd_ready = 1'h1; + assign io_bus_rsp_payload_data = { _zz_ramsymbol_read_3, _zz_ramsymbol_read_2, _zz_ramsymbol_read_1, _zz_ramsymbol_read }; + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid; +endmodule + +module PipelinedMemoryBusToApbBridge(io_pipelinedMemoryBus_cmd_valid, io_pipelinedMemoryBus_cmd_ready, io_pipelinedMemoryBus_cmd_payload_write, io_pipelinedMemoryBus_cmd_payload_address, io_pipelinedMemoryBus_cmd_payload_data, io_pipelinedMemoryBus_cmd_payload_mask, io_pipelinedMemoryBus_rsp_valid, io_pipelinedMemoryBus_rsp_payload_data, io_apb_PADDR, io_apb_PSEL, io_apb_PENABLE, io_apb_PREADY, io_apb_PWRITE, io_apb_PWDATA, io_apb_PRDATA, io_apb_PSLVERROR, io_mainClk, resetCtrl_systemReset); + wire _00_; + wire _01_; + wire _02_; + wire _03_; + wire _04_; + wire _05_; + wire _06_; + output [19:0] io_apb_PADDR; + wire [19:0] io_apb_PADDR; + output io_apb_PENABLE; + wire io_apb_PENABLE; + input [31:0] io_apb_PRDATA; + wire [31:0] io_apb_PRDATA; + input io_apb_PREADY; + wire io_apb_PREADY; + output io_apb_PSEL; + wire io_apb_PSEL; + input io_apb_PSLVERROR; + wire io_apb_PSLVERROR; + output [31:0] io_apb_PWDATA; + wire [31:0] io_apb_PWDATA; + output io_apb_PWRITE; + wire io_apb_PWRITE; + input io_mainClk; + wire io_mainClk; + wire io_pipelinedMemoryBus_cmd_halfPipe_fire; + wire [31:0] io_pipelinedMemoryBus_cmd_halfPipe_payload_address; + wire [31:0] io_pipelinedMemoryBus_cmd_halfPipe_payload_data; + wire io_pipelinedMemoryBus_cmd_halfPipe_payload_write; + wire io_pipelinedMemoryBus_cmd_halfPipe_ready; + wire io_pipelinedMemoryBus_cmd_halfPipe_valid; + input [31:0] io_pipelinedMemoryBus_cmd_payload_address; + wire [31:0] io_pipelinedMemoryBus_cmd_payload_address; + input [31:0] io_pipelinedMemoryBus_cmd_payload_data; + wire [31:0] io_pipelinedMemoryBus_cmd_payload_data; + input [3:0] io_pipelinedMemoryBus_cmd_payload_mask; + wire [3:0] io_pipelinedMemoryBus_cmd_payload_mask; + input io_pipelinedMemoryBus_cmd_payload_write; + wire io_pipelinedMemoryBus_cmd_payload_write; + wire [31:0] io_pipelinedMemoryBus_cmd_rData_address; + wire [31:0] io_pipelinedMemoryBus_cmd_rData_data; + wire io_pipelinedMemoryBus_cmd_rData_write; + wire io_pipelinedMemoryBus_cmd_rValid; + output io_pipelinedMemoryBus_cmd_ready; + wire io_pipelinedMemoryBus_cmd_ready; + input io_pipelinedMemoryBus_cmd_valid; + wire io_pipelinedMemoryBus_cmd_valid; + output [31:0] io_pipelinedMemoryBus_rsp_payload_data; + wire [31:0] io_pipelinedMemoryBus_rsp_payload_data; + output io_pipelinedMemoryBus_rsp_valid; + wire io_pipelinedMemoryBus_rsp_valid; + wire [31:0] pipelinedMemoryBusStage_cmd_payload_address; + wire [31:0] pipelinedMemoryBusStage_cmd_payload_data; + wire pipelinedMemoryBusStage_cmd_payload_write; + wire pipelinedMemoryBusStage_cmd_ready; + wire pipelinedMemoryBusStage_cmd_valid; + wire [31:0] pipelinedMemoryBusStage_rsp_payload_data; + wire [31:0] pipelinedMemoryBusStage_rsp_regNext_payload_data; + wire pipelinedMemoryBusStage_rsp_regNext_valid; + wire pipelinedMemoryBusStage_rsp_valid; + input resetCtrl_systemReset; + wire resetCtrl_systemReset; + wire state; + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) io_pipelinedMemoryBus_cmd_rValid_reg /* _07_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_00_), + .EN(_04_), + .Q(io_pipelinedMemoryBus_cmd_rValid) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd32) + ) _08_ ( + .CLK(io_mainClk), + .D(io_pipelinedMemoryBus_cmd_payload_data), + .EN(io_pipelinedMemoryBus_cmd_rValid), + .Q(io_pipelinedMemoryBus_cmd_rData_data) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd20) + ) _09_ ( + .CLK(io_mainClk), + .D(io_pipelinedMemoryBus_cmd_payload_address[19:0]), + .EN(io_pipelinedMemoryBus_cmd_rValid), + .Q(io_pipelinedMemoryBus_cmd_rData_address[19:0]) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd1) + ) io_pipelinedMemoryBus_cmd_rData_write_reg /* _10_ */ ( + .CLK(io_mainClk), + .D(io_pipelinedMemoryBus_cmd_payload_write), + .EN(io_pipelinedMemoryBus_cmd_rValid), + .Q(io_pipelinedMemoryBus_cmd_rData_write) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _11_ ( + .A({ io_pipelinedMemoryBus_cmd_halfPipe_fire, io_pipelinedMemoryBus_cmd_valid }), + .Y(_04_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _12_ ( + .A(io_pipelinedMemoryBus_cmd_rValid), + .B(io_pipelinedMemoryBus_cmd_halfPipe_ready), + .Y(io_pipelinedMemoryBus_cmd_halfPipe_fire) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _13_ ( + .A(io_pipelinedMemoryBus_cmd_rValid), + .Y(io_pipelinedMemoryBus_cmd_ready) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _14_ ( + .A(io_pipelinedMemoryBus_cmd_rData_write), + .Y(_05_) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd32) + ) _15_ ( + .CLK(io_mainClk), + .D(io_apb_PRDATA), + .Q(pipelinedMemoryBusStage_rsp_regNext_payload_data) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) pipelinedMemoryBusStage_rsp_regNext_valid_reg /* _16_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(pipelinedMemoryBusStage_rsp_valid), + .Q(pipelinedMemoryBusStage_rsp_regNext_valid) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) state_reg /* _17_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_01_), + .Q(state) + ); + \$mux #( + .WIDTH(32'd1) + ) _18_ ( + .A(1'h1), + .B(1'h0), + .S(io_apb_PREADY), + .Y(_06_) + ); + \$mux #( + .WIDTH(32'd1) + ) _19_ ( + .A(io_pipelinedMemoryBus_cmd_rValid), + .B(_06_), + .S(state), + .Y(_01_) + ); + \$mux #( + .WIDTH(32'd1) + ) _20_ ( + .A(1'h1), + .B(1'h0), + .S(io_pipelinedMemoryBus_cmd_halfPipe_fire), + .Y(_00_) + ); + \$mux #( + .WIDTH(32'd1) + ) _21_ ( + .A(1'h0), + .B(_05_), + .S(io_apb_PREADY), + .Y(_03_) + ); + \$mux #( + .WIDTH(32'd1) + ) _22_ ( + .A(1'h0), + .B(_03_), + .S(state), + .Y(pipelinedMemoryBusStage_rsp_valid) + ); + \$mux #( + .WIDTH(32'd1) + ) _23_ ( + .A(1'h0), + .B(1'h1), + .S(io_apb_PREADY), + .Y(_02_) + ); + \$mux #( + .WIDTH(32'd1) + ) _24_ ( + .A(1'h0), + .B(_02_), + .S(state), + .Y(io_pipelinedMemoryBus_cmd_halfPipe_ready) + ); + assign io_apb_PADDR = io_pipelinedMemoryBus_cmd_rData_address[19:0]; + assign io_apb_PENABLE = state; + assign io_apb_PSEL = io_pipelinedMemoryBus_cmd_rValid; + assign io_apb_PWDATA = io_pipelinedMemoryBus_cmd_rData_data; + assign io_apb_PWRITE = io_pipelinedMemoryBus_cmd_rData_write; + assign io_pipelinedMemoryBus_cmd_halfPipe_payload_address[19:0] = io_pipelinedMemoryBus_cmd_rData_address[19:0]; + assign io_pipelinedMemoryBus_cmd_halfPipe_payload_data = io_pipelinedMemoryBus_cmd_rData_data; + assign io_pipelinedMemoryBus_cmd_halfPipe_payload_write = io_pipelinedMemoryBus_cmd_rData_write; + assign io_pipelinedMemoryBus_cmd_halfPipe_valid = io_pipelinedMemoryBus_cmd_rValid; + assign io_pipelinedMemoryBus_cmd_rData_address[31:20] = io_pipelinedMemoryBus_cmd_halfPipe_payload_address[31:20]; + assign io_pipelinedMemoryBus_rsp_payload_data = pipelinedMemoryBusStage_rsp_regNext_payload_data; + assign io_pipelinedMemoryBus_rsp_valid = pipelinedMemoryBusStage_rsp_regNext_valid; + assign pipelinedMemoryBusStage_cmd_payload_address = { io_pipelinedMemoryBus_cmd_halfPipe_payload_address[31:20], io_pipelinedMemoryBus_cmd_rData_address[19:0] }; + assign pipelinedMemoryBusStage_cmd_payload_data = io_pipelinedMemoryBus_cmd_rData_data; + assign pipelinedMemoryBusStage_cmd_payload_write = io_pipelinedMemoryBus_cmd_rData_write; + assign pipelinedMemoryBusStage_cmd_ready = io_pipelinedMemoryBus_cmd_halfPipe_ready; + assign pipelinedMemoryBusStage_cmd_valid = io_pipelinedMemoryBus_cmd_rValid; + assign pipelinedMemoryBusStage_rsp_payload_data = io_apb_PRDATA; +endmodule + +module Prescaler(io_clear, io_limit, io_overflow, io_mainClk, resetCtrl_systemReset); + wire [15:0] _0_; + wire [15:0] _1_; + wire [15:0] _2_; + wire [15:0] counter; + input io_clear; + wire io_clear; + input [15:0] io_limit; + wire [15:0] io_limit; + input io_mainClk; + wire io_mainClk; + output io_overflow; + wire io_overflow; + input resetCtrl_systemReset; + wire resetCtrl_systemReset; + wire when_Prescaler_l17; + \$alu #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd16), + .Y_WIDTH(32'd16) + ) _3_ ( + .A(1'h1), + .B(counter), + .BI(1'h0), + .CI(1'h0), + .CO(_2_), + .X(_1_), + .Y(_0_) + ); + \$sdff #( + .CLK_POLARITY(32'd1), + .SRST_POLARITY(32'd1), + .SRST_VALUE(16'h0000), + .WIDTH(32'd16) + ) _4_ ( + .CLK(io_mainClk), + .D(_0_), + .Q(counter), + .SRST(when_Prescaler_l17) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd16), + .B_SIGNED(32'd0), + .B_WIDTH(32'd16), + .Y_WIDTH(32'd1) + ) _5_ ( + .A(counter), + .B(io_limit), + .Y(io_overflow) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _6_ ( + .A(io_clear), + .B(io_overflow), + .Y(when_Prescaler_l17) + ); +endmodule + +module StreamFifo(io_push_valid, io_push_ready, io_push_payload, io_pop_valid, io_pop_ready, io_pop_payload, io_flush, io_occupancy, io_availability, io_mainClk, resetCtrl_systemReset); + wire [7:0] _00_; + wire _01_; + wire _02_; + wire [3:0] _03_; + wire [3:0] _04_; + wire [3:0] _05_; + wire [3:0] _06_; + wire [3:0] _07_; + wire [3:0] _08_; + wire [3:0] _09_; + wire [3:0] _10_; + wire [3:0] _11_; + wire [3:0] _12_; + wire _13_; + wire _14_; + wire _15_; + wire _16_; + wire _17_; + wire _zz_1; + wire [3:0] _zz_io_availability; + wire _zz_io_pop_payload; + wire _zz_io_pop_valid; + wire [3:0] _zz_logic_popPtr_valueNext; + wire _zz_logic_popPtr_valueNext_1; + wire [3:0] _zz_logic_pushPtr_valueNext; + wire _zz_logic_pushPtr_valueNext_1; + wire [7:0] _zz_logic_ram_port0; + output [4:0] io_availability; + wire [4:0] io_availability; + input io_flush; + wire io_flush; + input io_mainClk; + wire io_mainClk; + output [4:0] io_occupancy; + wire [4:0] io_occupancy; + output [7:0] io_pop_payload; + wire [7:0] io_pop_payload; + input io_pop_ready; + wire io_pop_ready; + output io_pop_valid; + wire io_pop_valid; + input [7:0] io_push_payload; + wire [7:0] io_push_payload; + output io_push_ready; + wire io_push_ready; + input io_push_valid; + wire io_push_valid; + wire logic_empty; + wire logic_full; + wire [3:0] logic_popPtr_value; + wire [3:0] logic_popPtr_valueNext; + wire logic_popPtr_willClear; + wire logic_popPtr_willIncrement; + wire logic_popping; + wire [3:0] logic_ptrDif; + wire logic_ptrMatch; + wire [3:0] logic_pushPtr_value; + wire [3:0] logic_pushPtr_valueNext; + wire logic_pushPtr_willClear; + wire logic_pushPtr_willIncrement; + wire logic_pushing; + wire logic_risingOccupancy; + input resetCtrl_systemReset; + wire resetCtrl_systemReset; + wire when_Stream_l954; + reg [7:0] logic_ram [15:0]; + always @(posedge io_mainClk) begin + if (_00_[7]) + logic_ram[logic_pushPtr_value] <= io_push_payload; + end + reg [7:0] _47_; + always @(posedge io_mainClk) begin + _47_ <= logic_ram[logic_popPtr_valueNext]; + end + assign _zz_logic_ram_port0 = _47_; + \$alu #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd4), + .Y_WIDTH(32'd4) + ) _18_ ( + .A(_zz_1), + .B(logic_pushPtr_value), + .BI(1'h0), + .CI(1'h0), + .CO(_09_), + .X(_05_), + .Y(_03_) + ); + \$alu #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd4), + .Y_WIDTH(32'd4) + ) _19_ ( + .A(_zz_logic_popPtr_valueNext_1), + .B(logic_popPtr_value), + .BI(1'h0), + .CI(1'h0), + .CO(_10_), + .X(_06_), + .Y(_04_) + ); + \$alu #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd4), + .B_SIGNED(32'd0), + .B_WIDTH(32'd4), + .Y_WIDTH(32'd4) + ) _20_ ( + .A(logic_popPtr_value), + .B(logic_pushPtr_value), + .BI(1'h1), + .CI(1'h1), + .CO(_11_), + .X(_07_), + .Y(_zz_io_availability) + ); + \$alu #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd4), + .B_SIGNED(32'd0), + .B_WIDTH(32'd4), + .Y_WIDTH(32'd4) + ) _21_ ( + .A(logic_pushPtr_value), + .B(logic_popPtr_value), + .BI(1'h1), + .CI(1'h1), + .CO(_12_), + .X(_08_), + .Y(logic_ptrDif) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd4), + .Y_WIDTH(32'd1) + ) _22_ ( + .A(_08_), + .Y(logic_ptrMatch) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) logic_risingOccupancy_reg /* _23_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_02_), + .EN(_13_), + .Q(logic_risingOccupancy) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _24_ ( + .A({ when_Stream_l954, io_flush }), + .Y(_13_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd4), + .B_SIGNED(32'd0), + .B_WIDTH(32'd4), + .Y_WIDTH(32'd1) + ) _25_ ( + .A(logic_popPtr_valueNext), + .B(logic_pushPtr_value), + .Y(_01_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _26_ ( + .A(io_push_valid), + .B(io_push_ready), + .Y(logic_pushing) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _27_ ( + .A(io_pop_valid), + .B(io_pop_ready), + .Y(logic_popping) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _28_ ( + .A(logic_ptrMatch), + .B(_15_), + .Y(logic_empty) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _29_ ( + .A(logic_ptrMatch), + .B(logic_risingOccupancy), + .Y(logic_full) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _30_ ( + .A(_zz_io_pop_valid), + .B(io_push_ready), + .Y(_14_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _31_ ( + .A(_16_), + .B(_17_), + .Y(io_pop_valid) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _32_ ( + .A(logic_risingOccupancy), + .Y(_15_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _33_ ( + .A(logic_full), + .Y(io_push_ready) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _34_ ( + .A(logic_empty), + .Y(_16_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _35_ ( + .A(_14_), + .Y(_17_) + ); + \$ne #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _36_ ( + .A(logic_pushing), + .B(logic_popping), + .Y(when_Stream_l954) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(4'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd4) + ) _37_ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(logic_pushPtr_valueNext), + .Q(logic_pushPtr_value) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(4'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd4) + ) _38_ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(logic_popPtr_valueNext), + .Q(logic_popPtr_value) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) _zz_io_pop_valid_reg /* _39_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_01_), + .Q(_zz_io_pop_valid) + ); + \$mux #( + .WIDTH(32'd1) + ) _40_ ( + .A(logic_pushing), + .B(1'h0), + .S(io_flush), + .Y(_02_) + ); + \$mux #( + .WIDTH(32'd4) + ) _41_ ( + .A(_04_), + .B(4'h0), + .S(logic_popPtr_willClear), + .Y(logic_popPtr_valueNext) + ); + \$mux #( + .WIDTH(32'd1) + ) _42_ ( + .A(1'h0), + .B(1'h1), + .S(io_flush), + .Y(logic_popPtr_willClear) + ); + \$mux #( + .WIDTH(32'd1) + ) _43_ ( + .A(1'h0), + .B(1'h1), + .S(logic_popping), + .Y(_zz_logic_popPtr_valueNext_1) + ); + \$mux #( + .WIDTH(32'd4) + ) _44_ ( + .A(_03_), + .B(4'h0), + .S(logic_popPtr_willClear), + .Y(logic_pushPtr_valueNext) + ); + \$mux #( + .WIDTH(32'd1) + ) _45_ ( + .A(1'h0), + .B(1'h1), + .S(logic_pushing), + .Y(_zz_1) + ); + \$mux #( + .WIDTH(32'd1) + ) _46_ ( + .A(1'h0), + .B(1'h1), + .S(_zz_1), + .Y(_00_[7]) + ); + assign _00_[6:0] = { _00_[7], _00_[7], _00_[7], _00_[7], _00_[7], _00_[7], _00_[7] }; + assign _zz_io_pop_payload = 1'h1; + assign _zz_logic_popPtr_valueNext = { 3'h0, _zz_logic_popPtr_valueNext_1 }; + assign _zz_logic_pushPtr_valueNext = { 3'h0, _zz_1 }; + assign _zz_logic_pushPtr_valueNext_1 = _zz_1; + assign io_availability = { logic_empty, _zz_io_availability }; + assign io_occupancy = { logic_full, logic_ptrDif }; + assign io_pop_payload = _zz_logic_ram_port0; + assign logic_popPtr_willIncrement = _zz_logic_popPtr_valueNext_1; + assign logic_pushPtr_willClear = logic_popPtr_willClear; + assign logic_pushPtr_willIncrement = _zz_1; +endmodule + +module StreamFifoLowLatency(io_push_valid, io_push_ready, io_push_payload_error, io_push_payload_inst, io_pop_valid, io_pop_ready, io_pop_payload_error, io_pop_payload_inst, io_flush, io_occupancy, io_mainClk, resetCtrl_systemReset); + wire _00_; + wire _01_; + wire [32:0] _zz_readed_error; + wire [32:0] _zz_readed_error_1; + wire [32:0] _zz_readed_error_2; + wire full; + input io_flush; + wire io_flush; + input io_mainClk; + wire io_mainClk; + output io_occupancy; + wire io_occupancy; + output io_pop_payload_error; + wire io_pop_payload_error; + output [31:0] io_pop_payload_inst; + wire [31:0] io_pop_payload_inst; + input io_pop_ready; + wire io_pop_ready; + output io_pop_valid; + wire io_pop_valid; + input io_push_payload_error; + wire io_push_payload_error; + input [31:0] io_push_payload_inst; + wire [31:0] io_push_payload_inst; + output io_push_ready; + wire io_push_ready; + input io_push_valid; + wire io_push_valid; + wire popPtr_willOverflowIfInc; + wire popping; + wire ptrMatch; + wire pushPtr_willOverflowIfInc; + wire pushing; + wire readed_error; + wire [31:0] readed_inst; + input resetCtrl_systemReset; + wire resetCtrl_systemReset; + wire risingOccupancy; + wire when_Phase_l623; + wire when_Stream_l1019; + wire when_Stream_l1032; + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) risingOccupancy_reg /* _02_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_00_), + .EN(_01_), + .Q(risingOccupancy) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd33) + ) _03_ ( + .CLK(io_mainClk), + .D({ io_push_payload_inst, io_push_payload_error }), + .EN(when_Phase_l623), + .Q(_zz_readed_error_2) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _04_ ( + .A({ when_Stream_l1032, io_flush }), + .Y(_01_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _05_ ( + .A(io_push_valid), + .B(io_push_ready), + .Y(pushing) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _06_ ( + .A(io_pop_valid), + .B(io_pop_ready), + .Y(popping) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _07_ ( + .A(risingOccupancy), + .Y(io_push_ready) + ); + \$ne #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _08_ ( + .A(pushing), + .B(popping), + .Y(when_Stream_l1032) + ); + \$mux #( + .WIDTH(32'd1) + ) _09_ ( + .A(pushing), + .B(1'h0), + .S(io_flush), + .Y(_00_) + ); + \$mux #( + .WIDTH(32'd32) + ) _10_ ( + .A(io_push_payload_inst), + .B(_zz_readed_error_2[32:1]), + .S(risingOccupancy), + .Y(io_pop_payload_inst) + ); + \$mux #( + .WIDTH(32'd1) + ) _11_ ( + .A(io_push_payload_error), + .B(_zz_readed_error_2[0]), + .S(risingOccupancy), + .Y(io_pop_payload_error) + ); + \$mux #( + .WIDTH(32'd1) + ) _12_ ( + .A(io_push_valid), + .B(1'h1), + .S(risingOccupancy), + .Y(io_pop_valid) + ); + \$mux #( + .WIDTH(32'd1) + ) _13_ ( + .A(1'h0), + .B(1'h1), + .S(pushing), + .Y(when_Phase_l623) + ); + assign _zz_readed_error = _zz_readed_error_2; + assign _zz_readed_error_1 = _zz_readed_error_2; + assign full = risingOccupancy; + assign io_occupancy = risingOccupancy; + assign popPtr_willOverflowIfInc = 1'h1; + assign ptrMatch = 1'h1; + assign pushPtr_willOverflowIfInc = 1'h1; + assign readed_error = _zz_readed_error_2[0]; + assign readed_inst = _zz_readed_error_2[32:1]; + assign when_Stream_l1019 = risingOccupancy; +endmodule + +module SystemDebugger(io_remote_cmd_valid, io_remote_cmd_ready, io_remote_cmd_payload_last, io_remote_cmd_payload_fragment, io_remote_rsp_valid, io_remote_rsp_ready, io_remote_rsp_payload_error, io_remote_rsp_payload_data, io_mem_cmd_valid, io_mem_cmd_ready, io_mem_cmd_payload_address, io_mem_cmd_payload_data, io_mem_cmd_payload_wr, io_mem_cmd_payload_size, io_mem_rsp_valid, io_mem_rsp_payload, io_mainClk, resetCtrl_mainClkReset); + wire _00_; + wire _01_; + wire [2:0] _02_; + wire [2:0] _03_; + wire [2:0] _04_; + wire _05_; + wire _06_; + wire _07_; + wire _08_; + wire _09_; + wire _10_; + wire _11_; + wire _12_; + wire _13_; + wire _14_; + wire _15_; + wire _16_; + wire [2:0] _17_; + wire _18_; + wire _19_; + wire _20_; + wire [66:0] _zz_io_mem_cmd_payload_address; + wire [2:0] dispatcher_counter; + wire dispatcher_dataLoaded; + wire [66:0] dispatcher_dataShifter; + wire [7:0] dispatcher_header; + wire dispatcher_headerLoaded; + wire [7:0] dispatcher_headerShifter; + input io_mainClk; + wire io_mainClk; + wire io_mem_cmd_isStall; + output [31:0] io_mem_cmd_payload_address; + wire [31:0] io_mem_cmd_payload_address; + output [31:0] io_mem_cmd_payload_data; + wire [31:0] io_mem_cmd_payload_data; + output [1:0] io_mem_cmd_payload_size; + wire [1:0] io_mem_cmd_payload_size; + output io_mem_cmd_payload_wr; + wire io_mem_cmd_payload_wr; + input io_mem_cmd_ready; + wire io_mem_cmd_ready; + output io_mem_cmd_valid; + wire io_mem_cmd_valid; + input [31:0] io_mem_rsp_payload; + wire [31:0] io_mem_rsp_payload; + input io_mem_rsp_valid; + wire io_mem_rsp_valid; + input io_remote_cmd_payload_fragment; + wire io_remote_cmd_payload_fragment; + input io_remote_cmd_payload_last; + wire io_remote_cmd_payload_last; + output io_remote_cmd_ready; + wire io_remote_cmd_ready; + input io_remote_cmd_valid; + wire io_remote_cmd_valid; + output [31:0] io_remote_rsp_payload_data; + wire [31:0] io_remote_rsp_payload_data; + output io_remote_rsp_payload_error; + wire io_remote_rsp_payload_error; + input io_remote_rsp_ready; + wire io_remote_rsp_ready; + output io_remote_rsp_valid; + wire io_remote_rsp_valid; + input resetCtrl_mainClkReset; + wire resetCtrl_mainClkReset; + wire when_Fragment_l349; + wire when_Fragment_l372; + \$alu #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd3) + ) _21_ ( + .A(1'h1), + .B(dispatcher_counter), + .BI(1'h0), + .CI(1'h0), + .CO(_04_), + .X(_03_), + .Y(_02_) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(3'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd3) + ) _22_ ( + .ARST(resetCtrl_mainClkReset), + .CLK(io_mainClk), + .D(_17_), + .EN(_08_), + .Q(dispatcher_counter) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) dispatcher_headerLoaded_reg /* _23_ */ ( + .ARST(resetCtrl_mainClkReset), + .CLK(io_mainClk), + .D(_01_), + .EN(_06_), + .Q(dispatcher_headerLoaded) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) dispatcher_dataLoaded_reg /* _24_ */ ( + .ARST(resetCtrl_mainClkReset), + .CLK(io_mainClk), + .D(_00_), + .EN(_09_), + .Q(dispatcher_dataLoaded) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd8) + ) _25_ ( + .CLK(io_mainClk), + .D({ io_remote_cmd_payload_fragment, dispatcher_headerShifter[7:1] }), + .EN(_10_), + .Q(dispatcher_headerShifter) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd67) + ) _26_ ( + .CLK(io_mainClk), + .D({ io_remote_cmd_payload_fragment, dispatcher_dataShifter[66:1] }), + .EN(_11_), + .Q(dispatcher_dataShifter) + ); + \$ne #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _27_ ( + .A({ dispatcher_headerLoaded, io_remote_cmd_payload_last }), + .B(2'h2), + .Y(_05_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _28_ ( + .A({ when_Fragment_l372, io_remote_cmd_valid }), + .Y(_06_) + ); + \$ne #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _29_ ( + .A({ when_Fragment_l372, io_remote_cmd_payload_last, io_remote_cmd_valid }), + .B(1'h1), + .Y(_07_) + ); + \$not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _30_ ( + .A(dispatcher_headerLoaded), + .Y(_12_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _31_ ( + .A({ _05_, io_remote_cmd_valid }), + .Y(_08_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _32_ ( + .A({ _06_, _07_ }), + .Y(_09_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _33_ ( + .A({ _12_, io_remote_cmd_valid }), + .Y(_10_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _34_ ( + .A({ dispatcher_headerLoaded, io_remote_cmd_valid }), + .Y(_11_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _35_ ( + .A(dispatcher_counter), + .B(3'h7), + .Y(when_Fragment_l349) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd8), + .Y_WIDTH(32'd1) + ) _36_ ( + .A(dispatcher_headerShifter), + .Y(_13_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _37_ ( + .A(dispatcher_dataLoaded), + .B(_13_), + .Y(io_mem_cmd_valid) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _38_ ( + .A(io_mem_cmd_valid), + .B(_15_), + .Y(io_mem_cmd_isStall) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _39_ ( + .A(dispatcher_headerLoaded), + .B(dispatcher_dataLoaded), + .Y(_14_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _40_ ( + .A(_14_), + .B(_16_), + .Y(when_Fragment_l372) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _41_ ( + .A(dispatcher_dataLoaded), + .Y(io_remote_cmd_ready) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _42_ ( + .A(io_mem_cmd_ready), + .Y(_15_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _43_ ( + .A(io_mem_cmd_isStall), + .Y(_16_) + ); + \$mux #( + .WIDTH(32'd3) + ) _44_ ( + .A(_02_), + .B(3'h0), + .S(io_remote_cmd_payload_last), + .Y(_17_) + ); + \$mux #( + .WIDTH(32'd1) + ) _45_ ( + .A(1'h0), + .B(1'h1), + .S(when_Fragment_l349), + .Y(_18_) + ); + \$mux #( + .WIDTH(32'd1) + ) _46_ ( + .A(_18_), + .B(1'h1), + .S(dispatcher_headerLoaded), + .Y(_19_) + ); + \$mux #( + .WIDTH(32'd1) + ) _47_ ( + .A(_19_), + .B(1'h1), + .S(io_remote_cmd_payload_last), + .Y(_20_) + ); + \$mux #( + .WIDTH(32'd1) + ) _48_ ( + .A(_20_), + .B(1'h0), + .S(when_Fragment_l372), + .Y(_01_) + ); + \$mux #( + .WIDTH(32'd1) + ) _49_ ( + .A(1'h1), + .B(1'h0), + .S(when_Fragment_l372), + .Y(_00_) + ); + assign _zz_io_mem_cmd_payload_address = dispatcher_dataShifter; + assign dispatcher_header = dispatcher_headerShifter; + assign io_mem_cmd_payload_address = dispatcher_dataShifter[31:0]; + assign io_mem_cmd_payload_data = dispatcher_dataShifter[63:32]; + assign io_mem_cmd_payload_size = dispatcher_dataShifter[66:65]; + assign io_mem_cmd_payload_wr = dispatcher_dataShifter[64]; + assign io_remote_rsp_payload_data = io_mem_rsp_payload; + assign io_remote_rsp_payload_error = 1'h0; + assign io_remote_rsp_valid = io_mem_rsp_valid; +endmodule + +module Timer(io_tick, io_clear, io_limit, io_full, io_value, io_mainClk, resetCtrl_systemReset); + wire _00_; + wire [15:0] _01_; + wire [15:0] _02_; + wire [15:0] _03_; + wire _04_; + wire _05_; + wire _06_; + wire [15:0] _zz_counter; + wire _zz_counter_1; + wire [15:0] counter; + wire inhibitFull; + input io_clear; + wire io_clear; + output io_full; + wire io_full; + input [15:0] io_limit; + wire [15:0] io_limit; + input io_mainClk; + wire io_mainClk; + input io_tick; + wire io_tick; + output [15:0] io_value; + wire [15:0] io_value; + wire limitHit; + input resetCtrl_systemReset; + wire resetCtrl_systemReset; + \$alu #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd16), + .Y_WIDTH(32'd16) + ) _07_ ( + .A(_zz_counter_1), + .B(counter), + .BI(1'h0), + .CI(1'h0), + .CO(_03_), + .X(_02_), + .Y(_01_) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) inhibitFull_reg /* _08_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_00_), + .EN(_04_), + .Q(inhibitFull) + ); + \$sdffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .SRST_POLARITY(32'd1), + .SRST_VALUE(16'h0000), + .WIDTH(32'd16) + ) _09_ ( + .CLK(io_mainClk), + .D(_01_), + .EN(io_tick), + .Q(counter), + .SRST(io_clear) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _10_ ( + .A({ io_tick, io_clear }), + .Y(_04_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd16), + .B_SIGNED(32'd0), + .B_WIDTH(32'd16), + .Y_WIDTH(32'd1) + ) _11_ ( + .A(counter), + .B(io_limit), + .Y(limitHit) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _12_ ( + .A(limitHit), + .B(io_tick), + .Y(_05_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _13_ ( + .A(_05_), + .B(_06_), + .Y(io_full) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _14_ ( + .A(limitHit), + .Y(_zz_counter_1) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _15_ ( + .A(inhibitFull), + .Y(_06_) + ); + \$mux #( + .WIDTH(32'd1) + ) _16_ ( + .A(limitHit), + .B(1'h0), + .S(io_clear), + .Y(_00_) + ); + assign _zz_counter = { 15'h0000, _zz_counter_1 }; + assign io_value = counter; +endmodule + +module UartCtrl(io_config_frame_dataLength, io_config_frame_stop, io_config_frame_parity, io_config_clockDivider, io_write_valid, io_write_ready, io_write_payload, io_read_valid, io_read_ready, io_read_payload, io_uart_txd, io_uart_rxd, io_readError, io_writeBreak, io_readBreak, io_mainClk, resetCtrl_systemReset); + wire [19:0] _00_; + wire [19:0] _01_; + wire [19:0] _02_; + wire [19:0] _03_; + wire [19:0] clockDivider_counter; + wire clockDivider_tick; + wire clockDivider_tickReg; + input [19:0] io_config_clockDivider; + wire [19:0] io_config_clockDivider; + input [2:0] io_config_frame_dataLength; + wire [2:0] io_config_frame_dataLength; + input [1:0] io_config_frame_parity; + wire [1:0] io_config_frame_parity; + input io_config_frame_stop; + wire io_config_frame_stop; + input io_mainClk; + wire io_mainClk; + output io_readBreak; + wire io_readBreak; + output io_readError; + wire io_readError; + output [7:0] io_read_payload; + wire [7:0] io_read_payload; + input io_read_ready; + wire io_read_ready; + output io_read_valid; + wire io_read_valid; + input io_uart_rxd; + wire io_uart_rxd; + output io_uart_txd; + wire io_uart_txd; + input io_writeBreak; + wire io_writeBreak; + input [7:0] io_write_payload; + wire [7:0] io_write_payload; + output io_write_ready; + wire io_write_ready; + wire [7:0] io_write_thrown_payload; + wire io_write_thrown_ready; + wire io_write_thrown_valid; + input io_write_valid; + wire io_write_valid; + input resetCtrl_systemReset; + wire resetCtrl_systemReset; + wire rx_io_break; + wire rx_io_error; + wire [7:0] rx_io_read_payload; + wire rx_io_read_valid; + wire rx_io_rts; + wire tx_io_txd; + wire tx_io_write_ready; + \$alu #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd20), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd20) + ) _04_ ( + .A(clockDivider_counter), + .B(1'h1), + .BI(1'h1), + .CI(1'h1), + .CO(_02_), + .X(_01_), + .Y(_03_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd20), + .Y_WIDTH(32'd1) + ) _05_ ( + .A(clockDivider_counter), + .Y(clockDivider_tick) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(20'h00000), + .CLK_POLARITY(1'h1), + .WIDTH(32'd20) + ) _06_ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_00_), + .Q(clockDivider_counter) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) clockDivider_tickReg_reg /* _07_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(clockDivider_tick), + .Q(clockDivider_tickReg) + ); + \$mux #( + .WIDTH(32'd20) + ) _08_ ( + .A(_03_), + .B(io_config_clockDivider), + .S(clockDivider_tick), + .Y(_00_) + ); + \$mux #( + .WIDTH(32'd1) + ) _09_ ( + .A(tx_io_write_ready), + .B(1'h1), + .S(rx_io_break), + .Y(io_write_ready) + ); + \$mux #( + .WIDTH(32'd1) + ) _10_ ( + .A(io_write_valid), + .B(1'h0), + .S(rx_io_break), + .Y(io_write_thrown_valid) + ); + UartCtrlRx rx ( + .io_break(rx_io_break), + .io_configFrame_dataLength(io_config_frame_dataLength), + .io_configFrame_parity(io_config_frame_parity), + .io_configFrame_stop(io_config_frame_stop), + .io_error(rx_io_error), + .io_mainClk(io_mainClk), + .io_read_payload(rx_io_read_payload), + .io_read_ready(io_read_ready), + .io_read_valid(rx_io_read_valid), + .io_rts(rx_io_rts), + .io_rxd(io_uart_rxd), + .io_samplingTick(clockDivider_tickReg), + .resetCtrl_systemReset(resetCtrl_systemReset) + ); + UartCtrlTx tx ( + .io_break(io_writeBreak), + .io_configFrame_dataLength(io_config_frame_dataLength), + .io_configFrame_parity(io_config_frame_parity), + .io_configFrame_stop(io_config_frame_stop), + .io_cts(1'h0), + .io_mainClk(io_mainClk), + .io_samplingTick(clockDivider_tickReg), + .io_txd(tx_io_txd), + .io_write_payload(io_write_payload), + .io_write_ready(tx_io_write_ready), + .io_write_valid(io_write_thrown_valid), + .resetCtrl_systemReset(resetCtrl_systemReset) + ); + assign io_readBreak = rx_io_break; + assign io_readError = rx_io_error; + assign io_read_payload = rx_io_read_payload; + assign io_read_valid = rx_io_read_valid; + assign io_uart_txd = tx_io_txd; + assign io_write_thrown_payload = io_write_payload; + assign io_write_thrown_ready = tx_io_write_ready; +endmodule + +module UartCtrlRx(io_configFrame_dataLength, io_configFrame_stop, io_configFrame_parity, io_samplingTick, io_read_valid, io_read_ready, io_read_payload, io_rxd, io_rts, io_error, io_break, io_mainClk, resetCtrl_systemReset); + wire _000_; + wire [2:0] _001_; + wire [2:0] _002_; + wire [6:0] _003_; + wire _004_; + wire _005_; + wire _006_; + wire _007_; + wire _008_; + wire _009_; + wire _010_; + wire _011_; + wire [6:0] _012_; + wire [2:0] _013_; + wire [7:0] _014_; + wire [6:0] _015_; + wire [2:0] _016_; + wire [2:0] _017_; + wire [6:0] _018_; + wire [2:0] _019_; + wire [2:0] _020_; + wire _021_; + wire _022_; + wire _023_; + wire _024_; + wire _025_; + wire _026_; + wire _027_; + wire _028_; + wire _029_; + wire _030_; + wire _031_; + wire _032_; + wire _033_; + wire _034_; + wire _035_; + wire _036_; + wire [4:0] _037_; + wire _038_; + wire _039_; + wire _040_; + wire _041_; + wire _042_; + wire _043_; + wire _044_; + wire _045_; + wire _046_; + wire _047_; + wire _048_; + wire _049_; + wire _050_; + wire _051_; + wire _052_; + wire _053_; + wire _054_; + wire _055_; + wire _056_; + wire _057_; + wire _058_; + wire _059_; + wire _060_; + wire [7:0] _061_; + wire [7:0] _062_; + wire _063_; + wire _064_; + wire [2:0] _065_; + wire [2:0] _066_; + wire [2:0] _067_; + wire [2:0] _068_; + wire [2:0] _069_; + wire [2:0] _070_; + wire [2:0] _071_; + wire _072_; + wire _073_; + wire _074_; + wire _075_; + wire _076_; + wire [7:0] _077_; + wire [7:0] _078_; + wire [2:0] _079_; + wire _080_; + wire _zz_io_rts; + wire [2:0] _zz_when_UartCtrlRx_l139; + wire _zz_when_UartCtrlRx_l139_1; + wire [2:0] bitCounter_value; + wire [2:0] bitTimer_counter; + wire bitTimer_tick; + wire [6:0] break_counter; + wire break_valid; + output io_break; + wire io_break; + input [2:0] io_configFrame_dataLength; + wire [2:0] io_configFrame_dataLength; + input [1:0] io_configFrame_parity; + wire [1:0] io_configFrame_parity; + input io_configFrame_stop; + wire io_configFrame_stop; + output io_error; + wire io_error; + input io_mainClk; + wire io_mainClk; + output [7:0] io_read_payload; + wire [7:0] io_read_payload; + input io_read_ready; + wire io_read_ready; + output io_read_valid; + wire io_read_valid; + output io_rts; + wire io_rts; + input io_rxd; + wire io_rxd; + wire io_rxd_buffercc_io_dataOut; + input io_samplingTick; + wire io_samplingTick; + input resetCtrl_systemReset; + wire resetCtrl_systemReset; + wire sampler_samples_0; + wire sampler_samples_1; + wire sampler_samples_2; + wire sampler_synchroniser; + wire sampler_tick; + wire sampler_value; + wire stateMachine_parity; + wire [7:0] stateMachine_shifter; + wire [4:0] stateMachine_state; + wire stateMachine_validReg; + wire when_UartCtrlRx_l103; + wire when_UartCtrlRx_l111; + wire when_UartCtrlRx_l113; + wire when_UartCtrlRx_l125; + wire when_UartCtrlRx_l139; + wire when_UartCtrlRx_l43; + wire when_UartCtrlRx_l69; + wire when_UartCtrlRx_l93; + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd8), + .B_SIGNED(32'd0), + .B_WIDTH(32'd8), + .Y_WIDTH(32'd8) + ) _081_ ( + .A(stateMachine_shifter), + .B(_061_), + .Y(_014_) + ); + \$alu #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd7), + .Y_WIDTH(32'd7) + ) _082_ ( + .A(1'h1), + .B(break_counter), + .BI(1'h0), + .CI(1'h0), + .CO(_018_), + .X(_015_), + .Y(_012_) + ); + \$alu #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd3) + ) _083_ ( + .A(1'h1), + .B(bitCounter_value), + .BI(1'h0), + .CI(1'h0), + .CO(_019_), + .X(_016_), + .Y(_013_) + ); + \$alu #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd3) + ) _084_ ( + .A(bitTimer_counter), + .B(1'h1), + .BI(1'h1), + .CI(1'h1), + .CO(_020_), + .X(_017_), + .Y(_079_) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(7'h00), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd7) + ) _085_ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_003_), + .EN(_049_), + .Q(break_counter) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h1), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) sampler_samples_2_reg /* _086_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(sampler_samples_1), + .EN(io_samplingTick), + .Q(sampler_samples_2) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h1), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) sampler_samples_1_reg /* _087_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(io_rxd_buffercc_io_dataOut), + .EN(io_samplingTick), + .Q(sampler_samples_1) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd8) + ) _088_ ( + .CLK(io_mainClk), + .D(_062_), + .EN(_050_), + .Q(stateMachine_shifter) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _089_ ( + .A(_038_), + .B(stateMachine_state[1]), + .Y(_021_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _090_ ( + .A(_039_), + .B(stateMachine_state[1]), + .Y(_022_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _091_ ( + .A(_040_), + .B(stateMachine_state[3]), + .Y(_023_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _092_ ( + .A(_041_), + .B(stateMachine_state[4]), + .Y(_024_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _093_ ( + .A(_042_), + .B(stateMachine_state[0]), + .Y(_025_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _094_ ( + .A(_043_), + .B(stateMachine_state[1]), + .Y(_026_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _095_ ( + .A(_044_), + .B(stateMachine_state[1]), + .Y(_027_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _096_ ( + .A(_045_), + .B(stateMachine_state[2]), + .Y(_028_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _097_ ( + .A(_046_), + .B(stateMachine_state[4]), + .Y(_029_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _098_ ( + .A(_038_), + .B(stateMachine_state[3]), + .Y(_030_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _099_ ( + .A(_044_), + .B(stateMachine_state[2]), + .Y(_031_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _100_ ( + .A(_047_), + .B(stateMachine_state[2]), + .Y(_032_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _101_ ( + .A(_044_), + .B(stateMachine_state[3]), + .Y(_033_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _102_ ( + .A(when_UartCtrlRx_l93), + .B(stateMachine_state[0]), + .Y(_034_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _103_ ( + .A(_044_), + .B(stateMachine_state[4]), + .Y(_035_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _104_ ( + .A(_048_), + .B(stateMachine_state[2]), + .Y(_036_) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .Y_WIDTH(32'd1) + ) _105_ ( + .A({ _021_, _022_, _023_, _024_, _025_ }), + .Y(_037_[0]) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd4), + .Y_WIDTH(32'd1) + ) _106_ ( + .A({ _029_, _028_, _027_, _026_ }), + .Y(_037_[1]) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _107_ ( + .A({ _032_, _031_, _030_ }), + .Y(_037_[2]) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _108_ ( + .A({ _034_, _033_ }), + .Y(_037_[3]) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _109_ ( + .A({ _036_, _035_ }), + .Y(_037_[4]) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(5'h01), + .CLK_POLARITY(1'h1), + .WIDTH(32'd5) + ) _110_ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_037_), + .Q(stateMachine_state) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _111_ ( + .A({ when_UartCtrlRx_l139, bitTimer_tick, sampler_value }), + .B(3'h7), + .Y(_039_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _112_ ( + .A({ bitTimer_tick, sampler_value }), + .B(2'h3), + .Y(_040_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _113_ ( + .A({ when_UartCtrlRx_l125, bitTimer_tick }), + .B(1'h1), + .Y(_041_) + ); + \$not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _114_ ( + .A(when_UartCtrlRx_l93), + .Y(_042_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _115_ ( + .A({ when_UartCtrlRx_l139, bitTimer_tick, sampler_value }), + .B(2'h3), + .Y(_043_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _116_ ( + .A({ when_UartCtrlRx_l113, when_UartCtrlRx_l111, bitTimer_tick }), + .B(3'h7), + .Y(_045_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _117_ ( + .A({ when_UartCtrlRx_l125, bitTimer_tick }), + .B(2'h3), + .Y(_046_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _118_ ( + .A({ bitTimer_tick, sampler_value }), + .B(2'h2), + .Y(_038_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _119_ ( + .A({ when_UartCtrlRx_l111, bitTimer_tick }), + .B(1'h1), + .Y(_047_) + ); + \$not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _120_ ( + .A(bitTimer_tick), + .Y(_044_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _121_ ( + .A({ when_UartCtrlRx_l113, when_UartCtrlRx_l111, bitTimer_tick }), + .B(2'h3), + .Y(_048_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _122_ ( + .A({ when_UartCtrlRx_l69, sampler_value }), + .Y(_049_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _123_ ( + .A({ bitTimer_tick, stateMachine_state[2] }), + .Y(_050_) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _124_ ( + .A({ stateMachine_state[3:2], stateMachine_state[0] }), + .Y(_051_) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _125_ ( + .A(stateMachine_state[4:3]), + .Y(_052_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _126_ ( + .A(bitTimer_counter), + .Y(when_UartCtrlRx_l43) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd7), + .B_SIGNED(32'd0), + .B_WIDTH(32'd7), + .Y_WIDTH(32'd1) + ) _127_ ( + .A(break_counter), + .B(7'h41), + .Y(break_valid) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _128_ ( + .A(bitCounter_value), + .B(io_configFrame_dataLength), + .Y(when_UartCtrlRx_l111) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _129_ ( + .A(io_configFrame_parity), + .Y(when_UartCtrlRx_l113) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _130_ ( + .A(stateMachine_parity), + .B(sampler_value), + .Y(when_UartCtrlRx_l125) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _131_ ( + .A(bitCounter_value), + .B(_zz_when_UartCtrlRx_l139_1), + .Y(when_UartCtrlRx_l139) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _132_ ( + .A(io_configFrame_parity), + .B(2'h2), + .Y(_053_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _133_ ( + .A(io_samplingTick), + .B(_058_), + .Y(when_UartCtrlRx_l69) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _134_ ( + .A(sampler_tick), + .B(_059_), + .Y(_054_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _135_ ( + .A(_054_), + .B(_058_), + .Y(when_UartCtrlRx_l93) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _136_ ( + .A(io_rxd_buffercc_io_dataOut), + .B(sampler_samples_1), + .Y(_055_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _137_ ( + .A(io_rxd_buffercc_io_dataOut), + .B(sampler_samples_2), + .Y(_056_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _138_ ( + .A(sampler_samples_1), + .B(sampler_samples_2), + .Y(_057_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _139_ ( + .A(break_valid), + .Y(_058_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _140_ ( + .A(sampler_value), + .Y(_059_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _141_ ( + .A(io_read_ready), + .Y(_000_) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _142_ ( + .A(_055_), + .B(_056_), + .Y(_060_) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _143_ ( + .A(_060_), + .B(_057_), + .Y(_004_) + ); + \$not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd8), + .Y_WIDTH(32'd8) + ) _144_ ( + .A(_077_), + .Y(_061_) + ); + \$or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd8), + .B_SIGNED(32'd0), + .B_WIDTH(32'd8), + .Y_WIDTH(32'd8) + ) _145_ ( + .A(_014_), + .B(_078_), + .Y(_062_) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd3) + ) _146_ ( + .CLK(io_mainClk), + .D(_002_), + .Q(bitTimer_counter) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd3) + ) _147_ ( + .CLK(io_mainClk), + .D(_001_), + .Q(bitCounter_value) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) stateMachine_parity_reg /* _148_ */ ( + .CLK(io_mainClk), + .D(_005_), + .Q(stateMachine_parity) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) _zz_io_rts_reg /* _149_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_000_), + .Q(_zz_io_rts) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h1), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) sampler_value_reg /* _150_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_004_), + .Q(sampler_value) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) sampler_tick_reg /* _151_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(io_samplingTick), + .Q(sampler_tick) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) stateMachine_validReg_reg /* _152_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_006_), + .Q(stateMachine_validReg) + ); + \$mux #( + .WIDTH(32'd1) + ) _153_ ( + .A(stateMachine_parity), + .B(_080_), + .S(bitTimer_tick), + .Y(_063_) + ); + \$mux #( + .WIDTH(32'd1) + ) _154_ ( + .A(_063_), + .B(_053_), + .S(bitTimer_tick), + .Y(_064_) + ); + \$mux #( + .WIDTH(32'd1) + ) _155_ ( + .A(_063_), + .B(_064_), + .S(stateMachine_state[3]), + .Y(_005_) + ); + \$mux #( + .WIDTH(32'd3) + ) _156_ ( + .A(bitCounter_value), + .B(_013_), + .S(bitTimer_tick), + .Y(_065_) + ); + \$mux #( + .WIDTH(32'd3) + ) _157_ ( + .A(_065_), + .B(3'h0), + .S(bitTimer_tick), + .Y(_066_) + ); + \$pmux #( + .S_WIDTH(32'd2), + .WIDTH(32'd3) + ) _158_ ( + .A(_065_), + .B({ _068_, _066_ }), + .S({ stateMachine_state[2], _052_ }), + .Y(_001_) + ); + \$mux #( + .WIDTH(32'd3) + ) _159_ ( + .A(_065_), + .B(3'h0), + .S(when_UartCtrlRx_l111), + .Y(_067_) + ); + \$mux #( + .WIDTH(32'd3) + ) _160_ ( + .A(_065_), + .B(_067_), + .S(bitTimer_tick), + .Y(_068_) + ); + \$mux #( + .WIDTH(32'd3) + ) _161_ ( + .A(_079_), + .B(3'h4), + .S(when_UartCtrlRx_l43), + .Y(_069_) + ); + \$mux #( + .WIDTH(32'd3) + ) _162_ ( + .A(bitTimer_counter), + .B(_069_), + .S(sampler_tick), + .Y(_070_) + ); + \$mux #( + .WIDTH(32'd3) + ) _163_ ( + .A(_070_), + .B(3'h1), + .S(when_UartCtrlRx_l93), + .Y(_071_) + ); + \$mux #( + .WIDTH(32'd3) + ) _164_ ( + .A(_070_), + .B(_071_), + .S(stateMachine_state[0]), + .Y(_002_) + ); + \$mux #( + .WIDTH(32'd1) + ) _165_ ( + .A(1'h0), + .B(1'h1), + .S(when_UartCtrlRx_l125), + .Y(_072_) + ); + \$mux #( + .WIDTH(32'd1) + ) _166_ ( + .A(1'h0), + .B(_072_), + .S(bitTimer_tick), + .Y(_073_) + ); + \$pmux #( + .S_WIDTH(32'd2), + .WIDTH(32'd1) + ) _167_ ( + .A(1'h0), + .B({ _076_, _073_ }), + .S({ stateMachine_state[2], stateMachine_state[4] }), + .Y(_006_) + ); + \$mux #( + .WIDTH(32'd1) + ) _168_ ( + .A(1'h0), + .B(1'h1), + .S(when_UartCtrlRx_l113), + .Y(_074_) + ); + \$mux #( + .WIDTH(32'd1) + ) _169_ ( + .A(1'h0), + .B(_074_), + .S(when_UartCtrlRx_l111), + .Y(_075_) + ); + \$mux #( + .WIDTH(32'd1) + ) _170_ ( + .A(1'h0), + .B(_075_), + .S(bitTimer_tick), + .Y(_076_) + ); + \$mux #( + .WIDTH(32'd7) + ) _171_ ( + .A(_012_), + .B(7'h00), + .S(sampler_value), + .Y(_003_) + ); + \$mux #( + .WIDTH(32'd1) + ) _172_ ( + .A(1'h0), + .B(1'h1), + .S(when_UartCtrlRx_l43), + .Y(_007_) + ); + \$mux #( + .WIDTH(32'd1) + ) _173_ ( + .A(1'h0), + .B(_007_), + .S(sampler_tick), + .Y(bitTimer_tick) + ); + \$mux #( + .WIDTH(32'd1) + ) _174_ ( + .A(1'h1), + .B(1'h0), + .S(sampler_value), + .Y(_011_) + ); + \$mux #( + .WIDTH(32'd1) + ) _175_ ( + .A(1'h0), + .B(_011_), + .S(bitTimer_tick), + .Y(_010_) + ); + \$mux #( + .WIDTH(32'd1) + ) _176_ ( + .A(1'h1), + .B(1'h0), + .S(when_UartCtrlRx_l125), + .Y(_009_) + ); + \$mux #( + .WIDTH(32'd1) + ) _177_ ( + .A(1'h0), + .B(_009_), + .S(bitTimer_tick), + .Y(_008_) + ); + \$pmux #( + .S_WIDTH(32'd2), + .WIDTH(32'd1) + ) _178_ ( + .A(_010_), + .B({ 1'h0, _008_ }), + .S({ _051_, stateMachine_state[4] }), + .Y(io_error) + ); + \$shl #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd8) + ) _179_ ( + .A(1'h1), + .B(bitCounter_value), + .Y(_077_) + ); + \$shl #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd8) + ) _180_ ( + .A(sampler_value), + .B(bitCounter_value), + .Y(_078_) + ); + \$mux #( + .WIDTH(32'd1) + ) _181_ ( + .A(1'h0), + .B(1'h1), + .S(io_configFrame_stop), + .Y(_zz_when_UartCtrlRx_l139_1) + ); + \$xor #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _182_ ( + .A(stateMachine_parity), + .B(sampler_value), + .Y(_080_) + ); + BufferCC io_rxd_buffercc ( + .io_dataIn(io_rxd), + .io_dataOut(io_rxd_buffercc_io_dataOut), + .io_mainClk(io_mainClk), + .resetCtrl_systemReset(resetCtrl_systemReset) + ); + assign _zz_when_UartCtrlRx_l139 = { 2'h0, _zz_when_UartCtrlRx_l139_1 }; + assign io_break = break_valid; + assign io_read_payload = stateMachine_shifter; + assign io_read_valid = stateMachine_validReg; + assign io_rts = _zz_io_rts; + assign sampler_samples_0 = io_rxd_buffercc_io_dataOut; + assign sampler_synchroniser = io_rxd_buffercc_io_dataOut; + assign when_UartCtrlRx_l103 = sampler_value; +endmodule + +module UartCtrlTx(io_configFrame_dataLength, io_configFrame_stop, io_configFrame_parity, io_samplingTick, io_write_valid, io_write_ready, io_write_payload, io_cts, io_txd, io_break, io_mainClk, resetCtrl_systemReset); + wire _000_; + wire _001_; + wire [2:0] _002_; + wire _003_; + wire _004_; + wire [2:0] _005_; + wire [2:0] _006_; + wire [2:0] _007_; + wire [2:0] _008_; + wire [2:0] _009_; + wire [2:0] _010_; + wire _011_; + wire _012_; + wire _013_; + wire _014_; + wire _015_; + wire _016_; + wire _017_; + wire _018_; + wire _019_; + wire _020_; + wire _021_; + wire _022_; + wire _023_; + wire _024_; + wire [4:0] _025_; + wire _026_; + wire _027_; + wire _028_; + wire _029_; + wire _030_; + wire _031_; + wire _032_; + wire _033_; + wire _034_; + wire _035_; + wire _036_; + wire _037_; + wire _038_; + wire [2:0] _039_; + wire [2:0] _040_; + wire [2:0] _041_; + wire [2:0] _042_; + wire _043_; + wire _044_; + wire _045_; + wire _046_; + wire [2:0] _zz_clockDivider_counter_valueNext; + wire _zz_clockDivider_counter_valueNext_1; + wire _zz_io_txd; + wire [2:0] _zz_when_UartCtrlTx_l93; + wire _zz_when_UartCtrlTx_l93_1; + wire [2:0] clockDivider_counter_value; + wire [2:0] clockDivider_counter_valueNext; + wire clockDivider_counter_willClear; + wire clockDivider_counter_willIncrement; + wire clockDivider_counter_willOverflow; + wire clockDivider_counter_willOverflowIfInc; + input io_break; + wire io_break; + input [2:0] io_configFrame_dataLength; + wire [2:0] io_configFrame_dataLength; + input [1:0] io_configFrame_parity; + wire [1:0] io_configFrame_parity; + input io_configFrame_stop; + wire io_configFrame_stop; + input io_cts; + wire io_cts; + input io_mainClk; + wire io_mainClk; + input io_samplingTick; + wire io_samplingTick; + output io_txd; + wire io_txd; + input [7:0] io_write_payload; + wire [7:0] io_write_payload; + output io_write_ready; + wire io_write_ready; + input io_write_valid; + wire io_write_valid; + input resetCtrl_systemReset; + wire resetCtrl_systemReset; + wire stateMachine_parity; + wire [4:0] stateMachine_state; + wire stateMachine_txd; + wire [2:0] tickCounter_value; + wire when_UartCtrlTx_l58; + wire when_UartCtrlTx_l73; + wire when_UartCtrlTx_l76; + wire when_UartCtrlTx_l93; + \$alu #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd3) + ) _047_ ( + .A(clockDivider_counter_willIncrement), + .B(clockDivider_counter_value), + .BI(1'h0), + .CI(1'h0), + .CO(_009_), + .X(_007_), + .Y(_005_) + ); + \$alu #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd3) + ) _048_ ( + .A(1'h1), + .B(tickCounter_value), + .BI(1'h0), + .CI(1'h0), + .CO(_010_), + .X(_008_), + .Y(_006_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _049_ ( + .A(_026_), + .B(stateMachine_state[1]), + .Y(_011_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _050_ ( + .A(_027_), + .B(stateMachine_state[0]), + .Y(_012_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _051_ ( + .A(_028_), + .B(stateMachine_state[1]), + .Y(_013_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _052_ ( + .A(_029_), + .B(stateMachine_state[2]), + .Y(_014_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _053_ ( + .A(_030_), + .B(stateMachine_state[1]), + .Y(_015_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _054_ ( + .A(clockDivider_counter_willOverflow), + .B(stateMachine_state[4]), + .Y(_016_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _055_ ( + .A(_028_), + .B(stateMachine_state[2]), + .Y(_017_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _056_ ( + .A(_031_), + .B(stateMachine_state[2]), + .Y(_018_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _057_ ( + .A(clockDivider_counter_willOverflow), + .B(stateMachine_state[3]), + .Y(_019_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _058_ ( + .A(_032_), + .B(stateMachine_state[1]), + .Y(_020_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _059_ ( + .A(_028_), + .B(stateMachine_state[3]), + .Y(_021_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _060_ ( + .A(when_UartCtrlTx_l58), + .B(stateMachine_state[0]), + .Y(_022_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _061_ ( + .A(_028_), + .B(stateMachine_state[4]), + .Y(_023_) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _062_ ( + .A(_033_), + .B(stateMachine_state[2]), + .Y(_024_) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _063_ ( + .A({ _012_, _011_ }), + .Y(_025_[0]) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd4), + .Y_WIDTH(32'd1) + ) _064_ ( + .A({ _016_, _015_, _014_, _013_ }), + .Y(_025_[1]) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _065_ ( + .A({ _019_, _018_, _017_ }), + .Y(_025_[2]) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _066_ ( + .A({ _021_, _020_, _022_ }), + .Y(_025_[3]) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _067_ ( + .A({ _024_, _023_ }), + .Y(_025_[4]) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(5'h01), + .CLK_POLARITY(1'h1), + .WIDTH(32'd5) + ) _068_ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_025_), + .Q(stateMachine_state) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _069_ ( + .A({ when_UartCtrlTx_l93, clockDivider_counter_willOverflow, io_write_valid }), + .B(3'h6), + .Y(_026_) + ); + \$not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _070_ ( + .A(when_UartCtrlTx_l58), + .Y(_027_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _071_ ( + .A({ when_UartCtrlTx_l76, when_UartCtrlTx_l73, clockDivider_counter_willOverflow }), + .B(3'h7), + .Y(_029_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _072_ ( + .A({ when_UartCtrlTx_l93, clockDivider_counter_willOverflow }), + .B(1'h1), + .Y(_030_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _073_ ( + .A({ when_UartCtrlTx_l73, clockDivider_counter_willOverflow }), + .B(1'h1), + .Y(_031_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _074_ ( + .A({ when_UartCtrlTx_l93, clockDivider_counter_willOverflow, io_write_valid }), + .B(3'h7), + .Y(_032_) + ); + \$not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _075_ ( + .A(clockDivider_counter_willOverflow), + .Y(_028_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _076_ ( + .A({ when_UartCtrlTx_l76, when_UartCtrlTx_l73, clockDivider_counter_willOverflow }), + .B(2'h3), + .Y(_033_) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _077_ ( + .A(stateMachine_state[4:3]), + .Y(_034_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _078_ ( + .A(clockDivider_counter_value), + .B(3'h4), + .Y(clockDivider_counter_willOverflowIfInc) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _079_ ( + .A(tickCounter_value), + .B(io_configFrame_dataLength), + .Y(when_UartCtrlTx_l73) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _080_ ( + .A(io_configFrame_parity), + .Y(when_UartCtrlTx_l76) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _081_ ( + .A(tickCounter_value), + .B(_zz_when_UartCtrlTx_l93_1), + .Y(when_UartCtrlTx_l93) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _082_ ( + .A(io_configFrame_parity), + .B(2'h2), + .Y(_035_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _083_ ( + .A(clockDivider_counter_willOverflowIfInc), + .B(clockDivider_counter_willIncrement), + .Y(clockDivider_counter_willOverflow) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _084_ ( + .A(io_write_valid), + .B(_037_), + .Y(_036_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _085_ ( + .A(_036_), + .B(clockDivider_counter_willOverflow), + .Y(when_UartCtrlTx_l58) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _086_ ( + .A(stateMachine_txd), + .B(_038_), + .Y(_000_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _087_ ( + .A(io_cts), + .Y(_037_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _088_ ( + .A(io_break), + .Y(_038_) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) stateMachine_parity_reg /* _089_ */ ( + .CLK(io_mainClk), + .D(_001_), + .Q(stateMachine_parity) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd3) + ) _090_ ( + .CLK(io_mainClk), + .D(_002_), + .Q(tickCounter_value) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(3'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd3) + ) _091_ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(clockDivider_counter_valueNext), + .Q(clockDivider_counter_value) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h1), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) _zz_io_txd_reg /* _092_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_000_), + .Q(_zz_io_txd) + ); + \$mux #( + .WIDTH(32'd3) + ) _093_ ( + .A(tickCounter_value), + .B(_006_), + .S(clockDivider_counter_willOverflow), + .Y(_039_) + ); + \$mux #( + .WIDTH(32'd3) + ) _094_ ( + .A(_039_), + .B(3'h0), + .S(clockDivider_counter_willOverflow), + .Y(_040_) + ); + \$pmux #( + .S_WIDTH(32'd2), + .WIDTH(32'd3) + ) _095_ ( + .A(_039_), + .B({ _042_, _040_ }), + .S({ stateMachine_state[2], _034_ }), + .Y(_002_) + ); + \$mux #( + .WIDTH(32'd3) + ) _096_ ( + .A(_039_), + .B(3'h0), + .S(when_UartCtrlTx_l73), + .Y(_041_) + ); + \$mux #( + .WIDTH(32'd3) + ) _097_ ( + .A(_039_), + .B(_041_), + .S(clockDivider_counter_willOverflow), + .Y(_042_) + ); + \$mux #( + .WIDTH(32'd1) + ) _098_ ( + .A(stateMachine_parity), + .B(_046_), + .S(clockDivider_counter_willOverflow), + .Y(_043_) + ); + \$mux #( + .WIDTH(32'd1) + ) _099_ ( + .A(_043_), + .B(_035_), + .S(clockDivider_counter_willOverflow), + .Y(_044_) + ); + \$mux #( + .WIDTH(32'd1) + ) _100_ ( + .A(_043_), + .B(_044_), + .S(stateMachine_state[3]), + .Y(_001_) + ); + \$mux #( + .WIDTH(32'd1) + ) _101_ ( + .A(io_break), + .B(1'h1), + .S(when_UartCtrlTx_l73), + .Y(_004_) + ); + \$mux #( + .WIDTH(32'd1) + ) _102_ ( + .A(io_break), + .B(_004_), + .S(clockDivider_counter_willOverflow), + .Y(_003_) + ); + \$mux #( + .WIDTH(32'd1) + ) _103_ ( + .A(io_break), + .B(_003_), + .S(stateMachine_state[2]), + .Y(io_write_ready) + ); + \$pmux #( + .S_WIDTH(32'd3), + .WIDTH(32'd1) + ) _104_ ( + .A(1'h1), + .B({ 1'h0, _045_, stateMachine_parity }), + .S({ stateMachine_state[3:2], stateMachine_state[4] }), + .Y(stateMachine_txd) + ); + \$mux #( + .WIDTH(32'd3) + ) _105_ ( + .A(_005_), + .B(3'h0), + .S(clockDivider_counter_willOverflow), + .Y(clockDivider_counter_valueNext) + ); + \$mux #( + .WIDTH(32'd1) + ) _106_ ( + .A(1'h0), + .B(1'h1), + .S(io_samplingTick), + .Y(clockDivider_counter_willIncrement) + ); + \$shiftx #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd8), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _107_ ( + .A(io_write_payload), + .B(tickCounter_value), + .Y(_045_) + ); + \$mux #( + .WIDTH(32'd1) + ) _108_ ( + .A(1'h0), + .B(1'h1), + .S(io_configFrame_stop), + .Y(_zz_when_UartCtrlTx_l93_1) + ); + \$xor #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _109_ ( + .A(stateMachine_parity), + .B(stateMachine_txd), + .Y(_046_) + ); + assign _zz_clockDivider_counter_valueNext = { 2'h0, clockDivider_counter_willIncrement }; + assign _zz_clockDivider_counter_valueNext_1 = clockDivider_counter_willIncrement; + assign _zz_when_UartCtrlTx_l93 = { 2'h0, _zz_when_UartCtrlTx_l93_1 }; + assign clockDivider_counter_willClear = 1'h0; + assign io_txd = _zz_io_txd; +endmodule + +module VexRiscv(iBus_cmd_valid, iBus_cmd_ready, iBus_cmd_payload_pc, iBus_rsp_valid, iBus_rsp_payload_error, iBus_rsp_payload_inst, timerInterrupt, externalInterrupt, softwareInterrupt, debug_bus_cmd_valid, debug_bus_cmd_ready, debug_bus_cmd_payload_wr, debug_bus_cmd_payload_address, debug_bus_cmd_payload_data, debug_bus_rsp_data, debug_resetOut, dBus_cmd_valid, dBus_cmd_ready, dBus_cmd_payload_wr, dBus_cmd_payload_address, dBus_cmd_payload_data +, dBus_cmd_payload_size, dBus_rsp_ready, dBus_rsp_error, dBus_rsp_data, io_mainClk, resetCtrl_systemReset, resetCtrl_mainClkReset); + wire [31:0] _000_; + wire _001_; + wire _002_; + wire _003_; + wire _004_; + wire [1:0] _005_; + wire _006_; + wire _007_; + wire _008_; + wire [31:0] _009_; + wire _010_; + wire _011_; + wire _012_; + wire _013_; + wire [2:0] _014_; + wire _015_; + wire _016_; + wire [31:0] _017_; + wire _018_; + wire _019_; + wire _020_; + wire _021_; + wire [2:0] _022_; + wire _023_; + wire _024_; + wire _025_; + wire _026_; + wire _027_; + wire _028_; + wire [31:0] _029_; + wire _030_; + wire [31:0] _031_; + wire _032_; + wire _033_; + wire _034_; + wire _035_; + wire _036_; + wire _037_; + wire _038_; + wire _039_; + wire _040_; + wire [31:0] _041_; + wire _042_; + wire _043_; + wire _044_; + wire _045_; + wire _046_; + wire _047_; + wire _048_; + wire _049_; + wire _050_; + wire _051_; + wire _052_; + wire _053_; + wire _054_; + wire _055_; + wire _056_; + wire _057_; + wire _058_; + wire [31:0] _059_; + wire [12:0] _060_; + wire [31:0] _061_; + wire [2:0] _062_; + wire [4:0] _063_; + wire [31:0] _064_; + wire [31:0] _065_; + wire _066_; + wire [2:0] _067_; + wire [4:0] _068_; + wire [31:0] _069_; + wire [31:0] _070_; + wire _071_; + wire _072_; + wire _073_; + wire _074_; + wire _075_; + wire _076_; + wire _077_; + wire _078_; + wire _079_; + wire _080_; + wire _081_; + wire _082_; + wire _083_; + wire _084_; + wire _085_; + wire _086_; + wire _087_; + wire _088_; + wire _089_; + wire _090_; + wire _091_; + wire _092_; + wire _093_; + wire _094_; + wire _095_; + wire _096_; + wire _097_; + wire _098_; + wire _099_; + wire _100_; + wire _101_; + wire [2:0] _102_; + wire _103_; + wire [6:0] _104_; + wire _105_; + wire _106_; + wire _107_; + wire [1:0] _108_; + wire [31:0] _109_; + wire _110_; + wire _111_; + wire _112_; + wire _113_; + wire _114_; + wire _115_; + wire _116_; + wire _117_; + wire _118_; + wire _119_; + wire _120_; + wire _121_; + wire _122_; + wire _123_; + wire _124_; + wire _125_; + wire _126_; + wire _127_; + wire _128_; + wire _129_; + wire _130_; + wire _131_; + wire _132_; + wire _133_; + wire _134_; + wire _135_; + wire _136_; + wire _137_; + wire _138_; + wire _139_; + wire _140_; + wire _141_; + wire _142_; + wire _143_; + wire _144_; + wire _145_; + wire _146_; + wire _147_; + wire _148_; + wire _149_; + wire _150_; + wire _151_; + wire _152_; + wire _153_; + wire _154_; + wire _155_; + wire _156_; + wire _157_; + wire _158_; + wire _159_; + wire _160_; + wire _161_; + wire _162_; + wire _163_; + wire _164_; + wire _165_; + wire _166_; + wire _167_; + wire _168_; + wire _169_; + wire _170_; + wire _171_; + wire _172_; + wire _173_; + wire _174_; + wire _175_; + wire [31:0] _176_; + wire [31:0] _177_; + wire _178_; + wire _179_; + wire _180_; + wire _181_; + wire _182_; + wire _183_; + wire _184_; + wire _185_; + wire _186_; + wire _187_; + wire _188_; + wire _189_; + wire _190_; + wire _191_; + wire _192_; + wire _193_; + wire _194_; + wire _195_; + wire _196_; + wire _197_; + wire _198_; + wire _199_; + wire _200_; + wire _201_; + wire _202_; + wire _203_; + wire _204_; + wire [1:0] _205_; + wire [1:0] _206_; + wire _207_; + wire [1:0] _208_; + wire [1:0] _209_; + wire _210_; + wire _211_; + wire _212_; + wire _213_; + wire _214_; + wire _215_; + wire _216_; + wire _217_; + wire _218_; + wire _219_; + wire _220_; + wire _221_; + wire _222_; + wire _223_; + wire _224_; + wire _225_; + wire _226_; + wire _227_; + wire _228_; + wire _229_; + wire _230_; + wire _231_; + wire _232_; + wire _233_; + wire _234_; + wire _235_; + wire _236_; + wire _237_; + wire _238_; + wire _239_; + wire _240_; + wire _241_; + wire _242_; + wire [2:0] _243_; + wire [4:0] _244_; + wire [31:0] _245_; + wire _246_; + wire [31:0] _247_; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_jumpInterface_valid; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [12:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_exception; + wire CsrPlugin_hadException; + wire CsrPlugin_inWfi; + wire CsrPlugin_interruptJump; + wire [3:0] CsrPlugin_interrupt_code; + wire [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_interrupt_valid; + wire [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_jumpInterface_valid; + wire CsrPlugin_lastStageWasWfi; + wire [3:0] CsrPlugin_mcause_exceptionCode; + wire CsrPlugin_mcause_interrupt; + wire [31:0] CsrPlugin_mepc; + wire CsrPlugin_mie_MEIE; + wire CsrPlugin_mie_MSIE; + wire CsrPlugin_mie_MTIE; + wire CsrPlugin_mip_MEIP; + wire CsrPlugin_mip_MSIP; + wire CsrPlugin_mip_MTIP; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + wire CsrPlugin_mstatus_MIE; + wire CsrPlugin_mstatus_MPIE; + wire [1:0] CsrPlugin_mstatus_MPP; + wire [29:0] CsrPlugin_mtvec_base; + wire [1:0] CsrPlugin_mtvec_mode; + wire CsrPlugin_pipelineLiberator_active; + wire CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_pipelineLiberator_pcValids_0; + wire CsrPlugin_pipelineLiberator_pcValids_1; + wire CsrPlugin_pipelineLiberator_pcValids_2; + wire [1:0] CsrPlugin_privilege; + wire [1:0] CsrPlugin_targetPrivilege; + wire [3:0] CsrPlugin_trapCause; + wire [29:0] CsrPlugin_xtvec_base; + wire DebugPlugin_allowEBreak; + wire [31:0] DebugPlugin_busReadDataReg; + wire DebugPlugin_debugUsed; + wire DebugPlugin_disableEbreak; + wire DebugPlugin_haltIt; + wire DebugPlugin_haltedByBreak; + wire DebugPlugin_isPipBusy; + wire DebugPlugin_resetIt; + wire DebugPlugin_resetIt_regNext; + wire DebugPlugin_stepIt; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire HazardSimplePlugin_src0Hazard; + wire HazardSimplePlugin_src1Hazard; + wire [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + wire HazardSimplePlugin_writeBackBuffer_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + wire HazardSimplePlugin_writeBackWrites_valid; + wire IBusSimplePlugin_cmdFork_canEmit; + wire IBusSimplePlugin_cmd_fire; + wire [31:0] IBusSimplePlugin_cmd_payload_pc; + wire IBusSimplePlugin_cmd_ready; + wire IBusSimplePlugin_cmd_valid; + wire IBusSimplePlugin_externalFlush; + wire IBusSimplePlugin_fetchPc_booted; + wire IBusSimplePlugin_fetchPc_correction; + wire IBusSimplePlugin_fetchPc_inc; + wire IBusSimplePlugin_fetchPc_output_fire_1; + wire [31:0] IBusSimplePlugin_fetchPc_output_payload; + wire IBusSimplePlugin_fetchPc_output_ready; + wire IBusSimplePlugin_fetchPc_output_valid; + wire [31:0] IBusSimplePlugin_fetchPc_pc; + wire [31:0] IBusSimplePlugin_fetchPc_pcReg; + wire IBusSimplePlugin_fetchPc_pcRegPropagate; + wire IBusSimplePlugin_fetcherHalt; + wire IBusSimplePlugin_iBusRsp_flush; + wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_pc; + wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + wire IBusSimplePlugin_iBusRsp_output_ready; + wire IBusSimplePlugin_iBusRsp_output_valid; + wire IBusSimplePlugin_iBusRsp_redoFetch; + wire IBusSimplePlugin_iBusRsp_stages_0_halt; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_0_input_ready; + wire IBusSimplePlugin_iBusRsp_stages_0_input_valid; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload; + wire IBusSimplePlugin_iBusRsp_stages_0_output_ready; + wire IBusSimplePlugin_iBusRsp_stages_0_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_halt; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_1_input_ready; + wire IBusSimplePlugin_iBusRsp_stages_1_input_valid; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload; + wire IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload; + wire IBusSimplePlugin_iBusRsp_stages_1_output_ready; + wire IBusSimplePlugin_iBusRsp_stages_1_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_2_halt; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_2_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_2_input_ready; + wire IBusSimplePlugin_iBusRsp_stages_2_input_valid; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_2_output_payload; + wire IBusSimplePlugin_iBusRsp_stages_2_output_ready; + wire IBusSimplePlugin_iBusRsp_stages_2_output_valid; + wire IBusSimplePlugin_incomingInstruction; + wire [31:0] IBusSimplePlugin_injectionPort_payload; + wire IBusSimplePlugin_injectionPort_ready; + wire IBusSimplePlugin_injectionPort_valid; + wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc; + wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + wire IBusSimplePlugin_injector_decodeInput_ready; + wire IBusSimplePlugin_injector_decodeInput_valid; + wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; + wire IBusSimplePlugin_jump_pcLoad_valid; + wire IBusSimplePlugin_pending_dec; + wire IBusSimplePlugin_pending_inc; + wire [2:0] IBusSimplePlugin_pending_next; + wire [2:0] IBusSimplePlugin_pending_value; + wire IBusSimplePlugin_rspJoin_exceptionDetected; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; + wire IBusSimplePlugin_rspJoin_join_fire; + wire IBusSimplePlugin_rspJoin_join_fire_1; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + wire IBusSimplePlugin_rspJoin_join_ready; + wire IBusSimplePlugin_rspJoin_join_valid; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; + wire [2:0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter; + wire IBusSimplePlugin_rspJoin_rspBuffer_flush; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_ready; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_valid; + wire _zz_1; + wire _zz_2; + wire [12:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [11:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + wire [11:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + wire [12:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire [31:0] _zz_IBusSimplePlugin_fetchPc_pc; + wire [2:0] _zz_IBusSimplePlugin_fetchPc_pc_1; + wire _zz_IBusSimplePlugin_iBusRsp_output_valid; + wire _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_1; + wire _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2; + wire _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready; + wire [31:0] _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload; + wire _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire _zz_IBusSimplePlugin_iBusRsp_stages_2_input_ready; + wire [31:0] _zz_IBusSimplePlugin_injector_decodeInput_payload_pc; + wire [31:0] _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + wire _zz_IBusSimplePlugin_injector_decodeInput_valid; + wire [1:0] _zz_IBusSimplePlugin_jump_pcLoad_payload; + wire _zz_IBusSimplePlugin_jump_pcLoad_payload_1; + wire [1:0] _zz_IBusSimplePlugin_jump_pcLoad_payload_2; + wire [2:0] _zz_IBusSimplePlugin_pending_next_1; + wire _zz_IBusSimplePlugin_pending_next_2; + wire [2:0] _zz_IBusSimplePlugin_pending_next_3; + wire _zz_IBusSimplePlugin_pending_next_4; + wire [2:0] _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter; + wire _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1; + wire [31:0] _zz_RegFilePlugin_regFile_port0; + wire [31:0] _zz_RegFilePlugin_regFile_port1; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_1; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_10; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_11; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_12; + wire _zz__zz_decode_BRANCH_CTRL_2_13; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_14; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_15; + wire [18:0] _zz__zz_decode_BRANCH_CTRL_2_16; + wire _zz__zz_decode_BRANCH_CTRL_2_17; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_18; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_19; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_2; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_20; + wire _zz__zz_decode_BRANCH_CTRL_2_21; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_22; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_23; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_24; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_25; + wire _zz__zz_decode_BRANCH_CTRL_2_26; + wire [14:0] _zz__zz_decode_BRANCH_CTRL_2_27; + wire _zz__zz_decode_BRANCH_CTRL_2_28; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_29; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_3; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_30; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_31; + wire _zz__zz_decode_BRANCH_CTRL_2_32; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_33; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_34; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_35; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_36; + wire _zz__zz_decode_BRANCH_CTRL_2_37; + wire _zz__zz_decode_BRANCH_CTRL_2_39; + wire _zz__zz_decode_BRANCH_CTRL_2_4; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_41; + wire [10:0] _zz__zz_decode_BRANCH_CTRL_2_42; + wire _zz__zz_decode_BRANCH_CTRL_2_43; + wire _zz__zz_decode_BRANCH_CTRL_2_44; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_45; + wire _zz__zz_decode_BRANCH_CTRL_2_46; + wire _zz__zz_decode_BRANCH_CTRL_2_47; + wire _zz__zz_decode_BRANCH_CTRL_2_48; + wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_49; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_5; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_50; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_51; + wire _zz__zz_decode_BRANCH_CTRL_2_52; + wire _zz__zz_decode_BRANCH_CTRL_2_53; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_54; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_55; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_56; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_57; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_58; + wire [6:0] _zz__zz_decode_BRANCH_CTRL_2_59; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_6; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_60; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_61; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_62; + wire _zz__zz_decode_BRANCH_CTRL_2_63; + wire _zz__zz_decode_BRANCH_CTRL_2_64; + wire _zz__zz_decode_BRANCH_CTRL_2_65; + wire _zz__zz_decode_BRANCH_CTRL_2_66; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_67; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_68; + wire _zz__zz_decode_BRANCH_CTRL_2_69; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_7; + wire [3:0] _zz__zz_decode_BRANCH_CTRL_2_70; + wire _zz__zz_decode_BRANCH_CTRL_2_71; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_72; + wire _zz__zz_decode_BRANCH_CTRL_2_73; + wire _zz__zz_decode_BRANCH_CTRL_2_74; + wire _zz__zz_decode_BRANCH_CTRL_2_75; + wire _zz__zz_decode_BRANCH_CTRL_2_76; + wire _zz__zz_decode_BRANCH_CTRL_2_77; + wire _zz__zz_decode_BRANCH_CTRL_2_78; + wire _zz__zz_decode_BRANCH_CTRL_2_79; + wire _zz__zz_decode_BRANCH_CTRL_2_8; + wire _zz__zz_decode_BRANCH_CTRL_2_80; + wire _zz__zz_decode_BRANCH_CTRL_2_81; + wire _zz__zz_decode_BRANCH_CTRL_2_82; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_9; + wire [2:0] _zz__zz_decode_SRC1_1; + wire [4:0] _zz__zz_decode_SRC1_1_1; + wire [11:0] _zz__zz_decode_SRC2_4; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire _zz__zz_execute_REGFILE_WRITE_DATA; + wire [31:0] _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1; + wire [32:0] _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1_1; + wire [31:0] _zz_dBus_cmd_payload_data; + wire _zz_dBus_cmd_valid; + wire [1:0] _zz_decode_ALU_BITWISE_CTRL; + wire [1:0] _zz_decode_ALU_BITWISE_CTRL_1; + wire [1:0] _zz_decode_ALU_BITWISE_CTRL_2; + wire [1:0] _zz_decode_ALU_CTRL; + wire [1:0] _zz_decode_ALU_CTRL_1; + wire [1:0] _zz_decode_ALU_CTRL_2; + wire [1:0] _zz_decode_BRANCH_CTRL; + wire [1:0] _zz_decode_BRANCH_CTRL_1; + wire [25:0] _zz_decode_BRANCH_CTRL_2; + wire _zz_decode_BRANCH_CTRL_3; + wire _zz_decode_BRANCH_CTRL_4; + wire _zz_decode_BRANCH_CTRL_5; + wire _zz_decode_BRANCH_CTRL_6; + wire _zz_decode_BRANCH_CTRL_7; + wire _zz_decode_BRANCH_CTRL_8; + wire [1:0] _zz_decode_BRANCH_CTRL_9; + wire _zz_decode_ENV_CTRL; + wire _zz_decode_ENV_CTRL_1; + wire _zz_decode_ENV_CTRL_2; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [1:0] _zz_decode_SHIFT_CTRL; + wire [1:0] _zz_decode_SHIFT_CTRL_1; + wire [1:0] _zz_decode_SHIFT_CTRL_2; + wire [31:0] _zz_decode_SRC1; + wire [31:0] _zz_decode_SRC1_1; + wire [1:0] _zz_decode_SRC1_CTRL; + wire [1:0] _zz_decode_SRC1_CTRL_1; + wire [1:0] _zz_decode_SRC1_CTRL_2; + wire [31:0] _zz_decode_SRC2; + wire [31:0] _zz_decode_SRC2_1; + wire _zz_decode_SRC2_2; + wire [19:0] _zz_decode_SRC2_3; + wire _zz_decode_SRC2_4; + wire [19:0] _zz_decode_SRC2_5; + wire [31:0] _zz_decode_SRC2_6; + wire [1:0] _zz_decode_SRC2_CTRL; + wire [1:0] _zz_decode_SRC2_CTRL_1; + wire [1:0] _zz_decode_SRC2_CTRL_2; + wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + wire [1:0] _zz_decode_to_execute_ALU_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_CTRL_1; + wire [1:0] _zz_decode_to_execute_BRANCH_CTRL; + wire [1:0] _zz_decode_to_execute_BRANCH_CTRL_1; + wire _zz_decode_to_execute_ENV_CTRL; + wire _zz_decode_to_execute_ENV_CTRL_1; + wire [1:0] _zz_decode_to_execute_SHIFT_CTRL; + wire [1:0] _zz_decode_to_execute_SHIFT_CTRL_1; + wire [1:0] _zz_execute_ALU_BITWISE_CTRL; + wire [1:0] _zz_execute_ALU_CTRL; + wire [1:0] _zz_execute_BRANCH_CTRL; + wire _zz_execute_BRANCH_DO; + wire _zz_execute_BRANCH_DO_1; + wire _zz_execute_BranchPlugin_branch_src2; + wire [10:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + wire [19:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + wire [18:0] _zz_execute_BranchPlugin_branch_src2_5; + wire [31:0] _zz_execute_BranchPlugin_branch_src2_6; + wire _zz_execute_ENV_CTRL; + wire [31:0] _zz_execute_REGFILE_WRITE_DATA; + wire [1:0] _zz_execute_SHIFT_CTRL; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire _zz_execute_to_memory_ENV_CTRL; + wire _zz_execute_to_memory_ENV_CTRL_1; + wire [31:0] _zz_execute_to_memory_REGFILE_WRITE_DATA; + wire [31:0] _zz_execute_to_memory_REGFILE_WRITE_DATA_1; + wire [29:0] _zz_lastStageRegFileWrite_payload_address; + wire [31:0] _zz_lastStageRegFileWrite_payload_data; + wire _zz_lastStageRegFileWrite_valid; + wire _zz_memory_ENV_CTRL; + wire _zz_memory_to_writeBack_ENV_CTRL; + wire _zz_memory_to_writeBack_ENV_CTRL_1; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; + wire _zz_when_DebugPlugin_l244; + wire _zz_writeBack_DBusSimplePlugin_rspFormated; + wire [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_1; + wire _zz_writeBack_DBusSimplePlugin_rspFormated_2; + wire [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_3; + wire _zz_writeBack_ENV_CTRL; + wire contextSwitching; + output [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_address; + output [31:0] dBus_cmd_payload_data; + wire [31:0] dBus_cmd_payload_data; + output [1:0] dBus_cmd_payload_size; + wire [1:0] dBus_cmd_payload_size; + output dBus_cmd_payload_wr; + wire dBus_cmd_payload_wr; + input dBus_cmd_ready; + wire dBus_cmd_ready; + output dBus_cmd_valid; + wire dBus_cmd_valid; + input [31:0] dBus_rsp_data; + wire [31:0] dBus_rsp_data; + input dBus_rsp_error; + wire dBus_rsp_error; + input dBus_rsp_ready; + wire dBus_rsp_ready; + input [7:0] debug_bus_cmd_payload_address; + wire [7:0] debug_bus_cmd_payload_address; + input [31:0] debug_bus_cmd_payload_data; + wire [31:0] debug_bus_cmd_payload_data; + input debug_bus_cmd_payload_wr; + wire debug_bus_cmd_payload_wr; + output debug_bus_cmd_ready; + wire debug_bus_cmd_ready; + input debug_bus_cmd_valid; + wire debug_bus_cmd_valid; + output [31:0] debug_bus_rsp_data; + wire [31:0] debug_bus_rsp_data; + output debug_resetOut; + wire debug_resetOut; + wire [1:0] decode_ALU_BITWISE_CTRL; + wire [1:0] decode_ALU_CTRL; + wire [1:0] decode_BRANCH_CTRL; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_CSR_WRITE_OPCODE; + wire decode_DO_EBREAK; + wire decode_ENV_CTRL; + wire [31:0] decode_INSTRUCTION; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + wire decode_IS_CSR; + wire decode_IS_EBREAK; + wire decode_MEMORY_ENABLE; + wire decode_MEMORY_STORE; + wire [31:0] decode_PC; + wire [31:0] decode_RS1; + wire decode_RS1_USE; + wire [31:0] decode_RS2; + wire decode_RS2_USE; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + wire [1:0] decode_SHIFT_CTRL; + wire [31:0] decode_SRC1; + wire [1:0] decode_SRC1_CTRL; + wire [31:0] decode_SRC2; + wire [1:0] decode_SRC2_CTRL; + wire decode_SRC2_FORCE_ZERO; + wire decode_SRC_ADD_ZERO; + wire decode_SRC_LESS_UNSIGNED; + wire decode_SRC_USE_SUB_LESS; + wire decode_arbitration_flushIt; + wire decode_arbitration_flushNext; + wire decode_arbitration_haltByOther; + wire decode_arbitration_haltItself; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isValid; + wire decode_arbitration_removeIt; + wire [1:0] decode_to_execute_ALU_BITWISE_CTRL; + wire [1:0] decode_to_execute_ALU_CTRL; + wire [1:0] decode_to_execute_BRANCH_CTRL; + wire decode_to_execute_CSR_WRITE_OPCODE; + wire decode_to_execute_DO_EBREAK; + wire decode_to_execute_ENV_CTRL; + wire [31:0] decode_to_execute_INSTRUCTION; + wire decode_to_execute_IS_CSR; + wire decode_to_execute_MEMORY_ENABLE; + wire decode_to_execute_MEMORY_STORE; + wire [31:0] decode_to_execute_PC; + wire decode_to_execute_REGFILE_WRITE_VALID; + wire [31:0] decode_to_execute_RS1; + wire [31:0] decode_to_execute_RS2; + wire [1:0] decode_to_execute_SHIFT_CTRL; + wire [31:0] decode_to_execute_SRC1; + wire [31:0] decode_to_execute_SRC2; + wire decode_to_execute_SRC2_FORCE_ZERO; + wire decode_to_execute_SRC_LESS_UNSIGNED; + wire decode_to_execute_SRC_USE_SUB_LESS; + wire execute_ALIGNEMENT_FAULT; + wire [1:0] execute_ALU_BITWISE_CTRL; + wire [1:0] execute_ALU_CTRL; + wire [31:0] execute_BRANCH_CALC; + wire [1:0] execute_BRANCH_CTRL; + wire execute_BRANCH_DO; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [31:0] execute_BranchPlugin_branch_src1; + wire [31:0] execute_BranchPlugin_branch_src2; + wire execute_BranchPlugin_eq; + wire execute_CSR_WRITE_OPCODE; + wire execute_CsrPlugin_blockedBySideEffects; + wire [11:0] execute_CsrPlugin_csrAddress; + wire execute_CsrPlugin_csr_768; + wire execute_CsrPlugin_csr_772; + wire execute_CsrPlugin_csr_834; + wire execute_CsrPlugin_csr_836; + wire [31:0] execute_CsrPlugin_readToWriteData; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_writeInstruction; + wire execute_DBusSimplePlugin_skipCmd; + wire execute_DO_EBREAK; + wire execute_ENV_CTRL; + wire [31:0] execute_INSTRUCTION; + wire execute_IS_CSR; + wire [31:0] execute_IntAluPlugin_bitwise; + wire [4:0] execute_LightShifterPlugin_amplitude; + wire [4:0] execute_LightShifterPlugin_amplitudeReg; + wire execute_LightShifterPlugin_done; + wire execute_LightShifterPlugin_isActive; + wire execute_LightShifterPlugin_isShift; + wire [31:0] execute_LightShifterPlugin_shiftInput; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire execute_MEMORY_ENABLE; + wire execute_MEMORY_STORE; + wire [31:0] execute_PC; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire execute_REGFILE_WRITE_VALID; + wire [31:0] execute_RS1; + wire [31:0] execute_RS2; + wire [1:0] execute_SHIFT_CTRL; + wire [31:0] execute_SRC1; + wire [31:0] execute_SRC2; + wire execute_SRC2_FORCE_ZERO; + wire [31:0] execute_SRC_ADD; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire execute_arbitration_flushIt; + wire execute_arbitration_flushNext; + wire execute_arbitration_haltByOther; + wire execute_arbitration_haltItself; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isValid; + wire execute_arbitration_removeIt; + wire [31:0] execute_to_memory_BRANCH_CALC; + wire execute_to_memory_BRANCH_DO; + wire execute_to_memory_ENV_CTRL; + wire [29:0] execute_to_memory_INSTRUCTION; + wire [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + wire execute_to_memory_MEMORY_ENABLE; + wire execute_to_memory_MEMORY_STORE; + wire [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire execute_to_memory_REGFILE_WRITE_VALID; + input externalInterrupt; + wire externalInterrupt; + output [31:0] iBus_cmd_payload_pc; + wire [31:0] iBus_cmd_payload_pc; + input iBus_cmd_ready; + wire iBus_cmd_ready; + output iBus_cmd_valid; + wire iBus_cmd_valid; + input iBus_rsp_payload_error; + wire iBus_rsp_payload_error; + input [31:0] iBus_rsp_payload_inst; + wire [31:0] iBus_rsp_payload_inst; + wire iBus_rsp_toStream_payload_error; + wire [31:0] iBus_rsp_toStream_payload_inst; + wire iBus_rsp_toStream_ready; + wire iBus_rsp_toStream_valid; + input iBus_rsp_valid; + wire iBus_rsp_valid; + input io_mainClk; + wire io_mainClk; + wire [31:0] lastStageInstruction; + wire lastStageIsFiring; + wire lastStageIsValid; + wire [4:0] lastStageRegFileWrite_payload_address; + wire [31:0] lastStageRegFileWrite_payload_data; + wire lastStageRegFileWrite_valid; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire memory_ENV_CTRL; + wire [31:0] memory_INSTRUCTION; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire memory_MEMORY_ENABLE; + wire [31:0] memory_MEMORY_READ_DATA; + wire memory_MEMORY_STORE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_REGFILE_WRITE_VALID; + wire memory_arbitration_flushIt; + wire memory_arbitration_flushNext; + wire memory_arbitration_haltByOther; + wire memory_arbitration_haltItself; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isValid; + wire memory_arbitration_removeIt; + wire memory_to_writeBack_ENV_CTRL; + wire [31:0] memory_to_writeBack_INSTRUCTION; + wire [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + wire memory_to_writeBack_MEMORY_ENABLE; + wire [31:0] memory_to_writeBack_MEMORY_READ_DATA; + wire [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire memory_to_writeBack_REGFILE_WRITE_VALID; + input resetCtrl_mainClkReset; + wire resetCtrl_mainClkReset; + input resetCtrl_systemReset; + wire resetCtrl_systemReset; + input softwareInterrupt; + wire softwareInterrupt; + wire [1:0] switch_CsrPlugin_l1068; + wire [5:0] switch_DebugPlugin_l267; + wire [2:0] switch_Fetcher_l362; + wire [1:0] switch_Misc_l211; + wire switch_Misc_l211_1; + wire [2:0] switch_Misc_l211_2; + input timerInterrupt; + wire timerInterrupt; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire when_CsrPlugin_l1116; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; + wire when_DBusSimplePlugin_l428; + wire when_DBusSimplePlugin_l482; + wire when_DBusSimplePlugin_l558; + wire when_DebugPlugin_l271; + wire when_DebugPlugin_l271_1; + wire when_DebugPlugin_l272; + wire when_DebugPlugin_l272_1; + wire when_DebugPlugin_l273; + wire when_DebugPlugin_l274; + wire when_DebugPlugin_l275; + wire when_DebugPlugin_l275_1; + wire when_DebugPlugin_l295; + wire when_DebugPlugin_l311; + wire when_DebugPlugin_l327; + wire when_Fetcher_l131; + wire when_Fetcher_l131_1; + wire when_Fetcher_l158; + wire when_Fetcher_l240; + wire when_Fetcher_l329; + wire when_Fetcher_l329_1; + wire when_Fetcher_l329_5; + wire when_Fetcher_l398; + wire when_HazardSimplePlugin_l113; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l59; + wire when_HazardSimplePlugin_l59_1; + wire when_HazardSimplePlugin_l59_2; + wire when_HazardSimplePlugin_l62; + wire when_HazardSimplePlugin_l62_1; + wire when_HazardSimplePlugin_l62_2; + wire when_IBusSimplePlugin_l305; + wire when_Pipeline_l124_14; + wire when_Pipeline_l124_17; + wire when_Pipeline_l124_2; + wire when_Pipeline_l124_26; + wire when_Pipeline_l124_39; + wire when_Pipeline_l124_40; + wire when_Pipeline_l124_41; + wire when_Pipeline_l124_44; + wire when_Pipeline_l124_5; + wire when_Pipeline_l124_8; + wire when_Pipeline_l151; + wire when_Pipeline_l151_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154; + wire when_Pipeline_l154_1; + wire when_Pipeline_l154_2; + wire when_RegFilePlugin_l63; + wire when_ShiftPlugins_l169; + wire [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire [31:0] writeBack_DBusSimplePlugin_rspShifted; + wire writeBack_ENV_CTRL; + wire [31:0] writeBack_INSTRUCTION; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_ENABLE; + wire [31:0] writeBack_MEMORY_READ_DATA; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_REGFILE_WRITE_VALID; + wire writeBack_arbitration_flushIt; + wire writeBack_arbitration_flushNext; + wire writeBack_arbitration_haltByOther; + wire writeBack_arbitration_haltItself; + wire writeBack_arbitration_isFiring; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isValid; + wire writeBack_arbitration_removeIt; + reg [31:0] RegFilePlugin_regFile [31:0]; + always @(posedge io_mainClk) begin + if (_000_[31]) + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + reg [31:0] _774_; + reg [31:0] _775_; + always @(posedge io_mainClk) begin + _774_ <= RegFilePlugin_regFile[decode_INSTRUCTION_ANTICIPATED[24:20]]; + _775_ <= RegFilePlugin_regFile[decode_INSTRUCTION_ANTICIPATED[19:15]]; + end + assign _zz_RegFilePlugin_regFile_port1 = _774_; + assign _zz_RegFilePlugin_regFile_port0 = _775_; + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _248_ ( + .A(CsrPlugin_jumpInterface_valid), + .B(_108_[0]), + .Y(_zz_IBusSimplePlugin_jump_pcLoad_payload_1) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd32), + .B_SIGNED(32'd0), + .B_WIDTH(32'd32), + .Y_WIDTH(32'd32) + ) _249_ ( + .A(decode_to_execute_SRC1), + .B(decode_to_execute_SRC2), + .Y(_061_) + ); + \$macc #( + .A_WIDTH(32'd66), + .B_WIDTH(32'd0), + .CONFIG(46'h008100240816), + .CONFIG_WIDTH(32'd46), + .Y_WIDTH(32'd32) + ) _250_ ( + .A({ _zz_execute_SrcPlugin_addSub_3, 1'h0, _zz_execute_SrcPlugin_addSub_4, decode_to_execute_SRC1 }), + .B(), + .Y(_zz_execute_SrcPlugin_addSub) + ); + \$macc #( + .A_WIDTH(32'd4), + .B_WIDTH(32'd1), + .CONFIG(16'h18c2), + .CONFIG_WIDTH(32'd16), + .Y_WIDTH(32'd3) + ) _251_ ( + .A({ IBusSimplePlugin_pending_dec, IBusSimplePlugin_pending_value }), + .B(IBusSimplePlugin_cmd_fire), + .Y(IBusSimplePlugin_pending_next) + ); + \$alu #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd3) + ) _252_ ( + .A(IBusSimplePlugin_rspJoin_rspBuffer_discardCounter), + .B(_zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1), + .BI(1'h1), + .CI(1'h1), + .CO(_067_), + .X(_062_), + .Y(_243_) + ); + \$alu #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd5) + ) _253_ ( + .A(execute_LightShifterPlugin_amplitude), + .B(1'h1), + .BI(1'h1), + .CI(1'h1), + .CO(_068_), + .X(_063_), + .Y(_244_) + ); + \$alu #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd30), + .Y_WIDTH(32'd30) + ) _254_ ( + .A(IBusSimplePlugin_fetchPc_inc), + .B(IBusSimplePlugin_fetchPc_pcReg[31:2]), + .BI(1'h0), + .CI(1'h0), + .CO(_069_[31:2]), + .X(_064_[31:2]), + .Y(_059_[31:2]) + ); + \$alu #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd32), + .B_SIGNED(32'd0), + .B_WIDTH(32'd32), + .Y_WIDTH(32'd32) + ) _255_ ( + .A(execute_BranchPlugin_branch_src1), + .B({ decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], execute_BranchPlugin_branch_src2[19:11], decode_to_execute_INSTRUCTION[30:25], execute_BranchPlugin_branch_src2[4:0] }), + .BI(1'h0), + .CI(1'h0), + .CO(_070_), + .X(_065_), + .Y(execute_BranchPlugin_branchAdder) + ); + \$alu #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _256_ ( + .A(CsrPlugin_jumpInterface_valid), + .B(1'h1), + .BI(1'h1), + .CI(1'h1), + .CO(_071_), + .X(_066_), + .Y(_zz_IBusSimplePlugin_jump_pcLoad_payload_2[0]) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(3'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd3) + ) _257_ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_022_), + .EN(_091_), + .Q(switch_Fetcher_l362) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) execute_LightShifterPlugin_isActive_reg /* _258_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_019_), + .EN(_092_), + .Q(execute_LightShifterPlugin_isActive) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) CsrPlugin_pipelineLiberator_pcValids_2_reg /* _259_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_008_), + .EN(_077_), + .Q(CsrPlugin_pipelineLiberator_pcValids_2) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) CsrPlugin_pipelineLiberator_pcValids_1_reg /* _260_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_007_), + .EN(_093_), + .Q(CsrPlugin_pipelineLiberator_pcValids_1) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) CsrPlugin_pipelineLiberator_pcValids_0_reg /* _261_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_006_), + .EN(_094_), + .Q(CsrPlugin_pipelineLiberator_pcValids_0) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) CsrPlugin_mie_MSIE_reg /* _262_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(CsrPlugin_csrMapping_writeDataSignal[3]), + .EN(_095_), + .Q(CsrPlugin_mie_MSIE) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) CsrPlugin_mie_MTIE_reg /* _263_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(CsrPlugin_csrMapping_writeDataSignal[7]), + .EN(_095_), + .Q(CsrPlugin_mie_MTIE) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) CsrPlugin_mie_MEIE_reg /* _264_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(CsrPlugin_csrMapping_writeDataSignal[11]), + .EN(_095_), + .Q(CsrPlugin_mie_MEIE) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) _zz_IBusSimplePlugin_injector_decodeInput_valid_reg /* _265_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_018_), + .EN(_080_), + .Q(_zz_IBusSimplePlugin_injector_decodeInput_valid) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid_reg /* _266_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_016_), + .EN(_081_), + .Q(_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2_reg /* _267_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_015_), + .EN(_082_), + .Q(_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) IBusSimplePlugin_fetchPc_inc_reg /* _268_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_013_), + .EN(_083_), + .Q(IBusSimplePlugin_fetchPc_inc) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) memory_arbitration_isValid_reg /* _269_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_021_), + .EN(_084_), + .Q(memory_arbitration_isValid) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) execute_arbitration_isValid_reg /* _270_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_020_), + .EN(_085_), + .Q(execute_arbitration_isValid) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd1) + ) execute_CsrPlugin_csr_834_reg /* _271_ */ ( + .CLK(io_mainClk), + .D(_127_), + .EN(execute_arbitration_isStuck), + .Q(execute_CsrPlugin_csr_834) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd1) + ) execute_CsrPlugin_csr_772_reg /* _272_ */ ( + .CLK(io_mainClk), + .D(_126_), + .EN(execute_arbitration_isStuck), + .Q(execute_CsrPlugin_csr_772) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd1) + ) execute_CsrPlugin_csr_836_reg /* _273_ */ ( + .CLK(io_mainClk), + .D(_125_), + .EN(execute_arbitration_isStuck), + .Q(execute_CsrPlugin_csr_836) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd1) + ) execute_CsrPlugin_csr_768_reg /* _274_ */ ( + .CLK(io_mainClk), + .D(_124_), + .EN(execute_arbitration_isStuck), + .Q(execute_CsrPlugin_csr_768) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd1) + ) execute_to_memory_BRANCH_DO_reg /* _275_ */ ( + .CLK(io_mainClk), + .D(_zz_execute_BRANCH_DO_1), + .EN(memory_arbitration_isStuck), + .Q(execute_to_memory_BRANCH_DO) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd32) + ) _276_ ( + .CLK(io_mainClk), + .D(_zz_execute_to_memory_REGFILE_WRITE_DATA), + .EN(when_Pipeline_l124_40), + .Q(execute_to_memory_REGFILE_WRITE_DATA) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd2) + ) _277_ ( + .CLK(io_mainClk), + .D(execute_SrcPlugin_addSub[1:0]), + .EN(memory_arbitration_isStuck), + .Q(execute_to_memory_MEMORY_ADDRESS_LOW) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd1) + ) decode_to_execute_DO_EBREAK_reg /* _278_ */ ( + .CLK(io_mainClk), + .D(decode_DO_EBREAK), + .EN(execute_arbitration_isStuck), + .Q(decode_to_execute_DO_EBREAK) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd32) + ) _279_ ( + .CLK(io_mainClk), + .D(_zz_decode_SRC2_6), + .EN(execute_arbitration_isStuck), + .Q(decode_to_execute_SRC2) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd32) + ) _280_ ( + .CLK(io_mainClk), + .D(_zz_decode_SRC1_1), + .EN(execute_arbitration_isStuck), + .Q(decode_to_execute_SRC1) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd1) + ) decode_to_execute_SRC2_FORCE_ZERO_reg /* _281_ */ ( + .CLK(io_mainClk), + .D(decode_SRC2_FORCE_ZERO), + .EN(execute_arbitration_isStuck), + .Q(decode_to_execute_SRC2_FORCE_ZERO) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd32) + ) _282_ ( + .CLK(io_mainClk), + .D(_zz_RegFilePlugin_regFile_port1), + .EN(execute_arbitration_isStuck), + .Q(decode_to_execute_RS2) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd32) + ) _283_ ( + .CLK(io_mainClk), + .D(_zz_RegFilePlugin_regFile_port0), + .EN(execute_arbitration_isStuck), + .Q(decode_to_execute_RS1) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd2) + ) _284_ ( + .CLK(io_mainClk), + .D(_zz_decode_BRANCH_CTRL), + .EN(execute_arbitration_isStuck), + .Q(decode_to_execute_BRANCH_CTRL) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd2) + ) _285_ ( + .CLK(io_mainClk), + .D({ _zz__zz_decode_BRANCH_CTRL_2_4, _zz_decode_BRANCH_CTRL_2[21] }), + .EN(execute_arbitration_isStuck), + .Q(decode_to_execute_SHIFT_CTRL) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd2) + ) _286_ ( + .CLK(io_mainClk), + .D({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz__zz_decode_BRANCH_CTRL_2_17 }), + .EN(execute_arbitration_isStuck), + .Q(decode_to_execute_ALU_BITWISE_CTRL) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd1) + ) decode_to_execute_SRC_LESS_UNSIGNED_reg /* _287_ */ ( + .CLK(io_mainClk), + .D(decode_SRC_LESS_UNSIGNED), + .EN(execute_arbitration_isStuck), + .Q(decode_to_execute_SRC_LESS_UNSIGNED) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd2) + ) _288_ ( + .CLK(io_mainClk), + .D({ _zz__zz_decode_BRANCH_CTRL_2_21, _zz__zz_decode_BRANCH_CTRL_2_26 }), + .EN(execute_arbitration_isStuck), + .Q(decode_to_execute_ALU_CTRL) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd1) + ) execute_to_memory_ENV_CTRL_reg /* _289_ */ ( + .CLK(io_mainClk), + .D(decode_to_execute_ENV_CTRL), + .EN(memory_arbitration_isStuck), + .Q(execute_to_memory_ENV_CTRL) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd1) + ) decode_to_execute_ENV_CTRL_reg /* _290_ */ ( + .CLK(io_mainClk), + .D(_zz__zz_decode_BRANCH_CTRL_2_28), + .EN(execute_arbitration_isStuck), + .Q(decode_to_execute_ENV_CTRL) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd1) + ) decode_to_execute_IS_CSR_reg /* _291_ */ ( + .CLK(io_mainClk), + .D(decode_IS_CSR), + .EN(execute_arbitration_isStuck), + .Q(decode_to_execute_IS_CSR) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd1) + ) execute_to_memory_MEMORY_STORE_reg /* _292_ */ ( + .CLK(io_mainClk), + .D(decode_to_execute_MEMORY_STORE), + .EN(memory_arbitration_isStuck), + .Q(execute_to_memory_MEMORY_STORE) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd1) + ) decode_to_execute_MEMORY_STORE_reg /* _293_ */ ( + .CLK(io_mainClk), + .D(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5]), + .EN(execute_arbitration_isStuck), + .Q(decode_to_execute_MEMORY_STORE) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd1) + ) execute_to_memory_REGFILE_WRITE_VALID_reg /* _294_ */ ( + .CLK(io_mainClk), + .D(decode_to_execute_REGFILE_WRITE_VALID), + .EN(memory_arbitration_isStuck), + .Q(execute_to_memory_REGFILE_WRITE_VALID) + ); + \$sdffce #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .SRST_POLARITY(32'd1), + .SRST_VALUE(1'h0), + .WIDTH(32'd1) + ) decode_to_execute_REGFILE_WRITE_VALID_reg /* _295_ */ ( + .CLK(io_mainClk), + .D(_zz__zz_decode_BRANCH_CTRL_2_47), + .EN(execute_arbitration_isStuck), + .Q(decode_to_execute_REGFILE_WRITE_VALID), + .SRST(when_RegFilePlugin_l63) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd1) + ) execute_to_memory_MEMORY_ENABLE_reg /* _296_ */ ( + .CLK(io_mainClk), + .D(decode_to_execute_MEMORY_ENABLE), + .EN(memory_arbitration_isStuck), + .Q(execute_to_memory_MEMORY_ENABLE) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd1) + ) decode_to_execute_MEMORY_ENABLE_reg /* _297_ */ ( + .CLK(io_mainClk), + .D(_zz__zz_decode_BRANCH_CTRL_2_71), + .EN(execute_arbitration_isStuck), + .Q(decode_to_execute_MEMORY_ENABLE) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd1) + ) decode_to_execute_SRC_USE_SUB_LESS_reg /* _298_ */ ( + .CLK(io_mainClk), + .D(decode_SRC_USE_SUB_LESS), + .EN(execute_arbitration_isStuck), + .Q(decode_to_execute_SRC_USE_SUB_LESS) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd1) + ) decode_to_execute_CSR_WRITE_OPCODE_reg /* _299_ */ ( + .CLK(io_mainClk), + .D(decode_CSR_WRITE_OPCODE), + .EN(execute_arbitration_isStuck), + .Q(decode_to_execute_CSR_WRITE_OPCODE) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd30) + ) _300_ ( + .CLK(io_mainClk), + .D(decode_to_execute_INSTRUCTION[29:0]), + .EN(memory_arbitration_isStuck), + .Q(execute_to_memory_INSTRUCTION) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd32) + ) _301_ ( + .CLK(io_mainClk), + .D(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst), + .EN(execute_arbitration_isStuck), + .Q(decode_to_execute_INSTRUCTION) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd5) + ) _302_ ( + .CLK(io_mainClk), + .D(_244_), + .EN(_096_), + .Q(execute_LightShifterPlugin_amplitudeReg) + ); + \$sdffce #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .SRST_POLARITY(32'd1), + .SRST_VALUE(1'h0), + .WIDTH(32'd1) + ) \CsrPlugin_interrupt_code_reg[2] /* _303_ */ ( + .CLK(io_mainClk), + .D(1'h1), + .EN(_097_), + .Q(CsrPlugin_interrupt_code[2]), + .SRST(_101_) + ); + \$sdffce #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .SRST_POLARITY(32'd1), + .SRST_VALUE(1'h1), + .WIDTH(32'd1) + ) \CsrPlugin_interrupt_code_reg[3] /* _304_ */ ( + .CLK(io_mainClk), + .D(1'h0), + .EN(_097_), + .Q(CsrPlugin_interrupt_code[3]), + .SRST(_zz_when_CsrPlugin_l952_2) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd22) + ) _305_ ( + .CLK(io_mainClk), + .D({ _017_[31:25], _017_[14:0] }), + .EN(_087_), + .Q({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:25], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14:0] }) + ); + \$dff #( + .CLK_POLARITY(32'd1), + .WIDTH(32'd10) + ) _306_ ( + .CLK(io_mainClk), + .D(_017_[24:15]), + .Q(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24:15]) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) DebugPlugin_disableEbreak_reg /* _307_ */ ( + .ARST(resetCtrl_mainClkReset), + .CLK(io_mainClk), + .D(_178_), + .EN(_098_), + .Q(DebugPlugin_disableEbreak) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) DebugPlugin_debugUsed_reg /* _308_ */ ( + .ARST(resetCtrl_mainClkReset), + .CLK(io_mainClk), + .D(1'h1), + .EN(debug_bus_cmd_valid), + .Q(DebugPlugin_debugUsed) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) DebugPlugin_stepIt_reg /* _309_ */ ( + .ARST(resetCtrl_mainClkReset), + .CLK(io_mainClk), + .D(debug_bus_cmd_payload_data[4]), + .EN(_099_), + .Q(DebugPlugin_stepIt) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd1) + ) DebugPlugin_resetIt_reg /* _310_ */ ( + .ARST(resetCtrl_mainClkReset), + .CLK(io_mainClk), + .D(_193_), + .EN(_100_), + .Q(DebugPlugin_resetIt) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd31) + ) _311_ ( + .CLK(io_mainClk), + .D(execute_BranchPlugin_branchAdder[31:1]), + .EN(memory_arbitration_isStuck), + .Q(execute_to_memory_BRANCH_CALC[31:1]) + ); + \$adffe #( + .ARST_POLARITY(32'd1), + .ARST_VALUE(30'h20000000), + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd30) + ) _312_ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(IBusSimplePlugin_fetchPc_pc[31:2]), + .EN(when_Fetcher_l158), + .Q(IBusSimplePlugin_fetchPc_pcReg[31:2]) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd2) + ) _313_ ( + .CLK(io_mainClk), + .D(CsrPlugin_interrupt_code[3:2]), + .EN(CsrPlugin_interruptJump), + .Q(CsrPlugin_mcause_exceptionCode[3:2]) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd30) + ) _314_ ( + .CLK(io_mainClk), + .D(IBusSimplePlugin_fetchPc_pcReg[31:2]), + .EN(IBusSimplePlugin_iBusRsp_stages_1_output_ready), + .Q(_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload[31:2]) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd30) + ) _315_ ( + .CLK(io_mainClk), + .D(_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload[31:2]), + .EN(decode_arbitration_isStuck), + .Q(_zz_IBusSimplePlugin_injector_decodeInput_payload_pc[31:2]) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd0), + .WIDTH(32'd30) + ) _316_ ( + .CLK(io_mainClk), + .D(_zz_IBusSimplePlugin_injector_decodeInput_payload_pc[31:2]), + .EN(execute_arbitration_isStuck), + .Q(decode_to_execute_PC[31:2]) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd30) + ) _317_ ( + .CLK(io_mainClk), + .D(_zz_IBusSimplePlugin_injector_decodeInput_payload_pc[31:2]), + .EN(CsrPlugin_interruptJump), + .Q(CsrPlugin_mepc[31:2]) + ); + \$sdffce #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .SRST_POLARITY(32'd1), + .SRST_VALUE(2'h0), + .WIDTH(32'd2) + ) _318_ ( + .CLK(io_mainClk), + .D(_zz_lastStageRegFileWrite_payload_data[1:0]), + .EN(_088_), + .Q(DebugPlugin_busReadDataReg[1:0]), + .SRST(when_DebugPlugin_l295) + ); + \$dffe #( + .CLK_POLARITY(32'd1), + .EN_POLARITY(32'd1), + .WIDTH(32'd30) + ) _319_ ( + .CLK(io_mainClk), + .D(_009_[31:2]), + .EN(_088_), + .Q(DebugPlugin_busReadDataReg[31:2]) + ); + \$ne #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _320_ ( + .A({ _200_, decode_arbitration_isStuck }), + .B(2'h3), + .Y(_072_) + ); + \$ne #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _321_ ( + .A({ _203_, IBusSimplePlugin_injectionPort_valid }), + .B(2'h2), + .Y(_073_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .Y_WIDTH(32'd1) + ) _322_ ( + .A({ _203_, _202_, _201_, _200_, _199_ }), + .Y(_074_) + ); + \$ne #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _323_ ( + .A({ when_ShiftPlugins_l169, execute_arbitration_isStuckByOthers, execute_arbitration_removeIt }), + .B(3'h6), + .Y(_075_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _324_ ( + .A({ when_ShiftPlugins_l169, execute_arbitration_removeIt }), + .Y(_076_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _325_ ( + .A({ when_CsrPlugin_l985, CsrPlugin_pipelineLiberator_active }), + .Y(_077_) + ); + \$ne #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _326_ ( + .A({ when_CsrPlugin_l985, CsrPlugin_pipelineLiberator_active, memory_arbitration_isStuck }), + .B(2'h3), + .Y(_078_) + ); + \$ne #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _327_ ( + .A({ when_CsrPlugin_l985, CsrPlugin_pipelineLiberator_active, execute_arbitration_isStuck }), + .B(2'h3), + .Y(_079_) + ); + \$ne #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _328_ ( + .A({ decode_arbitration_isStuck, decode_arbitration_removeIt }), + .B(2'h2), + .Y(_080_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _329_ ( + .A({ IBusSimplePlugin_iBusRsp_stages_1_output_ready, IBusSimplePlugin_externalFlush }), + .Y(_081_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _330_ ( + .A({ IBusSimplePlugin_fetchPc_output_ready, IBusSimplePlugin_externalFlush }), + .Y(_082_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _331_ ( + .A({ when_Fetcher_l131_1, IBusSimplePlugin_fetchPc_output_fire_1, when_Fetcher_l131 }), + .Y(_083_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _332_ ( + .A({ when_Pipeline_l154_1, when_Pipeline_l151_1 }), + .Y(_084_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _333_ ( + .A({ when_Pipeline_l154, when_Pipeline_l151 }), + .Y(_085_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _334_ ( + .A({ _zz_when_CsrPlugin_l952_2, _zz_when_CsrPlugin_l952_1, _zz_when_CsrPlugin_l952 }), + .Y(_086_) + ); + \$ne #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _335_ ( + .A({ when_Fetcher_l398, decode_arbitration_isStuck }), + .B(1'h1), + .Y(_087_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _336_ ( + .A({ when_DebugPlugin_l295, writeBack_arbitration_isValid }), + .Y(_088_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _337_ ( + .A({ debug_bus_cmd_payload_data[26], debug_bus_cmd_payload_data[18] }), + .Y(_089_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _338_ ( + .A({ debug_bus_cmd_payload_data[24], debug_bus_cmd_payload_data[16] }), + .Y(_090_) + ); + \$not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _339_ ( + .A(execute_arbitration_isStuckByOthers), + .Y(_107_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _340_ ( + .A({ _073_, _072_, _074_ }), + .Y(_091_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _341_ ( + .A({ _076_, _075_ }), + .Y(_092_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _342_ ( + .A({ _078_, _077_ }), + .Y(_093_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _343_ ( + .A({ _079_, _077_ }), + .Y(_094_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _344_ ( + .A({ execute_CsrPlugin_csr_772, execute_CsrPlugin_writeEnable }), + .Y(_095_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _345_ ( + .A({ when_ShiftPlugins_l169, _107_ }), + .Y(_096_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _346_ ( + .A({ _086_, CsrPlugin_mstatus_MIE }), + .Y(_097_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd4), + .Y_WIDTH(32'd1) + ) _347_ ( + .A({ _089_, _179_, debug_bus_cmd_payload_wr, debug_bus_cmd_valid }), + .Y(_098_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _348_ ( + .A({ _179_, debug_bus_cmd_payload_wr, debug_bus_cmd_valid }), + .Y(_099_) + ); + \$reduce_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd4), + .Y_WIDTH(32'd1) + ) _349_ ( + .A({ _090_, _179_, debug_bus_cmd_payload_wr, debug_bus_cmd_valid }), + .Y(_100_) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _350_ ( + .A({ _zz_when_CsrPlugin_l952_2, _zz_when_CsrPlugin_l952_1 }), + .Y(_101_) + ); + \$or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd3) + ) _351_ ( + .A({ _zz_CsrPlugin_csrMapping_readDataInit[11], _zz_CsrPlugin_csrMapping_readDataInit[7], _zz_CsrPlugin_csrMapping_readDataInit[3] }), + .B({ _zz_CsrPlugin_csrMapping_readDataInit_1[11], _zz_CsrPlugin_csrMapping_readDataInit_1[7], _zz_CsrPlugin_csrMapping_readDataInit_1[3] }), + .Y(_102_) + ); + \$or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _352_ ( + .A(_zz_CsrPlugin_csrMapping_readDataInit_2[3]), + .B(_zz_CsrPlugin_csrMapping_readDataInit_3[3]), + .Y(_103_) + ); + \$or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd3) + ) _353_ ( + .A(_102_), + .B({ _zz_CsrPlugin_csrMapping_readDataInit_2[11], _zz_CsrPlugin_csrMapping_readDataInit_2[7], _103_ }), + .Y({ execute_CsrPlugin_readToWriteData[11], execute_CsrPlugin_readToWriteData[7], execute_CsrPlugin_readToWriteData[3] }) + ); + \$and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd7), + .B_SIGNED(32'd0), + .B_WIDTH(32'd7), + .Y_WIDTH(32'd7) + ) _354_ ( + .A({ execute_CsrPlugin_readToWriteData[11], execute_CsrPlugin_readToWriteData[7], execute_CsrPlugin_readToWriteData[3], _zz_CsrPlugin_csrMapping_readDataInit_3[2:1], _zz_CsrPlugin_csrMapping_readDataInit_3[1], _zz_CsrPlugin_csrMapping_readDataInit[12] }), + .B({ _109_[11], _109_[7], _109_[3:0], _109_[12] }), + .Y({ _060_[11], _060_[7], _060_[3:0], _060_[12] }) + ); + \$or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd7), + .B_SIGNED(32'd0), + .B_WIDTH(32'd7), + .Y_WIDTH(32'd7) + ) _355_ ( + .A({ execute_CsrPlugin_readToWriteData[11], execute_CsrPlugin_readToWriteData[7], execute_CsrPlugin_readToWriteData[3], _zz_CsrPlugin_csrMapping_readDataInit_3[2:1], _zz_CsrPlugin_csrMapping_readDataInit_3[1], _zz_CsrPlugin_csrMapping_readDataInit[12] }), + .B({ decode_to_execute_SRC1[11], decode_to_execute_SRC1[7], decode_to_execute_SRC1[3:0], decode_to_execute_SRC1[12] }), + .Y(_104_) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _356_ ( + .A({ _220_, _123_ }), + .Y(_105_) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _357_ ( + .A({ _201_, _200_ }), + .Y(_106_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _358_ ( + .A(decode_to_execute_SHIFT_CTRL), + .B(2'h3), + .Y(_110_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd6), + .B_SIGNED(32'd0), + .B_WIDTH(32'd6), + .Y_WIDTH(32'd1) + ) _359_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14:12], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }), + .B(6'h2a), + .Y(_zz__zz_decode_BRANCH_CTRL_2_4) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd6), + .B_SIGNED(32'd0), + .B_WIDTH(32'd6), + .Y_WIDTH(32'd1) + ) _360_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14:12], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }), + .B(6'h0a), + .Y(_zz__zz_decode_BRANCH_CTRL_2_5[0]) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd6), + .B_SIGNED(32'd0), + .B_WIDTH(32'd6), + .Y_WIDTH(32'd1) + ) _361_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13:12], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }), + .B(6'h2a), + .Y(_zz__zz_decode_BRANCH_CTRL_2_5[1]) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .B_SIGNED(32'd0), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd1) + ) _362_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13:12], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }), + .B(5'h0a), + .Y(_111_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _363_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6:5], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }), + .B(3'h3), + .Y(_112_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _364_ ( + .A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13:12]), + .B(2'h2), + .Y(_zz__zz_decode_BRANCH_CTRL_2_17) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _365_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12] }), + .B(2'h1), + .Y(_zz__zz_decode_BRANCH_CTRL_2_18[0]) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _366_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] }), + .B(2'h2), + .Y(_zz__zz_decode_BRANCH_CTRL_2_18[1]) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _367_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }), + .B(3'h4), + .Y(_113_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _368_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14:13], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }), + .B(3'h6), + .Y(_114_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .B_SIGNED(32'd0), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd1) + ) _369_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13:12], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] }), + .B(5'h03), + .Y(_zz__zz_decode_BRANCH_CTRL_2_28) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _370_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] }), + .B(3'h7), + .Y(_zz__zz_decode_BRANCH_CTRL_2_29[0]) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _371_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] }), + .B(3'h7), + .Y(_zz__zz_decode_BRANCH_CTRL_2_29[1]) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _372_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6:5], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }), + .B(3'h2), + .Y(_115_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _373_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5:4], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }), + .B(3'h4), + .Y(_116_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _374_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] }), + .B(2'h3), + .Y(_zz__zz_decode_BRANCH_CTRL_2_49[4]) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _375_ ( + .A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6:4]), + .B(3'h2), + .Y(_zz__zz_decode_BRANCH_CTRL_2_60[0]) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _376_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] }), + .B(2'h3), + .Y(_zz__zz_decode_BRANCH_CTRL_2_52) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _377_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] }), + .Y(_zz__zz_decode_BRANCH_CTRL_2_49[0]) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _378_ ( + .A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3:2]), + .B(2'h1), + .Y(_zz__zz_decode_BRANCH_CTRL_2_49[1]) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _379_ ( + .A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5]), + .Y(_zz__zz_decode_BRANCH_CTRL_2_64) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _380_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }), + .Y(_zz__zz_decode_BRANCH_CTRL_2_66) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _381_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4:3] }), + .Y(_zz__zz_decode_BRANCH_CTRL_2_71) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _382_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }), + .B(3'h2), + .Y(_zz__zz_decode_BRANCH_CTRL_2_69) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _383_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }), + .B(2'h2), + .Y(_zz__zz_decode_BRANCH_CTRL_2_74) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _384_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }), + .B(3'h6), + .Y(_zz__zz_decode_BRANCH_CTRL_2_75) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .B_SIGNED(32'd0), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd1) + ) _385_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5:4], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }), + .B(5'h16), + .Y(_zz__zz_decode_BRANCH_CTRL_2_76) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _386_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }), + .B(2'h1), + .Y(_zz__zz_decode_BRANCH_CTRL_2_78) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _387_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }), + .B(2'h1), + .Y(_zz__zz_decode_BRANCH_CTRL_2_81) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _388_ ( + .A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14:13]), + .B(1'h1), + .Y(_117_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .Y_WIDTH(32'd1) + ) _389_ ( + .A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19:15]), + .Y(_118_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _390_ ( + .A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14:13]), + .B(2'h3), + .Y(_119_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _391_ ( + .A(IBusSimplePlugin_rspJoin_rspBuffer_discardCounter), + .Y(_120_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _392_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] }), + .B(3'h7), + .Y(_zz__zz_decode_BRANCH_CTRL_2_79) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _393_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14:13], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }), + .B(3'h2), + .Y(_zz__zz_decode_BRANCH_CTRL_2_26) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _394_ ( + .A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4:3]), + .Y(_zz__zz_decode_BRANCH_CTRL_2_39) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _395_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] }), + .B(2'h1), + .Y(_zz__zz_decode_BRANCH_CTRL_2_46) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _396_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] }), + .B(2'h3), + .Y(_zz__zz_decode_BRANCH_CTRL_2_48) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _397_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4:3] }), + .B(3'h4), + .Y(_zz_decode_BRANCH_CTRL[0]) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _398_ ( + .A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4:2]), + .B(3'h1), + .Y(_121_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .B_SIGNED(32'd0), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd1) + ) _399_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13:12], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] }), + .B(5'h03), + .Y(decode_IS_EBREAK) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .Y_WIDTH(32'd1) + ) _400_ ( + .A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11:7]), + .Y(when_RegFilePlugin_l63) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _401_ ( + .A(decode_to_execute_SRC1[31]), + .B(decode_to_execute_SRC2[31]), + .Y(_122_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd4), + .Y_WIDTH(32'd1) + ) _402_ ( + .A(execute_LightShifterPlugin_amplitude[4:1]), + .Y(execute_LightShifterPlugin_done) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .B_SIGNED(32'd0), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd1) + ) _403_ ( + .A(HazardSimplePlugin_writeBackBuffer_payload_address), + .B(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19:15]), + .Y(HazardSimplePlugin_addr0Match) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .B_SIGNED(32'd0), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd1) + ) _404_ ( + .A(HazardSimplePlugin_writeBackBuffer_payload_address), + .B(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24:20]), + .Y(HazardSimplePlugin_addr1Match) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .B_SIGNED(32'd0), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd1) + ) _405_ ( + .A(memory_to_writeBack_INSTRUCTION[11:7]), + .B(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19:15]), + .Y(when_HazardSimplePlugin_l59) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .B_SIGNED(32'd0), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd1) + ) _406_ ( + .A(memory_to_writeBack_INSTRUCTION[11:7]), + .B(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24:20]), + .Y(when_HazardSimplePlugin_l62) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .B_SIGNED(32'd0), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd1) + ) _407_ ( + .A(execute_to_memory_INSTRUCTION[11:7]), + .B(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19:15]), + .Y(when_HazardSimplePlugin_l59_1) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .B_SIGNED(32'd0), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd1) + ) _408_ ( + .A(execute_to_memory_INSTRUCTION[11:7]), + .B(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24:20]), + .Y(when_HazardSimplePlugin_l62_1) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .B_SIGNED(32'd0), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd1) + ) _409_ ( + .A(decode_to_execute_INSTRUCTION[11:7]), + .B(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19:15]), + .Y(when_HazardSimplePlugin_l59_2) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .B_SIGNED(32'd0), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd1) + ) _410_ ( + .A(decode_to_execute_INSTRUCTION[11:7]), + .B(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24:20]), + .Y(when_HazardSimplePlugin_l62_2) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd32), + .B_SIGNED(32'd0), + .B_WIDTH(32'd32), + .Y_WIDTH(32'd1) + ) _411_ ( + .A(decode_to_execute_SRC1), + .B(decode_to_execute_SRC2), + .Y(execute_BranchPlugin_eq) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _412_ ( + .A(decode_to_execute_BRANCH_CTRL), + .B(2'h3), + .Y(_123_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd12), + .B_SIGNED(32'd0), + .B_WIDTH(32'd10), + .Y_WIDTH(32'd1) + ) _413_ ( + .A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:20]), + .B(10'h300), + .Y(_124_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd12), + .B_SIGNED(32'd0), + .B_WIDTH(32'd10), + .Y_WIDTH(32'd1) + ) _414_ ( + .A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:20]), + .B(10'h344), + .Y(_125_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd12), + .B_SIGNED(32'd0), + .B_WIDTH(32'd10), + .Y_WIDTH(32'd1) + ) _415_ ( + .A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:20]), + .B(10'h304), + .Y(_126_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd12), + .B_SIGNED(32'd0), + .B_WIDTH(32'd10), + .Y_WIDTH(32'd1) + ) _416_ ( + .A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:20]), + .B(10'h342), + .Y(_127_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _417_ ( + .A(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid), + .B(_170_), + .Y(_zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _418_ ( + .A(_110_), + .B(execute_LightShifterPlugin_shiftInput[31]), + .Y(_zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1[31]) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _419_ ( + .A(_142_), + .B(decode_IS_EBREAK), + .Y(_128_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _420_ ( + .A(_128_), + .B(DebugPlugin_allowEBreak), + .Y(decode_DO_EBREAK) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _421_ ( + .A(decode_SRC_ADD_ZERO), + .B(_143_), + .Y(decode_SRC2_FORCE_ZERO) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _422_ ( + .A(_117_), + .B(_118_), + .Y(_129_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _423_ ( + .A(_119_), + .B(_118_), + .Y(_130_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _424_ ( + .A(IBusSimplePlugin_fetchPc_output_valid), + .B(IBusSimplePlugin_fetchPc_output_ready), + .Y(IBusSimplePlugin_fetchPc_output_fire_1) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _425_ ( + .A(_144_), + .B(IBusSimplePlugin_fetchPc_output_ready), + .Y(when_Fetcher_l131_1) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _426_ ( + .A(IBusSimplePlugin_fetchPc_booted), + .B(_166_), + .Y(when_Fetcher_l158) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _427_ ( + .A(_145_), + .B(IBusSimplePlugin_fetchPc_booted), + .Y(IBusSimplePlugin_fetchPc_output_valid) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _428_ ( + .A(IBusSimplePlugin_iBusRsp_stages_1_output_ready), + .B(_zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready), + .Y(IBusSimplePlugin_fetchPc_output_ready) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _429_ ( + .A(_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2), + .B(_zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready), + .Y(IBusSimplePlugin_iBusRsp_stages_1_output_valid) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _430_ ( + .A(IBusSimplePlugin_iBusRsp_stages_1_output_ready), + .B(_171_), + .Y(IBusSimplePlugin_cmdFork_canEmit) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _431_ ( + .A(_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2), + .B(_167_), + .Y(when_IBusSimplePlugin_l305) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _432_ ( + .A(_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2), + .B(IBusSimplePlugin_cmdFork_canEmit), + .Y(IBusSimplePlugin_cmd_valid) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _433_ ( + .A(IBusSimplePlugin_cmd_valid), + .B(iBus_cmd_ready), + .Y(IBusSimplePlugin_cmd_fire) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _434_ ( + .A(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid), + .B(_120_), + .Y(IBusSimplePlugin_rspJoin_rspBuffer_output_valid) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _435_ ( + .A(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid), + .B(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready), + .Y(IBusSimplePlugin_pending_dec) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _436_ ( + .A(_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid), + .B(IBusSimplePlugin_rspJoin_rspBuffer_output_valid), + .Y(IBusSimplePlugin_iBusRsp_output_valid) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _437_ ( + .A(IBusSimplePlugin_iBusRsp_output_valid), + .B(IBusSimplePlugin_rspJoin_join_ready), + .Y(IBusSimplePlugin_rspJoin_join_fire) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _438_ ( + .A(execute_arbitration_isValid), + .B(decode_to_execute_MEMORY_ENABLE), + .Y(_131_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _439_ ( + .A(_131_), + .B(_148_), + .Y(_132_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _440_ ( + .A(_132_), + .B(_149_), + .Y(dBus_cmd_valid) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _441_ ( + .A(_131_), + .B(_150_), + .Y(when_DBusSimplePlugin_l428) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _442_ ( + .A(memory_arbitration_isValid), + .B(execute_to_memory_MEMORY_ENABLE), + .Y(_133_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _443_ ( + .A(_133_), + .B(_151_), + .Y(_134_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _444_ ( + .A(_134_), + .B(_152_), + .Y(when_DBusSimplePlugin_l482) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _445_ ( + .A(_zz_writeBack_DBusSimplePlugin_rspFormated_1[7]), + .B(_153_), + .Y(_zz_writeBack_DBusSimplePlugin_rspFormated) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _446_ ( + .A(_zz_writeBack_DBusSimplePlugin_rspFormated_3[15]), + .B(_153_), + .Y(_zz_writeBack_DBusSimplePlugin_rspFormated_2) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _447_ ( + .A(writeBack_arbitration_isValid), + .B(memory_to_writeBack_MEMORY_ENABLE), + .Y(when_DBusSimplePlugin_l558) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _448_ ( + .A(CsrPlugin_mip_MTIP), + .B(CsrPlugin_mie_MTIE), + .Y(_zz_when_CsrPlugin_l952) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _449_ ( + .A(CsrPlugin_mip_MSIP), + .B(CsrPlugin_mie_MSIE), + .Y(_zz_when_CsrPlugin_l952_1) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _450_ ( + .A(CsrPlugin_mip_MEIP), + .B(CsrPlugin_mie_MEIE), + .Y(_zz_when_CsrPlugin_l952_2) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _451_ ( + .A(CsrPlugin_interrupt_valid), + .B(CsrPlugin_allowInterrupts), + .Y(_135_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _452_ ( + .A(_135_), + .B(decode_arbitration_isValid), + .Y(CsrPlugin_pipelineLiberator_active) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _453_ ( + .A(CsrPlugin_interrupt_valid), + .B(CsrPlugin_pipelineLiberator_pcValids_2), + .Y(_136_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _454_ ( + .A(_136_), + .B(CsrPlugin_allowInterrupts), + .Y(CsrPlugin_interruptJump) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _455_ ( + .A(writeBack_arbitration_isValid), + .B(memory_to_writeBack_ENV_CTRL), + .Y(when_CsrPlugin_l1064) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _456_ ( + .A(execute_arbitration_isValid), + .B(decode_to_execute_ENV_CTRL), + .Y(_137_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _457_ ( + .A(memory_arbitration_isValid), + .B(execute_to_memory_ENV_CTRL), + .Y(_138_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _458_ ( + .A(execute_arbitration_isValid), + .B(decode_to_execute_IS_CSR), + .Y(when_CsrPlugin_l1176) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _459_ ( + .A(when_CsrPlugin_l1176), + .B(decode_to_execute_CSR_WRITE_OPCODE), + .Y(execute_CsrPlugin_writeInstruction) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _460_ ( + .A(execute_CsrPlugin_writeInstruction), + .B(_155_), + .Y(execute_CsrPlugin_writeEnable) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _461_ ( + .A(memory_to_writeBack_REGFILE_WRITE_VALID), + .B(writeBack_arbitration_isValid), + .Y(HazardSimplePlugin_writeBackWrites_valid) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _462_ ( + .A(execute_arbitration_isValid), + .B(execute_LightShifterPlugin_isShift), + .Y(_139_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _463_ ( + .A(_139_), + .B(_172_), + .Y(when_ShiftPlugins_l169) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _464_ ( + .A(memory_arbitration_isValid), + .B(execute_to_memory_REGFILE_WRITE_VALID), + .Y(when_HazardSimplePlugin_l57_1) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _465_ ( + .A(execute_arbitration_isValid), + .B(decode_to_execute_REGFILE_WRITE_VALID), + .Y(when_HazardSimplePlugin_l57_2) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _466_ ( + .A(decode_arbitration_isValid), + .B(_168_), + .Y(when_HazardSimplePlugin_l113) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _467_ ( + .A(memory_arbitration_isValid), + .B(execute_to_memory_BRANCH_DO), + .Y(BranchPlugin_jumpInterface_valid) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _468_ ( + .A(DebugPlugin_debugUsed), + .B(_158_), + .Y(DebugPlugin_allowEBreak) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _469_ ( + .A(execute_arbitration_isValid), + .B(decode_to_execute_DO_EBREAK), + .Y(when_DebugPlugin_l295) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _470_ ( + .A(DebugPlugin_stepIt), + .B(IBusSimplePlugin_incomingInstruction), + .Y(when_DebugPlugin_l311) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _471_ ( + .A(_159_), + .B(_148_), + .Y(when_Pipeline_l124_40) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _472_ ( + .A(IBusSimplePlugin_rspJoin_join_ready), + .B(_160_), + .Y(when_Pipeline_l154) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _473_ ( + .A(_155_), + .B(_161_), + .Y(when_Pipeline_l154_1) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _474_ ( + .A(_159_), + .B(_162_), + .Y(when_Pipeline_l154_2) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _475_ ( + .A(IBusSimplePlugin_iBusRsp_stages_1_output_valid), + .B(_163_), + .Y(_140_) + ); + \$logic_and #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _476_ ( + .A(IBusSimplePlugin_iBusRsp_output_valid), + .B(_163_), + .Y(_141_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _477_ ( + .A(DebugPlugin_haltIt), + .Y(_142_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _478_ ( + .A(decode_SRC_USE_SUB_LESS), + .Y(_143_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _479_ ( + .A(_164_), + .Y(decode_CSR_WRITE_OPCODE) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _480_ ( + .A(IBusSimplePlugin_fetchPc_output_valid), + .Y(_144_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _481_ ( + .A(IBusSimplePlugin_fetcherHalt), + .Y(_145_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _482_ ( + .A(IBusSimplePlugin_iBusRsp_stages_1_halt), + .Y(_zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _483_ ( + .A(decode_arbitration_isStuck), + .Y(IBusSimplePlugin_rspJoin_join_ready) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _484_ ( + .A(IBusSimplePlugin_cmdFork_canEmit), + .Y(_146_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _485_ ( + .A(iBus_cmd_ready), + .Y(_147_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _486_ ( + .A(execute_arbitration_isStuckByOthers), + .Y(_148_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _487_ ( + .A(execute_arbitration_isFlushed), + .Y(_149_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _488_ ( + .A(dBus_cmd_ready), + .Y(_150_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _489_ ( + .A(execute_to_memory_MEMORY_STORE), + .Y(_151_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _490_ ( + .A(dBus_rsp_ready), + .Y(_152_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _491_ ( + .A(memory_to_writeBack_INSTRUCTION[14]), + .Y(_153_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _492_ ( + .A(CsrPlugin_pipelineLiberator_active), + .Y(_154_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _493_ ( + .A(execute_arbitration_isStuck), + .Y(_155_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _494_ ( + .A(execute_BranchPlugin_eq), + .Y(_156_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _495_ ( + .A(execute_SRC_LESS), + .Y(_157_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _496_ ( + .A(DebugPlugin_disableEbreak), + .Y(_158_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _497_ ( + .A(memory_arbitration_isStuck), + .Y(_159_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _498_ ( + .A(decode_arbitration_removeIt), + .Y(_160_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _499_ ( + .A(execute_arbitration_removeIt), + .Y(_161_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _500_ ( + .A(memory_arbitration_removeIt), + .Y(_162_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _501_ ( + .A(IBusSimplePlugin_externalFlush), + .Y(_163_) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _502_ ( + .A(_129_), + .B(_130_), + .Y(_164_) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _503_ ( + .A(IBusSimplePlugin_fetchPc_correction), + .B(IBusSimplePlugin_fetchPc_pcRegPropagate), + .Y(when_Fetcher_l131) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _504_ ( + .A(IBusSimplePlugin_fetchPc_output_ready), + .B(IBusSimplePlugin_fetchPc_correction), + .Y(_165_) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _505_ ( + .A(_165_), + .B(IBusSimplePlugin_fetchPc_pcRegPropagate), + .Y(_166_) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _506_ ( + .A(_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2), + .B(_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid), + .Y(when_Fetcher_l240) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _507_ ( + .A(_146_), + .B(_147_), + .Y(_167_) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _508_ ( + .A(_170_), + .B(IBusSimplePlugin_externalFlush), + .Y(IBusSimplePlugin_rspJoin_rspBuffer_flush) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _509_ ( + .A(IBusSimplePlugin_rspJoin_join_fire), + .B(IBusSimplePlugin_rspJoin_rspBuffer_flush), + .Y(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _510_ ( + .A(_154_), + .B(decode_arbitration_removeIt), + .Y(when_CsrPlugin_l985) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _511_ ( + .A(HazardSimplePlugin_src0Hazard), + .B(HazardSimplePlugin_src1Hazard), + .Y(_168_) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _512_ ( + .A(DebugPlugin_haltIt), + .B(DebugPlugin_stepIt), + .Y(when_DebugPlugin_l327) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _513_ ( + .A(IBusSimplePlugin_externalFlush), + .B(execute_arbitration_flushIt), + .Y(decode_arbitration_isFlushed) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _514_ ( + .A(_174_), + .B(execute_arbitration_flushIt), + .Y(execute_arbitration_isFlushed) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _515_ ( + .A(execute_arbitration_isStuck), + .B(memory_arbitration_isStuck), + .Y(_169_) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _516_ ( + .A(decode_arbitration_haltByOther), + .B(_169_), + .Y(decode_arbitration_isStuckByOthers) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _517_ ( + .A(decode_arbitration_haltItself), + .B(decode_arbitration_isStuckByOthers), + .Y(decode_arbitration_isStuck) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _518_ ( + .A(execute_arbitration_haltByOther), + .B(memory_arbitration_isStuck), + .Y(execute_arbitration_isStuckByOthers) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _519_ ( + .A(execute_arbitration_haltItself), + .B(execute_arbitration_isStuckByOthers), + .Y(execute_arbitration_isStuck) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _520_ ( + .A(_155_), + .B(execute_arbitration_removeIt), + .Y(when_Pipeline_l151) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _521_ ( + .A(_159_), + .B(memory_arbitration_removeIt), + .Y(when_Pipeline_l151_1) + ); + \$logic_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _522_ ( + .A(_175_), + .B(IBusSimplePlugin_incomingInstruction), + .Y(_012_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _523_ ( + .A(IBusSimplePlugin_rspJoin_rspBuffer_discardCounter), + .Y(_170_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _524_ ( + .A({ CsrPlugin_jumpInterface_valid, memory_arbitration_flushNext, execute_arbitration_flushIt }), + .Y(IBusSimplePlugin_externalFlush) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _525_ ( + .A({ BranchPlugin_jumpInterface_valid, CsrPlugin_jumpInterface_valid }), + .Y(IBusSimplePlugin_jump_pcLoad_valid) + ); + \$ne #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _526_ ( + .A(IBusSimplePlugin_pending_value), + .B(3'h7), + .Y(_171_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _527_ ( + .A(decode_to_execute_SHIFT_CTRL), + .Y(execute_LightShifterPlugin_isShift) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd5), + .Y_WIDTH(32'd1) + ) _528_ ( + .A(decode_to_execute_SRC2[4:0]), + .Y(_172_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _529_ ( + .A({ writeBack_arbitration_isValid, memory_arbitration_isValid }), + .Y(_173_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _530_ ( + .A({ CsrPlugin_jumpInterface_valid, memory_arbitration_flushNext }), + .Y(_174_) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _531_ ( + .A(switch_Fetcher_l362), + .Y(when_Fetcher_l398) + ); + \$reduce_bool #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd4), + .Y_WIDTH(32'd1) + ) _532_ ( + .A({ writeBack_arbitration_isValid, memory_arbitration_isValid, execute_arbitration_isValid, decode_arbitration_isValid }), + .Y(_175_) + ); + \$not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _533_ ( + .A(_zz_IBusSimplePlugin_jump_pcLoad_payload_2[0]), + .Y(_108_[0]) + ); + \$not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd32), + .Y_WIDTH(32'd32) + ) _534_ ( + .A(decode_to_execute_SRC2), + .Y(_176_) + ); + \$not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd13), + .Y_WIDTH(32'd13) + ) _535_ ( + .A(decode_to_execute_SRC1[12:0]), + .Y(_109_[12:0]) + ); + \$or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd32), + .B_SIGNED(32'd0), + .B_WIDTH(32'd32), + .Y_WIDTH(32'd32) + ) _536_ ( + .A(decode_to_execute_SRC1), + .B(decode_to_execute_SRC2), + .Y(_177_) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) DebugPlugin_haltIt_reg /* _537_ */ ( + .ARST(resetCtrl_mainClkReset), + .CLK(io_mainClk), + .D(_010_), + .Q(DebugPlugin_haltIt) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) DebugPlugin_haltedByBreak_reg /* _538_ */ ( + .ARST(resetCtrl_mainClkReset), + .CLK(io_mainClk), + .D(_011_), + .Q(DebugPlugin_haltedByBreak) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) DebugPlugin_isPipBusy_reg /* _539_ */ ( + .CLK(io_mainClk), + .D(_012_), + .Q(DebugPlugin_isPipBusy) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) _zz_when_DebugPlugin_l244_reg /* _540_ */ ( + .CLK(io_mainClk), + .D(debug_bus_cmd_payload_address[2]), + .Q(_zz_when_DebugPlugin_l244) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) DebugPlugin_resetIt_regNext_reg /* _541_ */ ( + .CLK(io_mainClk), + .D(DebugPlugin_resetIt), + .Q(DebugPlugin_resetIt_regNext) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) CsrPlugin_mip_MEIP_reg /* _542_ */ ( + .CLK(io_mainClk), + .D(externalInterrupt), + .Q(CsrPlugin_mip_MEIP) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) CsrPlugin_mip_MTIP_reg /* _543_ */ ( + .CLK(io_mainClk), + .D(timerInterrupt), + .Q(CsrPlugin_mip_MTIP) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) CsrPlugin_mip_MSIP_reg /* _544_ */ ( + .CLK(io_mainClk), + .D(_002_), + .Q(CsrPlugin_mip_MSIP) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd5) + ) _545_ ( + .CLK(io_mainClk), + .D(memory_to_writeBack_INSTRUCTION[11:7]), + .Q(HazardSimplePlugin_writeBackBuffer_payload_address) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd30) + ) _546_ ( + .CLK(io_mainClk), + .D(execute_to_memory_INSTRUCTION), + .Q(memory_to_writeBack_INSTRUCTION[29:0]) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) memory_to_writeBack_MEMORY_ENABLE_reg /* _547_ */ ( + .CLK(io_mainClk), + .D(execute_to_memory_MEMORY_ENABLE), + .Q(memory_to_writeBack_MEMORY_ENABLE) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) memory_to_writeBack_REGFILE_WRITE_VALID_reg /* _548_ */ ( + .CLK(io_mainClk), + .D(execute_to_memory_REGFILE_WRITE_VALID), + .Q(memory_to_writeBack_REGFILE_WRITE_VALID) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) memory_to_writeBack_ENV_CTRL_reg /* _549_ */ ( + .CLK(io_mainClk), + .D(execute_to_memory_ENV_CTRL), + .Q(memory_to_writeBack_ENV_CTRL) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd2) + ) _550_ ( + .CLK(io_mainClk), + .D(execute_to_memory_MEMORY_ADDRESS_LOW), + .Q(memory_to_writeBack_MEMORY_ADDRESS_LOW) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd32) + ) _551_ ( + .CLK(io_mainClk), + .D(execute_to_memory_REGFILE_WRITE_DATA), + .Q(memory_to_writeBack_REGFILE_WRITE_DATA) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd32) + ) _552_ ( + .CLK(io_mainClk), + .D(dBus_rsp_data), + .Q(memory_to_writeBack_MEMORY_READ_DATA) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) writeBack_arbitration_isValid_reg /* _553_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_023_), + .Q(writeBack_arbitration_isValid) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) IBusSimplePlugin_fetchPc_booted_reg /* _554_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(1'h1), + .Q(IBusSimplePlugin_fetchPc_booted) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(3'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd3) + ) _555_ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(IBusSimplePlugin_pending_next), + .Q(IBusSimplePlugin_pending_value) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(3'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd3) + ) _556_ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_014_), + .Q(IBusSimplePlugin_rspJoin_rspBuffer_discardCounter) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) CsrPlugin_mstatus_MIE_reg /* _557_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_003_), + .Q(CsrPlugin_mstatus_MIE) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) CsrPlugin_mstatus_MPIE_reg /* _558_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_004_), + .Q(CsrPlugin_mstatus_MPIE) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(2'h3), + .CLK_POLARITY(1'h1), + .WIDTH(32'd2) + ) _559_ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_005_), + .Q(CsrPlugin_mstatus_MPP) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) CsrPlugin_interrupt_valid_reg /* _560_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(_001_), + .Q(CsrPlugin_interrupt_valid) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h1), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) _zz_2_reg /* _561_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(1'h0), + .Q(_zz_2) + ); + \$adff #( + .ARST_POLARITY(1'h1), + .ARST_VALUE(1'h0), + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) HazardSimplePlugin_writeBackBuffer_valid_reg /* _562_ */ ( + .ARST(resetCtrl_systemReset), + .CLK(io_mainClk), + .D(HazardSimplePlugin_writeBackWrites_valid), + .Q(HazardSimplePlugin_writeBackBuffer_valid) + ); + \$mux #( + .WIDTH(32'd1) + ) _563_ ( + .A(1'h1), + .B(1'h0), + .S(debug_bus_cmd_payload_data[26]), + .Y(_178_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd6), + .Y_WIDTH(32'd1) + ) _564_ ( + .A(debug_bus_cmd_payload_address[7:2]), + .Y(_179_) + ); + \$mux #( + .WIDTH(32'd1) + ) _565_ ( + .A(DebugPlugin_haltedByBreak), + .B(1'h0), + .S(debug_bus_cmd_payload_data[25]), + .Y(_180_) + ); + \$mux #( + .WIDTH(32'd1) + ) _566_ ( + .A(DebugPlugin_haltedByBreak), + .B(_180_), + .S(debug_bus_cmd_payload_wr), + .Y(_181_) + ); + \$mux #( + .WIDTH(32'd1) + ) _567_ ( + .A(DebugPlugin_haltedByBreak), + .B(_181_), + .S(_179_), + .Y(_182_) + ); + \$mux #( + .WIDTH(32'd1) + ) _568_ ( + .A(DebugPlugin_haltedByBreak), + .B(_182_), + .S(debug_bus_cmd_valid), + .Y(_183_) + ); + \$mux #( + .WIDTH(32'd1) + ) _569_ ( + .A(1'h1), + .B(_183_), + .S(_173_), + .Y(_184_) + ); + \$mux #( + .WIDTH(32'd1) + ) _570_ ( + .A(_183_), + .B(_184_), + .S(when_DebugPlugin_l295), + .Y(_011_) + ); + \$mux #( + .WIDTH(32'd1) + ) _571_ ( + .A(DebugPlugin_haltIt), + .B(1'h1), + .S(debug_bus_cmd_payload_data[17]), + .Y(_185_) + ); + \$mux #( + .WIDTH(32'd1) + ) _572_ ( + .A(_185_), + .B(1'h0), + .S(debug_bus_cmd_payload_data[25]), + .Y(_186_) + ); + \$mux #( + .WIDTH(32'd1) + ) _573_ ( + .A(DebugPlugin_haltIt), + .B(_186_), + .S(debug_bus_cmd_payload_wr), + .Y(_187_) + ); + \$mux #( + .WIDTH(32'd1) + ) _574_ ( + .A(DebugPlugin_haltIt), + .B(_187_), + .S(_179_), + .Y(_188_) + ); + \$mux #( + .WIDTH(32'd1) + ) _575_ ( + .A(DebugPlugin_haltIt), + .B(_188_), + .S(debug_bus_cmd_valid), + .Y(_189_) + ); + \$mux #( + .WIDTH(32'd1) + ) _576_ ( + .A(1'h1), + .B(_189_), + .S(_173_), + .Y(_190_) + ); + \$mux #( + .WIDTH(32'd1) + ) _577_ ( + .A(_189_), + .B(_190_), + .S(when_DebugPlugin_l295), + .Y(_191_) + ); + \$mux #( + .WIDTH(32'd1) + ) _578_ ( + .A(_191_), + .B(1'h1), + .S(decode_arbitration_isValid), + .Y(_192_) + ); + \$mux #( + .WIDTH(32'd1) + ) _579_ ( + .A(_191_), + .B(_192_), + .S(when_DebugPlugin_l311), + .Y(_010_) + ); + \$mux #( + .WIDTH(32'd1) + ) _580_ ( + .A(1'h1), + .B(1'h0), + .S(debug_bus_cmd_payload_data[24]), + .Y(_193_) + ); + \$mux #( + .WIDTH(32'd32) + ) _581_ ( + .A(_zz_lastStageRegFileWrite_payload_data), + .B({ decode_to_execute_PC[31:2], 2'h0 }), + .S(when_DebugPlugin_l295), + .Y(_009_) + ); + \$mux #( + .WIDTH(32'd1) + ) _582_ ( + .A(softwareInterrupt), + .B(CsrPlugin_csrMapping_writeDataSignal[3]), + .S(execute_CsrPlugin_writeEnable), + .Y(_194_) + ); + \$mux #( + .WIDTH(32'd1) + ) _583_ ( + .A(softwareInterrupt), + .B(_194_), + .S(execute_CsrPlugin_csr_836), + .Y(_002_) + ); + \$mux #( + .WIDTH(32'd25) + ) _584_ ( + .A(IBusSimplePlugin_iBusRsp_output_payload_rsp_inst[24:0]), + .B({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24:15], 15'hxxxx }), + .S(decode_arbitration_isStuck), + .Y(decode_INSTRUCTION_ANTICIPATED[24:0]) + ); + \$mux #( + .WIDTH(32'd32) + ) _585_ ( + .A({ IBusSimplePlugin_iBusRsp_output_payload_rsp_inst[31:25], decode_INSTRUCTION_ANTICIPATED[24:0] }), + .B(debug_bus_cmd_payload_data), + .S(when_Fetcher_l398), + .Y(_017_) + ); + \$mux #( + .WIDTH(32'd1) + ) _586_ ( + .A(1'h0), + .B(1'h1), + .S(_zz_when_CsrPlugin_l952), + .Y(_195_) + ); + \$mux #( + .WIDTH(32'd1) + ) _587_ ( + .A(_195_), + .B(1'h1), + .S(_zz_when_CsrPlugin_l952_1), + .Y(_196_) + ); + \$mux #( + .WIDTH(32'd1) + ) _588_ ( + .A(_196_), + .B(1'h1), + .S(_zz_when_CsrPlugin_l952_2), + .Y(_197_) + ); + \$mux #( + .WIDTH(32'd1) + ) _589_ ( + .A(1'h0), + .B(_197_), + .S(CsrPlugin_mstatus_MIE), + .Y(_198_) + ); + \$mux #( + .WIDTH(32'd1) + ) _590_ ( + .A(_198_), + .B(1'h0), + .S(CsrPlugin_interruptJump), + .Y(_001_) + ); + \$mux #( + .WIDTH(32'd3) + ) _591_ ( + .A(_243_), + .B(IBusSimplePlugin_pending_next), + .S(IBusSimplePlugin_externalFlush), + .Y(_014_) + ); + \$pmux #( + .S_WIDTH(32'd5), + .WIDTH(32'd3) + ) _592_ ( + .A(3'hx), + .B(15'h14e0), + .S({ _203_, _202_, _201_, _200_, _199_ }), + .Y(_022_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _593_ ( + .A(switch_Fetcher_l362), + .B(3'h4), + .Y(_199_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _594_ ( + .A(switch_Fetcher_l362), + .B(2'h3), + .Y(_200_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _595_ ( + .A(switch_Fetcher_l362), + .B(2'h2), + .Y(_201_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _596_ ( + .A(switch_Fetcher_l362), + .B(1'h1), + .Y(_202_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _597_ ( + .A(switch_Fetcher_l362), + .Y(_203_) + ); + \$mux #( + .WIDTH(32'd1) + ) _598_ ( + .A(1'h1), + .B(1'h0), + .S(execute_LightShifterPlugin_done), + .Y(_204_) + ); + \$mux #( + .WIDTH(32'd1) + ) _599_ ( + .A(_204_), + .B(1'h0), + .S(execute_arbitration_removeIt), + .Y(_019_) + ); + \$mux #( + .WIDTH(32'd1) + ) _600_ ( + .A(CsrPlugin_pipelineLiberator_pcValids_1), + .B(1'h0), + .S(when_CsrPlugin_l985), + .Y(_008_) + ); + \$mux #( + .WIDTH(32'd1) + ) _601_ ( + .A(CsrPlugin_pipelineLiberator_pcValids_0), + .B(1'h0), + .S(when_CsrPlugin_l985), + .Y(_007_) + ); + \$mux #( + .WIDTH(32'd1) + ) _602_ ( + .A(1'h1), + .B(1'h0), + .S(when_CsrPlugin_l985), + .Y(_006_) + ); + \$mux #( + .WIDTH(32'd2) + ) _603_ ( + .A(CsrPlugin_mstatus_MPP), + .B(2'h3), + .S(CsrPlugin_interruptJump), + .Y(_205_) + ); + \$mux #( + .WIDTH(32'd2) + ) _604_ ( + .A(_205_), + .B(2'h0), + .S(_207_), + .Y(_206_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _605_ ( + .A(memory_to_writeBack_INSTRUCTION[29:28]), + .B(2'h3), + .Y(_207_) + ); + \$mux #( + .WIDTH(32'd2) + ) _606_ ( + .A(_205_), + .B(_206_), + .S(when_CsrPlugin_l1064), + .Y(_208_) + ); + \$mux #( + .WIDTH(32'd2) + ) _607_ ( + .A(_208_), + .B(CsrPlugin_csrMapping_writeDataSignal[12:11]), + .S(execute_CsrPlugin_writeEnable), + .Y(_209_) + ); + \$mux #( + .WIDTH(32'd2) + ) _608_ ( + .A(_208_), + .B(_209_), + .S(execute_CsrPlugin_csr_768), + .Y(_005_) + ); + \$mux #( + .WIDTH(32'd1) + ) _609_ ( + .A(CsrPlugin_mstatus_MPIE), + .B(CsrPlugin_mstatus_MIE), + .S(CsrPlugin_interruptJump), + .Y(_210_) + ); + \$mux #( + .WIDTH(32'd1) + ) _610_ ( + .A(_210_), + .B(1'h1), + .S(_207_), + .Y(_211_) + ); + \$mux #( + .WIDTH(32'd1) + ) _611_ ( + .A(_210_), + .B(_211_), + .S(when_CsrPlugin_l1064), + .Y(_212_) + ); + \$mux #( + .WIDTH(32'd1) + ) _612_ ( + .A(_212_), + .B(CsrPlugin_csrMapping_writeDataSignal[7]), + .S(execute_CsrPlugin_writeEnable), + .Y(_213_) + ); + \$mux #( + .WIDTH(32'd1) + ) _613_ ( + .A(_212_), + .B(_213_), + .S(execute_CsrPlugin_csr_768), + .Y(_004_) + ); + \$mux #( + .WIDTH(32'd1) + ) _614_ ( + .A(CsrPlugin_mstatus_MIE), + .B(1'h0), + .S(CsrPlugin_interruptJump), + .Y(_214_) + ); + \$mux #( + .WIDTH(32'd1) + ) _615_ ( + .A(_214_), + .B(CsrPlugin_mstatus_MPIE), + .S(_207_), + .Y(_215_) + ); + \$mux #( + .WIDTH(32'd1) + ) _616_ ( + .A(_214_), + .B(_215_), + .S(when_CsrPlugin_l1064), + .Y(_216_) + ); + \$mux #( + .WIDTH(32'd1) + ) _617_ ( + .A(_216_), + .B(CsrPlugin_csrMapping_writeDataSignal[3]), + .S(execute_CsrPlugin_writeEnable), + .Y(_217_) + ); + \$mux #( + .WIDTH(32'd1) + ) _618_ ( + .A(_216_), + .B(_217_), + .S(execute_CsrPlugin_csr_768), + .Y(_003_) + ); + \$mux #( + .WIDTH(32'd1) + ) _619_ ( + .A(_141_), + .B(1'h0), + .S(decode_arbitration_isStuck), + .Y(_018_) + ); + \$mux #( + .WIDTH(32'd1) + ) _620_ ( + .A(1'h0), + .B(_140_), + .S(IBusSimplePlugin_iBusRsp_stages_1_output_ready), + .Y(_016_) + ); + \$mux #( + .WIDTH(32'd1) + ) _621_ ( + .A(1'h0), + .B(IBusSimplePlugin_fetchPc_output_valid), + .S(IBusSimplePlugin_fetchPc_output_ready), + .Y(_015_) + ); + \$mux #( + .WIDTH(32'd1) + ) _622_ ( + .A(1'h0), + .B(1'h1), + .S(IBusSimplePlugin_fetchPc_output_fire_1), + .Y(_218_) + ); + \$mux #( + .WIDTH(32'd1) + ) _623_ ( + .A(_218_), + .B(1'h0), + .S(when_Fetcher_l131_1), + .Y(_013_) + ); + \$mux #( + .WIDTH(32'd1) + ) _624_ ( + .A(1'h0), + .B(memory_arbitration_isValid), + .S(when_Pipeline_l154_2), + .Y(_023_) + ); + \$mux #( + .WIDTH(32'd1) + ) _625_ ( + .A(1'h0), + .B(execute_arbitration_isValid), + .S(when_Pipeline_l154_1), + .Y(_021_) + ); + \$mux #( + .WIDTH(32'd1) + ) _626_ ( + .A(1'h0), + .B(decode_arbitration_isValid), + .S(when_Pipeline_l154), + .Y(_020_) + ); + \$mux #( + .WIDTH(32'd3) + ) _627_ ( + .A(3'h0), + .B({ CsrPlugin_mcause_exceptionCode[3:2], 1'h1 }), + .S(execute_CsrPlugin_csr_834), + .Y(_zz_CsrPlugin_csrMapping_readDataInit_3[3:1]) + ); + \$mux #( + .WIDTH(32'd1) + ) _628_ ( + .A(1'h0), + .B(1'h1), + .S(execute_CsrPlugin_csr_834), + .Y(_zz_CsrPlugin_csrMapping_readDataInit_3[31]) + ); + \$mux #( + .WIDTH(32'd1) + ) _629_ ( + .A(1'h0), + .B(CsrPlugin_mie_MSIE), + .S(execute_CsrPlugin_csr_772), + .Y(_zz_CsrPlugin_csrMapping_readDataInit_2[3]) + ); + \$mux #( + .WIDTH(32'd1) + ) _630_ ( + .A(1'h0), + .B(CsrPlugin_mie_MTIE), + .S(execute_CsrPlugin_csr_772), + .Y(_zz_CsrPlugin_csrMapping_readDataInit_2[7]) + ); + \$mux #( + .WIDTH(32'd1) + ) _631_ ( + .A(1'h0), + .B(CsrPlugin_mie_MEIE), + .S(execute_CsrPlugin_csr_772), + .Y(_zz_CsrPlugin_csrMapping_readDataInit_2[11]) + ); + \$mux #( + .WIDTH(32'd1) + ) _632_ ( + .A(1'h0), + .B(CsrPlugin_mip_MSIP), + .S(execute_CsrPlugin_csr_836), + .Y(_zz_CsrPlugin_csrMapping_readDataInit_1[3]) + ); + \$mux #( + .WIDTH(32'd1) + ) _633_ ( + .A(1'h0), + .B(CsrPlugin_mip_MTIP), + .S(execute_CsrPlugin_csr_836), + .Y(_zz_CsrPlugin_csrMapping_readDataInit_1[7]) + ); + \$mux #( + .WIDTH(32'd1) + ) _634_ ( + .A(1'h0), + .B(CsrPlugin_mip_MEIP), + .S(execute_CsrPlugin_csr_836), + .Y(_zz_CsrPlugin_csrMapping_readDataInit_1[11]) + ); + \$mux #( + .WIDTH(32'd1) + ) _635_ ( + .A(1'h0), + .B(CsrPlugin_mstatus_MIE), + .S(execute_CsrPlugin_csr_768), + .Y(_zz_CsrPlugin_csrMapping_readDataInit[3]) + ); + \$mux #( + .WIDTH(32'd1) + ) _636_ ( + .A(1'h0), + .B(CsrPlugin_mstatus_MPIE), + .S(execute_CsrPlugin_csr_768), + .Y(_zz_CsrPlugin_csrMapping_readDataInit[7]) + ); + \$mux #( + .WIDTH(32'd2) + ) _637_ ( + .A(2'h0), + .B(CsrPlugin_mstatus_MPP), + .S(execute_CsrPlugin_csr_768), + .Y(_zz_CsrPlugin_csrMapping_readDataInit[12:11]) + ); + \$mux #( + .WIDTH(32'd1) + ) _638_ ( + .A(1'h0), + .B(1'h1), + .S(_199_), + .Y(IBusSimplePlugin_injectionPort_ready) + ); + \$mux #( + .WIDTH(32'd1) + ) _639_ ( + .A(1'h0), + .B(1'h1), + .S(debug_bus_cmd_payload_wr), + .Y(_045_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd6), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _640_ ( + .A(debug_bus_cmd_payload_address[7:2]), + .B(1'h1), + .Y(_219_) + ); + \$mux #( + .WIDTH(32'd1) + ) _641_ ( + .A(1'h0), + .B(_045_), + .S(_219_), + .Y(_036_) + ); + \$mux #( + .WIDTH(32'd1) + ) _642_ ( + .A(1'h0), + .B(_036_), + .S(debug_bus_cmd_valid), + .Y(IBusSimplePlugin_injectionPort_valid) + ); + \$mux #( + .WIDTH(32'd1) + ) _643_ ( + .A(DebugPlugin_stepIt), + .B(DebugPlugin_busReadDataReg[4]), + .S(_zz_when_DebugPlugin_l244), + .Y(debug_bus_rsp_data[4]) + ); + \$mux #( + .WIDTH(32'd1) + ) _644_ ( + .A(DebugPlugin_isPipBusy), + .B(DebugPlugin_busReadDataReg[2]), + .S(_zz_when_DebugPlugin_l244), + .Y(debug_bus_rsp_data[2]) + ); + \$mux #( + .WIDTH(32'd1) + ) _645_ ( + .A(DebugPlugin_haltIt), + .B(DebugPlugin_busReadDataReg[1]), + .S(_zz_when_DebugPlugin_l244), + .Y(debug_bus_rsp_data[1]) + ); + \$mux #( + .WIDTH(32'd1) + ) _646_ ( + .A(DebugPlugin_resetIt), + .B(DebugPlugin_busReadDataReg[0]), + .S(_zz_when_DebugPlugin_l244), + .Y(debug_bus_rsp_data[0]) + ); + \$mux #( + .WIDTH(32'd1) + ) _647_ ( + .A(DebugPlugin_haltedByBreak), + .B(DebugPlugin_busReadDataReg[3]), + .S(_zz_when_DebugPlugin_l244), + .Y(debug_bus_rsp_data[3]) + ); + \$mux #( + .WIDTH(32'd1) + ) _648_ ( + .A(1'h1), + .B(IBusSimplePlugin_injectionPort_ready), + .S(debug_bus_cmd_payload_wr), + .Y(_046_) + ); + \$mux #( + .WIDTH(32'd1) + ) _649_ ( + .A(1'h1), + .B(_046_), + .S(_219_), + .Y(_037_) + ); + \$mux #( + .WIDTH(32'd1) + ) _650_ ( + .A(1'h1), + .B(_037_), + .S(debug_bus_cmd_valid), + .Y(debug_bus_cmd_ready) + ); + \$pmux #( + .S_WIDTH(32'd2), + .WIDTH(32'd14) + ) _651_ ( + .A({ decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[7], decode_to_execute_INSTRUCTION[11:8], 1'h0 }), + .B({ decode_to_execute_INSTRUCTION[19:12], decode_to_execute_INSTRUCTION[20], decode_to_execute_INSTRUCTION[24:21], 1'h0, decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[24:20] }), + .S({ _220_, _123_ }), + .Y({ execute_BranchPlugin_branch_src2[19:11], execute_BranchPlugin_branch_src2[4:0] }) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _652_ ( + .A(decode_to_execute_BRANCH_CTRL), + .B(2'h2), + .Y(_220_) + ); + \$pmux #( + .S_WIDTH(32'd2), + .WIDTH(32'd1) + ) _653_ ( + .A(_zz_execute_BRANCH_DO), + .B(2'h1), + .S({ _221_, _105_ }), + .Y(_zz_execute_BRANCH_DO_1) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _654_ ( + .A(decode_to_execute_BRANCH_CTRL), + .Y(_221_) + ); + \$pmux #( + .S_WIDTH(32'd3), + .WIDTH(32'd1) + ) _655_ ( + .A(execute_SRC_LESS), + .B({ execute_BranchPlugin_eq, _156_, _157_ }), + .S({ _224_, _223_, _222_ }), + .Y(_zz_execute_BRANCH_DO) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _656_ ( + .A({ decode_to_execute_INSTRUCTION[14], decode_to_execute_INSTRUCTION[12] }), + .B(2'h3), + .Y(_222_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _657_ ( + .A(decode_to_execute_INSTRUCTION[14:12]), + .B(1'h1), + .Y(_223_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _658_ ( + .A(decode_to_execute_INSTRUCTION[14:12]), + .Y(_224_) + ); + \$mux #( + .WIDTH(32'd1) + ) _659_ ( + .A(1'h0), + .B(_058_), + .S(_zz__zz_decode_BRANCH_CTRL_2_32), + .Y(HazardSimplePlugin_src1Hazard) + ); + \$mux #( + .WIDTH(32'd1) + ) _660_ ( + .A(_054_), + .B(1'h1), + .S(when_HazardSimplePlugin_l62_2), + .Y(_025_) + ); + \$mux #( + .WIDTH(32'd1) + ) _661_ ( + .A(_054_), + .B(_025_), + .S(when_HazardSimplePlugin_l57_2), + .Y(_058_) + ); + \$mux #( + .WIDTH(32'd1) + ) _662_ ( + .A(_043_), + .B(1'h1), + .S(when_HazardSimplePlugin_l62_1), + .Y(_056_) + ); + \$mux #( + .WIDTH(32'd1) + ) _663_ ( + .A(_043_), + .B(_056_), + .S(when_HazardSimplePlugin_l57_1), + .Y(_054_) + ); + \$mux #( + .WIDTH(32'd1) + ) _664_ ( + .A(_028_), + .B(1'h1), + .S(when_HazardSimplePlugin_l62), + .Y(_049_) + ); + \$mux #( + .WIDTH(32'd1) + ) _665_ ( + .A(_028_), + .B(_049_), + .S(HazardSimplePlugin_writeBackWrites_valid), + .Y(_043_) + ); + \$mux #( + .WIDTH(32'd1) + ) _666_ ( + .A(1'h0), + .B(1'h1), + .S(HazardSimplePlugin_addr1Match), + .Y(_035_) + ); + \$mux #( + .WIDTH(32'd1) + ) _667_ ( + .A(1'h0), + .B(_035_), + .S(HazardSimplePlugin_writeBackBuffer_valid), + .Y(_028_) + ); + \$mux #( + .WIDTH(32'd1) + ) _668_ ( + .A(1'h0), + .B(_057_), + .S(_zz__zz_decode_BRANCH_CTRL_2_65), + .Y(HazardSimplePlugin_src0Hazard) + ); + \$mux #( + .WIDTH(32'd1) + ) _669_ ( + .A(_053_), + .B(1'h1), + .S(when_HazardSimplePlugin_l59_2), + .Y(_024_) + ); + \$mux #( + .WIDTH(32'd1) + ) _670_ ( + .A(_053_), + .B(_024_), + .S(when_HazardSimplePlugin_l57_2), + .Y(_057_) + ); + \$mux #( + .WIDTH(32'd1) + ) _671_ ( + .A(_042_), + .B(1'h1), + .S(when_HazardSimplePlugin_l59_1), + .Y(_055_) + ); + \$mux #( + .WIDTH(32'd1) + ) _672_ ( + .A(_042_), + .B(_055_), + .S(when_HazardSimplePlugin_l57_1), + .Y(_053_) + ); + \$mux #( + .WIDTH(32'd1) + ) _673_ ( + .A(_027_), + .B(1'h1), + .S(when_HazardSimplePlugin_l59), + .Y(_048_) + ); + \$mux #( + .WIDTH(32'd1) + ) _674_ ( + .A(_027_), + .B(_048_), + .S(HazardSimplePlugin_writeBackWrites_valid), + .Y(_042_) + ); + \$mux #( + .WIDTH(32'd1) + ) _675_ ( + .A(1'h0), + .B(1'h1), + .S(HazardSimplePlugin_addr0Match), + .Y(_034_) + ); + \$mux #( + .WIDTH(32'd1) + ) _676_ ( + .A(1'h0), + .B(_034_), + .S(HazardSimplePlugin_writeBackBuffer_valid), + .Y(_027_) + ); + \$mux #( + .WIDTH(32'd32) + ) _677_ ( + .A({ _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1[31], execute_LightShifterPlugin_shiftInput[31:1] }), + .B({ execute_LightShifterPlugin_shiftInput[30:0], 1'h0 }), + .S(_225_), + .Y(_zz_execute_to_memory_REGFILE_WRITE_DATA_1) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _678_ ( + .A(decode_to_execute_SHIFT_CTRL), + .B(1'h1), + .Y(_225_) + ); + \$mux #( + .WIDTH(32'd32) + ) _679_ ( + .A(_zz_execute_SrcPlugin_addSub), + .B(decode_to_execute_SRC1), + .S(decode_to_execute_SRC2_FORCE_ZERO), + .Y(execute_SrcPlugin_addSub) + ); + \$pmux #( + .S_WIDTH(32'd3), + .WIDTH(32'd32) + ) _680_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_pc[31:2], 2'h0 }), + .B({ _zz_RegFilePlugin_regFile_port1, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:20], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:25], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11:7] }), + .S({ _228_, _227_, _226_ }), + .Y(_zz_decode_SRC2_6) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _681_ ( + .A({ decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63 }), + .B(2'h2), + .Y(_226_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _682_ ( + .A({ decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63 }), + .B(1'h1), + .Y(_227_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _683_ ( + .A({ decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63 }), + .Y(_228_) + ); + \$pmux #( + .S_WIDTH(32'd3), + .WIDTH(32'd32) + ) _684_ ( + .A({ 27'h0000000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19:15] }), + .B({ _zz_RegFilePlugin_regFile_port0, 32'h00000004, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:12], 12'h000 }), + .S({ _231_, _230_, _229_ }), + .Y(_zz_decode_SRC1_1) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _685_ ( + .A({ _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 }), + .B(1'h1), + .Y(_229_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _686_ ( + .A({ _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 }), + .B(2'h2), + .Y(_230_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _687_ ( + .A({ _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 }), + .Y(_231_) + ); + \$pmux #( + .S_WIDTH(32'd2), + .WIDTH(32'd32) + ) _688_ ( + .A(execute_SrcPlugin_addSub), + .B({ execute_IntAluPlugin_bitwise, 31'h00000000, execute_SRC_LESS }), + .S({ _233_, _232_ }), + .Y(_zz_execute_REGFILE_WRITE_DATA) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _689_ ( + .A(decode_to_execute_ALU_CTRL), + .B(1'h1), + .Y(_232_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _690_ ( + .A(decode_to_execute_ALU_CTRL), + .B(2'h2), + .Y(_233_) + ); + \$pmux #( + .S_WIDTH(32'd2), + .WIDTH(32'd32) + ) _691_ ( + .A(_247_), + .B({ _061_, _177_ }), + .S({ _235_, _234_ }), + .Y(execute_IntAluPlugin_bitwise) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _692_ ( + .A(decode_to_execute_ALU_BITWISE_CTRL), + .B(1'h1), + .Y(_234_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _693_ ( + .A(decode_to_execute_ALU_BITWISE_CTRL), + .B(2'h2), + .Y(_235_) + ); + \$mux #( + .WIDTH(32'd32) + ) _694_ ( + .A(_zz_lastStageRegFileWrite_payload_data), + .B(32'd0), + .S(_zz_2), + .Y(lastStageRegFileWrite_payload_data) + ); + \$mux #( + .WIDTH(32'd5) + ) _695_ ( + .A(memory_to_writeBack_INSTRUCTION[11:7]), + .B(5'h00), + .S(_zz_2), + .Y(lastStageRegFileWrite_payload_address) + ); + \$mux #( + .WIDTH(32'd1) + ) _696_ ( + .A(HazardSimplePlugin_writeBackWrites_valid), + .B(1'h1), + .S(_zz_2), + .Y(lastStageRegFileWrite_valid) + ); + \$mux #( + .WIDTH(32'd13) + ) _697_ ( + .A(decode_to_execute_SRC1[12:0]), + .B(_245_[12:0]), + .S(decode_to_execute_INSTRUCTION[13]), + .Y(CsrPlugin_csrMapping_writeDataSignal) + ); + \$pmux #( + .S_WIDTH(32'd2), + .WIDTH(32'd24) + ) _698_ ( + .A({ memory_to_writeBack_MEMORY_READ_DATA[31:16], _zz_writeBack_DBusSimplePlugin_rspFormated_3[15:8] }), + .B({ _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_3[15:8] }), + .S({ _237_, _236_ }), + .Y(writeBack_DBusSimplePlugin_rspFormated[31:8]) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _699_ ( + .A(memory_to_writeBack_INSTRUCTION[13:12]), + .B(1'h1), + .Y(_236_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _700_ ( + .A(memory_to_writeBack_INSTRUCTION[13:12]), + .Y(_237_) + ); + \$mux #( + .WIDTH(32'd8) + ) _701_ ( + .A(memory_to_writeBack_MEMORY_READ_DATA[15:8]), + .B(memory_to_writeBack_MEMORY_READ_DATA[31:24]), + .S(_238_), + .Y(_zz_writeBack_DBusSimplePlugin_rspFormated_3[15:8]) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _702_ ( + .A(memory_to_writeBack_MEMORY_ADDRESS_LOW), + .B(2'h2), + .Y(_238_) + ); + \$pmux #( + .S_WIDTH(32'd3), + .WIDTH(32'd8) + ) _703_ ( + .A(memory_to_writeBack_MEMORY_READ_DATA[7:0]), + .B({ memory_to_writeBack_MEMORY_READ_DATA[15:8], memory_to_writeBack_MEMORY_READ_DATA[23:16], memory_to_writeBack_MEMORY_READ_DATA[31:24] }), + .S({ _240_, _238_, _239_ }), + .Y(_zz_writeBack_DBusSimplePlugin_rspFormated_1[7:0]) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _704_ ( + .A(memory_to_writeBack_MEMORY_ADDRESS_LOW), + .B(2'h3), + .Y(_239_) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _705_ ( + .A(memory_to_writeBack_MEMORY_ADDRESS_LOW), + .B(1'h1), + .Y(_240_) + ); + \$pmux #( + .S_WIDTH(32'd2), + .WIDTH(32'd24) + ) _706_ ( + .A(decode_to_execute_RS2[31:8]), + .B({ decode_to_execute_RS2[7:0], decode_to_execute_RS2[7:0], decode_to_execute_RS2[7:0], decode_to_execute_RS2[15:0], decode_to_execute_RS2[15:8] }), + .S({ _242_, _241_ }), + .Y(dBus_cmd_payload_data[31:8]) + ); + \$eq #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .B_SIGNED(32'd0), + .B_WIDTH(32'd1), + .Y_WIDTH(32'd1) + ) _707_ ( + .A(decode_to_execute_INSTRUCTION[13:12]), + .B(1'h1), + .Y(_241_) + ); + \$logic_not #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _708_ ( + .A(decode_to_execute_INSTRUCTION[13:12]), + .Y(_242_) + ); + \$mux #( + .WIDTH(32'd1) + ) _709_ ( + .A(_zz_IBusSimplePlugin_injector_decodeInput_valid), + .B(1'h1), + .S(_106_), + .Y(decode_arbitration_isValid) + ); + \$mux #( + .WIDTH(32'd1) + ) _710_ ( + .A(1'h0), + .B(1'h1), + .S(when_IBusSimplePlugin_l305), + .Y(IBusSimplePlugin_iBusRsp_stages_1_halt) + ); + \$mux #( + .WIDTH(32'd31) + ) _711_ ( + .A({ _059_[31:2], 1'h0 }), + .B(IBusSimplePlugin_jump_pcLoad_payload[31:1]), + .S(IBusSimplePlugin_jump_pcLoad_valid), + .Y({ IBusSimplePlugin_fetchPc_pc[31:2], _029_[1] }) + ); + \$mux #( + .WIDTH(32'd1) + ) _712_ ( + .A(1'h0), + .B(1'h1), + .S(IBusSimplePlugin_fetchPc_output_ready), + .Y(IBusSimplePlugin_fetchPc_pcRegPropagate) + ); + \$mux #( + .WIDTH(32'd1) + ) _713_ ( + .A(1'h0), + .B(1'h1), + .S(IBusSimplePlugin_jump_pcLoad_valid), + .Y(IBusSimplePlugin_fetchPc_correction) + ); + \$mux #( + .WIDTH(32'd1) + ) _714_ ( + .A(1'h1), + .B(1'h0), + .S(when_DebugPlugin_l327), + .Y(CsrPlugin_allowInterrupts) + ); + \$mux #( + .WIDTH(32'd30) + ) _715_ ( + .A(30'h20000008), + .B(CsrPlugin_mepc[31:2]), + .S(_207_), + .Y(_041_[31:2]) + ); + \$mux #( + .WIDTH(32'd30) + ) _716_ ( + .A(30'h20000008), + .B(_041_[31:2]), + .S(when_CsrPlugin_l1064), + .Y(CsrPlugin_jumpInterface_payload[31:2]) + ); + \$mux #( + .WIDTH(32'd1) + ) _717_ ( + .A(_026_), + .B(1'h1), + .S(when_CsrPlugin_l1064), + .Y(CsrPlugin_jumpInterface_valid) + ); + \$mux #( + .WIDTH(32'd1) + ) _718_ ( + .A(1'h0), + .B(1'h1), + .S(CsrPlugin_interruptJump), + .Y(_026_) + ); + \$mux #( + .WIDTH(32'd1) + ) _719_ ( + .A(_030_), + .B(1'h1), + .S(_zz_IBusSimplePlugin_injector_decodeInput_valid), + .Y(IBusSimplePlugin_incomingInstruction) + ); + \$mux #( + .WIDTH(32'd1) + ) _720_ ( + .A(1'h0), + .B(1'h1), + .S(when_Fetcher_l240), + .Y(_030_) + ); + \$mux #( + .WIDTH(32'd1) + ) _721_ ( + .A(_051_), + .B(1'h1), + .S(when_DebugPlugin_l311), + .Y(IBusSimplePlugin_fetcherHalt) + ); + \$mux #( + .WIDTH(32'd1) + ) _722_ ( + .A(_044_), + .B(1'h1), + .S(DebugPlugin_haltIt), + .Y(_051_) + ); + \$mux #( + .WIDTH(32'd1) + ) _723_ ( + .A(1'h1), + .B(CsrPlugin_jumpInterface_valid), + .S(_173_), + .Y(_050_) + ); + \$mux #( + .WIDTH(32'd1) + ) _724_ ( + .A(CsrPlugin_jumpInterface_valid), + .B(_050_), + .S(when_DebugPlugin_l295), + .Y(_044_) + ); + \$mux #( + .WIDTH(32'd1) + ) _725_ ( + .A(1'h0), + .B(1'h1), + .S(BranchPlugin_jumpInterface_valid), + .Y(memory_arbitration_flushNext) + ); + \$mux #( + .WIDTH(32'd1) + ) _726_ ( + .A(1'h0), + .B(1'h1), + .S(CsrPlugin_jumpInterface_valid), + .Y(memory_arbitration_removeIt) + ); + \$mux #( + .WIDTH(32'd1) + ) _727_ ( + .A(1'h0), + .B(1'h1), + .S(when_DBusSimplePlugin_l482), + .Y(memory_arbitration_isStuck) + ); + \$mux #( + .WIDTH(32'd1) + ) _728_ ( + .A(1'h1), + .B(1'h0), + .S(_173_), + .Y(_039_) + ); + \$mux #( + .WIDTH(32'd1) + ) _729_ ( + .A(1'h0), + .B(_039_), + .S(when_DebugPlugin_l295), + .Y(execute_arbitration_flushIt) + ); + \$mux #( + .WIDTH(32'd1) + ) _730_ ( + .A(1'h0), + .B(1'h1), + .S(execute_arbitration_isFlushed), + .Y(execute_arbitration_removeIt) + ); + \$mux #( + .WIDTH(32'd1) + ) _731_ ( + .A(1'h0), + .B(1'h1), + .S(when_DebugPlugin_l295), + .Y(execute_arbitration_haltByOther) + ); + \$mux #( + .WIDTH(32'd1) + ) _732_ ( + .A(1'h1), + .B(_040_), + .S(execute_LightShifterPlugin_done), + .Y(_052_) + ); + \$mux #( + .WIDTH(32'd1) + ) _733_ ( + .A(_040_), + .B(_052_), + .S(when_ShiftPlugins_l169), + .Y(execute_arbitration_haltItself) + ); + \$mux #( + .WIDTH(32'd1) + ) _734_ ( + .A(_033_), + .B(1'h1), + .S(execute_CsrPlugin_blockedBySideEffects), + .Y(_047_) + ); + \$mux #( + .WIDTH(32'd1) + ) _735_ ( + .A(_033_), + .B(_047_), + .S(when_CsrPlugin_l1176), + .Y(_040_) + ); + \$mux #( + .WIDTH(32'd1) + ) _736_ ( + .A(1'h0), + .B(1'h1), + .S(when_DBusSimplePlugin_l428), + .Y(_033_) + ); + \$mux #( + .WIDTH(32'd1) + ) _737_ ( + .A(1'h0), + .B(1'h1), + .S(decode_arbitration_isFlushed), + .Y(decode_arbitration_removeIt) + ); + \$mux #( + .WIDTH(32'd1) + ) _738_ ( + .A(_038_), + .B(1'h1), + .S(when_HazardSimplePlugin_l113), + .Y(decode_arbitration_haltByOther) + ); + \$mux #( + .WIDTH(32'd1) + ) _739_ ( + .A(_032_), + .B(1'h1), + .S(when_CsrPlugin_l1116), + .Y(_038_) + ); + \$mux #( + .WIDTH(32'd1) + ) _740_ ( + .A(1'h0), + .B(1'h1), + .S(CsrPlugin_pipelineLiberator_active), + .Y(_032_) + ); + \$mux #( + .WIDTH(32'd1) + ) _741_ ( + .A(1'h0), + .B(1'h1), + .S(_201_), + .Y(decode_arbitration_haltItself) + ); + \$mux #( + .WIDTH(32'd32) + ) _742_ ( + .A(memory_to_writeBack_REGFILE_WRITE_DATA), + .B({ writeBack_DBusSimplePlugin_rspFormated[31:8], _zz_writeBack_DBusSimplePlugin_rspFormated_1[7:0] }), + .S(when_DBusSimplePlugin_l558), + .Y(_zz_lastStageRegFileWrite_payload_data) + ); + \$mux #( + .WIDTH(32'd32) + ) _743_ ( + .A(_031_), + .B(_zz_execute_to_memory_REGFILE_WRITE_DATA_1), + .S(when_ShiftPlugins_l169), + .Y(_zz_execute_to_memory_REGFILE_WRITE_DATA) + ); + \$mux #( + .WIDTH(32'd32) + ) _744_ ( + .A(_zz_execute_REGFILE_WRITE_DATA), + .B({ _zz_CsrPlugin_csrMapping_readDataInit_3[31], 18'h00000, _zz_CsrPlugin_csrMapping_readDataInit[12], execute_CsrPlugin_readToWriteData[11], 3'h0, execute_CsrPlugin_readToWriteData[7], 3'h0, execute_CsrPlugin_readToWriteData[3], _zz_CsrPlugin_csrMapping_readDataInit_3[2:1], _zz_CsrPlugin_csrMapping_readDataInit_3[1] }), + .S(when_CsrPlugin_l1176), + .Y(_031_) + ); + \$mux #( + .WIDTH(32'd1) + ) _745_ ( + .A(1'h0), + .B(1'h1), + .S(lastStageRegFileWrite_valid), + .Y(_zz_1) + ); + \$mux #( + .WIDTH(32'd1) + ) _746_ ( + .A(1'h0), + .B(1'h1), + .S(_zz_1), + .Y(_000_[31]) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _747_ ( + .A({ _112_, _111_ }), + .Y(decode_SRC_ADD_ZERO) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _748_ ( + .A(_zz__zz_decode_BRANCH_CTRL_2_18), + .Y(decode_SRC_LESS_UNSIGNED) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _749_ ( + .A({ _114_, _113_ }), + .Y(_zz__zz_decode_BRANCH_CTRL_2_21) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _750_ ( + .A(_zz__zz_decode_BRANCH_CTRL_2_29), + .Y(decode_IS_CSR) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _751_ ( + .A({ _116_, _115_ }), + .Y(_zz__zz_decode_BRANCH_CTRL_2_32) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd6), + .Y_WIDTH(32'd1) + ) _752_ ( + .A({ _zz__zz_decode_BRANCH_CTRL_2_52, _zz__zz_decode_BRANCH_CTRL_2_49[4], _zz__zz_decode_BRANCH_CTRL_2_49[1:0], _zz__zz_decode_BRANCH_CTRL_2_48, _zz__zz_decode_BRANCH_CTRL_2_46 }), + .Y(_zz__zz_decode_BRANCH_CTRL_2_47) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _753_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2], _zz__zz_decode_BRANCH_CTRL_2_60[0] }), + .Y(decode_SRC2_CTRL[1]) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _754_ ( + .A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2], _zz__zz_decode_BRANCH_CTRL_2_64 }), + .Y(_zz__zz_decode_BRANCH_CTRL_2_63) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd4), + .Y_WIDTH(32'd1) + ) _755_ ( + .A({ _zz__zz_decode_BRANCH_CTRL_2_69, _zz__zz_decode_BRANCH_CTRL_2_66, _zz__zz_decode_BRANCH_CTRL_2_39, _zz__zz_decode_BRANCH_CTRL_2_26 }), + .Y(_zz__zz_decode_BRANCH_CTRL_2_65) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _756_ ( + .A({ _zz__zz_decode_BRANCH_CTRL_2_76, _zz__zz_decode_BRANCH_CTRL_2_75, _zz__zz_decode_BRANCH_CTRL_2_74 }), + .Y(decode_SRC_USE_SUB_LESS) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _757_ ( + .A({ _zz__zz_decode_BRANCH_CTRL_2_79, _zz__zz_decode_BRANCH_CTRL_2_78 }), + .Y(_zz__zz_decode_BRANCH_CTRL_2_77) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _758_ ( + .A({ _zz__zz_decode_BRANCH_CTRL_2_81, _zz__zz_decode_BRANCH_CTRL_2_79 }), + .Y(_zz__zz_decode_BRANCH_CTRL_2_80) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd3), + .Y_WIDTH(32'd1) + ) _759_ ( + .A({ _138_, _137_, when_CsrPlugin_l1064 }), + .Y(when_CsrPlugin_l1116) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _760_ ( + .A({ writeBack_arbitration_isValid, memory_arbitration_isValid }), + .Y(execute_CsrPlugin_blockedBySideEffects) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _761_ ( + .A(_zz__zz_decode_BRANCH_CTRL_2_5), + .Y(_zz_decode_BRANCH_CTRL_2[21]) + ); + \$reduce_or #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd2), + .Y_WIDTH(32'd1) + ) _762_ ( + .A({ _121_, _zz__zz_decode_BRANCH_CTRL_2_48 }), + .Y(_zz_decode_BRANCH_CTRL[1]) + ); + \$mux #( + .WIDTH(32'd32) + ) _763_ ( + .A(decode_to_execute_SRC2), + .B(_176_), + .S(decode_to_execute_SRC_USE_SUB_LESS), + .Y(_zz_execute_SrcPlugin_addSub_3) + ); + \$mux #( + .WIDTH(32'd1) + ) _764_ ( + .A(1'h0), + .B(1'h1), + .S(decode_to_execute_SRC_USE_SUB_LESS), + .Y(_zz_execute_SrcPlugin_addSub_4) + ); + \$mux #( + .WIDTH(32'd31) + ) _765_ ( + .A(execute_to_memory_BRANCH_CALC[31:1]), + .B({ CsrPlugin_jumpInterface_payload[31:2], 1'h0 }), + .S(_zz_IBusSimplePlugin_jump_pcLoad_payload_1), + .Y(IBusSimplePlugin_jump_pcLoad_payload[31:1]) + ); + \$mux #( + .WIDTH(32'd1) + ) _766_ ( + .A(IBusSimplePlugin_rspJoin_join_ready), + .B(IBusSimplePlugin_rspJoin_join_fire), + .S(_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid), + .Y(IBusSimplePlugin_iBusRsp_stages_1_output_ready) + ); + \$mux #( + .WIDTH(32'd13) + ) _767_ ( + .A({ _104_[0], _104_[6], decode_to_execute_SRC1[10:8], _104_[5], decode_to_execute_SRC1[6:4], _104_[4:1] }), + .B({ _060_[12:11], 3'h0, _060_[7], 3'h0, _060_[3:0] }), + .S(decode_to_execute_INSTRUCTION[12]), + .Y(_245_[12:0]) + ); + \$mux #( + .WIDTH(32'd1) + ) _768_ ( + .A(decode_to_execute_SRC1[31]), + .B(decode_to_execute_SRC2[31]), + .S(decode_to_execute_SRC_LESS_UNSIGNED), + .Y(_246_) + ); + \$mux #( + .WIDTH(32'd1) + ) _769_ ( + .A(_246_), + .B(execute_SrcPlugin_addSub[31]), + .S(_122_), + .Y(execute_SRC_LESS) + ); + \$mux #( + .WIDTH(32'd5) + ) _770_ ( + .A(decode_to_execute_SRC2[4:0]), + .B(execute_LightShifterPlugin_amplitudeReg), + .S(execute_LightShifterPlugin_isActive), + .Y(execute_LightShifterPlugin_amplitude) + ); + \$mux #( + .WIDTH(32'd32) + ) _771_ ( + .A(decode_to_execute_SRC1), + .B(execute_to_memory_REGFILE_WRITE_DATA), + .S(execute_LightShifterPlugin_isActive), + .Y(execute_LightShifterPlugin_shiftInput) + ); + \$mux #( + .WIDTH(32'd32) + ) _772_ ( + .A({ decode_to_execute_PC[31:2], 2'h0 }), + .B(decode_to_execute_RS1), + .S(_123_), + .Y(execute_BranchPlugin_branch_src1) + ); + \$xor #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd32), + .B_SIGNED(32'd0), + .B_WIDTH(32'd32), + .Y_WIDTH(32'd32) + ) _773_ ( + .A(decode_to_execute_SRC1), + .B(decode_to_execute_SRC2), + .Y(_247_) + ); + StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( + .io_flush(1'h0), + .io_mainClk(io_mainClk), + .io_occupancy(IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy), + .io_pop_payload_error(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error), + .io_pop_payload_inst(IBusSimplePlugin_iBusRsp_output_payload_rsp_inst), + .io_pop_ready(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready), + .io_pop_valid(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid), + .io_push_payload_error(iBus_rsp_payload_error), + .io_push_payload_inst(iBus_rsp_payload_inst), + .io_push_ready(IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready), + .io_push_valid(iBus_rsp_valid), + .resetCtrl_systemReset(resetCtrl_systemReset) + ); + assign _000_[30:0] = { _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31] }; + assign { _029_[31:2], _029_[0] } = { IBusSimplePlugin_fetchPc_pc[31:2], 1'h0 }; + assign _041_[1:0] = 2'h0; + assign _059_[1:0] = 2'h0; + assign { _060_[10:8], _060_[6:4] } = 6'h00; + assign _064_[1:0] = 2'h0; + assign _069_[1:0] = 2'h0; + assign _245_[31:13] = 19'hxxxxx; + assign BranchPlugin_jumpInterface_payload = { execute_to_memory_BRANCH_CALC[31:1], 1'h0 }; + assign CsrPlugin_csrMapping_allowCsrSignal = 1'h0; + assign CsrPlugin_csrMapping_readDataInit = { _zz_CsrPlugin_csrMapping_readDataInit_3[31], 18'h00000, _zz_CsrPlugin_csrMapping_readDataInit[12], execute_CsrPlugin_readToWriteData[11], 3'h0, execute_CsrPlugin_readToWriteData[7], 3'h0, execute_CsrPlugin_readToWriteData[3], _zz_CsrPlugin_csrMapping_readDataInit_3[2:1], _zz_CsrPlugin_csrMapping_readDataInit_3[1] }; + assign CsrPlugin_csrMapping_readDataSignal = { _zz_CsrPlugin_csrMapping_readDataInit_3[31], 18'h00000, _zz_CsrPlugin_csrMapping_readDataInit[12], execute_CsrPlugin_readToWriteData[11], 3'h0, execute_CsrPlugin_readToWriteData[7], 3'h0, execute_CsrPlugin_readToWriteData[3], _zz_CsrPlugin_csrMapping_readDataInit_3[2:1], _zz_CsrPlugin_csrMapping_readDataInit_3[1] }; + assign CsrPlugin_exception = 1'h0; + assign CsrPlugin_hadException = 1'h0; + assign CsrPlugin_inWfi = 1'h0; + assign CsrPlugin_interrupt_code[1:0] = 2'h3; + assign CsrPlugin_interrupt_targetPrivilege = 2'h3; + assign CsrPlugin_jumpInterface_payload[1:0] = 2'h0; + assign CsrPlugin_lastStageWasWfi = 1'h0; + assign CsrPlugin_mcause_exceptionCode[1:0] = 2'h3; + assign CsrPlugin_mcause_interrupt = 1'h1; + assign CsrPlugin_mepc[1:0] = 2'h0; + assign CsrPlugin_misa_base = 2'h1; + assign CsrPlugin_misa_extensions = 26'h0000042; + assign CsrPlugin_mtvec_base = 30'h20000008; + assign CsrPlugin_mtvec_mode = 2'h0; + assign CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + assign CsrPlugin_privilege = 2'h3; + assign CsrPlugin_targetPrivilege = 2'h3; + assign CsrPlugin_trapCause = { CsrPlugin_interrupt_code[3:2], 2'h3 }; + assign CsrPlugin_xtvec_base = 30'h20000008; + assign HazardSimplePlugin_writeBackWrites_payload_address = memory_to_writeBack_INSTRUCTION[11:7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_lastStageRegFileWrite_payload_data; + assign IBusSimplePlugin_cmd_payload_pc = { IBusSimplePlugin_fetchPc_pcReg[31:2], 2'h0 }; + assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; + assign IBusSimplePlugin_fetchPc_output_payload = { IBusSimplePlugin_fetchPc_pc[31:2], 2'h0 }; + assign IBusSimplePlugin_fetchPc_pc[1:0] = 2'h0; + assign IBusSimplePlugin_fetchPc_pcReg[1:0] = 2'h0; + assign IBusSimplePlugin_iBusRsp_flush = IBusSimplePlugin_externalFlush; + assign IBusSimplePlugin_iBusRsp_output_payload_pc = { _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload[31:2], 2'h0 }; + assign IBusSimplePlugin_iBusRsp_output_ready = IBusSimplePlugin_rspJoin_join_ready; + assign IBusSimplePlugin_iBusRsp_redoFetch = 1'h0; + assign IBusSimplePlugin_iBusRsp_stages_0_halt = 1'h0; + assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = { IBusSimplePlugin_fetchPc_pc[31:2], 2'h0 }; + assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = IBusSimplePlugin_fetchPc_output_ready; + assign IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; + assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = { IBusSimplePlugin_fetchPc_pc[31:2], 2'h0 }; + assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = IBusSimplePlugin_fetchPc_output_ready; + assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = IBusSimplePlugin_fetchPc_output_valid; + assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = { IBusSimplePlugin_fetchPc_pcReg[31:2], 2'h0 }; + assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = IBusSimplePlugin_fetchPc_output_ready; + assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2; + assign IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload = { _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload[31:2], 2'h0 }; + assign IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusSimplePlugin_iBusRsp_stages_1_output_ready; + assign IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = { IBusSimplePlugin_fetchPc_pcReg[31:2], 2'h0 }; + assign IBusSimplePlugin_iBusRsp_stages_2_halt = 1'h0; + assign IBusSimplePlugin_iBusRsp_stages_2_input_payload = { _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload[31:2], 2'h0 }; + assign IBusSimplePlugin_iBusRsp_stages_2_input_ready = IBusSimplePlugin_iBusRsp_stages_1_output_ready; + assign IBusSimplePlugin_iBusRsp_stages_2_input_valid = _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusSimplePlugin_iBusRsp_stages_2_output_payload = { _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload[31:2], 2'h0 }; + assign IBusSimplePlugin_iBusRsp_stages_2_output_ready = IBusSimplePlugin_iBusRsp_stages_1_output_ready; + assign IBusSimplePlugin_iBusRsp_stages_2_output_valid = _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusSimplePlugin_injectionPort_payload = debug_bus_cmd_payload_data; + assign IBusSimplePlugin_injector_decodeInput_payload_pc = { _zz_IBusSimplePlugin_injector_decodeInput_payload_pc[31:2], 2'h0 }; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + assign IBusSimplePlugin_injector_decodeInput_ready = IBusSimplePlugin_rspJoin_join_ready; + assign IBusSimplePlugin_injector_decodeInput_valid = _zz_IBusSimplePlugin_injector_decodeInput_valid; + assign IBusSimplePlugin_jump_pcLoad_payload[0] = 1'h0; + assign IBusSimplePlugin_pending_inc = IBusSimplePlugin_cmd_fire; + assign IBusSimplePlugin_rspJoin_exceptionDetected = 1'h0; + assign IBusSimplePlugin_rspJoin_fetchRsp_pc = { _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload[31:2], 2'h0 }; + assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + assign IBusSimplePlugin_rspJoin_join_fire_1 = IBusSimplePlugin_rspJoin_join_fire; + assign IBusSimplePlugin_rspJoin_join_payload_pc = { _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload[31:2], 2'h0 }; + assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + assign IBusSimplePlugin_rspJoin_join_valid = IBusSimplePlugin_iBusRsp_output_valid; + assign IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire = IBusSimplePlugin_pending_dec; + assign IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst = IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + assign IBusSimplePlugin_rspJoin_rspBuffer_output_ready = IBusSimplePlugin_rspJoin_join_fire; + assign { _zz_CsrPlugin_csrMapping_readDataInit[10:8], _zz_CsrPlugin_csrMapping_readDataInit[6:4], _zz_CsrPlugin_csrMapping_readDataInit[2:0] } = 9'h000; + assign { _zz_CsrPlugin_csrMapping_readDataInit_1[10:8], _zz_CsrPlugin_csrMapping_readDataInit_1[6:4], _zz_CsrPlugin_csrMapping_readDataInit_1[2:0] } = 9'h000; + assign { _zz_CsrPlugin_csrMapping_readDataInit_2[10:8], _zz_CsrPlugin_csrMapping_readDataInit_2[6:4], _zz_CsrPlugin_csrMapping_readDataInit_2[2:0] } = 9'h000; + assign { _zz_CsrPlugin_csrMapping_readDataInit_3[30:4], _zz_CsrPlugin_csrMapping_readDataInit_3[0] } = { 27'h0000000, _zz_CsrPlugin_csrMapping_readDataInit_3[1] }; + assign _zz_CsrPlugin_csrMapping_writeDataSignal = CsrPlugin_csrMapping_writeDataSignal; + assign _zz_IBusSimplePlugin_fetchPc_pc = { 29'h00000000, IBusSimplePlugin_fetchPc_inc, 2'h0 }; + assign _zz_IBusSimplePlugin_fetchPc_pc_1 = { IBusSimplePlugin_fetchPc_inc, 2'h0 }; + assign _zz_IBusSimplePlugin_iBusRsp_output_valid = 1'h1; + assign _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready = 1'h1; + assign _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready = IBusSimplePlugin_fetchPc_output_ready; + assign _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2; + assign _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload[1:0] = 2'h0; + assign _zz_IBusSimplePlugin_iBusRsp_stages_2_input_ready = 1'h1; + assign _zz_IBusSimplePlugin_injector_decodeInput_payload_pc[1:0] = 2'h0; + assign _zz_IBusSimplePlugin_jump_pcLoad_payload = { BranchPlugin_jumpInterface_valid, CsrPlugin_jumpInterface_valid }; + assign _zz_IBusSimplePlugin_pending_next_1 = { 2'h0, IBusSimplePlugin_cmd_fire }; + assign _zz_IBusSimplePlugin_pending_next_2 = IBusSimplePlugin_cmd_fire; + assign _zz_IBusSimplePlugin_pending_next_3 = { 2'h0, IBusSimplePlugin_pending_dec }; + assign _zz_IBusSimplePlugin_pending_next_4 = IBusSimplePlugin_pending_dec; + assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter = { 2'h0, _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1 }; + assign _zz__zz_decode_BRANCH_CTRL_2 = { 27'h0000000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4:2], 2'h0 }; + assign _zz__zz_decode_BRANCH_CTRL_2_1 = 32'd4; + assign _zz__zz_decode_BRANCH_CTRL_2_10 = 32'd36; + assign _zz__zz_decode_BRANCH_CTRL_2_11 = { 18'h00000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13:12], 5'h00, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], 1'h0, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4], 1'h0, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2], 2'h0 }; + assign _zz__zz_decode_BRANCH_CTRL_2_12 = 32'd4112; + assign _zz__zz_decode_BRANCH_CTRL_2_13 = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12]; + assign _zz__zz_decode_BRANCH_CTRL_2_14 = { 19'h00000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], 12'h000 }; + assign _zz__zz_decode_BRANCH_CTRL_2_15 = 32'd4096; + assign { _zz__zz_decode_BRANCH_CTRL_2_16[18:12], _zz__zz_decode_BRANCH_CTRL_2_16[10], _zz__zz_decode_BRANCH_CTRL_2_16[8:0] } = { _zz__zz_decode_BRANCH_CTRL_2_17, decode_SRC_LESS_UNSIGNED, _zz__zz_decode_BRANCH_CTRL_2_21, _zz__zz_decode_BRANCH_CTRL_2_26, _zz__zz_decode_BRANCH_CTRL_2_28, decode_IS_CSR, _zz__zz_decode_BRANCH_CTRL_2_32, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5], _zz__zz_decode_BRANCH_CTRL_2_46, _zz__zz_decode_BRANCH_CTRL_2_47, decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63, _zz__zz_decode_BRANCH_CTRL_2_65, _zz__zz_decode_BRANCH_CTRL_2_71, decode_SRC_USE_SUB_LESS, _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 }; + assign _zz__zz_decode_BRANCH_CTRL_2_19 = 32'd8208; + assign _zz__zz_decode_BRANCH_CTRL_2_2 = { 25'h0000000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], 1'h0, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4:3], 3'h0 }; + assign _zz__zz_decode_BRANCH_CTRL_2_20 = 32'd20480; + assign _zz__zz_decode_BRANCH_CTRL_2_22 = { 17'h00000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14:13], 10'h000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2], 2'h0 }; + assign _zz__zz_decode_BRANCH_CTRL_2_23 = 32'd24576; + assign _zz__zz_decode_BRANCH_CTRL_2_24 = { 17'h00000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14], 1'h0, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], 9'h000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2], 2'h0 }; + assign _zz__zz_decode_BRANCH_CTRL_2_25 = 32'd16384; + assign _zz__zz_decode_BRANCH_CTRL_2_27 = { _zz__zz_decode_BRANCH_CTRL_2_28, decode_IS_CSR, _zz__zz_decode_BRANCH_CTRL_2_32, _zz__zz_decode_BRANCH_CTRL_2_16[11], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5], _zz__zz_decode_BRANCH_CTRL_2_16[9], _zz__zz_decode_BRANCH_CTRL_2_46, _zz__zz_decode_BRANCH_CTRL_2_47, decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63, _zz__zz_decode_BRANCH_CTRL_2_65, _zz__zz_decode_BRANCH_CTRL_2_71, decode_SRC_USE_SUB_LESS, _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 }; + assign _zz__zz_decode_BRANCH_CTRL_2_3 = 32'd64; + assign _zz__zz_decode_BRANCH_CTRL_2_30 = 32'd4176; + assign _zz__zz_decode_BRANCH_CTRL_2_31 = 32'd8272; + assign _zz__zz_decode_BRANCH_CTRL_2_33 = { 26'h0000000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5:4], 1'h0, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2], 2'h0 }; + assign _zz__zz_decode_BRANCH_CTRL_2_34 = 32'd32; + assign _zz__zz_decode_BRANCH_CTRL_2_35 = { 25'h0000000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6:5], 2'h0, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2], 2'h0 }; + assign _zz__zz_decode_BRANCH_CTRL_2_36 = 32'd32; + assign _zz__zz_decode_BRANCH_CTRL_2_37 = _zz__zz_decode_BRANCH_CTRL_2_16[11]; + assign _zz__zz_decode_BRANCH_CTRL_2_41 = 32'd1060928; + assign _zz__zz_decode_BRANCH_CTRL_2_42 = { _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5], _zz__zz_decode_BRANCH_CTRL_2_16[9], _zz__zz_decode_BRANCH_CTRL_2_46, _zz__zz_decode_BRANCH_CTRL_2_47, decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63, _zz__zz_decode_BRANCH_CTRL_2_65, _zz__zz_decode_BRANCH_CTRL_2_71, decode_SRC_USE_SUB_LESS, _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 }; + assign _zz__zz_decode_BRANCH_CTRL_2_43 = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5]; + assign _zz__zz_decode_BRANCH_CTRL_2_44 = _zz__zz_decode_BRANCH_CTRL_2_16[9]; + assign _zz__zz_decode_BRANCH_CTRL_2_45 = 32'd16; + assign _zz__zz_decode_BRANCH_CTRL_2_49[3:2] = { _zz__zz_decode_BRANCH_CTRL_2_52, _zz__zz_decode_BRANCH_CTRL_2_46 }; + assign _zz__zz_decode_BRANCH_CTRL_2_50 = { 19'h00000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], 7'h00, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4], 4'h0 }; + assign _zz__zz_decode_BRANCH_CTRL_2_51 = 32'd4112; + assign _zz__zz_decode_BRANCH_CTRL_2_53 = _zz__zz_decode_BRANCH_CTRL_2_46; + assign _zz__zz_decode_BRANCH_CTRL_2_54 = _zz__zz_decode_BRANCH_CTRL_2_49[1:0]; + assign _zz__zz_decode_BRANCH_CTRL_2_55 = { 28'h0000000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3:2], 2'h0 }; + assign _zz__zz_decode_BRANCH_CTRL_2_56 = 32'd4; + assign _zz__zz_decode_BRANCH_CTRL_2_57 = { 26'h0000000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5], 1'h0, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3], 3'h0 }; + assign _zz__zz_decode_BRANCH_CTRL_2_58 = 32'd0; + assign _zz__zz_decode_BRANCH_CTRL_2_59 = { decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63, _zz__zz_decode_BRANCH_CTRL_2_65, _zz__zz_decode_BRANCH_CTRL_2_71, decode_SRC_USE_SUB_LESS, _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 }; + assign _zz__zz_decode_BRANCH_CTRL_2_6 = 32'd1073754196; + assign _zz__zz_decode_BRANCH_CTRL_2_60[1] = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2]; + assign _zz__zz_decode_BRANCH_CTRL_2_61 = { 25'h0000000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6:4], 4'h0 }; + assign _zz__zz_decode_BRANCH_CTRL_2_62 = 32'd32; + assign _zz__zz_decode_BRANCH_CTRL_2_67 = 32'd68; + assign _zz__zz_decode_BRANCH_CTRL_2_68 = { _zz__zz_decode_BRANCH_CTRL_2_39, _zz__zz_decode_BRANCH_CTRL_2_26, _zz__zz_decode_BRANCH_CTRL_2_69 }; + assign _zz__zz_decode_BRANCH_CTRL_2_7 = 32'd28756; + assign _zz__zz_decode_BRANCH_CTRL_2_70 = { _zz__zz_decode_BRANCH_CTRL_2_71, decode_SRC_USE_SUB_LESS, _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 }; + assign _zz__zz_decode_BRANCH_CTRL_2_72 = 32'd88; + assign _zz__zz_decode_BRANCH_CTRL_2_73 = decode_SRC_USE_SUB_LESS; + assign _zz__zz_decode_BRANCH_CTRL_2_8 = decode_SRC_ADD_ZERO; + assign _zz__zz_decode_BRANCH_CTRL_2_82 = _zz__zz_decode_BRANCH_CTRL_2_79; + assign _zz__zz_decode_BRANCH_CTRL_2_9 = { 25'h0000000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6:5], 2'h0, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2], 2'h0 }; + assign _zz__zz_decode_SRC1_1 = 3'h4; + assign _zz__zz_decode_SRC1_1_1 = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19:15]; + assign _zz__zz_decode_SRC2_4 = { _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:25], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11:7] }; + assign _zz__zz_execute_BranchPlugin_branch_src2 = { decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[19:12], decode_to_execute_INSTRUCTION[20], decode_to_execute_INSTRUCTION[30:21] }; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = { decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[7], decode_to_execute_INSTRUCTION[30:25], decode_to_execute_INSTRUCTION[11:8] }; + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1[30:0] = execute_LightShifterPlugin_shiftInput[31:1]; + assign _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1_1 = { _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1[31], execute_LightShifterPlugin_shiftInput }; + assign _zz_dBus_cmd_payload_data = { dBus_cmd_payload_data[31:8], decode_to_execute_RS2[7:0] }; + assign _zz_dBus_cmd_valid = 1'h0; + assign _zz_decode_ALU_BITWISE_CTRL = { _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz__zz_decode_BRANCH_CTRL_2_17 }; + assign _zz_decode_ALU_BITWISE_CTRL_1 = { _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz__zz_decode_BRANCH_CTRL_2_17 }; + assign _zz_decode_ALU_BITWISE_CTRL_2 = { _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz__zz_decode_BRANCH_CTRL_2_17 }; + assign _zz_decode_ALU_CTRL = { _zz__zz_decode_BRANCH_CTRL_2_21, _zz__zz_decode_BRANCH_CTRL_2_26 }; + assign _zz_decode_ALU_CTRL_1 = { _zz__zz_decode_BRANCH_CTRL_2_21, _zz__zz_decode_BRANCH_CTRL_2_26 }; + assign _zz_decode_ALU_CTRL_2 = { _zz__zz_decode_BRANCH_CTRL_2_21, _zz__zz_decode_BRANCH_CTRL_2_26 }; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign { _zz_decode_BRANCH_CTRL_2[25:22], _zz_decode_BRANCH_CTRL_2[20:0] } = { decode_IS_EBREAK, _zz_decode_BRANCH_CTRL, _zz__zz_decode_BRANCH_CTRL_2_4, decode_SRC_ADD_ZERO, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz__zz_decode_BRANCH_CTRL_2_17, decode_SRC_LESS_UNSIGNED, _zz__zz_decode_BRANCH_CTRL_2_21, _zz__zz_decode_BRANCH_CTRL_2_26, _zz__zz_decode_BRANCH_CTRL_2_28, decode_IS_CSR, _zz__zz_decode_BRANCH_CTRL_2_32, _zz__zz_decode_BRANCH_CTRL_2_16[11], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5], _zz__zz_decode_BRANCH_CTRL_2_16[9], _zz__zz_decode_BRANCH_CTRL_2_46, _zz__zz_decode_BRANCH_CTRL_2_47, decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63, _zz__zz_decode_BRANCH_CTRL_2_65, _zz__zz_decode_BRANCH_CTRL_2_71, decode_SRC_USE_SUB_LESS, _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 }; + assign _zz_decode_BRANCH_CTRL_3 = _zz__zz_decode_BRANCH_CTRL_2_79; + assign _zz_decode_BRANCH_CTRL_4 = _zz__zz_decode_BRANCH_CTRL_2_26; + assign _zz_decode_BRANCH_CTRL_5 = _zz__zz_decode_BRANCH_CTRL_2_39; + assign _zz_decode_BRANCH_CTRL_6 = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2]; + assign _zz_decode_BRANCH_CTRL_7 = _zz__zz_decode_BRANCH_CTRL_2_46; + assign _zz_decode_BRANCH_CTRL_8 = _zz__zz_decode_BRANCH_CTRL_2_48; + assign _zz_decode_BRANCH_CTRL_9 = _zz_decode_BRANCH_CTRL; + assign _zz_decode_ENV_CTRL = _zz__zz_decode_BRANCH_CTRL_2_28; + assign _zz_decode_ENV_CTRL_1 = _zz__zz_decode_BRANCH_CTRL_2_28; + assign _zz_decode_ENV_CTRL_2 = _zz__zz_decode_BRANCH_CTRL_2_28; + assign _zz_decode_RegFilePlugin_rs1Data = 1'h1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'h1; + assign _zz_decode_SHIFT_CTRL = { _zz__zz_decode_BRANCH_CTRL_2_4, _zz_decode_BRANCH_CTRL_2[21] }; + assign _zz_decode_SHIFT_CTRL_1 = { _zz__zz_decode_BRANCH_CTRL_2_4, _zz_decode_BRANCH_CTRL_2[21] }; + assign _zz_decode_SHIFT_CTRL_2 = { _zz__zz_decode_BRANCH_CTRL_2_4, _zz_decode_BRANCH_CTRL_2[21] }; + assign _zz_decode_SRC1 = _zz_RegFilePlugin_regFile_port0; + assign _zz_decode_SRC1_CTRL = { _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 }; + assign _zz_decode_SRC1_CTRL_1 = { _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 }; + assign _zz_decode_SRC1_CTRL_2 = { _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 }; + assign _zz_decode_SRC2 = { _zz_IBusSimplePlugin_injector_decodeInput_payload_pc[31:2], 2'h0 }; + assign _zz_decode_SRC2_1 = _zz_RegFilePlugin_regFile_port1; + assign _zz_decode_SRC2_2 = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31]; + assign _zz_decode_SRC2_3 = { _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31] }; + assign _zz_decode_SRC2_4 = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31]; + assign _zz_decode_SRC2_5 = { _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31] }; + assign _zz_decode_SRC2_CTRL = { decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63 }; + assign _zz_decode_SRC2_CTRL_1 = { decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63 }; + assign _zz_decode_SRC2_CTRL_2 = { decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63 }; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = { _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz__zz_decode_BRANCH_CTRL_2_17 }; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = { _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz__zz_decode_BRANCH_CTRL_2_17 }; + assign _zz_decode_to_execute_ALU_CTRL = { _zz__zz_decode_BRANCH_CTRL_2_21, _zz__zz_decode_BRANCH_CTRL_2_26 }; + assign _zz_decode_to_execute_ALU_CTRL_1 = { _zz__zz_decode_BRANCH_CTRL_2_21, _zz__zz_decode_BRANCH_CTRL_2_26 }; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_BRANCH_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz__zz_decode_BRANCH_CTRL_2_28; + assign _zz_decode_to_execute_ENV_CTRL_1 = _zz__zz_decode_BRANCH_CTRL_2_28; + assign _zz_decode_to_execute_SHIFT_CTRL = { _zz__zz_decode_BRANCH_CTRL_2_4, _zz_decode_BRANCH_CTRL_2[21] }; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = { _zz__zz_decode_BRANCH_CTRL_2_4, _zz_decode_BRANCH_CTRL_2[21] }; + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign _zz_execute_BranchPlugin_branch_src2 = decode_to_execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_1 = { decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31] }; + assign _zz_execute_BranchPlugin_branch_src2_2 = decode_to_execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_3 = { decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31] }; + assign _zz_execute_BranchPlugin_branch_src2_4 = decode_to_execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_5 = { decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31] }; + assign _zz_execute_BranchPlugin_branch_src2_6 = { decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], execute_BranchPlugin_branch_src2[19:11], decode_to_execute_INSTRUCTION[30:25], execute_BranchPlugin_branch_src2[4:0] }; + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign _zz_execute_SrcPlugin_addSub_2 = decode_to_execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_5 = 32'd1; + assign _zz_execute_SrcPlugin_addSub_6 = 32'd0; + assign _zz_execute_to_memory_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = decode_to_execute_ENV_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = memory_to_writeBack_INSTRUCTION[29:0]; + assign _zz_lastStageRegFileWrite_valid = memory_to_writeBack_REGFILE_WRITE_VALID; + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = execute_to_memory_ENV_CTRL; + assign _zz_writeBack_DBusSimplePlugin_rspFormated_1[31:8] = { _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated }; + assign { _zz_writeBack_DBusSimplePlugin_rspFormated_3[31:16], _zz_writeBack_DBusSimplePlugin_rspFormated_3[7:0] } = { _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_1[7:0] }; + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign dBus_cmd_payload_address = execute_SrcPlugin_addSub; + assign dBus_cmd_payload_data[7:0] = decode_to_execute_RS2[7:0]; + assign dBus_cmd_payload_size = decode_to_execute_INSTRUCTION[13:12]; + assign dBus_cmd_payload_wr = decode_to_execute_MEMORY_STORE; + assign debug_bus_rsp_data[31:5] = DebugPlugin_busReadDataReg[31:5]; + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign decode_ALU_BITWISE_CTRL = { _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz__zz_decode_BRANCH_CTRL_2_17 }; + assign decode_ALU_CTRL = { _zz__zz_decode_BRANCH_CTRL_2_21, _zz__zz_decode_BRANCH_CTRL_2_26 }; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz__zz_decode_BRANCH_CTRL_2_46; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz__zz_decode_BRANCH_CTRL_2_16[9]; + assign decode_ENV_CTRL = _zz__zz_decode_BRANCH_CTRL_2_28; + assign decode_INSTRUCTION = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + assign decode_INSTRUCTION_ANTICIPATED[31:25] = IBusSimplePlugin_iBusRsp_output_payload_rsp_inst[31:25]; + assign decode_MEMORY_ENABLE = _zz__zz_decode_BRANCH_CTRL_2_71; + assign decode_MEMORY_STORE = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5]; + assign decode_PC = { _zz_IBusSimplePlugin_injector_decodeInput_payload_pc[31:2], 2'h0 }; + assign decode_RS1 = _zz_RegFilePlugin_regFile_port0; + assign decode_RS1_USE = _zz__zz_decode_BRANCH_CTRL_2_65; + assign decode_RS2 = _zz_RegFilePlugin_regFile_port1; + assign decode_RS2_USE = _zz__zz_decode_BRANCH_CTRL_2_32; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19:15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24:20]; + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + assign decode_SHIFT_CTRL = { _zz__zz_decode_BRANCH_CTRL_2_4, _zz_decode_BRANCH_CTRL_2[21] }; + assign decode_SRC1 = _zz_decode_SRC1_1; + assign decode_SRC1_CTRL = { _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 }; + assign decode_SRC2 = _zz_decode_SRC2_6; + assign decode_SRC2_CTRL[0] = _zz__zz_decode_BRANCH_CTRL_2_63; + assign decode_arbitration_flushIt = 1'h0; + assign decode_arbitration_flushNext = 1'h0; + assign decode_to_execute_PC[1:0] = 2'h0; + assign execute_ALIGNEMENT_FAULT = 1'h0; + assign execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign execute_BRANCH_CALC = { execute_BranchPlugin_branchAdder[31:1], 1'h0 }; + assign execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign execute_BRANCH_DO = _zz_execute_BRANCH_DO_1; + assign { execute_BranchPlugin_branch_src2[31:20], execute_BranchPlugin_branch_src2[10:5] } = { decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31:25] }; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_CsrPlugin_csrAddress = decode_to_execute_INSTRUCTION[31:20]; + assign { execute_CsrPlugin_readToWriteData[31:12], execute_CsrPlugin_readToWriteData[10:8], execute_CsrPlugin_readToWriteData[6:4], execute_CsrPlugin_readToWriteData[2:0] } = { _zz_CsrPlugin_csrMapping_readDataInit_3[31], 18'h00000, _zz_CsrPlugin_csrMapping_readDataInit[12], 6'h00, _zz_CsrPlugin_csrMapping_readDataInit_3[2:1], _zz_CsrPlugin_csrMapping_readDataInit_3[1] }; + assign execute_DBusSimplePlugin_skipCmd = 1'h0; + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign execute_MEMORY_ADDRESS_LOW = execute_SrcPlugin_addSub[1:0]; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; + assign execute_PC = { decode_to_execute_PC[31:2], 2'h0 }; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign execute_SRC1 = decode_to_execute_SRC1; + assign execute_SRC2 = decode_to_execute_SRC2; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign execute_SrcPlugin_less = execute_SRC_LESS; + assign execute_arbitration_flushNext = execute_arbitration_flushIt; + assign execute_to_memory_BRANCH_CALC[0] = 1'h0; + assign iBus_cmd_payload_pc = { IBusSimplePlugin_fetchPc_pcReg[31:2], 2'h0 }; + assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; + assign iBus_rsp_toStream_payload_error = iBus_rsp_payload_error; + assign iBus_rsp_toStream_payload_inst = iBus_rsp_payload_inst; + assign iBus_rsp_toStream_ready = IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; + assign iBus_rsp_toStream_valid = iBus_rsp_valid; + assign lastStageInstruction[29:0] = memory_to_writeBack_INSTRUCTION[29:0]; + assign lastStageIsFiring = writeBack_arbitration_isValid; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign memory_BRANCH_CALC = { execute_to_memory_BRANCH_CALC[31:1], 1'h0 }; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign memory_INSTRUCTION[29:0] = execute_to_memory_INSTRUCTION; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign memory_MEMORY_READ_DATA = dBus_rsp_data; + assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_arbitration_flushIt = 1'h0; + assign memory_arbitration_haltByOther = 1'h0; + assign memory_arbitration_haltItself = memory_arbitration_isStuck; + assign memory_arbitration_isFlushed = CsrPlugin_jumpInterface_valid; + assign memory_arbitration_isStuckByOthers = 1'h0; + assign memory_to_writeBack_INSTRUCTION[31:30] = lastStageInstruction[31:30]; + assign switch_CsrPlugin_l1068 = memory_to_writeBack_INSTRUCTION[29:28]; + assign switch_DebugPlugin_l267 = debug_bus_cmd_payload_address[7:2]; + assign switch_Misc_l211 = memory_to_writeBack_INSTRUCTION[13:12]; + assign switch_Misc_l211_1 = decode_to_execute_INSTRUCTION[13]; + assign switch_Misc_l211_2 = decode_to_execute_INSTRUCTION[14:12]; + assign when_CsrPlugin_l1019 = CsrPlugin_interruptJump; + assign when_CsrPlugin_l1180 = when_CsrPlugin_l1176; + assign when_CsrPlugin_l946 = CsrPlugin_mstatus_MIE; + assign when_CsrPlugin_l952 = _zz_when_CsrPlugin_l952; + assign when_CsrPlugin_l952_1 = _zz_when_CsrPlugin_l952_1; + assign when_CsrPlugin_l952_2 = _zz_when_CsrPlugin_l952_2; + assign when_CsrPlugin_l980_2 = 1'h1; + assign when_DebugPlugin_l271 = debug_bus_cmd_payload_data[16]; + assign when_DebugPlugin_l271_1 = debug_bus_cmd_payload_data[24]; + assign when_DebugPlugin_l272 = debug_bus_cmd_payload_data[17]; + assign when_DebugPlugin_l272_1 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l273 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l274 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l275 = debug_bus_cmd_payload_data[18]; + assign when_DebugPlugin_l275_1 = debug_bus_cmd_payload_data[26]; + assign when_Fetcher_l329 = IBusSimplePlugin_fetchPc_output_ready; + assign when_Fetcher_l329_1 = IBusSimplePlugin_iBusRsp_stages_1_output_ready; + assign when_Fetcher_l329_5 = 1'h1; + assign when_HazardSimplePlugin_l57 = HazardSimplePlugin_writeBackWrites_valid; + assign when_HazardSimplePlugin_l58 = 1'h1; + assign when_HazardSimplePlugin_l58_1 = 1'h1; + assign when_HazardSimplePlugin_l58_2 = 1'h1; + assign when_Pipeline_l124_14 = 1'h1; + assign when_Pipeline_l124_17 = 1'h1; + assign when_Pipeline_l124_2 = 1'h1; + assign when_Pipeline_l124_26 = 1'h1; + assign when_Pipeline_l124_39 = 1'h1; + assign when_Pipeline_l124_41 = 1'h1; + assign when_Pipeline_l124_44 = 1'h1; + assign when_Pipeline_l124_5 = 1'h1; + assign when_Pipeline_l124_8 = 1'h1; + assign when_Pipeline_l151_2 = 1'h1; + assign writeBack_DBusSimplePlugin_rspFormated[7:0] = _zz_writeBack_DBusSimplePlugin_rspFormated_1[7:0]; + assign writeBack_DBusSimplePlugin_rspShifted = { memory_to_writeBack_MEMORY_READ_DATA[31:16], _zz_writeBack_DBusSimplePlugin_rspFormated_3[15:8], _zz_writeBack_DBusSimplePlugin_rspFormated_1[7:0] }; + assign writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign writeBack_INSTRUCTION = { lastStageInstruction[31:30], memory_to_writeBack_INSTRUCTION[29:0] }; + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + assign writeBack_arbitration_flushIt = 1'h0; + assign writeBack_arbitration_flushNext = CsrPlugin_jumpInterface_valid; + assign writeBack_arbitration_haltByOther = 1'h0; + assign writeBack_arbitration_haltItself = 1'h0; + assign writeBack_arbitration_isFiring = writeBack_arbitration_isValid; + assign writeBack_arbitration_isFlushed = 1'h0; + assign writeBack_arbitration_isMoving = 1'h1; + assign writeBack_arbitration_isStuck = 1'h0; + assign writeBack_arbitration_isStuckByOthers = 1'h0; + assign writeBack_arbitration_removeIt = 1'h0; +endmodule diff --git a/VexRiscv/fpga/gen/synth.ys b/VexRiscv/fpga/gen/synth.ys new file mode 100644 index 0000000..b0788d6 --- /dev/null +++ b/VexRiscv/fpga/gen/synth.ys @@ -0,0 +1,5 @@ +read_verilog ../Murax.v +hierarchy -check -top Murax +synth -run coarse; opt -fine +write_verilog -noexpr -noattr gen/synth.v +synth_ecp5 -top Murax -json gen/soc.json diff --git a/VexRiscv/fpga/soc.cfg b/VexRiscv/fpga/soc.cfg new file mode 100644 index 0000000..61373bf --- /dev/null +++ b/VexRiscv/fpga/soc.cfg @@ -0,0 +1,67147 @@ +.device LFE5U-25F + +.comment Part: LFE5U-25F-6CABGA381 + +.tile CIB_R19C1:CIB_LR +arc: S3_V06S0103 E3_H06W0103 + +.tile CIB_R20C1:CIB_LR +arc: S3_V06S0103 H06W0103 + +.tile CIB_R22C1:CIB_LR +arc: E3_H06E0003 S3_V06N0003 + +.tile CIB_R23C1:CIB_LR +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 E1_H01W0000 + +.tile CIB_R24C1:CIB_LR +arc: E1_H02E0101 V02N0101 + +.tile CIB_R25C10:CIB_EBR +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 V06N0203 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 S1_V02N0701 +arc: JA0 S1_V02N0701 +arc: JA1 V02N0701 +arc: JA2 V00B0000 +arc: JA3 V00T0000 +arc: JA4 V00T0100 +arc: JA5 V02S0301 +arc: JC0 H00R0100 +arc: JC1 H02W0601 +arc: JC2 H00L0000 +arc: JC3 H00L0100 +arc: JC4 S1_V02N0001 +arc: JC5 V02S0001 +arc: JCE1 V02N0201 +arc: JCLK0 G_HPBX0100 +arc: JD6 V02S0601 +arc: JD7 V02N0601 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0401 JQ6 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 JQ7 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +enum: CIB.JB5MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JLSR1MUX 0 +enum: CIB.JLSR0MUX 0 +enum: CIB.JCE0MUX 1 +enum: CIB.JD5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 +enum: CIB.JB7MUX 0 +enum: CIB.JB6MUX 0 + +.tile CIB_R25C11:CIB_EBR +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V06N0303 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 S1_V02N0401 +arc: H01W0000 JQ3 +arc: H01W0100 JQ5 +arc: JA0 H02E0501 +arc: JA1 H02E0501 +arc: JA2 V00B0000 +arc: JA3 V00B0000 +arc: JA6 H00R0000 +arc: JA7 H00R0000 +arc: JB1 V02S0101 +arc: JB3 S1_V02N0101 +arc: JB5 H02E0301 +arc: JC0 H00L0100 +arc: JC1 H00L0100 +arc: JC2 V02S0401 +arc: JC3 V02S0401 +arc: JCLK0 G_HPBX0100 +arc: JD0 S1_V02N0201 +arc: JD2 H02E0201 +arc: JD4 H02E0001 +arc: JLSR1 V00T0000 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 JQ0 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 JQ2 +arc: S3_V06S0203 JQ4 +arc: V00B0000 V02N0201 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 JQ1 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 E1_H02W0601 +arc: N1_V02N0301 W3_H06E0003 +arc: S1_V02S0301 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JLSR0MUX 0 +enum: CIB.JCE0MUX 1 +enum: CIB.JB7MUX 0 +enum: CIB.JCE1MUX 1 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 + +.tile CIB_R25C12:CIB_EBR +arc: H00L0000 V02S0201 +arc: JA0 H00L0000 +arc: JA1 H00L0000 +arc: JA4 H02E0501 +arc: JA5 H02E0501 +arc: JA6 W1_H02E0701 +arc: JA7 W1_H02E0701 +arc: JC0 S1_V02N0601 +arc: JC1 S1_V02N0601 +arc: JC4 V00T0100 +arc: JC5 V00T0100 +arc: JC6 H02E0401 +arc: JC7 H02E0401 +arc: JCE1 S1_V02N0201 +arc: JCLK0 G_HPBX0100 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: S3_V06S0103 N1_V01S0100 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 V06N0303 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JLSR1MUX 0 +enum: CIB.JLSR0MUX 0 +enum: CIB.JCE0MUX 1 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R25C13:CIB_EBR +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0203 N3_V06S0103 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: E3_H06E0103 W3_H06E0103 + +.tile CIB_R25C14:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0103 N1_V02S0101 + +.tile CIB_R25C15:CIB_EBR +arc: E1_H02E0101 V01N0101 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 N1_V02S0301 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V01N0101 +arc: E1_H02E0301 W3_H06E0003 +arc: E1_H02E0701 W3_H06E0203 +arc: W1_H02W0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 + +.tile CIB_R25C16:CIB_EBR +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 S3_V06N0203 + +.tile CIB_R25C17:CIB_EBR +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 E1_H02W0101 +arc: W1_H02W0101 E1_H02W0101 +arc: N1_V02N0301 W3_H06E0003 + +.tile CIB_R25C18:CIB_EBR +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0401 H06W0203 +arc: S3_V06S0003 H06E0003 + +.tile CIB_R25C19:CIB_EBR +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0401 N1_V01S0000 +arc: W1_H02W0101 S1_V02N0101 +arc: N1_V02N0201 W3_H06E0103 + +.tile CIB_R25C1:CIB_LR_S +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0601 E3_H06W0303 +arc: N1_V02N0101 N3_V06S0103 +arc: V01S0100 S3_V06N0303 + +.tile CIB_R25C20:CIB_EBR +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0601 H02W0601 + +.tile CIB_R25C21:CIB_EBR +arc: E1_H02E0501 V06S0303 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0501 S3_V06N0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0601 V06N0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 W3_H06E0203 +arc: W3_H06W0203 V01N0001 + +.tile CIB_R25C22:CIB_EBR +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 N3_V06S0003 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 N3_V06S0003 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N1_V02S0601 +arc: V01S0100 S3_V06N0303 + +.tile CIB_R25C23:CIB_EBR +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 V01N0001 +arc: S1_V02S0101 N1_V02S0101 + +.tile CIB_R25C24:CIB_EBR +arc: N1_V02N0101 S3_V06N0103 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0301 W1_H02E0301 + +.tile CIB_R25C2:CIB_EBR +arc: N1_V02N0201 H02E0201 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 E3_H06W0203 + +.tile CIB_R25C3:CIB_EBR +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0303 V06S0303 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V01S0100 S3_V06N0303 + +.tile CIB_R25C4:CIB_EBR +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 JQ1 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 V02S0701 +arc: H01W0000 JQ7 +arc: H01W0100 JQ3 +arc: JA0 V02S0501 +arc: JA1 V02S0501 +arc: JA2 V00B0000 +arc: JA3 V00B0000 +arc: JA6 S1_V02N0301 +arc: JA7 N1_V02S0101 +arc: JB1 V00T0000 +arc: JB3 V02N0101 +arc: JB5 H02E0301 +arc: JB7 H02W0101 +arc: JC0 E1_H02W0601 +arc: JC1 E1_H02W0601 +arc: JC2 H00R0100 +arc: JC3 H00R0100 +arc: JCLK0 G_HPBX0100 +arc: JD0 N1_V02S0201 +arc: JD2 E1_H02W0001 +arc: JD4 H00L0100 +arc: JD6 V02N0401 +arc: JLSR1 H02E0501 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 JQ4 +arc: N1_V02N0501 H06W0303 +arc: S1_V02S0001 JQ2 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0003 JQ0 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0401 JQ6 +arc: W1_H02W0501 JQ5 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JLSR0MUX 0 +enum: CIB.JCE0MUX 1 +enum: CIB.JCE1MUX 1 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 + +.tile CIB_R25C5:CIB_EBR +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 V02N0601 +arc: H00R0100 S1_V02N0501 +arc: JA0 V02N0501 +arc: JA1 H00R0000 +arc: JA4 V02N0101 +arc: JA5 V00B0000 +arc: JA6 V02N0301 +arc: JA7 S1_V02N0101 +arc: JC0 H00L0000 +arc: JC1 W1_H02E0601 +arc: JC4 W1_H02E0601 +arc: JC5 H02E0601 +arc: JC6 H02E0601 +arc: JC7 S1_V02N0001 +arc: JCE1 H00R0100 +arc: JCLK0 G_HPBX0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0003 E1_H01W0000 +arc: V00B0000 V02N0001 +arc: W1_H02W0101 E1_H02W0001 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JLSR1MUX 0 +enum: CIB.JLSR0MUX 0 +enum: CIB.JCE0MUX 1 +enum: CIB.JB1MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R25C6:CIB_EBR +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 H02W0401 +arc: H00R0100 V02S0701 +arc: H01W0000 JQ5 +arc: JA0 W1_H02E0701 +arc: JA1 W1_H02E0701 +arc: JA2 V00T0000 +arc: JA3 V00T0000 +arc: JA6 H00L0000 +arc: JA7 H00L0000 +arc: JB3 H00R0000 +arc: JB5 V02N0701 +arc: JB7 V02N0501 +arc: JC0 S1_V02N0601 +arc: JC1 S1_V02N0601 +arc: JC2 H00R0100 +arc: JC3 H00R0100 +arc: JCLK0 G_HPBX0100 +arc: JD2 V00B0100 +arc: JD4 V02N0601 +arc: JD6 V02N0401 +arc: JLSR1 H02W0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 JQ3 +arc: N1_V02N0201 JQ2 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 JQ4 +arc: S3_V06S0303 JQ6 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0601 S1_V02N0601 +arc: W3_H06W0203 JQ7 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JLSR0MUX 0 +enum: CIB.JCE0MUX 1 +enum: CIB.JCE1MUX 1 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R25C7:CIB_EBR +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 N1_V02S0301 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 V02N0601 +arc: H00R0100 N1_V02S0501 +arc: JA0 H00R0000 +arc: JA1 H00R0000 +arc: JA4 W1_H02E0501 +arc: JA5 W1_H02E0501 +arc: JA6 H00L0000 +arc: JA7 H00L0000 +arc: JB1 H00R0100 +arc: JC0 W1_H02E0601 +arc: JC1 W1_H02E0601 +arc: JC4 V00T0100 +arc: JC5 V00T0100 +arc: JC6 H02E0601 +arc: JC7 H02E0601 +arc: JCE1 S1_V02N0201 +arc: JCLK0 G_HPBX0100 +arc: JD0 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0301 S3_V06N0003 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 JQ0 +arc: W1_H02W0301 JQ1 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 S3_V06N0303 +arc: W3_H06W0003 E3_H06W0303 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JLSR1MUX 0 +enum: CIB.JLSR0MUX 0 +enum: CIB.JCE0MUX 1 +enum: CIB.JB3MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD4MUX 0 + +.tile CIB_R25C8:CIB_EBR +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0401 N1_V02S0401 +arc: H01W0000 JQ5 +arc: H01W0100 JQ4 +arc: JB5 V02N0501 +arc: JB7 W1_H02E0101 +arc: JD4 V02N0601 +arc: JD6 V00B0000 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W3_H06W0203 JQ7 +arc: W3_H06W0303 JQ6 +enum: CIB.JLSR1MUX 0 +enum: CIB.JCLK1MUX 0 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JLSR0MUX 0 +enum: CIB.JCLK0MUX 0 +enum: CIB.JCE1MUX 1 +enum: CIB.JCE0MUX 1 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JD0MUX 0 + +.tile CIB_R25C9:CIB_EBR +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 W1_H02E0301 +arc: E3_H06E0003 N1_V01S0000 +arc: E3_H06E0203 N1_V01S0000 +arc: E3_H06E0303 V06S0303 +arc: H00R0100 N1_V02S0701 +arc: H01W0000 JQ2 +arc: H01W0100 JQ0 +arc: JA0 S1_V02N0501 +arc: JA1 S1_V02N0501 +arc: JA2 V00T0000 +arc: JA3 V00T0000 +arc: JA6 S1_V02N0101 +arc: JA7 S1_V02N0101 +arc: JB1 H00R0100 +arc: JB3 V02S0301 +arc: JC0 H02E0401 +arc: JC1 H02E0401 +arc: JC2 V02S0401 +arc: JC3 V02S0401 +arc: JCLK0 G_HPBX0100 +arc: JD0 H02W0201 +arc: JD2 V00B0100 +arc: JLSR1 E1_H02W0301 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0101 JQ3 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 V02N0301 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: E1_H02E0601 W3_H06E0303 +arc: W3_H06W0103 JQ1 +arc: W3_H06W0303 S3_V06N0303 +enum: CIB.JCE3MUX 1 +enum: CIB.JCE2MUX 1 +enum: CIB.JB6MUX 0 +enum: CIB.JD7MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JD5MUX 0 +enum: CIB.JB2MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JB0MUX 0 +enum: CIB.JD1MUX 0 +enum: CIB.JLSR0MUX 0 +enum: CIB.JCE0MUX 1 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD6MUX 0 +enum: CIB.JCE1MUX 1 +enum: CIB.JC7MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JC4MUX 0 + +.tile CIB_R26C1:CIB_LR +arc: E1_H02E0501 N1_V01S0100 +arc: S3_V06S0103 N3_V06S0103 + +.tile CIB_R27C1:CIB_LR +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 S1_V02N0501 + +.tile CIB_R28C1:CIB_LR +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0303 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 + +.tile CIB_R29C1:CIB_LR +arc: JD7 S1_V02N0601 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0501 S1_V02N0501 + +.tile CIB_R30C1:CIB_LR +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0501 V02N0501 + +.tile CIB_R31C1:CIB_LR +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0303 E3_H06W0303 + +.tile CIB_R32C1:CIB_LR +arc: S3_V06S0203 N3_V06S0103 + +.tile CIB_R34C1:CIB_LR +arc: E1_H02E0001 S1_V02N0001 +arc: N3_V06N0303 S3_V06N0303 + +.tile CIB_R35C1:CIB_LR +arc: N3_V06N0103 E3_H06W0103 + +.tile CIB_R36C1:CIB_LR +arc: E1_H02E0001 E3_H06W0003 +arc: N1_V02N0001 E3_H06W0003 + +.tile CIB_R37C10:CIB_EBR +arc: E3_H06E0003 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 E1_H01W0100 +arc: W1_H02W0001 S3_V06N0003 +arc: W3_H06W0003 S3_V06N0003 + +.tile CIB_R37C11:CIB_EBR +arc: E1_H02E0701 N3_V06S0203 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0501 S1_V02N0501 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0501 W3_H06E0303 +arc: S1_V02S0601 W3_H06E0303 + +.tile CIB_R37C12:CIB_EBR +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H06E0103 +arc: V01S0000 N3_V06S0103 + +.tile CIB_R37C13:CIB_EBR +arc: E1_H02E0301 N3_V06S0003 +arc: E3_H06E0003 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 W1_H02E0701 +arc: E3_H06E0303 W3_H06E0203 + +.tile CIB_R37C14:CIB_EBR +arc: E1_H02E0101 S1_V02N0101 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0003 N1_V01S0000 + +.tile CIB_R37C15:CIB_EBR +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S3_V06S0103 N3_V06S0003 +arc: N1_V02N0101 W3_H06E0103 + +.tile CIB_R37C16:CIB_EBR +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 V06S0103 +arc: E3_H06E0303 N1_V01S0100 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 S1_V02N0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: N1_V02N0301 W3_H06E0003 + +.tile CIB_R37C17:CIB_EBR +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0701 N3_V06S0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: W3_H06W0103 V06S0103 + +.tile CIB_R37C18:CIB_EBR +arc: E1_H02E0701 N3_V06S0203 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N1_V01S0100 + +.tile CIB_R37C19:CIB_EBR +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N3_V06S0303 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 N3_V06S0203 +arc: E1_H02E0501 W3_H06E0303 +arc: N1_V02N0301 W3_H06E0003 +arc: S1_V02S0301 W3_H06E0003 + +.tile CIB_R37C1:CIB_LR_S +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0701 V01N0101 + +.tile CIB_R37C20:CIB_EBR +arc: E1_H02E0401 N3_V06S0203 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0301 H02W0301 + +.tile CIB_R37C21:CIB_EBR +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 N3_V06S0003 +arc: W1_H02W0301 V06S0003 + +.tile CIB_R37C22:CIB_EBR +arc: E1_H02E0401 V02N0401 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N3_V06S0203 +arc: V01S0100 N3_V06S0303 + +.tile CIB_R37C23:CIB_EBR +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0303 S1_V02N0601 + +.tile CIB_R37C24:CIB_EBR +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 + +.tile CIB_R37C2:CIB_EBR +arc: E1_H02E0001 V06S0003 +arc: N1_V02N0301 H02W0301 + +.tile CIB_R37C3:CIB_EBR +arc: N1_V02N0201 N1_V01S0000 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 E1_H02W0201 +arc: W1_H02W0301 N3_V06S0003 + +.tile CIB_R37C4:CIB_EBR +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 V01N0001 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0201 E1_H02W0201 + +.tile CIB_R37C5:CIB_EBR +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: W1_H02W0201 V06S0103 + +.tile CIB_R37C6:CIB_EBR +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: W1_H02W0201 V06S0103 + +.tile CIB_R37C7:CIB_EBR +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0203 N3_V06S0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 H02W0701 + +.tile CIB_R37C8:CIB_EBR +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 H06E0303 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 N3_V06S0203 + +.tile CIB_R37C9:CIB_EBR +arc: E3_H06E0103 N3_V06S0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H02W0501 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0303 N3_V06S0203 + +.tile CIB_R38C1:CIB_LR +arc: JA0 V02S0701 +arc: N1_V01N0101 N3_V06S0203 +enum: CIB.JB0MUX 0 + +.tile CIB_R39C1:CIB_LR +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0701 E1_H01W0100 +arc: S1_V02S0501 E3_H06W0303 + +.tile CIB_R40C1:CIB_LR +arc: N3_V06N0303 JF5 + +.tile CIB_R41C1:CIB_LR +arc: E1_H02E0501 E1_H01W0100 +arc: JA0 N1_V02S0501 +enum: CIB.JB0MUX 0 + +.tile CIB_R43C1:CIB_LR +arc: E1_H02E0401 V01N0001 +arc: N3_V06N0303 S3_V06N0303 + +.tile CIB_R44C1:CIB_LR +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V01N0001 JF5 + +.tile CIB_R45C1:CIB_LR +arc: E1_H02E0701 S1_V02N0701 + +.tile CIB_R47C1:CIB_LR +arc: N1_V02N0701 S1_V02N0701 + +.tile CIB_R49C13:CIB +arc: E1_H01E0101 JQ0 + +.tile CIB_R49C14:CIB +arc: E3_H06E0303 H01E0101 + +.tile CIB_R49C18:CIB +arc: E3_H06E0003 JQ0 +arc: N3_V06N0003 JQ0 + +.tile CIB_R49C1:CIB_LR_S +arc: N1_V02N0701 JQ5 +arc: N3_V06N0303 JF5 + +.tile CIB_R49C20:CIB +arc: E3_H06E0303 W3_H06E0303 + +.tile CIB_R49C24:CIB +arc: N3_V06N0003 W3_H06E0003 + +.tile CIB_R49C25:CIB +arc: JD7 E1_H01W0100 + +.tile CIB_R49C26:CIB +arc: H01W0100 W3_H06E0303 + +.tile CIB_R49C3:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R49C42:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C43:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C44:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C45:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C46:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C47:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C48:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C49:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C50:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C51:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C52:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C53:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R49C69:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R49C6:CIB_EFB0 +enum: CIB.JB3MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C7:CIB_EFB1 +enum: CIB.JA3MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD5MUX 0 + +.tile MIB_R13C21:DSP_SPINE_UL0 +arc: G_VPTX0000 G_HPRX0000 +arc: G_VPTX0100 G_HPRX0100 + +.tile MIB_R13C31:CMUX_UL_0 +arc: G_DCS0CLK0 G_VPFN0000 +arc: G_ULPCLK0 G_VPFN0000 +arc: G_ULPCLK1 G_HPFE0000 + +.tile MIB_R13C32:CMUX_UR_0 +arc: G_DCS0CLK1 G_VPFN0000 +arc: G_URPCLK0 G_VPFN0000 +arc: G_URPCLK1 G_HPFE0000 + +.tile MIB_R13C3:DSP_SPINE_UL1 +arc: G_VPTX0000 G_HPRX0000 +arc: G_VPTX0100 G_HPRX0100 +unknown: F2B0 +unknown: F3B0 +unknown: F5B0 +unknown: F11B0 +unknown: F13B0 + +.tile MIB_R25C3:LMID_0 +arc: G_LDCC0CLKI G_JLLQPCLKCIB0 + +.tile MIB_R37C21:EBR_SPINE_LL0 +arc: G_VPTX0000 G_HPRX0000 +arc: G_VPTX0100 G_HPRX0100 + +.tile MIB_R37C31:CMUX_LL_0 +arc: G_DCS1CLK0 G_VPFN0000 +arc: G_LLPCLK0 G_VPFN0000 +arc: G_LLPCLK1 G_HPFE0000 + +.tile MIB_R37C32:CMUX_LR_0 +arc: G_DCS1CLK1 G_VPFN0000 +arc: G_LRPCLK0 G_VPFN0000 +arc: G_LRPCLK1 G_HPFE0000 + +.tile MIB_R37C3:EBR_SPINE_LL3 +arc: G_VPTX0100 G_HPRX0100 + +.tile MIB_R38C0:PICL0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R39C0:PICL1 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON + +.tile MIB_R40C0:PICL2 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R41C0:PICL0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R42C0:PICL1_DQS0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R44C0:PICL0_DQS2 +arc: JDIA JPADDIA_PIO +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R45C0:PICL1_DQS3 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R48C0:PICL1 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON + +.tile MIB_R49C0:MIB_CIB_LR +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R50C13:PICB0 +arc: JDIA JPADDIA_PIO +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R50C18:SPICB0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R50C1:BANKREF6 +enum: BANK.VCCIO 3V3 + +.tile MIB_R50C31:BMID_0V +arc: G_BDCC0CLKI G_JBLQPCLKCIB0 + +.tile MIB_R50C4:EFB0_PICB0 +unknown: F54B1 +unknown: F56B1 +unknown: F82B1 +unknown: F94B1 + +.tile R15C13:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 S1_V02N0601 +arc: V00B0000 V02N0001 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CE2 S1_V02N0601 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q2 +arc: M0 V00B0000 +arc: M2 N1_V01N0001 +arc: M4 E1_H01E0101 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R15C14:PLC2 +arc: H00R0000 H02E0601 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0001 Q2 +arc: M0 H01E0001 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R15C15:PLC2 +arc: H00R0000 W1_H02E0601 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0100 +arc: M0 H01E0001 +arc: MUXCLK0 CLK0 +arc: S1_V02S0001 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R16C10:PLC2 +arc: E1_H02E0601 E1_H01W0000 +arc: H00R0100 H02W0701 +arc: W1_H02W0101 V02N0101 +arc: CE1 H00R0100 +arc: CE2 V02N0601 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0201 Q2 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: V00B0000 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R16C11:PLC2 +arc: H00R0000 E1_H02W0601 +arc: V00T0000 H02E0201 +arc: W1_H02W0701 E1_H02W0601 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0001 Q0 +arc: H01W0000 Q2 +arc: M0 H02E0601 +arc: M2 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: V00B0000 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R16C12:PLC2 +arc: S1_V02S0501 V01N0101 +arc: V00T0000 H02E0001 +arc: CE2 V02N0601 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0601 Q4 +arc: M4 V00T0000 +arc: MUXCLK2 CLK0 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R16C13:PLC2 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 V02N0601 +arc: W1_H02W0601 V02N0601 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0100 +arc: M0 H02E0601 +arc: MUXCLK0 CLK0 +arc: N1_V02N0001 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R16C14:PLC2 +arc: E1_H02E0601 E1_H01W0000 + +.tile R16C15:PLC2 +arc: H00R0000 W1_H02E0601 +arc: V00B0000 V02S0001 +arc: CE0 H00R0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: H01W0000 Q6 +arc: M0 H02E0601 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0001 Q0 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R16C9:PLC2 +arc: V00B0000 V02N0201 +arc: CE3 H02W0101 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0401 Q6 +arc: M6 V00B0000 +arc: MUXCLK3 CLK0 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R17C10:PLC2 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: W1_H02W0101 S1_V02N0101 + +.tile R17C11:PLC2 +arc: E1_H02E0401 E1_H01W0000 + +.tile R17C12:PLC2 +arc: H00L0000 V02N0001 +arc: N1_V02N0601 S1_V02N0601 +arc: W1_H02W0601 S1_V02N0601 +arc: CE0 V02N0201 +arc: CE1 V02N0201 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: H01W0000 Q0 +arc: M0 V00T0000 +arc: M2 E1_H02W0601 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q6 +arc: S1_V02S0201 Q2 +arc: S1_V02S0601 Q6 +arc: V00T0000 Q2 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R17C13:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0601 S1_V02N0301 +arc: V00T0100 E1_H02W0301 +arc: CE0 V02N0201 +arc: CE1 V02N0201 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0001 Q0 +arc: M0 V00T0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0201 Q0 +arc: V00T0000 Q2 +arc: V01S0100 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R17C14:PLC2 +arc: H00L0100 H02E0301 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0601 H01E0001 +arc: CE2 H00L0100 +arc: CLK0 G_HPBX0100 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0601 Q4 +arc: V00T0000 Q2 +arc: V01S0000 Q0 +arc: V01S0100 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R17C15:PLC2 +arc: H00L0100 W1_H02E0301 +arc: V00B0000 V02S0001 +arc: W1_H02W0301 E1_H02W0201 +arc: CE0 H00L0100 +arc: CE1 H00L0100 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q2 +arc: V00T0000 Q0 +arc: W1_H02W0401 Q6 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R17C17:PLC2 +arc: W1_H02W0201 S1_V02N0201 + +.tile R17C19:PLC2 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V01N0001 + +.tile R17C20:PLC2 +arc: CE1 V02N0201 +arc: CLK0 G_HPBX0000 +arc: E1_H02E0001 Q2 +arc: LSR0 H02E0501 +arc: M2 H02E0601 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R17C21:PLC2 +arc: V00T0000 H02E0001 +arc: CE1 V02N0201 +arc: CE2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: E1_H02E0601 Q4 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M2 H02W0601 +arc: M4 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: S1_V02S0001 Q2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET SET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R17C22:PLC2 +arc: H00R0100 V02N0701 +arc: V00T0100 V02N0501 +arc: CE1 V02N0201 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M2 H02E0601 +arc: M6 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: V00T0000 Q2 +arc: W1_H02W0601 Q6 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET SET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R17C8:PLC2 +arc: E1_H02E0401 V01N0001 + +.tile R17C9:PLC2 +arc: CE1 H02W0101 +arc: CE3 H02W0101 +arc: CLK0 G_HPBX0100 +arc: M2 V00B0000 +arc: M6 H02E0401 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0201 Q2 +arc: V00B0000 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R18C11:PLC2 +arc: S1_V02S0601 H06W0303 + +.tile R18C12:PLC2 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 E1_H02W0201 +arc: S1_V02S0701 E1_H02W0701 +arc: V00T0100 N1_V02S0501 +arc: A0 H00R0000 +arc: A1 E1_H01E0001 +arc: B0 V00B0000 +arc: B1 V00T0000 +arc: C0 N1_V01S0100 +arc: C1 E1_H01W0000 +arc: CE1 H00L0000 +arc: CE2 H00L0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D0 V02S0201 +arc: D1 F0 +arc: E1_H01E0001 Q4 +arc: E1_H02E0101 F1 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: M6 V00T0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0103 F1 +arc: V00B0000 Q6 +arc: V00T0000 Q2 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 0001000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R18C13:PLC2 +arc: N1_V02N0201 H02W0201 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 E1_H01W0100 +arc: V00B0100 V02N0101 +arc: V00T0100 H02E0101 +arc: A0 E1_H01E0001 +arc: A2 E1_H01E0001 +arc: A3 V00T0000 +arc: A5 V00T0000 +arc: A7 E1_H02W0501 +arc: B0 E1_H02W0101 +arc: B1 V00T0000 +arc: B2 E1_H02W0301 +arc: B5 E1_H02W0301 +arc: B6 V02N0501 +arc: B7 E1_H02W0101 +arc: C1 N1_V01S0100 +arc: C2 E1_H01W0000 +arc: C5 V00T0100 +arc: C7 V00T0100 +arc: CE0 H00R0000 +arc: CE2 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D0 V00T0100 +arc: D1 V02S0201 +arc: D2 V00T0100 +arc: D3 V01S0100 +arc: D4 V02N0401 +arc: D6 E1_H01W0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F3 +arc: E1_H02E0401 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H00R0000 F6 +arc: H01W0000 F1 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M4 V00B0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 F3 +arc: V00B0000 Q4 +arc: V00T0000 Q0 +arc: V01S0000 Q4 +arc: V01S0100 Q4 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICEC.K1.INIT 1101010111010101 +word: SLICED.K0.INIT 1100110000000000 +word: SLICED.K1.INIT 1011111100111111 +word: SLICEA.K0.INIT 1101110101010101 +word: SLICEA.K1.INIT 0000000000001100 +word: SLICEB.K0.INIT 1111001011111010 +word: SLICEB.K1.INIT 1010101000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R18C14:PLC2 +arc: S1_V02S0601 V01N0001 +arc: V00B0100 V02N0101 +arc: B5 W1_H02E0101 +arc: C0 H02E0401 +arc: C1 N1_V01S0100 +arc: CLK0 G_HPBX0100 +arc: D0 V01S0100 +arc: D1 N1_V01S0000 +arc: D5 E1_H01W0100 +arc: E1_H02E0701 Q5 +arc: E3_H06E0103 F1 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q1 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR0 +arc: S1_V02S0501 Q5 +arc: S3_V06S0103 Q1 +arc: V01S0100 Q1 +arc: W1_H02W0001 F0 +arc: W1_H02W0201 F0 +arc: W1_H02W0701 Q5 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 0000111100000000 +word: SLICEA.K1.INIT 0000111111110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000011001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R18C15:PLC2 +arc: H00R0000 S1_V02N0601 +arc: S1_V02S0201 H06E0103 +arc: W1_H02W0501 V02N0501 +arc: A3 V00T0000 +arc: B2 H00R0100 +arc: B3 S1_V02N0301 +arc: B7 V00T0000 +arc: C2 N1_V01N0001 +arc: C3 H00R0100 +arc: C7 V02N0001 +arc: CE1 H00R0000 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D7 H00R0100 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q7 +arc: H01W0100 F3 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0001 Q2 +arc: S1_V02S0501 Q7 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q7 +arc: V00T0000 Q2 +arc: W1_H02W0101 F3 +arc: W1_H02W0301 F3 +word: SLICEB.K0.INIT 0000110000000000 +word: SLICEB.K1.INIT 1100110011000100 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1100110011110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 + +.tile R18C16:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0301 V01N0101 + +.tile R18C17:PLC2 +arc: H00R0100 H02E0701 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0601 H06E0303 +arc: V00T0000 H02W0201 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q0 +arc: LSR1 E1_H02W0501 +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: V00B0000 Q4 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R18C18:PLC2 +arc: E1_H02E0601 E1_H01W0000 +arc: H00R0100 E1_H02W0701 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: LSR0 H02W0501 +arc: LSR1 H02W0501 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M4 E1_H02W0401 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q4 +arc: V00B0000 Q6 +arc: V00T0000 Q2 +arc: W1_H02W0201 Q0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R18C19:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0501 S1_V02N0501 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0501 S1_V02N0501 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: H01W0000 Q4 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M0 H02E0601 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: V00B0000 Q6 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R18C20:PLC2 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0201 S1_V02N0701 +arc: V00T0000 V02N0401 +arc: W1_H02W0701 E1_H02W0701 +arc: S1_V02S0101 W3_H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M0 V00B0000 +arc: M2 N1_V01N0001 +arc: M4 E1_H01E0101 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q0 +arc: V00B0000 Q6 +arc: W1_H02W0401 Q4 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R18C21:PLC2 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0601 +arc: V00B0000 V02S0001 +arc: W1_H02W0701 S1_V02N0701 +arc: CE0 S1_V02N0201 +arc: CE1 S1_V02N0201 +arc: CE2 S1_V02N0601 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 Q6 +arc: E1_H02E0401 Q4 +arc: LSR0 W1_H02E0501 +arc: LSR1 W1_H02E0501 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q0 +arc: V00T0000 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET SET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET SET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R18C22:PLC2 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0701 +arc: W1_H02W0701 S1_V02N0701 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: LSR0 E1_H02W0501 +arc: LSR1 E1_H02W0501 +arc: M0 V00B0000 +arc: M2 N1_V01N0001 +arc: M4 H02E0401 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: S1_V02S0601 Q6 +arc: V00B0000 Q4 +arc: V00T0000 Q2 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET SET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET SET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R18C23:PLC2 +arc: S3_V06S0003 H06E0003 + +.tile R18C24:PLC2 +arc: W1_H02W0501 S1_V02N0501 + +.tile R18C7:PLC2 +arc: E1_H02E0101 V02N0101 + +.tile R18C8:PLC2 +arc: V00T0000 V02N0601 +arc: CE0 H02E0101 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0100 +arc: M0 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R19C10:PLC2 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 H02E0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 H06W0103 +arc: W1_H02W0301 S3_V06N0003 +arc: A3 V02N0701 +arc: B2 V02N0301 +arc: B3 V02N0301 +arc: C2 H00L0100 +arc: C3 E1_H02W0601 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D2 S1_V02N0201 +arc: E3_H06E0103 Q2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0100 Q3 +arc: MUXCLK1 CLK0 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1110001011100010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R19C11:PLC2 +arc: E1_H02E0601 V02N0601 +arc: H00R0100 H02W0701 +arc: V00B0000 H02E0401 +arc: V00B0100 H02E0501 +arc: V00T0100 W1_H02E0101 +arc: E1_H02E0101 W3_H06E0103 +arc: E3_H06E0103 W3_H06E0103 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 V02S0601 +arc: CE3 V02S0601 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0101 Q6 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q2 +arc: E1_H02E0401 Q4 +arc: M0 V00B0000 +arc: M2 H02E0601 +arc: M4 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R19C12:PLC2 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 V01N0001 +arc: W1_H02W0701 V02S0701 +arc: A0 E1_H01E0001 +arc: A2 V02N0501 +arc: A3 V00B0000 +arc: A4 V02N0101 +arc: A5 V02N0301 +arc: B1 E1_H02W0301 +arc: B6 V01S0000 +arc: B7 V00T0000 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C3 H02E0401 +arc: C4 V00B0100 +arc: C5 E1_H01E0101 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: CE0 E1_H02W0101 +arc: CE1 E1_H02W0101 +arc: CE2 E1_H02W0101 +arc: CE3 E1_H02W0101 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 S1_V02N0001 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 H02E0001 +arc: D7 H02E0201 +arc: E1_H01E0001 Q1 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V00B0000 Q6 +arc: V00B0100 Q5 +arc: V00T0000 Q0 +arc: V00T0100 Q3 +arc: V01S0000 Q7 +arc: W1_H02W0601 Q4 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1111101000001010 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R19C13:PLC2 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0501 E1_H02W0501 +arc: V00B0000 E1_H02W0601 +arc: V00T0100 W1_H02E0101 +arc: A4 E1_H02W0501 +arc: A5 Q5 +arc: A6 H00R0000 +arc: B3 V02S0301 +arc: B4 V00B0100 +arc: B6 V00B0100 +arc: C1 N1_V01S0100 +arc: C3 E1_H02W0601 +arc: C4 Q4 +arc: C5 E1_H01E0101 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0601 +arc: CE2 H00L0100 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D1 V02S0001 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0101 Q7 +arc: E1_H02E0101 F1 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0000 Q4 +arc: H00R0100 Q7 +arc: H01W0000 F1 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V02N0301 F1 +arc: N1_V02N0401 F6 +arc: S1_V02S0101 F1 +arc: S3_V06S0103 F1 +arc: V00B0100 Q5 +arc: V01S0100 F1 +arc: W3_H06W0103 F1 +word: SLICEC.K0.INIT 0001010001010000 +word: SLICEC.K1.INIT 0000000001011010 +word: SLICED.K0.INIT 0000011100001111 +word: SLICED.K1.INIT 0000000000001111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1100000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 + +.tile R19C14:PLC2 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 H06E0103 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 E1_H01W0100 +arc: CE0 H02E0101 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0401 Q4 +arc: M0 V00T0000 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0201 Q2 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R19C15:PLC2 +arc: H00L0000 H02W0001 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0501 E3_H06W0303 +arc: V00B0000 H02E0401 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 E3_H06W0303 +arc: B4 V02N0501 +arc: B5 V02N0501 +arc: C4 V00B0100 +arc: C5 V02N0201 +arc: CE1 H00R0100 +arc: CE2 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D3 V01S0100 +arc: D4 E1_H01W0100 +arc: D5 V00B0000 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q4 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: V00B0100 Q5 +arc: V01S0100 Q3 +arc: W1_H02W0301 Q3 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000011111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R19C16:PLC2 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: S1_V02S0201 H06E0103 +arc: S3_V06S0103 H06E0103 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 E3_H06W0003 +arc: E3_H06E0203 W3_H06E0103 +arc: W3_H06W0103 E3_H06W0003 +arc: CE1 V02N0201 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: H01W0100 Q6 +arc: M2 V00T0000 +arc: M6 H02W0401 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R19C17:PLC2 +arc: V00T0000 H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: CE0 V02S0201 +arc: CLK0 G_HPBX0100 +arc: M0 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 Q0 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R19C18:PLC2 +arc: H00R0100 V02N0501 +arc: V00B0000 V02N0201 +arc: CE0 H00R0100 +arc: CLK0 G_HPBX0000 +arc: M0 V00B0000 +arc: MUXCLK0 CLK0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R19C19:PLC2 +arc: E1_H02E0501 V02N0501 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0601 E1_H02W0601 + +.tile R19C20:PLC2 +arc: E1_H02E0101 V02S0101 +arc: H00R0100 V02N0701 +arc: V00T0000 V02N0401 +arc: CE1 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: LSR0 H02E0501 +arc: M2 V00T0000 +arc: M6 N1_V01N0101 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0401 Q6 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET SET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R19C21:PLC2 +arc: V00B0100 V02N0301 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0601 E1_H01W0000 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0100 +arc: M6 V00B0100 +arc: MUXCLK3 CLK0 +arc: W3_H06W0303 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R19C22:PLC2 +arc: S1_V02S0401 E1_H01W0000 +arc: V00T0100 V02N0501 +arc: E1_H02E0701 W3_H06E0203 +arc: A3 V02N0501 +arc: B2 F3 +arc: C3 V02N0401 +arc: D2 V00T0100 +arc: D3 V02N0201 +arc: E1_H02E0101 F3 +arc: E1_H02E0201 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F3 +arc: S1_V02S0101 F3 +arc: S3_V06S0003 F3 +arc: W3_H06W0003 F3 +word: SLICEB.K0.INIT 0000000011001100 +word: SLICEB.K1.INIT 1111101000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R19C23:PLC2 +arc: S1_V02S0401 H02W0401 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: CE1 H02E0101 +arc: CLK0 G_HPBX0000 +arc: H01W0000 Q2 +arc: LSR0 V00T0000 +arc: M2 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R19C24:PLC2 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 S3_V06N0203 + +.tile R19C3:PLC2 +arc: S3_V06S0003 H06W0003 + +.tile R19C4:PLC2 +arc: S3_V06S0103 H06W0103 + +.tile R19C5:PLC2 +arc: E3_H06E0103 S3_V06N0103 + +.tile R19C6:PLC2 +arc: W3_H06W0003 E1_H01W0000 + +.tile R19C7:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 V01N0001 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E3_H06W0103 +arc: S1_V02S0101 E3_H06W0103 +arc: S3_V06S0103 E3_H06W0103 +arc: W3_H06W0103 E3_H06W0103 + +.tile R19C8:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 S1_V02N0501 +arc: CE2 H02E0101 +arc: CLK0 G_HPBX0100 +arc: M4 H02E0401 +arc: MUXCLK2 CLK0 +arc: N1_V02N0601 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R19C9:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0601 E1_H01W0000 +arc: S1_V02S0301 H02W0301 + +.tile R20C10:PLC2 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 H02W0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: V00B0100 H02W0701 +arc: W3_H06W0103 E3_H06W0003 +arc: A7 E1_H02W0701 +arc: B1 E1_H02W0101 +arc: C1 E1_H02W0601 +arc: C7 H02W0401 +arc: CE0 H00R0000 +arc: CE1 H02E0101 +arc: CE2 H00R0100 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D1 V02N0001 +arc: D7 H00L0100 +arc: E1_H02E0001 Q2 +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0701 Q7 +arc: S1_V02S0201 Q2 +arc: S3_V06S0103 Q2 +arc: V00B0000 Q4 +arc: V01S0000 Q1 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 + +.tile R20C11:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0601 E3_H06W0303 +arc: E3_H06E0003 S3_V06N0003 +arc: H00L0000 V02N0001 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 H02E0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 V02N0701 +arc: CE1 E1_H02W0101 +arc: CE2 H00L0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: M2 V00T0000 +arc: M4 W1_H02E0401 +arc: M6 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0001 Q2 +arc: W1_H02W0201 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R20C12:PLC2 +arc: H00R0100 N1_V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0601 H02E0601 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H01W0100 +arc: A7 S1_V02N0101 +arc: B1 E1_H02W0101 +arc: B3 E1_H01W0100 +arc: C1 E1_H01W0000 +arc: C3 V02N0601 +arc: C7 V02S0001 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D1 H02E0201 +arc: D3 V00B0100 +arc: D7 H02W0001 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q3 +arc: N1_V02N0501 Q7 +arc: V01S0000 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111110000110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 + +.tile R20C13:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E3_H06E0103 N1_V01S0100 +arc: H00L0100 V02S0101 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0101 E1_H02W0101 +arc: CE1 H00L0100 +arc: CLK0 G_HPBX0100 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: M0 V00B0000 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: W1_H02W0001 Q0 +arc: W3_H06W0103 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R20C14:PLC2 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 V01N0001 +arc: S3_V06S0103 W3_H06E0103 +arc: A0 H00L0000 +arc: B0 V00B0000 +arc: B1 E1_H01W0100 +arc: C0 N1_V01S0100 +arc: C1 N1_V01N0001 +arc: CE1 H02E0101 +arc: CE2 H02E0101 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0100 +arc: D0 H00R0000 +arc: D1 E1_H02W0201 +arc: E1_H02E0101 F1 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: M2 V00T0000 +arc: M4 V00B0000 +arc: M6 N1_V01N0101 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 Q2 +arc: S1_V02S0101 F1 +arc: V00B0000 Q6 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 0011000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R20C15:PLC2 +arc: E1_H02E0101 V02N0101 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0000 N1_V02S0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0601 E1_H01W0000 +arc: A4 V00B0000 +arc: B2 F3 +arc: B3 H02E0101 +arc: B4 N1_V02S0501 +arc: C2 V02N0401 +arc: C4 V02N0201 +arc: CE0 W1_H02E0101 +arc: CE3 W1_H02E0101 +arc: CLK0 G_HPBX0100 +arc: D2 N1_V02S0201 +arc: D3 H00R0000 +arc: D4 V01N0001 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 Q6 +arc: H01W0100 Q0 +arc: M0 H02E0601 +arc: M4 E1_H01E0101 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0301 F3 +arc: N1_V02N0601 F4 +arc: S1_V02S0601 F4 +arc: V00T0000 Q0 +arc: W1_H02W0401 Q6 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0011000011110000 +word: SLICEB.K1.INIT 1100110000000000 +word: SLICEC.K0.INIT 0001010101110111 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R20C16:PLC2 +arc: H00L0000 V02S0201 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0701 E3_H06W0203 +arc: V00T0000 N1_V02S0401 +arc: W3_H06W0003 E3_H06W0303 +arc: CE0 V02S0201 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: H01W0000 Q0 +arc: M0 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: V00B0000 Q6 +arc: W1_H02W0201 Q0 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R20C17:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0100 V02N0701 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0701 E3_H06W0203 +arc: E3_H06E0003 W3_H06E0003 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0303 E3_H06W0303 +arc: CE0 H00R0100 +arc: CE2 W1_H02E0101 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0401 Q4 +arc: M0 V00B0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: S3_V06S0203 Q4 +arc: V00T0000 Q0 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R20C18:PLC2 +arc: H00R0000 H02E0601 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 H01E0101 +arc: S1_V02S0401 H02E0401 +arc: V00B0100 H02E0701 +arc: V00T0100 V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CE2 H00R0000 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q0 +arc: E1_H02E0601 Q4 +arc: M0 H02W0601 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R20C19:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0501 E3_H06W0303 +arc: N1_V02N0501 E3_H06W0303 +arc: W1_H02W0601 V02N0601 +arc: A0 E1_H02W0501 +arc: A4 E1_H02W0501 +arc: A5 E1_H02W0501 +arc: B1 V02N0301 +arc: C0 H00L0100 +arc: C1 V02N0401 +arc: C4 H02E0601 +arc: C5 V00T0000 +arc: CE0 V02S0201 +arc: CE2 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q1 +arc: H00R0100 Q5 +arc: H01W0100 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R20C20:PLC2 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 H06E0003 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0201 E1_H01W0000 +arc: CE0 H00R0100 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0000 +arc: LSR0 H02E0501 +arc: M0 V00B0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V02N0401 Q4 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R20C21:PLC2 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0501 E1_H02W0501 +arc: C1 E1_H02W0401 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: E1_H02E0601 Q6 +arc: F1 F1_SLICE +arc: H01W0000 Q6 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0301 Q1 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000111100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R20C22:PLC2 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0701 H02W0701 +arc: V00T0000 N1_V02S0601 +arc: A1 H02W0701 +arc: A6 F7 +arc: A7 H02W0701 +arc: B1 V02N0301 +arc: B6 F1 +arc: B7 V02N0501 +arc: C1 H02E0601 +arc: C6 V00T0000 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0000 +arc: D1 H02W0201 +arc: D6 E1_H01W0100 +arc: D7 H02W0001 +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: MUXCLK3 CLK0 +arc: N1_V02N0701 F7 +arc: W1_H02W0701 F7 +arc: W3_H06W0203 F7 +arc: W3_H06W0303 Q6 +word: SLICED.K0.INIT 1110110011111111 +word: SLICED.K1.INIT 0010000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111000000010000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX INV +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R20C23:PLC2 +arc: H00R0000 E1_H02W0401 +arc: V00B0000 V02N0201 +arc: V00T0100 V02N0701 +arc: A3 V01N0101 +arc: A4 N1_V01N0101 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B1 V01N0001 +arc: B3 H00R0100 +arc: B4 V01S0000 +arc: B5 H00R0000 +arc: B6 F1 +arc: B7 V02N0501 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C3 V02N0401 +arc: C4 V02N0001 +arc: C5 E1_H02W0601 +arc: C7 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 F0 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: D5 V02S0401 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0101 F1 +arc: E1_H02E0501 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0100 Q5 +arc: H01W0000 F1 +arc: H01W0100 F6 +arc: M2 V00B0000 +arc: M6 V00T0100 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q5 +arc: S3_V06S0303 Q5 +arc: V01S0000 F0 +arc: W1_H02W0001 F0 +arc: W1_H02W0201 F2 +arc: W1_H02W0401 F4 +arc: W1_H02W0501 Q5 +arc: W1_H02W0601 Q4 +arc: W1_H02W0701 Q5 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0111011111111111 +word: SLICED.K1.INIT 0001001100110011 +word: SLICEA.K0.INIT 0000000000001111 +word: SLICEA.K1.INIT 1100000000000000 +word: SLICEC.K0.INIT 0000000010000000 +word: SLICEC.K1.INIT 0000000011111100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R20C24:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V02N0501 H02W0501 +arc: W1_H02W0401 E1_H01W0000 + +.tile R20C25:PLC2 +arc: H00R0100 S1_V02N0501 +arc: S1_V02S0501 W1_H02E0501 +arc: A4 W1_H02E0501 +arc: A7 Q7 +arc: B0 V00B0000 +arc: B4 V02N0501 +arc: C0 H00L0100 +arc: C1 F4 +arc: C4 V00B0100 +arc: C5 H02E0601 +arc: C6 E1_H01E0101 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0001 +arc: D4 H00R0100 +arc: D5 V01N0001 +arc: D6 H02E0001 +arc: D7 H02E0201 +arc: E1_H01E0101 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q5 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0701 Q5 +arc: V00B0000 Q6 +arc: V00B0100 Q5 +arc: V00T0100 Q1 +arc: W1_H02W0401 Q6 +arc: W1_H02W0501 Q5 +arc: W1_H02W0601 F4 +arc: W3_H06W0303 Q5 +word: SLICEC.K0.INIT 0000000000110010 +word: SLICEC.K1.INIT 0000111100000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 0000000011111010 +word: SLICEA.K0.INIT 1111110000000000 +word: SLICEA.K1.INIT 1111000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R20C4:PLC2 +arc: S3_V06S0103 H06W0103 +arc: W3_H06W0103 E3_H06W0103 + +.tile R20C5:PLC2 +arc: S1_V02S0201 V01N0001 + +.tile R20C6:PLC2 +arc: S1_V02S0501 V01N0101 + +.tile R20C7:PLC2 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0100 V02S0101 +arc: V00B0000 S1_V02N0201 +arc: W3_H06W0103 E3_H06W0103 +arc: CE2 H00L0100 +arc: CLK0 G_HPBX0100 +arc: M4 V00B0000 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q4 +arc: S3_V06S0203 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R20C8:PLC2 +arc: E1_H02E0101 V01N0101 +arc: H00R0000 V02N0401 +arc: H00R0100 H02W0501 +arc: V00B0000 V02N0001 +arc: CE0 H02W0101 +arc: CE1 H00R0100 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0001 Q2 +arc: E3_H06E0103 Q2 +arc: H01W0000 Q6 +arc: M0 H02E0601 +arc: M2 V00T0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0003 Q0 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R20C9:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 H01E0001 +arc: H00L0100 V02N0101 +arc: H00R0000 V02N0401 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0100 V02S0301 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 S1_V02N0501 +arc: A7 V02N0301 +arc: B1 V00T0000 +arc: B7 S1_V02N0701 +arc: C1 S1_V02N0401 +arc: CE0 H00R0000 +arc: CE1 H02E0101 +arc: CE2 H00L0100 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: D1 V02N0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 Q2 +arc: E1_H02E0601 Q4 +arc: E1_H02E0701 Q7 +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q1 +arc: V01S0000 Q4 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1101110100010001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1100000011001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 + +.tile R21C10:PLC2 +arc: E1_H02E0501 H01E0101 +arc: H00R0000 H02E0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 H01E0101 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W3_H06W0003 E1_H01W0000 +arc: A1 V02N0501 +arc: B4 H02E0301 +arc: C1 H02E0401 +arc: C4 H01E0001 +arc: C5 W1_H02E0601 +arc: CE0 H00R0000 +arc: CE1 H00R0100 +arc: CE2 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D1 V01S0100 +arc: D4 S1_V02N0401 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q2 +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: M2 V00B0100 +arc: M4 H02E0401 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0601 Q4 +arc: V01S0000 Q6 +arc: V01S0100 Q2 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111010100000101 +word: SLICEC.K0.INIT 0011001111110000 +word: SLICEC.K1.INIT 1111000011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R21C11:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0201 W1_H02E0201 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0701 S3_V06N0203 +arc: A6 H00L0000 +arc: B2 V02N0101 +arc: B6 H02W0101 +arc: B7 V02N0701 +arc: C3 F6 +arc: C6 S1_V02N0201 +arc: C7 F6 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0100 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D6 H01W0000 +arc: D7 V01N0001 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 Q7 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: M0 V00T0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0003 F3 +arc: S3_V06S0103 F2 +arc: W1_H02W0401 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000010100110101 +word: SLICED.K1.INIT 1100111100000011 +word: SLICEB.K0.INIT 0000000000110011 +word: SLICEB.K1.INIT 0000000000001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R21C12:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0100 V02N0301 +arc: V00T0000 V02N0401 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0101 W3_H06E0103 +arc: A2 V00B0000 +arc: A3 E1_H02W0701 +arc: B2 E1_H02W0101 +arc: B3 H00L0000 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: CE0 H02W0101 +arc: CE2 H02W0101 +arc: CE3 H02W0101 +arc: CLK0 G_HPBX0100 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: M0 V00B0100 +arc: M4 V00T0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V00B0000 Q4 +arc: V01S0000 Q6 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1010110011001100 +word: SLICEB.K1.INIT 1100101010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R21C13:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0100 V02N0301 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0100 V02N0101 +arc: V00T0000 H02W0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H02W0101 +arc: E1_H02E0101 W3_H06E0103 +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: A2 S1_V02N0501 +arc: A3 E1_H02W0501 +arc: B2 H00L0000 +arc: B3 H00R0000 +arc: C2 H02E0601 +arc: CE1 H00L0100 +arc: CE2 E1_H02W0101 +arc: CE3 E1_H02W0101 +arc: CLK0 G_HPBX0100 +arc: D2 W1_H02E0201 +arc: D3 F2 +arc: E1_H02E0301 Q3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: M0 V00B0100 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0001 F2 +arc: V01S0000 Q6 +arc: V01S0100 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0001000100011011 +word: SLICEB.K1.INIT 1000100011011101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R21C14:PLC2 +arc: H00R0000 H02W0401 +arc: N1_V02N0301 H02E0301 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0103 H06E0103 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0701 W3_H06E0203 +arc: A2 E1_H02W0501 +arc: A3 V00B0000 +arc: B2 E1_H01W0100 +arc: C2 E1_H02W0401 +arc: C3 V02N0401 +arc: CE1 H00R0000 +arc: CE2 H02W0101 +arc: CLK0 G_HPBX0100 +arc: D2 V01S0100 +arc: D3 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F2 +arc: M0 V00T0100 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q3 +arc: V00B0000 Q4 +arc: V01S0000 Q4 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000001001010111 +word: SLICEB.K1.INIT 1010000010101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R21C15:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0501 W3_H06E0303 +arc: A5 V02N0301 +arc: A7 Q7 +arc: B5 W1_H02E0101 +arc: B6 V02S0501 +arc: C4 E1_H02W0401 +arc: C5 F4 +arc: C6 V00B0100 +arc: C7 V02S0001 +arc: CE3 V02S0601 +arc: CLK0 G_HPBX0100 +arc: D4 V02N0601 +arc: D5 H02W0001 +arc: D6 V00B0000 +arc: D7 H00R0100 +arc: E1_H01E0101 F4 +arc: E1_H02E0401 F4 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F5 +arc: LSR0 V00T0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 Q7 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 F6 +arc: V00B0100 Q7 +arc: W3_H06W0203 F4 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 0000000000000011 +word: SLICED.K1.INIT 0000010100001010 +word: SLICEC.K0.INIT 0000000000001111 +word: SLICEC.K1.INIT 0000101100001000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 + +.tile R21C16:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 H02E0601 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0100 V02N0301 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 S1_V02N0701 +arc: A4 E1_H01W0000 +arc: A5 H02E0701 +arc: B1 S1_V02N0301 +arc: B4 H00L0000 +arc: C0 F4 +arc: C4 V01N0101 +arc: C5 F4 +arc: CE2 H00R0000 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0100 +arc: D0 S1_V02N0201 +arc: D1 E1_H02W0001 +arc: D4 S1_V02N0601 +arc: D5 V00B0000 +arc: E1_H01E0101 F0 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q2 +arc: H01W0100 F1 +arc: M2 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0201 F0 +arc: S1_V02S0301 F1 +arc: S3_V06S0003 F0 +arc: S3_V06S0103 F1 +arc: V00B0000 Q6 +arc: V01S0000 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000010100110011 +word: SLICEC.K1.INIT 1010111100000101 +word: SLICEA.K0.INIT 0000000000001111 +word: SLICEA.K1.INIT 0000000000110011 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R21C17:PLC2 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 E1_H01W0000 +arc: N1_V02N0401 W3_H06E0203 +arc: A3 H02E0501 +arc: A6 W1_H02E0501 +arc: A7 E1_H01W0000 +arc: B1 V00B0000 +arc: B2 E1_H01W0100 +arc: B3 H00R0000 +arc: B7 V02N0501 +arc: C0 H02W0601 +arc: C1 F6 +arc: C2 W1_H02E0401 +arc: C3 N1_V01N0001 +arc: C6 E1_H02W0401 +arc: C7 F6 +arc: CLK0 G_HPBX0100 +arc: D1 F2 +arc: D2 W1_H02E0001 +arc: D3 E1_H02W0001 +arc: D6 V02N0401 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F0 +arc: E1_H02E0001 F0 +arc: E1_H02E0101 F3 +arc: E1_H02E0201 F2 +arc: E1_H02E0701 F7 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 F2 +arc: M0 H02E0601 +arc: M4 V00B0100 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F2 +arc: S1_V02S0101 F3 +arc: V01S0000 F2 +arc: W3_H06W0103 F2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000010111110101 +word: SLICED.K1.INIT 0000000000000010 +word: SLICEA.K0.INIT 0000111100001111 +word: SLICEA.K1.INIT 0000000011111100 +word: SLICEB.K0.INIT 0000000000110000 +word: SLICEB.K1.INIT 0001000100011011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R21C18:PLC2 +arc: H00L0100 V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0201 S3_V06N0103 +arc: V00B0000 V02N0001 +arc: V00T0000 V02N0601 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 S1_V02N0101 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: B5 H02E0101 +arc: C5 V02N0201 +arc: CE2 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D5 V02N0401 +arc: E1_H01E0001 Q5 +arc: F5 F5_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q2 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: W1_H02W0601 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111000000110011 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 + +.tile R21C19:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 V02N0001 +arc: H00R0100 H02W0501 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 H01E0001 +arc: E1_H02E0501 W3_H06E0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: B7 V02N0701 +arc: C7 V02N0201 +arc: CE2 H00R0100 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D7 W1_H02E0001 +arc: F7 F7_SLICE +arc: M4 V00B0100 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0401 Q4 +arc: V00B0100 Q7 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1100000011110011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 + +.tile R21C20:PLC2 +arc: E1_H02E0601 V06S0303 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 E1_H02W0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0501 V06S0303 +arc: A5 H02E0701 +arc: B5 F1 +arc: C1 V02N0601 +arc: C4 E1_H01E0101 +arc: CLK0 G_HPBX0100 +arc: D1 V02S0001 +arc: D5 H02E0201 +arc: E1_H01E0101 Q2 +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: M2 H02E0601 +arc: M4 V00B0100 +arc: MUXCLK1 CLK0 +arc: S1_V02S0601 F4 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000111100001111 +word: SLICEC.K1.INIT 0000000000010001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R21C21:PLC2 +arc: H00R0000 H02E0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02N0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0301 E1_H01W0100 +arc: A3 W1_H02E0501 +arc: B7 F3 +arc: C7 E1_H02W0401 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D3 S1_V02N0001 +arc: D6 V00B0000 +arc: D7 E1_H02W0201 +arc: E1_H02E0201 Q0 +arc: F3 F3_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M4 V00T0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: V00B0000 Q4 +arc: V01S0000 F6 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000000000000011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1010101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R21C22:PLC2 +arc: H00L0100 N1_V02S0101 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 E1_H01W0100 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0501 S1_V02N0501 +arc: A1 V02S0701 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: C1 N1_V02S0401 +arc: C4 V00B0100 +arc: C5 V02N0001 +arc: CE0 H00L0100 +arc: CE2 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D1 S1_V02N0201 +arc: D4 H02E0201 +arc: D5 V01N0001 +arc: E1_H02E0301 Q1 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: V00B0100 Q5 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 1111001111000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111010110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R21C23:PLC2 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 E1_H01W0100 +arc: V00T0000 H02W0001 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: H01W0000 Q6 +arc: H01W0100 Q2 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: M0 V00T0000 +arc: M2 H02W0601 +arc: M4 E1_H02W0401 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q4 +arc: N1_V02N0001 Q2 +arc: N1_V02N0201 Q0 +arc: N1_V02N0401 Q6 +arc: N1_V02N0601 Q4 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET SET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R21C24:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 H02W0201 +arc: V00B0100 V02N0101 +arc: W1_H02W0301 E1_H01W0100 +arc: CE0 H00L0000 +arc: CE1 H00L0000 +arc: CE2 H00L0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 Q0 +arc: H01W0100 Q4 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q0 +arc: V00B0000 Q6 +arc: V00T0000 Q2 +arc: W1_H02W0001 Q2 +arc: W1_H02W0401 Q4 +arc: W1_H02W0601 Q6 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET SET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R21C25:PLC2 +arc: H00R0000 H02E0401 +arc: H00R0100 V02S0501 +arc: V00B0000 H02E0401 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 H01E0001 +arc: A0 V02S0701 +arc: A2 V02N0501 +arc: A3 V02S0701 +arc: A4 V00T0000 +arc: A5 V02N0301 +arc: A7 Q7 +arc: B0 V01N0001 +arc: B3 H00R0000 +arc: B6 V02N0501 +arc: B7 V02N0501 +arc: C0 F4 +arc: C2 H00R0100 +arc: C3 F4 +arc: C4 V02S0001 +arc: C5 H02E0401 +arc: C6 V00B0100 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 V00B0100 +arc: D3 F2 +arc: D4 H01W0000 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q5 +arc: H01W0100 Q7 +arc: M0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q3 +arc: N1_V02N0501 Q7 +arc: V00B0100 Q7 +arc: V00T0000 Q0 +arc: V01S0000 Q7 +arc: V01S0100 Q3 +arc: W1_H02W0201 F2 +arc: W1_H02W0501 Q7 +arc: W1_H02W0701 Q5 +word: SLICEC.K0.INIT 0000000000000101 +word: SLICEC.K1.INIT 1111000010100000 +word: SLICEB.K0.INIT 1111111111111010 +word: SLICEB.K1.INIT 0000000000000100 +word: SLICED.K0.INIT 0000000000001100 +word: SLICED.K1.INIT 0000111100001110 +word: SLICEA.K0.INIT 1100110011001101 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R21C26:PLC2 +arc: W1_H02W0301 H01E0101 + +.tile R21C2:PLC2 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 S3_V06N0103 + +.tile R21C3:PLC2 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02N0001 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0101 Q4 +arc: M4 V00B0000 +arc: MUXCLK2 CLK0 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R21C4:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: V00B0000 S1_V02N0201 +arc: A2 V01N0101 +arc: B2 V02N0101 +arc: B3 H00R0000 +arc: C2 V02N0401 +arc: C3 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: D2 H01E0101 +arc: D3 F2 +arc: E3_H06E0003 F3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00R0000 Q6 +arc: M6 V00B0000 +arc: MUXCLK3 CLK0 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1010100010101010 +word: SLICEB.K1.INIT 1111001100000011 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R21C5:PLC2 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 V02S0201 +arc: V00T0100 H02W0101 +arc: A3 H02E0501 +arc: A4 N1_V01N0101 +arc: B4 V02N0701 +arc: B5 V01S0000 +arc: C2 V02N0401 +arc: C3 V02N0401 +arc: C4 V02N0201 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0100 +arc: D2 H02W0001 +arc: D3 H00R0000 +arc: D4 F2 +arc: D5 H01W0000 +arc: E1_H02E0701 F5 +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F4 +arc: M0 V00T0100 +arc: M2 E1_H02W0601 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q6 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000111111111111 +word: SLICEB.K1.INIT 0000010111110101 +word: SLICEC.K0.INIT 1111110100000000 +word: SLICEC.K1.INIT 1111001100000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R21C6:PLC2 +arc: H00R0000 E1_H02W0401 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0003 H06W0003 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 S3_V06N0203 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: B0 H01W0100 +arc: B1 E1_H01W0100 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: CE1 H02W0101 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D0 V02N0001 +arc: D1 H02W0201 +arc: E1_H01E0001 F0 +arc: E1_H02E0001 Q2 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q4 +arc: M2 N1_V01N0001 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q2 +arc: S3_V06S0103 Q2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1111111101010011 +word: SLICEA.K1.INIT 0000000011100010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R21C7:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: H00R0100 V02N0701 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0201 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: A0 E1_H02W0501 +arc: A1 H01E0001 +arc: A3 V00B0000 +arc: B0 V02N0101 +arc: B1 E1_H02W0301 +arc: B3 S1_V02N0301 +arc: C0 H00R0100 +arc: C1 N1_V01N0001 +arc: C2 V02N0401 +arc: C3 E1_H02W0401 +arc: CLK0 G_HPBX0100 +arc: D0 E1_H02W0201 +arc: D1 F0 +arc: D2 E1_H02W0201 +arc: D3 F2 +arc: E1_H02E0301 F1 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q4 +arc: H01W0100 F2 +arc: M4 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: V00B0000 Q4 +arc: V01S0100 F2 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0011111101110111 +word: SLICEA.K1.INIT 1000101100000011 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 0000110000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R21C8:PLC2 +arc: E1_H02E0401 V01N0001 +arc: H00L0100 V02N0301 +arc: H00R0000 V02N0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 S3_V06N0203 +arc: S1_V02S0101 E1_H02W0101 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: A1 H00L0000 +arc: A7 V02N0101 +arc: C1 V02N0401 +arc: C7 V01N0101 +arc: CE0 H00L0100 +arc: CE1 H00R0000 +arc: CE2 V02N0601 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D1 H02E0201 +arc: D7 V02N0401 +arc: E1_H02E0601 Q4 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: M2 V00T0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0501 Q7 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1010000010101111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111000001010101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 + +.tile R21C9:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: A3 V00B0000 +arc: B1 S1_V02N0301 +arc: B3 V01N0001 +arc: C1 H00L0100 +arc: C3 H02E0401 +arc: CLK0 G_HPBX0100 +arc: D0 H02W0001 +arc: D1 H00R0000 +arc: D3 V02N0201 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 F1 +arc: E1_H02E0201 F0 +arc: E1_H02E0301 F3 +arc: E3_H06E0003 F3 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: H00L0100 F3 +arc: H00R0000 Q4 +arc: M4 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0001 F0 +arc: V00B0000 Q6 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111011100000000 +word: SLICEA.K0.INIT 0000000001010101 +word: SLICEA.K1.INIT 0001010100000100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R22C10:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H02E0701 +arc: V00B0100 H02E0701 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 E3_H06W0203 +arc: E1_H02E0401 W3_H06E0203 +arc: H01W0100 W3_H06E0303 +arc: W1_H02W0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: A3 H02E0501 +arc: A6 V02N0301 +arc: A7 W1_H02E0501 +arc: B2 F3 +arc: B3 V01N0001 +arc: CE1 V02N0201 +arc: CLK0 G_HPBX0100 +arc: D2 H02E0201 +arc: D3 N1_V01S0000 +arc: D6 H02E0201 +arc: D7 H02E0201 +arc: E1_H02E0001 F2 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 F6 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0101 Q3 +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F6 +word: SLICEB.K0.INIT 0000000011001100 +word: SLICEB.K1.INIT 0111011101000100 +word: SLICED.K0.INIT 0000000001010101 +word: SLICED.K1.INIT 0000000001010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R22C11:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0701 S1_V02N0701 +arc: E3_H06E0103 W1_H02E0201 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 V02N0101 +arc: V00T0000 H02E0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: H01W0100 W3_H06E0303 +arc: S3_V06S0303 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: CE0 H00R0000 +arc: CE1 E1_H02W0101 +arc: CE2 E1_H02W0101 +arc: CE3 E1_H02W0101 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0201 Q2 +arc: E1_H02E0401 Q4 +arc: E1_H02E0601 Q6 +arc: E3_H06E0003 Q0 +arc: M0 V00T0000 +arc: M2 W1_H02E0601 +arc: M4 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R22C12:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 H02W0601 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S1_V02N0401 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 E1_H01W0000 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: N1_V02N0601 W3_H06E0303 +arc: W3_H06W0203 S3_V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: A0 V02N0701 +arc: A1 H02W0501 +arc: A6 V02N0301 +arc: A7 V02N0301 +arc: B0 V02N0301 +arc: B6 V02N0701 +arc: B7 N1_V01S0000 +arc: C0 H02E0401 +arc: C1 W1_H02E0401 +arc: C6 V00T0000 +arc: C7 V02S0201 +arc: CE0 H00R0000 +arc: CE1 H02W0101 +arc: CE2 H02W0101 +arc: CLK0 G_HPBX0100 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D6 H02E0001 +arc: D7 V02N0401 +arc: E1_H02E0401 Q4 +arc: E3_H06E0003 F0 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M2 E1_H02W0601 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0101 Q1 +arc: V00T0000 Q2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111011110000000 +word: SLICED.K1.INIT 1101100011110000 +word: SLICEA.K0.INIT 1111011110000000 +word: SLICEA.K1.INIT 1010111100000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R22C13:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0001 +arc: V00T0000 H02W0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E3_H06W0103 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0301 +arc: N1_V02N0401 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: W3_H06W0303 S3_V06N0303 +arc: E3_H06E0103 W3_H06E0003 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0701 +arc: A3 V00B0000 +arc: A4 V02N0301 +arc: A5 N1_V01S0100 +arc: A6 E1_H02W0501 +arc: B1 H01W0100 +arc: B4 N1_V01S0000 +arc: B5 V02N0701 +arc: B7 H02W0101 +arc: C1 H02W0401 +arc: C2 V02S0601 +arc: C4 W1_H02E0601 +arc: C5 V00T0000 +arc: C6 H02E0601 +arc: C7 V02S0201 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D1 H02E0001 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 V02N0401 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: H01W0000 F7 +arc: H01W0100 Q0 +arc: LSR0 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0101 F3 +arc: S3_V06S0003 F3 +arc: S3_V06S0103 F1 +arc: V01S0000 F2 +arc: W1_H02W0001 F2 +word: SLICEC.K0.INIT 1101100011110000 +word: SLICEC.K1.INIT 1110001010101010 +word: SLICEA.K0.INIT 0101010101010101 +word: SLICEA.K1.INIT 0000000000000010 +word: SLICED.K0.INIT 1111101000000000 +word: SLICED.K1.INIT 0000000011000000 +word: SLICEB.K0.INIT 0000000000001111 +word: SLICEB.K1.INIT 0000000001010101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R22C14:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0000 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 H01E0101 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V02N0601 +arc: E1_H02E0201 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A6 V02N0101 +arc: A7 E1_H02W0701 +arc: B6 H02E0101 +arc: B7 N1_V01S0000 +arc: C6 W1_H02E0401 +arc: C7 V02N0201 +arc: CE0 H00L0000 +arc: CE1 V02S0201 +arc: CE2 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: D6 V02N0401 +arc: D7 V00B0000 +arc: E1_H02E0001 Q2 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 F6 +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H02E0601 +arc: M2 V00T0100 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S3_V06S0103 Q2 +arc: V00B0000 Q4 +arc: W1_H02W0001 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1110010011001100 +word: SLICED.K1.INIT 1110110001001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R22C15:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 S1_V02N0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: S3_V06S0103 H06E0103 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 V01N0101 +arc: E1_H02E0701 W3_H06E0203 +arc: W1_H02W0501 W3_H06E0303 +arc: A7 H02E0501 +arc: C7 V02N0201 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CE2 V02N0601 +arc: CLK0 G_HPBX0100 +arc: D7 V01N0001 +arc: E1_H01E0101 Q2 +arc: E1_H02E0201 Q0 +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0203 Q7 +arc: V00B0100 Q7 +arc: V01S0100 Q4 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111010110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 + +.tile R22C16:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0501 V02N0501 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0103 H06W0103 +arc: V00B0100 H02W0701 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0701 V02N0701 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: W3_H06W0203 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0003 +arc: A2 H02E0501 +arc: A3 V02S0501 +arc: A6 V02N0101 +arc: A7 V02N0101 +arc: B3 V02S0101 +arc: B6 H01E0101 +arc: B7 N1_V01S0000 +arc: C3 H00R0100 +arc: C6 V01N0101 +arc: C7 V01N0101 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0201 +arc: D6 H02E0201 +arc: D7 H01W0000 +arc: E1_H02E0401 Q4 +arc: E3_H06E0103 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: M0 V00B0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F3 +arc: S3_V06S0203 F7 +arc: S3_V06S0303 F6 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1110110001001100 +word: SLICED.K1.INIT 1110110001001100 +word: SLICEB.K0.INIT 1010101000000000 +word: SLICEB.K1.INIT 0101010000010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R22C17:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 H02W0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 W1_H02E0501 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S3_V06S0303 H06E0303 +arc: V00T0000 V02N0401 +arc: W1_H02W0701 V02N0701 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0501 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: W3_H06W0003 E1_H02W0301 +arc: A0 W1_H02E0501 +arc: A1 V02N0501 +arc: A4 H02E0501 +arc: A7 V02S0101 +arc: B1 H02E0101 +arc: B4 N1_V01S0000 +arc: B5 H02E0301 +arc: C1 V02S0401 +arc: C4 H02E0401 +arc: C5 W1_H02E0401 +arc: C6 F4 +arc: CE1 V02S0201 +arc: CE2 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D4 H00L0100 +arc: D5 V00B0000 +arc: D6 H01W0000 +arc: D7 H00R0100 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0100 Q2 +arc: M2 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0701 Q5 +arc: S1_V02S0601 F6 +arc: V00B0000 F4 +arc: V01S0000 F7 +arc: V01S0100 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1010101000000000 +word: SLICEA.K1.INIT 0000111000000010 +word: SLICEC.K0.INIT 0000010100100111 +word: SLICEC.K1.INIT 1100000011001111 +word: SLICED.K0.INIT 0000000000001111 +word: SLICED.K1.INIT 0000000001010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R22C18:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 H02E0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 H02E0401 +arc: V00B0000 V02N0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 N1_V02S0401 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0701 V02N0701 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: CE0 H00R0000 +arc: CE1 H00R0100 +arc: CE2 S1_V02N0601 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0401 Q4 +arc: M0 V00T0000 +arc: M2 N1_V01N0001 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V02N0001 Q2 +arc: N1_V02N0201 Q0 +arc: N1_V02N0601 Q6 +arc: S1_V02S0001 Q0 +arc: V01S0100 Q4 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R22C19:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0401 H02E0401 +arc: V00B0000 V02N0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0701 S1_V02N0701 +arc: E1_H02E0201 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W3_H06W0203 S3_V06N0203 +arc: E3_H06E0103 W3_H06E0103 +arc: C2 E1_H01W0000 +arc: C3 E1_H02W0601 +arc: C5 E1_H02W0401 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D2 V00T0100 +arc: D3 V02N0001 +arc: D5 V02N0401 +arc: E1_H02E0701 F5 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0201 Q0 +arc: W1_H02W0201 F2 +arc: W1_H02W0301 F3 +arc: W3_H06W0003 F3 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 0000000000001111 +word: SLICEB.K1.INIT 0000000000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R22C20:PLC2 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0301 H06E0003 +arc: V00B0000 H02E0601 +arc: W1_H02W0501 S1_V02N0501 +arc: S3_V06S0203 W3_H06E0203 +arc: A3 H02W0501 +arc: A5 H02E0701 +arc: B7 F1 +arc: C1 E1_H01W0000 +arc: C3 F4 +arc: C4 V02N0201 +arc: C5 V02S0201 +arc: C7 V02S0201 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D1 H02E0001 +arc: D3 S1_V02N0201 +arc: D5 V02S0401 +arc: D6 V01N0001 +arc: D7 V02S0401 +arc: E1_H02E0101 Q3 +arc: E1_H02E0401 F6 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: M4 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK1 CLK0 +arc: V01S0100 F4 +word: SLICED.K0.INIT 0000000011111111 +word: SLICED.K1.INIT 0000000000000011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1010111100000101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0000111100001111 +word: SLICEC.K1.INIT 0000000000000101 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R22C21:PLC2 +arc: H00R0000 H02W0401 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0501 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0301 W3_H06E0003 +arc: W1_H02W0001 W3_H06E0003 +arc: B1 V00B0000 +arc: B5 S1_V02N0501 +arc: C1 V02N0601 +arc: C5 H02E0401 +arc: CE0 H00R0000 +arc: CE1 W1_H02E0101 +arc: CE2 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D1 N1_V01S0000 +arc: D5 V02N0401 +arc: E1_H02E0401 Q6 +arc: E3_H06E0303 Q6 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q1 +arc: M2 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0701 Q5 +arc: S3_V06S0303 Q6 +arc: V00T0000 Q2 +arc: V01S0000 Q6 +arc: W1_H02W0401 Q6 +arc: W3_H06W0303 Q6 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1100111100000011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1100000011001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 + +.tile R22C22:PLC2 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 S1_V02N0001 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0401 H01E0001 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0001 W3_H06E0003 +arc: CE1 H00R0000 +arc: CE3 V02S0601 +arc: CLK0 G_HPBX0100 +arc: M2 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0401 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R22C23:PLC2 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 + +.tile R22C24:PLC2 +arc: E1_H02E0401 V02N0401 +arc: N1_V02N0101 H02W0101 +arc: S3_V06S0303 H06E0303 + +.tile R22C25:PLC2 +arc: V00B0000 H02E0401 +arc: W1_H02W0101 W3_H06E0103 +arc: A2 V00B0000 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B6 N1_V01S0000 +arc: C0 N1_V01N0001 +arc: C1 N1_V01S0100 +arc: C2 H00L0000 +arc: C3 H02E0401 +arc: C6 H02E0401 +arc: C7 V00T0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D2 H00R0000 +arc: D3 V01S0100 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q6 +arc: H00R0100 Q7 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 Q6 +arc: N1_V02N0501 Q7 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +arc: V01S0100 Q2 +word: SLICED.K0.INIT 1111000011000000 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100000011000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R22C2:PLC2 +arc: E1_H02E0401 V01N0001 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0401 +arc: V01S0000 S3_V06N0103 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0001 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0303 Q6 +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R22C3:PLC2 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 E3_H06W0203 +arc: N1_V02N0001 S1_V02N0501 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 E3_H06W0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0601 +arc: CE2 H02W0101 +arc: CE3 H02W0101 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0303 Q6 +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: M4 H02E0401 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q4 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R22C4:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0203 V01N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 H02E0401 +arc: S1_V02S0301 H06W0003 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06S0103 +arc: A5 H02E0701 +arc: C4 H02E0401 +arc: C5 S1_V02N0201 +arc: CE1 H02W0101 +arc: CLK0 G_HPBX0100 +arc: D4 H02E0201 +arc: D5 W1_H02E0001 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0303 Q6 +arc: F4 F5C_SLICE +arc: M0 V00B0100 +arc: M2 H02E0601 +arc: M4 V00T0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F4 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000111111111111 +word: SLICEC.K1.INIT 0000010110101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R22C5:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0701 W1_H02E0701 +arc: V00B0000 H02E0601 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 E1_H02W0101 +arc: CE0 V02S0201 +arc: CE1 H00R0100 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0401 Q4 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: M0 V00T0100 +arc: M2 V00T0000 +arc: M4 V00B0000 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R22C6:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 V02N0101 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 S1_V02N0501 +arc: A4 N1_V01N0101 +arc: A5 V02S0301 +arc: B4 E1_H02W0301 +arc: B5 E1_H02W0301 +arc: B7 V02N0501 +arc: C4 E1_H02W0601 +arc: C5 S1_V02N0001 +arc: C6 E1_H02W0601 +arc: C7 H02E0401 +arc: CE0 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D4 E1_H02W0001 +arc: D5 V02S0401 +arc: D6 H02E0001 +arc: D7 V00B0000 +arc: E1_H02E0601 F4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0303 F5 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: M0 V00T0100 +arc: M2 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q2 +arc: V01S0100 F6 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000111111111111 +word: SLICED.K1.INIT 0011001100001111 +word: SLICEC.K0.INIT 1111111100110101 +word: SLICEC.K1.INIT 0000000011100100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R22C7:PLC2 +arc: H00R0000 V02S0401 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 H02W0401 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 E1_H01W0000 +arc: E3_H06E0003 W3_H06E0003 +arc: A2 V02S0701 +arc: A3 V02N0501 +arc: B2 E1_H02W0301 +arc: B3 H01W0100 +arc: C2 N1_V01S0100 +arc: C3 H00L0000 +arc: CE0 H00R0000 +arc: CE2 E1_H02W0101 +arc: CLK0 G_HPBX0100 +arc: D2 V02N0001 +arc: D3 V02S0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0101 F3 +arc: E3_H06E0203 Q4 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q6 +arc: M0 V00B0000 +arc: M4 E1_H01E0101 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0101010000000100 +word: SLICEB.K1.INIT 0001000100011011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R22C8:PLC2 +arc: H00R0000 H02W0601 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 H06E0303 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02S0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0501 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: A4 V02N0301 +arc: A5 V00B0000 +arc: B4 W1_H02E0301 +arc: B5 H00L0000 +arc: C4 E1_H01E0101 +arc: C5 F4 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D4 E1_H01W0100 +arc: D5 V02N0401 +arc: E1_H01E0101 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0501 F5 +arc: E3_H06E0303 Q6 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: M6 W1_H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q6 +arc: V01S0000 Q0 +arc: W1_H02W0001 Q0 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0011111101011111 +word: SLICEC.K1.INIT 1010000000110011 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R22C9:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S3_V06N0203 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H06W0203 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02E0201 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0301 W3_H06E0003 +arc: W3_H06W0303 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0303 +arc: A0 H02W0701 +arc: A1 V02N0701 +arc: A3 V00B0000 +arc: B2 H00R0000 +arc: B3 E1_H01W0100 +arc: CLK0 G_HPBX0100 +arc: D0 V02N0201 +arc: D1 V02S0201 +arc: D2 S1_V02N0001 +arc: D3 H00R0000 +arc: E1_H01E0001 F0 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: H01W0100 Q4 +arc: M2 V00T0000 +arc: M4 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V02N0201 F2 +arc: S1_V02S0001 F0 +arc: S1_V02S0301 F1 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q6 +arc: V01S0000 Q4 +arc: V01S0100 F1 +arc: W3_H06W0203 Q4 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000001010101 +word: SLICEA.K1.INIT 0000000001010101 +word: SLICEB.K0.INIT 1100110011111111 +word: SLICEB.K1.INIT 0011001101010101 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R23C10:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 H02E0601 +arc: H00R0100 H02E0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0000 H02W0601 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0001 +arc: V00T0100 V02S0701 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0501 E1_H01W0100 +arc: W3_H06W0103 S3_V06N0103 +arc: E3_H06E0003 W3_H06E0303 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: A2 V02S0501 +arc: A3 V02S0501 +arc: A4 H02W0701 +arc: A5 V00T0000 +arc: A6 N1_V01N0101 +arc: B0 V02S0301 +arc: B1 S1_V02N0301 +arc: B2 V02S0301 +arc: B3 S1_V02N0301 +arc: B4 H02W0101 +arc: B5 N1_V02S0701 +arc: B7 E1_H02W0101 +arc: C0 S1_V02N0601 +arc: C1 V02S0601 +arc: C2 S1_V02N0601 +arc: C3 V02S0601 +arc: C4 W1_H02E0601 +arc: C5 V02S0201 +arc: C7 F6 +arc: CE3 H00R0000 +arc: CLK1 G_HPBX0100 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V02N0601 +arc: D5 H00R0100 +arc: D6 V02N0401 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H02E0101 F1 +arc: E1_H02E0301 F3 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F6 +arc: LSR0 V00T0100 +arc: LSR1 E1_H02W0301 +arc: MUXCLK3 CLK1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V02N0401 F6 +arc: N1_V02N0501 Q7 +arc: V01S0000 F7 +arc: W1_H02W0001 F2 +arc: W1_H02W0401 F6 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1010101000000000 +word: SLICED.K1.INIT 0011111100110000 +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.A1MUX 1 + +.tile R23C11:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 N1_V02S0201 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H06W0303 +arc: V00B0000 H02W0601 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0701 E1_H02W0601 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: W3_H06W0003 V06N0003 +arc: A1 H02E0701 +arc: A2 H02E0701 +arc: A3 V02S0701 +arc: B0 H02E0101 +arc: B1 V00T0000 +arc: B2 H01W0100 +arc: B7 H02E0301 +arc: C0 V02S0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 V02N0401 +arc: C7 H02W0401 +arc: CLK0 G_HPBX0100 +arc: D0 E1_H02W0201 +arc: D1 H02E0001 +arc: D2 H02E0201 +arc: D3 V02N0001 +arc: D7 E1_H01W0100 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q3 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0103 F1 +arc: S3_V06S0203 Q7 +arc: V00T0000 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0601 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1111110000001100 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 1111010110100000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 + +.tile R23C12:PLC2 +arc: E1_H02E0201 V02N0201 +arc: H00R0100 V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0101 +arc: V00T0000 H02E0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0101 W3_H06E0103 +arc: W3_H06W0303 S3_V06N0303 +arc: E3_H06E0303 W3_H06E0203 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 V00B0000 +arc: A5 V00T0000 +arc: A7 E1_H02W0501 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 H02E0101 +arc: B5 N1_V02S0501 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C4 E1_H02W0601 +arc: C5 W1_H02E0401 +arc: C7 V02N0001 +arc: CLK1 G_HPBX0100 +arc: D0 N1_V01S0000 +arc: D1 V02S0201 +arc: D2 V02S0201 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F3 +arc: LSR1 V00B0100 +arc: MUXCLK3 CLK1 +arc: N1_V02N0501 Q7 +arc: S3_V06S0203 Q7 +arc: W1_H02W0201 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111101001010000 +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 + +.tile R23C13:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 V02S0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 N1_V01S0000 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A3 V01N0101 +arc: A7 V02N0301 +arc: B1 V02N0101 +arc: B5 V02N0701 +arc: B7 V02N0701 +arc: C1 V02N0401 +arc: C3 V02N0601 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0100 +arc: D1 V02N0001 +arc: D3 V02N0201 +arc: D5 E1_H01W0100 +arc: D7 H02W0001 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q3 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: S1_V02S0101 Q1 +arc: S3_V06S0003 Q3 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q5 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111110000110000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1110111000100010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.C1MUX 1 + +.tile R23C14:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0203 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: E3_H06E0303 W3_H06E0303 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 V02N0701 +arc: A1 V02N0701 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: A4 H02E0501 +arc: A5 V00B0000 +arc: B0 E1_H02W0301 +arc: B1 V02N0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 H02W0101 +arc: B5 H02E0101 +arc: B7 F3 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 S1_V02N0001 +arc: C5 S1_V02N0201 +arc: C7 V02N0001 +arc: CLK1 G_HPBX0100 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q7 +arc: H01W0100 F1 +arc: LSR1 V00B0100 +arc: MUXCLK3 CLK1 +arc: S3_V06S0203 Q7 +arc: W1_H02W0001 F2 +arc: W1_H02W0201 F0 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R23C15:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0303 V01N0101 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 H02E0301 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02W0601 +arc: V00T0000 H02E0001 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 S3_V06N0203 +arc: S3_V06S0203 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0103 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A4 S1_V02N0101 +arc: A5 N1_V02S0101 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0301 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: B4 H00L0000 +arc: B5 N1_V02S0501 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 H02E0601 +arc: C5 E1_H02W0601 +arc: CE3 H00L0100 +arc: CLK1 G_HPBX0100 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 H02W0001 +arc: D5 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H02E0201 F2 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: LSR0 E1_H02W0301 +arc: LSR1 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK3 CLK1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R23C16:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0000 H02W0001 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S3_V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A2 V01N0101 +arc: A3 V02N0701 +arc: A4 S1_V02N0101 +arc: A5 V00B0000 +arc: B0 V02N0101 +arc: B1 V02N0301 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B4 H00L0000 +arc: B5 V00B0100 +arc: B7 F1 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 H02W0401 +arc: C5 H02W0601 +arc: C7 H01E0001 +arc: CLK1 G_HPBX0100 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 E1_H02W0001 +arc: D5 H02W0201 +arc: D7 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q7 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: LSR1 V00T0100 +arc: MUXCLK3 CLK1 +arc: S3_V06S0203 Q7 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1100110011110000 +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 + +.tile R23C17:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 W1_H02E0601 +arc: H00L0000 V02N0001 +arc: H00L0100 H02E0301 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 H02W0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0003 S3_V06N0003 +arc: A3 H01E0001 +arc: B5 W1_H02E0301 +arc: C3 V02N0401 +arc: C5 V02N0201 +arc: CE0 H00L0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D3 W1_H02E0201 +arc: D5 H00L0100 +arc: E1_H01E0001 Q5 +arc: E1_H02E0101 Q3 +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0401 Q6 +arc: S3_V06S0003 Q3 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1010111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R23C18:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0100 V02N0301 +arc: H00R0000 H02E0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0201 V01N0001 +arc: S3_V06S0003 H01E0001 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0501 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S1_V02N0401 +arc: H01W0100 W3_H06E0303 +arc: CE0 H00L0100 +arc: CE1 N1_V02S0201 +arc: CE2 H00R0100 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q4 +arc: E1_H02E0201 Q2 +arc: E3_H06E0203 Q4 +arc: H01W0000 Q0 +arc: M0 H01E0001 +arc: M2 N1_V01N0001 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: V01S0100 Q4 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R23C19:PLC2 +arc: E1_H02E0601 V01N0001 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 H02E0401 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0701 E1_H01W0100 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C2 V02S0401 +arc: C3 N1_V01N0001 +arc: C6 H01E0001 +arc: C7 V02S0201 +arc: CE0 H00R0000 +arc: CE2 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D2 H01E0101 +arc: D3 H02E0001 +arc: D6 H01W0000 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: M0 V00B0000 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q4 +arc: S3_V06S0003 F3 +arc: S3_V06S0203 F7 +arc: V01S0100 F6 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111110100100000 +word: SLICEB.K1.INIT 1111011110000000 +word: SLICED.K0.INIT 1111001011010000 +word: SLICED.K1.INIT 1111100001110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R23C20:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0701 N1_V02S0701 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0203 H01E0001 +arc: V00B0000 V02N0001 +arc: V00B0100 W1_H02E0501 +arc: V01S0000 S3_V06N0103 +arc: E1_H02E0601 W3_H06E0303 +arc: W3_H06W0203 S3_V06N0203 +arc: A3 H02W0701 +arc: C2 N1_V01S0100 +arc: C3 N1_V02S0601 +arc: CLK0 G_HPBX0100 +arc: D2 H02W0001 +arc: E1_H02E0401 Q6 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0100 F3 +arc: M0 H02E0601 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V02N0201 Q0 +arc: W1_H02W0301 F3 +arc: W3_H06W0003 F3 +arc: W3_H06W0103 F2 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000001111 +word: SLICEB.K1.INIT 0000010100000101 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R23C21:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 E1_H01W0100 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0401 V01N0001 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 H02W0601 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: E1_H02E0601 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: W1_H02W0401 W3_H06E0203 +arc: A5 H02E0701 +arc: B1 H02E0301 +arc: C1 V02N0401 +arc: C2 S1_V02N0401 +arc: C3 S1_V02N0401 +arc: C5 V02N0201 +arc: CLK0 G_HPBX0100 +arc: D0 H00R0000 +arc: D1 H02E0201 +arc: D2 V01S0100 +arc: D3 E1_H02W0201 +arc: D4 V02N0601 +arc: D5 V02S0601 +arc: E1_H02E0001 F0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 Q6 +arc: M0 H02W0601 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK3 CLK0 +arc: S1_V02S0201 F0 +arc: S3_V06S0003 F3 +arc: S3_V06S0103 F2 +arc: V01S0100 F4 +arc: W3_H06W0003 F3 +arc: W3_H06W0103 F2 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000001111 +word: SLICEB.K1.INIT 0000000000001111 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICEA.K1.INIT 0000000000000011 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICEC.K1.INIT 0000000000000101 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R23C22:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 W1_H02E0601 +arc: H00R0100 H02W0701 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H02W0501 +arc: V00B0000 H02W0401 +arc: V00B0100 H02E0501 +arc: V00T0100 V02N0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0501 W3_H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 +arc: B7 H02W0101 +arc: C3 H02E0401 +arc: C6 W1_H02E0401 +arc: C7 E1_H01E0101 +arc: CE0 W1_H02E0101 +arc: CLK0 G_HPBX0100 +arc: D3 V02S0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F3 +arc: E1_H02E0401 F6 +arc: F3 F3_SLICE +arc: F6 F5D_SLICE +arc: LSR0 V00B0000 +arc: M0 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000111100001111 +word: SLICED.K1.INIT 0000000000000011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R23C23:PLC2 +arc: E1_H02E0401 V01N0001 +arc: H00L0000 V02N0001 +arc: H00L0100 V02S0301 +arc: H00R0000 V02S0401 +arc: S1_V02S0601 V01N0001 +arc: V00B0000 H02E0401 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0701 N1_V02S0701 +arc: A5 S1_V02N0101 +arc: B7 H02E0101 +arc: C3 H02E0601 +arc: C5 W1_H02E0601 +arc: C7 W1_H02E0601 +arc: CE0 H00L0000 +arc: CE2 H00L0100 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D3 H00R0000 +arc: D5 W1_H02E0001 +arc: D7 V00B0000 +arc: E1_H02E0501 Q5 +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: M0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0101 F3 +arc: V00B0100 Q7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1100000011001111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1010000010101111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R23C24:PLC2 +arc: H00R0000 H02E0401 +arc: N1_V02N0401 S1_V02N0101 +arc: V00B0100 H02E0501 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0100 +arc: M2 V00B0100 +arc: MUXCLK1 CLK0 +arc: V01S0000 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R23C25:PLC2 +arc: N1_V02N0601 N1_V01S0000 + +.tile R23C2:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 E1_H01W0100 +arc: N1_V02N0401 N1_V01S0000 +arc: V00B0100 V02N0101 +arc: V00T0100 E1_H02W0101 +arc: CE0 H02E0101 +arc: CE1 H02E0101 +arc: CE2 H02E0101 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0601 Q4 +arc: E3_H06E0303 Q6 +arc: H01W0000 Q0 +arc: M0 V00T0100 +arc: M2 H02E0601 +arc: M4 V00T0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: S1_V02S0001 Q0 +arc: S3_V06S0103 Q2 +arc: V00T0000 Q2 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R23C3:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 V02S0201 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0100 H02E0501 +arc: CE0 V02S0201 +arc: CE1 V02S0201 +arc: CE2 H00L0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: H01W0100 Q6 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: M4 H02E0401 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q4 +arc: V00T0000 Q2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R23C4:PLC2 +arc: E1_H02E0501 N1_V01S0100 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E3_H06W0303 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 V06S0103 +arc: A4 V02S0301 +arc: A5 H02E0701 +arc: B4 V01S0000 +arc: C4 H02E0401 +arc: C5 F4 +arc: CLK0 G_HPBX0100 +arc: D4 E1_H02W0201 +arc: D5 H01W0000 +arc: E1_H02E0601 Q6 +arc: E3_H06E0303 Q6 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q2 +arc: M0 E1_H02W0601 +arc: M2 V00T0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F5 +arc: V01S0000 Q0 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111101100000000 +word: SLICEC.K1.INIT 1010000011110101 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R23C5:PLC2 +arc: H00R0000 V02N0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0601 H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0501 +arc: CE0 H00R0000 +arc: CE1 H00R0100 +arc: CE2 E1_H02W0101 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0201 Q2 +arc: E3_H06E0103 Q2 +arc: M0 V00B0000 +arc: M2 N1_V01N0001 +arc: M4 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: S3_V06S0303 Q6 +arc: V00T0000 Q0 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R23C6:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 V01N0101 +arc: H00R0000 H02W0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0501 S1_V02N0501 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 V02N0201 +arc: V00T0000 H02W0201 +arc: V00T0100 H02W0301 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0601 S3_V06N0303 +arc: A2 V02S0701 +arc: B2 H01W0100 +arc: B3 H00R0000 +arc: C2 N1_V01S0100 +arc: C3 H02W0401 +arc: CE0 H00R0100 +arc: CE3 V02S0601 +arc: CLK0 G_HPBX0100 +arc: D2 V02S0001 +arc: D3 S1_V02N0201 +arc: E1_H02E0401 Q4 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0100 Q3 +arc: M0 V00T0000 +arc: M4 V00B0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0601 Q6 +arc: V01S0100 Q0 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111000010110000 +word: SLICEB.K1.INIT 1111001111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R23C7:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 E1_H02W0501 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0601 +arc: A1 H02E0701 +arc: A7 V02S0301 +arc: C0 H02E0601 +arc: C1 H00L0000 +arc: C6 H02E0401 +arc: C7 E1_H02W0401 +arc: CE1 V02S0201 +arc: CLK0 G_HPBX0100 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0001 +arc: D6 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F0 +arc: F0 F5A_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: LSR0 V00B0100 +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: M6 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: W1_H02W0201 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000111111111111 +word: SLICED.K1.INIT 0101010100001111 +word: SLICEA.K0.INIT 0000111111111111 +word: SLICEA.K1.INIT 0101000001011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R23C8:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0601 E3_H06W0303 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0401 S3_V06N0203 +arc: V00B0000 V02N0201 +arc: V00T0100 H02E0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0501 E1_H02W0501 +arc: H01W0100 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: A4 V02S0301 +arc: B4 N1_V01S0000 +arc: B5 W1_H02E0101 +arc: C4 H01E0001 +arc: C5 H02E0601 +arc: CE0 H00R0100 +arc: CE1 H02E0101 +arc: CLK0 G_HPBX0100 +arc: D4 H01W0000 +arc: D5 V02N0401 +arc: E1_H01E0101 F4 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q5 +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0601 Q6 +arc: S3_V06S0003 Q0 +arc: V00T0000 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1110000011110000 +word: SLICEC.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R23C9:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 V01N0001 +arc: H00R0000 V02N0401 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0303 H06E0303 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 S1_V02N0601 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0003 W3_H06E0003 +arc: A0 V02S0701 +arc: A1 W1_H02E0701 +arc: A7 W1_H02E0701 +arc: B1 V00T0000 +arc: B6 V02S0701 +arc: B7 V02N0501 +arc: C0 E1_H01W0000 +arc: C1 N1_V02S0601 +arc: C6 E1_H02W0401 +arc: C7 E1_H01E0101 +arc: CE2 V02S0601 +arc: CLK0 G_HPBX0100 +arc: D0 H02W0201 +arc: D1 H00R0000 +arc: D6 H02W0001 +arc: D7 V02N0401 +arc: E1_H01E0101 Q6 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0103 F1 +arc: S3_V06S0203 Q4 +arc: V00B0000 Q6 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +arc: W1_H02W0001 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 0000011101110111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 + +.tile R24C10:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0701 E3_H06W0203 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 S3_V06N0303 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 E3_H06W0203 +arc: N1_V02N0501 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: A5 E1_H02W0501 +arc: A7 E1_H02W0501 +arc: B3 H02E0101 +arc: B7 H02E0301 +arc: C3 E1_H01W0000 +arc: C5 H01E0001 +arc: CE0 H02W0101 +arc: CLK0 G_HPBX0100 +arc: D3 E1_H02W0001 +arc: D5 H02W0001 +arc: D7 E1_H01W0100 +arc: E1_H02E0001 Q0 +arc: E1_H02E0501 Q5 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 Q5 +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0301 Q3 +arc: S3_V06S0003 Q3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1101110110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.C1MUX 1 + +.tile R24C11:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02E0501 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0103 N1_V02S0201 +arc: V00B0000 W1_H02E0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: N1_V02N0701 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0501 W3_H06E0303 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 E1_H02W0701 +arc: A5 V02S0301 +arc: A7 H02W0501 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B4 N1_V01S0000 +arc: B5 H02E0101 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 V00T0100 +arc: C5 H02E0401 +arc: C7 E1_H01E0101 +arc: CLK1 G_HPBX0100 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 S1_V02N0601 +arc: D5 H00L0100 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F1 +arc: LSR1 E1_H02W0301 +arc: MUXCLK3 CLK1 +arc: S1_V02S0501 Q7 +arc: W1_H02W0001 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111101001010000 +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 + +.tile R24C12:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0601 V02S0601 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0201 S3_V06N0103 +arc: S3_V06S0003 N1_V02S0001 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H02W0501 +arc: S3_V06S0203 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0103 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 H02W0501 +arc: A3 V02N0701 +arc: A4 H02W0701 +arc: A5 V00B0000 +arc: B0 V00T0000 +arc: B1 H00R0100 +arc: B2 H00R0100 +arc: B3 H00R0000 +arc: B4 H02E0301 +arc: B5 V00B0100 +arc: B7 N1_V02S0701 +arc: C0 S1_V02N0401 +arc: C1 N1_V02S0601 +arc: C2 S1_V02N0401 +arc: C3 N1_V02S0601 +arc: C4 E1_H02W0601 +arc: C5 V00T0100 +arc: C7 V02N0001 +arc: CLK1 G_HPBX0100 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V02S0601 +arc: D5 H02E0001 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: LSR1 H02W0301 +arc: MUXCLK3 CLK1 +arc: S1_V02S0101 F1 +arc: S1_V02S0301 F3 +arc: V01S0100 Q7 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111001111000000 +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 + +.tile R24C13:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 N1_V01S0100 +arc: E3_H06E0103 S3_V06N0103 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0103 E1_H02W0101 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 N1_V01S0100 +arc: A5 V00T0100 +arc: B0 V02N0101 +arc: B1 V02N0301 +arc: B2 V02N0101 +arc: B3 V02N0301 +arc: B4 H00R0000 +arc: B5 N1_V02S0701 +arc: B7 F1 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 H02W0601 +arc: C5 W1_H02E0601 +arc: C7 S1_V02N0001 +arc: CLK1 G_HPBX0100 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 V00B0000 +arc: D5 N1_V02S0601 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F2 +arc: E3_H06E0203 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK3 CLK1 +arc: N1_V01N0101 F3 +arc: N1_V02N0001 F0 +arc: S1_V02S0501 Q7 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R24C14:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0103 N3_V06S0103 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H02W0701 +arc: E1_H02E0301 W3_H06E0003 +arc: S1_V02S0601 W3_H06E0303 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A4 H02E0701 +arc: A5 N1_V02S0101 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0101 +arc: B2 E1_H02W0301 +arc: B3 E1_H02W0101 +arc: B4 V00B0100 +arc: B5 V02S0701 +arc: B7 S1_V02N0701 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V00T0000 +arc: C5 H02E0601 +arc: C7 H01E0001 +arc: CLK1 G_HPBX0100 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 V02S0401 +arc: D5 V02N0601 +arc: D7 F2 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F1 +arc: LSR1 H02E0301 +arc: MUXCLK3 CLK1 +arc: N1_V01N0001 Q7 +arc: S3_V06S0203 Q7 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111001111000000 +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 + +.tile R24C15:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S3_V06N0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0601 +arc: V00T0100 V02N0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0601 S3_V06N0303 +arc: E1_H02E0401 W3_H06E0203 +arc: H01W0100 W3_H06E0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: A1 V02S0701 +arc: A2 E1_H02W0501 +arc: A3 V02S0501 +arc: A7 S1_V02N0101 +arc: B0 H02E0101 +arc: B1 V00B0000 +arc: B2 H02E0301 +arc: B5 V01S0000 +arc: B7 S1_V02N0501 +arc: C0 V02S0401 +arc: C1 W1_H02E0401 +arc: C2 V02N0401 +arc: C3 E1_H02W0401 +arc: C5 S1_V02N0001 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D0 V02N0001 +arc: D1 V02S0201 +arc: D2 S1_V02N0201 +arc: D3 F2 +arc: D5 V02N0601 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 F0 +arc: E1_H02E0501 F7 +arc: E1_H02E0701 F5 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR0 V00T0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F5 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 F1 +arc: W1_H02W0101 Q3 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F7 +arc: W3_H06W0203 F7 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 1010000010101111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1010101000110011 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1100110000001111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 1111011110000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R24C16:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 V02S0001 +arc: H00L0100 H02W0301 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0201 H01E0001 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 N1_V01S0000 +arc: E3_H06E0003 W3_H06E0003 +arc: A0 F7 +arc: A1 F7 +arc: A2 F7 +arc: A3 F7 +arc: A4 E1_H02W0501 +arc: A5 V02S0101 +arc: B0 S1_V02N0301 +arc: B1 V00B0000 +arc: B2 S1_V02N0301 +arc: B3 H00R0000 +arc: B4 H00L0000 +arc: B5 V00B0100 +arc: B7 S1_V02N0701 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V00T0100 +arc: C5 V00T0000 +arc: C7 W1_H02E0601 +arc: CLK1 G_HPBX0100 +arc: D0 H01E0101 +arc: D1 H01E0101 +arc: D2 H01E0101 +arc: D3 H01E0101 +arc: D4 E1_H02W0001 +arc: D5 H00L0100 +arc: D7 V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 F3 +arc: E1_H02E0201 F0 +arc: E1_H02E0301 F1 +arc: E1_H02E0501 F7 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: LSR1 E1_H02W0301 +arc: N1_V01N0101 F7 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F7 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F7 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F7 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1100110000001111 +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 + +.tile R24C17:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 H01E0001 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0000 V02S0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 H02E0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0401 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0303 N1_V02S0601 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: A0 H02E0501 +arc: A1 H02E0501 +arc: A2 H02E0501 +arc: A3 H02E0501 +arc: A4 H02W0501 +arc: A5 V02S0101 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B4 H00L0000 +arc: B5 V02S0701 +arc: B7 H02E0101 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V00T0000 +arc: C5 N1_V02S0201 +arc: C7 V00T0100 +arc: CLK1 G_HPBX0100 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H02W0001 +arc: D5 H00L0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 F1 +arc: E1_H02E0501 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: LSR1 E1_H02W0301 +arc: MUXCLK3 CLK1 +arc: S3_V06S0203 Q7 +arc: V00T0100 F3 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK + +.tile R24C18:PLC2 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 S3_V06N0303 +arc: H00L0100 H02E0301 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 H06E0003 +arc: V00B0100 H02E0501 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 S1_V02N0501 +arc: E3_H06E0203 W3_H06E0103 +arc: A1 E1_H02W0701 +arc: A5 E1_H02W0701 +arc: B7 W1_H02E0301 +arc: C1 H02E0601 +arc: C5 H01E0001 +arc: C7 H02E0401 +arc: CE1 V02S0201 +arc: CLK0 G_HPBX0100 +arc: D1 H01E0101 +arc: D5 W1_H02E0201 +arc: D7 H00L0100 +arc: E1_H01E0001 Q5 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q2 +arc: E1_H02E0701 Q7 +arc: E3_H06E0303 Q5 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q7 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111101001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R24C19:PLC2 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 H01E0001 +arc: H00R0000 H02E0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0103 N1_V01S0100 +arc: V00B0100 H02E0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0301 S1_V02N0301 +arc: N1_V02N0101 W3_H06E0103 +arc: A2 H02E0501 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: A5 V02S0101 +arc: B2 V02S0101 +arc: B3 E1_H01W0100 +arc: B4 V02S0701 +arc: B5 V02S0701 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 V02S0201 +arc: C5 H02W0401 +arc: CE0 H00R0000 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D2 S1_V02N0201 +arc: D3 V02S0201 +arc: D4 E1_H02W0201 +arc: D5 H02E0201 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: S3_V06S0203 F4 +arc: V00B0000 Q6 +arc: V00T0000 Q0 +arc: V01S0000 F2 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1011111110000000 +word: SLICEC.K1.INIT 1111100001110000 +word: SLICEB.K0.INIT 1011101010001010 +word: SLICEB.K1.INIT 1010110011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R24C20:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N3_V06S0303 +arc: H00L0000 H02W0001 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0501 S1_V02N0501 +arc: S1_V02S0301 E1_H01W0100 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0101 +arc: W1_H02W0701 S1_V02N0701 +arc: N1_V02N0101 W3_H06E0103 +arc: A7 H00R0000 +arc: C7 H02W0601 +arc: CE0 H00L0000 +arc: CE1 H00L0000 +arc: CE2 V02N0601 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D7 V02S0601 +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q7 +arc: H01W0100 Q0 +arc: M0 V00B0000 +arc: M2 H02E0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0201 Q2 +arc: W1_H02W0401 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1010000010101111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 + +.tile R24C21:PLC2 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 H02E0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0601 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 S1_V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: S1_V02S0101 W3_H06E0103 +arc: A5 N1_V01S0100 +arc: B5 V02N0501 +arc: CE0 V02N0201 +arc: CE1 V02N0201 +arc: CE2 H00L0000 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D5 V02N0601 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q6 +arc: F5 F5_SLICE +arc: H01W0100 Q2 +arc: M0 V00T0100 +arc: M2 V00B0100 +arc: M6 W1_H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V02N0001 Q0 +arc: W1_H02W0201 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1101110100010001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R24C22:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0401 V01N0001 +arc: H00L0000 V02N0001 +arc: H00L0100 V02N0301 +arc: H00R0000 H02W0601 +arc: N1_V02N0701 H02W0701 +arc: V00B0000 H02W0401 +arc: S3_V06S0003 W3_H06E0003 +arc: A0 V02S0501 +arc: A1 E1_H01E0001 +arc: B3 E1_H02W0301 +arc: B5 V02S0501 +arc: B6 V00B0100 +arc: B7 V01S0000 +arc: C0 N1_V02S0401 +arc: C1 H02W0601 +arc: C3 E1_H01W0000 +arc: C5 S1_V02N0001 +arc: C6 H02W0601 +arc: C7 H02W0601 +arc: CE0 H00L0100 +arc: CE1 H00L0000 +arc: CE2 H00L0000 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H01E0101 +arc: D3 H00R0000 +arc: D5 V02S0401 +arc: D6 E1_H01W0100 +arc: D7 V00B0000 +arc: E1_H01E0001 Q3 +arc: E1_H02E0601 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0001 Q0 +arc: V00B0100 Q7 +arc: V00T0100 Q1 +arc: V01S0000 Q5 +word: SLICEA.K0.INIT 1111101001010000 +word: SLICEA.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 + +.tile R24C23:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02E0001 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 W3_H06E0203 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CE2 V02S0601 +arc: CE3 V02S0601 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0201 Q0 +arc: H01W0000 Q2 +arc: H01W0100 Q4 +arc: M0 V00B0100 +arc: M2 V00T0100 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: W1_H02W0401 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R24C24:PLC2 +arc: H00R0000 W1_H02E0401 +arc: W1_H02W0301 S1_V02N0301 +arc: S3_V06S0203 W3_H06E0203 +arc: A2 E1_H01E0001 +arc: A3 H02E0501 +arc: C2 H02E0601 +arc: C3 W1_H02E0601 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D2 H02E0201 +arc: D3 N1_V01S0000 +arc: E1_H01E0001 Q3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: MUXCLK1 CLK0 +arc: S1_V02S0201 Q2 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111010110100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R24C2:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 E3_H06W0103 +arc: N1_V02N0101 S1_V02N0101 +arc: S1_V02S0201 S3_V06N0103 +arc: CE0 V02N0201 +arc: CE1 H02E0101 +arc: CE2 H02E0101 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: S1_V02S0001 Q2 +arc: S1_V02S0401 Q4 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q6 +arc: V00T0000 Q2 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R24C3:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 E3_H06W0303 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0301 S3_V06N0003 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: W1_H02W0401 V02S0401 +arc: A3 S1_V02N0701 +arc: A7 H02W0701 +arc: B5 F3 +arc: C3 V02N0601 +arc: C4 V02S0201 +arc: C5 V00T0100 +arc: C7 V02N0001 +arc: CE1 H02E0101 +arc: CE2 H00R0100 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0100 +arc: D3 V02N0001 +arc: D5 H02E0201 +arc: D7 V02N0401 +arc: E1_H01E0101 F3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 Q4 +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0501 F7 +arc: S1_V02S0501 F7 +arc: V00T0100 Q3 +arc: V01S0000 Q7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1010101011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R24C4:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: H00R0000 H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 H02E0001 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: A1 V02N0501 +arc: B7 F1 +arc: C1 V02N0401 +arc: C7 V00T0100 +arc: CE0 H02W0101 +arc: CE1 H00R0000 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0100 +arc: D1 S1_V02N0001 +arc: D6 V02S0601 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 Q6 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F1 F1_SLICE +arc: F6 F5D_SLICE +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0301 F1 +arc: N1_V02N0401 Q4 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: V00T0100 Q1 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111101001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R24C5:PLC2 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 H01E0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 V06N0203 +arc: CE0 V02N0201 +arc: CE1 V02N0201 +arc: CE2 V02N0601 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0101 Q2 +arc: E1_H02E0401 Q4 +arc: E1_H02E0601 Q6 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: M0 H02W0601 +arc: M2 V00T0100 +arc: M4 E1_H01E0101 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R24C6:PLC2 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 S3_V06N0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0100 V02S0501 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E1_H02W0701 +arc: CE0 E1_H02W0101 +arc: CE2 V02N0601 +arc: CE3 H02W0101 +arc: CLK0 G_HPBX0100 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0401 Q4 +arc: S3_V06S0303 Q6 +arc: V00T0000 Q0 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R24C7:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 W1_H02E0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0401 S3_V06N0203 +arc: CE1 S1_V02N0201 +arc: CLK0 G_HPBX0100 +arc: LSR1 V00B0000 +arc: M2 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: S3_V06S0103 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R24C8:PLC2 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0000 V02N0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0501 H02E0501 +arc: V00B0000 V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0103 E3_H06W0103 +arc: CE0 H00R0100 +arc: CE1 H00R0000 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0303 Q6 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0201 Q2 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R24C9:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 V02N0001 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02W0301 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S3_V06N0203 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 E1_H02W0701 +arc: A5 V02S0101 +arc: B0 V00T0000 +arc: B1 H00R0100 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 H00R0000 +arc: B5 H02W0101 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0601 +arc: C4 H02E0601 +arc: C5 N1_V02S0001 +arc: C6 V00B0100 +arc: CLK1 G_HPBX0100 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 V02S0601 +arc: D5 H00L0100 +arc: D6 H02W0001 +arc: E1_H01E0001 F0 +arc: E1_H02E0001 F2 +arc: E1_H02E0101 F3 +arc: E1_H02E0301 F1 +arc: E1_H02E0601 F6 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR0 V00B0000 +arc: LSR1 H02W0501 +arc: MUXCLK3 CLK1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q7 +arc: S3_V06S0303 F6 +arc: V00B0100 Q7 +arc: V01S0000 Q7 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R26C10:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 S3_V06N0303 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0701 +arc: W1_H02W0201 E1_H02W0201 +arc: E3_H06E0303 W3_H06E0203 +arc: A0 V02S0701 +arc: A2 V02S0501 +arc: A6 H02W0501 +arc: B1 W1_H02E0301 +arc: B3 W1_H02E0301 +arc: B6 H02E0101 +arc: B7 W1_H02E0301 +arc: C0 V02S0601 +arc: C1 N1_V01N0001 +arc: C2 V02N0601 +arc: C3 H00L0000 +arc: C7 F6 +arc: CE0 W1_H02E0101 +arc: CE1 W1_H02E0101 +arc: CE3 W1_H02E0101 +arc: CLK0 G_HPBX0100 +arc: D0 S1_V02N0001 +arc: D1 F0 +arc: D2 V02S0001 +arc: D3 F2 +arc: D6 V02S0401 +arc: D7 V00B0000 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 F0 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0401 Q4 +arc: S3_V06S0003 F3 +arc: V00B0000 Q6 +arc: W3_H06W0103 F2 +arc: W3_H06W0303 F6 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 0000110000111111 +word: SLICED.K0.INIT 1101110110001000 +word: SLICED.K1.INIT 0000001111001111 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 0000110000111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.A1MUX 1 + +.tile R26C11:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0000 V02N0001 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N1_V02S0501 +arc: V00T0000 V02S0601 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0103 S3_V06N0103 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0203 +arc: A3 E1_H02W0701 +arc: A4 E1_H02W0501 +arc: A5 V00B0000 +arc: B2 F3 +arc: C2 H00L0100 +arc: C3 H02E0601 +arc: C4 V02S0201 +arc: C5 F4 +arc: CE1 H00L0000 +arc: CE2 H00L0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D2 E1_H02W0201 +arc: D3 N1_V01S0000 +arc: D4 V02N0601 +arc: D5 E1_H02W0201 +arc: E1_H02E0001 F2 +arc: E3_H06E0303 F5 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q3 +arc: M0 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0203 F4 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q4 +arc: V00T0100 F3 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 0101010100001111 +word: SLICEB.K0.INIT 0000111100110011 +word: SLICEB.K1.INIT 1111010110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R26C12:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0601 V06N0303 +arc: E3_H06E0203 W1_H02E0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0601 N1_V02S0301 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V06N0303 +arc: CE0 H00R0100 +arc: CLK0 G_HPBX0100 +arc: LSR1 H02E0301 +arc: M0 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N3_V06N0003 Q0 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R26C13:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V06N0303 +arc: H00R0000 V02N0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02E0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 H02W0501 +arc: A3 H02W0701 +arc: A4 N1_V02S0301 +arc: A5 V02S0101 +arc: B0 V02N0101 +arc: B1 V02N0301 +arc: B2 V02N0101 +arc: B3 V02N0301 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 H02W0401 +arc: C5 N1_V02S0201 +arc: CE3 V02N0601 +arc: CLK1 G_HPBX0100 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 V00B0000 +arc: D5 W1_H02E0201 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0100 F0 +arc: LSR1 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK3 CLK1 +arc: N1_V01N0001 F1 +arc: N1_V02N0201 F2 +arc: N1_V02N0401 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R26C14:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0601 N1_V02S0601 +arc: H00L0100 H02W0101 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 H02W0401 +arc: V00T0000 H02E0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 N1_V02S0701 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: S1_V02S0101 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: W3_H06W0003 S3_V06N0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: A0 N1_V02S0701 +arc: A1 N1_V02S0701 +arc: A2 N1_V02S0701 +arc: A3 N1_V02S0701 +arc: A4 H02E0501 +arc: A5 V00B0000 +arc: A7 E1_H02W0701 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0101 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: B4 V02N0701 +arc: B5 H02W0301 +arc: B6 F3 +arc: B7 H02E0101 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V00T0100 +arc: C5 H02W0601 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0001 +arc: CLK1 G_HPBX0100 +arc: D0 N1_V02S0001 +arc: D1 N1_V02S0001 +arc: D2 N1_V02S0001 +arc: D3 N1_V02S0001 +arc: D4 V02S0401 +arc: D5 H00L0100 +arc: D6 E1_H01W0100 +arc: D7 H02W0001 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 Q6 +arc: E1_H02E0501 F7 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: LSR1 V00T0000 +arc: MUXCLK3 CLK1 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F7 +arc: S1_V02S0001 F0 +arc: S1_V02S0501 F7 +arc: V01S0000 F1 +arc: V01S0100 F2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 0101010111000101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK + +.tile R26C15:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0003 W1_H02E0301 +arc: H00R0000 V02S0601 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: S1_V02S0301 E3_H06W0003 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 V02N0201 +arc: V00T0000 V02N0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 H01E0001 +arc: N1_V02N0501 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A4 V00B0000 +arc: A5 V02S0101 +arc: A7 S1_V02N0301 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 E1_H02W0301 +arc: B5 H00R0000 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V00T0000 +arc: C5 H01E0001 +arc: C7 H02W0401 +arc: CLK1 G_HPBX0100 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 H02W0001 +arc: D5 V02N0601 +arc: D7 V01N0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: E1_H02E0701 F7 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 F3 +arc: LSR1 H02W0301 +arc: N1_V01N0101 F7 +arc: V01S0000 F0 +arc: V01S0100 F7 +arc: W1_H02W0201 F2 +arc: W3_H06W0203 F7 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1010101000001111 +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 + +.tile R26C16:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0501 W1_H02E0501 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 S3_V06N0203 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 S1_V02N0701 +arc: H01W0000 W3_H06E0103 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0401 W3_H06E0203 +arc: A0 N1_V02S0701 +arc: A1 N1_V02S0701 +arc: A2 N1_V02S0501 +arc: A3 N1_V02S0701 +arc: A4 V02S0101 +arc: A5 S1_V02N0101 +arc: A7 W1_H02E0501 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B2 H02E0101 +arc: B3 H02E0101 +arc: B4 H02W0301 +arc: B5 H00R0000 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 H02W0401 +arc: C5 V02N0201 +arc: C7 E1_H01E0101 +arc: CLK1 G_HPBX0100 +arc: D0 N1_V02S0201 +arc: D1 N1_V02S0001 +arc: D2 N1_V02S0201 +arc: D3 N1_V02S0001 +arc: D4 E1_H02W0001 +arc: D5 V02N0601 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F3 +arc: E1_H02E0001 F2 +arc: E1_H02E0201 F0 +arc: E3_H06E0203 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: LSR1 E1_H02W0301 +arc: MUXCLK3 CLK1 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R26C17:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 W1_H02E0501 +arc: H00L0000 V02S0001 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 V06S0303 +arc: S3_V06S0303 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: A0 N1_V02S0701 +arc: A1 N1_V02S0701 +arc: A2 N1_V02S0701 +arc: A3 N1_V02S0701 +arc: A4 V02S0101 +arc: A5 S1_V02N0101 +arc: A7 H02E0501 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B2 H02E0301 +arc: B3 H02E0101 +arc: B4 H00L0000 +arc: B5 V00B0100 +arc: B7 F1 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V00T0000 +arc: C5 V02N0201 +arc: C7 H01E0001 +arc: CLK1 G_HPBX0100 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 H02W0001 +arc: D5 E1_H02W0001 +arc: E1_H01E0001 F0 +arc: E3_H06E0203 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: LSR1 V00B0000 +arc: MUXCLK3 CLK1 +arc: V01S0000 F2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1101100011011000 +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.D1MUX 1 + +.tile R26C18:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 N1_V02S0701 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 V01N0101 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 S1_V02N0601 +arc: E3_H06E0303 W3_H06E0203 +arc: A0 N1_V02S0501 +arc: A1 N1_V02S0501 +arc: A2 N1_V02S0501 +arc: A3 N1_V02S0501 +arc: A4 H02W0501 +arc: A5 V02N0301 +arc: A7 E1_H02W0701 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B4 V02N0701 +arc: B5 V02N0501 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: C7 H01E0001 +arc: CLK1 G_HPBX0100 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 S1_V02N0401 +arc: D5 E1_H02W0001 +arc: D7 W1_H02E0201 +arc: E1_H01E0001 F0 +arc: E1_H02E0101 F3 +arc: E1_H02E0201 F2 +arc: E3_H06E0203 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: LSR1 H02W0301 +arc: MUXCLK3 CLK1 +arc: V01S0000 F1 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111010110100000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK + +.tile R26C19:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 H01E0001 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02E0701 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V06N0303 +arc: A0 N1_V02S0701 +arc: A1 N1_V02S0701 +arc: A2 N1_V02S0701 +arc: A3 N1_V02S0701 +arc: A4 V02N0101 +arc: A5 V00T0100 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B4 V02N0701 +arc: B5 V02N0501 +arc: B7 H02E0101 +arc: C0 H00R0100 +arc: C1 H00L0000 +arc: C2 H00R0100 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 V02S0001 +arc: C7 H02W0401 +arc: CLK1 G_HPBX0100 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H02E0001 +arc: D5 V02N0601 +arc: D7 H00L0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: LSR1 V00B0000 +arc: MUXCLK3 CLK1 +arc: S3_V06S0203 Q7 +arc: V01S0100 F1 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111110000001100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R26C20:PLC2 +arc: H00R0000 H02E0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S3_V06N0303 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0001 E1_H02W0001 +arc: E1_H01E0101 W3_H06E0203 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E1_H01W0000 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: B1 H02W0301 +arc: B2 H01W0100 +arc: B3 N1_V02S0301 +arc: B5 H02W0301 +arc: C1 H02E0601 +arc: C2 W1_H02E0401 +arc: C3 H02E0401 +arc: C5 H01E0001 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D1 H01E0101 +arc: D2 H00R0000 +arc: D3 N1_V02S0201 +arc: D5 W1_H02E0201 +arc: E3_H06E0303 Q5 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q6 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0001 F2 +arc: S1_V02S0301 F3 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q5 +arc: V01S0100 Q1 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111001111000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEB.K0.INIT 1111000011011000 +word: SLICEB.K1.INIT 1110110001001100 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R26C21:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02S0601 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0401 H06E0203 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 N1_V02S0101 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0701 S1_V02N0701 +arc: E1_H02E0001 W3_H06E0003 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0401 W3_H06E0203 +arc: A4 V02S0301 +arc: A5 V02S0301 +arc: C0 V02S0401 +arc: C1 E1_H02W0401 +arc: C3 V02N0601 +arc: CLK0 G_HPBX0100 +arc: D0 V02S0201 +arc: D1 H00R0000 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 E1_H01W0100 +arc: E1_H01E0001 F4 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F0 +arc: M6 V00B0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V02N0601 Q6 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F0 +arc: S3_V06S0103 F1 +arc: V01S0000 F4 +arc: V01S0100 F1 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F1 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000001111 +word: SLICEA.K1.INIT 0000000000001111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0000000001010101 +word: SLICEC.K1.INIT 0000000001010101 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R26C22:PLC2 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V06S0303 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H02E0001 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 H01E0001 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: A3 V02S0501 +arc: A5 N1_V01S0100 +arc: B1 F3 +arc: B7 V02S0501 +arc: C1 V02N0401 +arc: C3 E1_H02W0601 +arc: C5 H02E0401 +arc: C7 H02E0601 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 H02W0001 +arc: D1 V02N0201 +arc: D5 F0 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: MUXCLK2 CLK0 +arc: S1_V02S0501 F7 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICEA.K1.INIT 0000000000000011 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1010000010101111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1010000010100000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1100000011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R26C23:PLC2 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N3_V06S0303 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 H02E0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0501 V02N0501 +arc: S1_V02S0601 W3_H06E0303 +arc: A1 V02N0701 +arc: A5 V02S0101 +arc: C1 W1_H02E0401 +arc: C5 V02N0201 +arc: CE0 H00R0100 +arc: CE1 H00L0100 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D1 H00R0000 +arc: D4 V01N0001 +arc: D5 V02N0401 +arc: E1_H01E0101 Q6 +arc: E1_H02E0001 Q2 +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: H00R0000 F4 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: W1_H02W0401 F4 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICEC.K1.INIT 0000000000000101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1010000010101111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R26C24:PLC2 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0301 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 E1_H01E0001 +arc: A3 V00T0000 +arc: A7 H02E0501 +arc: B1 V00B0000 +arc: B2 H01W0100 +arc: B6 V00B0100 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C3 H02E0601 +arc: C6 H02E0601 +arc: C7 N1_V02S0201 +arc: CE0 H00L0100 +arc: CE1 H00L0100 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D1 H02E0001 +arc: D2 V02N0001 +arc: D3 V02N0201 +arc: D6 V01N0001 +arc: D7 V02N0401 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0301 Q3 +arc: V00B0000 Q6 +arc: V00B0100 Q7 +arc: V00T0000 Q2 +word: SLICED.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 1111010110100000 +word: SLICEA.K0.INIT 1010111110100000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1010111110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R26C2:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 V02S0401 +arc: S1_V02S0001 N1_V02S0001 +arc: V00B0000 V02N0001 +arc: A1 H02E0501 +arc: B1 V02N0101 +arc: B3 F1 +arc: C3 S1_V02N0601 +arc: CE0 N1_V02S0201 +arc: CE1 V02N0201 +arc: CLK0 G_HPBX0100 +arc: D1 H00R0000 +arc: D2 V02S0001 +arc: D3 V00T0100 +arc: E3_H06E0103 Q2 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V02N0101 F1 +arc: V00T0100 Q1 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1101110110001000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.A1MUX 1 + +.tile R26C3:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06S0203 +arc: H00R0000 V02S0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0501 N1_V02S0501 +arc: V00B0100 V02N0301 +arc: A7 V00T0100 +arc: B1 V02S0301 +arc: B3 V02S0101 +arc: B5 F1 +arc: B7 F3 +arc: C1 E1_H02W0601 +arc: C3 V02S0601 +arc: C5 H02E0601 +arc: C6 H02E0401 +arc: C7 H02E0601 +arc: CE0 V02N0201 +arc: CE1 V02N0201 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D1 H00R0000 +arc: D3 S1_V02N0001 +arc: D4 S1_V02N0401 +arc: D5 H01W0000 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F1 +arc: N1_V02N0301 F3 +arc: V00T0100 Q3 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1010110010101100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111000011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 + +.tile R26C4:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H01W0100 +arc: A1 V02S0501 +arc: A3 V02S0701 +arc: A7 V00T0100 +arc: B5 F3 +arc: B7 F1 +arc: C1 E1_H02W0401 +arc: C3 V02S0601 +arc: C4 N1_V02S0001 +arc: C5 E1_H02W0601 +arc: C6 H02E0601 +arc: C7 E1_H02W0601 +arc: CE0 E1_H02W0101 +arc: CE1 E1_H02W0101 +arc: CE2 H02E0101 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0100 +arc: D1 V02S0001 +arc: D3 H02E0001 +arc: D5 H00L0100 +arc: E1_H01E0001 F1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: M4 H02E0401 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F3 +arc: S3_V06S0303 Q6 +arc: V00T0100 Q1 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1010110010101100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111110000001100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111101000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R26C5:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 V01N0101 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 E3_H06W0303 +arc: V00B0100 V02N0301 +arc: V00T0100 H02E0101 +arc: W1_H02W0601 E1_H02W0601 +arc: A1 E1_H02W0501 +arc: A2 W1_H02E0701 +arc: A3 H00L0100 +arc: B1 V02S0301 +arc: C1 S1_V02N0401 +arc: C3 H02W0601 +arc: CE0 H02W0101 +arc: CE1 W1_H02E0101 +arc: CLK0 G_HPBX0100 +arc: D3 V01S0100 +arc: E1_H02E0101 F1 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q4 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: V01S0100 F1 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1110010011100100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R26C6:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 E1_H02W0301 +arc: A3 V00B0000 +arc: B3 E1_H01W0100 +arc: C3 E1_H01W0000 +arc: CLK0 G_HPBX0100 +arc: D3 V02N0201 +arc: E1_H01E0001 F2 +arc: F2 F5B_SLICE +arc: LSR1 H02W0301 +arc: M2 V00B0100 +arc: M6 E1_H02W0401 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: V00B0000 Q6 +arc: V01S0000 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111100010001000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R26C7:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H01E0001 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0103 V06N0103 +arc: A1 F7 +arc: A3 H00L0100 +arc: A5 H02W0501 +arc: A6 V02N0301 +arc: A7 H02W0501 +arc: B0 E1_H01W0100 +arc: B1 V02N0101 +arc: B3 V01N0001 +arc: B5 V02N0501 +arc: B7 V00B0000 +arc: C0 H00L0100 +arc: C1 H02E0401 +arc: C3 N1_V01N0001 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0001 +arc: CE2 V02N0601 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0100 +arc: D0 V00T0100 +arc: D1 F0 +arc: D3 V00B0100 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: D7 H02W0201 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 Q7 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q7 +arc: H01W0100 Q5 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 F6 +arc: S3_V06S0003 F3 +arc: V01S0100 Q5 +word: SLICED.K0.INIT 1010000000000000 +word: SLICED.K1.INIT 0101001011110010 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEA.K1.INIT 1011111110000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0100110001101110 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R26C8:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: H00L0100 H02E0101 +arc: H00R0100 V02S0701 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0601 S3_V06N0303 +arc: V00T0100 V02N0501 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: H01W0000 W3_H06E0103 +arc: W3_H06W0003 S3_V06N0003 +arc: E3_H06E0203 W3_H06E0103 +arc: A0 V01N0101 +arc: A1 H00L0100 +arc: A2 H02E0501 +arc: A3 N1_V02S0501 +arc: A4 N1_V01N0101 +arc: A5 H02E0701 +arc: A7 V02N0301 +arc: B0 F3 +arc: B1 V00T0000 +arc: B2 H00R0100 +arc: B3 V02S0101 +arc: B4 N1_V02S0501 +arc: B5 H02E0101 +arc: B7 V01S0000 +arc: C0 H00L0100 +arc: C1 N1_V01N0001 +arc: C2 V02N0401 +arc: C3 H00L0000 +arc: C4 V00T0000 +arc: C5 V01N0101 +arc: C7 V00T0100 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: D0 V00B0100 +arc: D1 H02E0001 +arc: D2 H02W0201 +arc: D3 F2 +arc: D4 F2 +arc: D5 V00B0000 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F2 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q5 +arc: S1_V02S0001 F2 +arc: S1_V02S0501 Q5 +arc: S1_V02S0701 Q7 +arc: S3_V06S0103 F2 +arc: V00B0000 F4 +arc: V00B0100 F7 +arc: V00T0000 Q0 +arc: W1_H02W0701 Q5 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 0000000000100111 +word: SLICEC.K0.INIT 0000111111011101 +word: SLICEC.K1.INIT 1000000010111111 +word: SLICEA.K0.INIT 1011001100010011 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0011111101010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R26C9:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06S0003 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0201 H01E0001 +arc: V00B0000 W1_H02E0401 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V02N0601 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W3_H06W0203 S3_V06N0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0203 +arc: A4 V02S0101 +arc: B5 H02E0301 +arc: C4 V02N0201 +arc: C5 F4 +arc: CE2 H02E0101 +arc: CLK0 G_HPBX0100 +arc: D4 H00R0100 +arc: D5 H01W0000 +arc: E3_H06E0303 F5 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q4 +arc: M0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0001 Q0 +arc: N3_V06N0203 F4 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 0000001111001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.A1MUX 1 + +.tile R27C10:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0203 W1_H02E0401 +arc: H00L0100 H02W0101 +arc: H00R0100 H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0303 E1_H02W0601 +arc: A1 F7 +arc: A6 H02W0501 +arc: A7 E1_H02W0501 +arc: B1 E1_H02W0301 +arc: B2 V02N0101 +arc: B3 F1 +arc: B6 V00B0100 +arc: C1 S1_V02N0601 +arc: C2 V02N0601 +arc: C6 V00T0000 +arc: C7 E1_H02W0401 +arc: CE1 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D2 W1_H02E0201 +arc: D6 H00L0100 +arc: D7 E1_H01W0100 +arc: E1_H02E0001 Q2 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V02N0401 Q4 +arc: N3_V06N0103 Q2 +arc: S1_V02S0601 F6 +arc: V00B0100 F7 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0011010100000000 +word: SLICED.K1.INIT 0000010111110101 +word: SLICEB.K0.INIT 0000001111110011 +word: SLICEB.K1.INIT 1100110011001100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0011010100110101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R27C11:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: W1_H02W0001 W3_H06E0003 +arc: W3_H06W0103 E3_H06W0103 +arc: A1 V01N0101 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A4 F5 +arc: A5 V02N0301 +arc: A6 N1_V01N0101 +arc: B3 H00L0000 +arc: B4 E1_H02W0101 +arc: B6 V02S0501 +arc: B7 V00B0000 +arc: C0 V02S0401 +arc: C1 H02W0401 +arc: C3 V02N0401 +arc: C4 H02E0601 +arc: C5 V00B0100 +arc: C7 H02W0401 +arc: CE0 H00R0000 +arc: CE2 H00R0100 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0100 +arc: D0 S1_V02N0201 +arc: D1 V01S0100 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 S1_V02N0401 +arc: D5 E1_H01W0100 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q6 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F1 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 Q4 +arc: M2 W1_H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V00B0000 Q6 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +arc: W1_H02W0501 F7 +arc: W3_H06W0203 Q4 +word: SLICEB.K0.INIT 0101010100000000 +word: SLICEB.K1.INIT 0011111100100010 +word: SLICEC.K0.INIT 0100010001000111 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 0101000001011111 +word: SLICED.K0.INIT 1000100010001000 +word: SLICED.K1.INIT 0000001111110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 + +.tile R27C12:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0701 V06S0203 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H02E0701 +arc: V00B0100 V02S0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0501 E1_H01W0100 +arc: S3_V06S0203 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0203 +arc: A0 H01E0001 +arc: A5 V02N0101 +arc: A6 E1_H01W0000 +arc: B1 V00T0000 +arc: B3 V02N0101 +arc: B6 H02W0301 +arc: B7 V00B0000 +arc: C0 E1_H01W0000 +arc: C1 E1_H02W0401 +arc: C3 S1_V02N0601 +arc: C5 H02W0401 +arc: C6 V02S0201 +arc: C7 E1_H02W0401 +arc: CE0 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 H02W0001 +arc: D1 W1_H02E0201 +arc: D3 V00B0100 +arc: D5 V02S0601 +arc: D6 H01W0000 +arc: D7 W1_H02E0001 +arc: E1_H02E0101 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0201 Q0 +arc: S1_V02S0501 Q5 +arc: S3_V06S0003 Q0 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q6 +arc: V00T0000 Q0 +arc: V01S0100 Q3 +arc: W1_H02W0101 F1 +arc: W1_H02W0301 F1 +arc: W1_H02W0601 Q6 +arc: W1_H02W0701 F7 +arc: W3_H06W0303 Q5 +word: SLICED.K0.INIT 1101110001010000 +word: SLICED.K1.INIT 0000001111110011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICEA.K0.INIT 1010111110101010 +word: SLICEA.K1.INIT 0000001111110011 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.A1MUX 1 + +.tile R27C13:PLC2 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0100 H02E0701 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A2 S1_V02N0501 +arc: A3 V02N0701 +arc: B2 S1_V02N0101 +arc: B3 H00L0000 +arc: C2 E1_H02W0401 +arc: C3 V02S0601 +arc: CE0 H00R0000 +arc: CE1 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D2 V02N0201 +arc: D3 H02E0201 +arc: E1_H02E0401 Q6 +arc: E3_H06E0003 Q0 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 F2 +arc: H01W0000 F2 +arc: H01W0100 Q3 +arc: M0 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0003 Q3 +arc: V01S0100 F2 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0011111111110101 +word: SLICEB.K1.INIT 1111001000100010 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R27C14:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 S1_V02N0401 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 H02W0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0201 V06N0103 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06S0203 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: W3_H06W0003 V01N0001 +arc: E3_H06E0103 W3_H06E0003 +arc: A1 V02S0501 +arc: A3 V02S0501 +arc: B7 V02S0501 +arc: C1 N1_V01S0100 +arc: C3 V02S0401 +arc: C7 V02S0001 +arc: CE2 V02N0601 +arc: CLK0 G_HPBX0100 +arc: D1 V02S0201 +arc: D3 N1_V01S0000 +arc: D7 H02W0201 +arc: E3_H06E0003 Q3 +arc: E3_H06E0203 Q7 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0203 Q4 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q7 +arc: V01S0100 Q1 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111101001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R27C15:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 W1_H02E0601 +arc: E3_H06E0203 V06N0203 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0601 V06N0303 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0401 W3_H06E0203 +arc: W3_H06W0103 S3_V06N0103 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0203 +arc: A0 V01N0101 +arc: A4 H02W0501 +arc: A6 H02W0501 +arc: B0 S1_V02N0301 +arc: B1 S1_V02N0301 +arc: B4 H02E0101 +arc: B5 S1_V02N0701 +arc: B6 H02E0101 +arc: B7 H02W0101 +arc: C1 W1_H02E0401 +arc: C4 V00T0100 +arc: C5 F4 +arc: C6 H02W0601 +arc: C7 V02N0201 +arc: CE2 V02N0601 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0100 +arc: D0 S1_V02N0201 +arc: D1 S1_V02N0201 +arc: D4 S1_V02N0601 +arc: D5 E1_H02W0001 +arc: D6 V02S0601 +arc: D7 H01W0000 +arc: E1_H01E0101 F1 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: LSR0 V00B0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: V01S0000 F0 +arc: W1_H02W0501 Q5 +arc: W1_H02W0701 Q7 +arc: W3_H06W0203 Q7 +word: SLICED.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 1100000011001111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 1100110000001111 +word: SLICEA.K0.INIT 1000100000000000 +word: SLICEA.K1.INIT 1100000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.A1MUX 1 + +.tile R27C16:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 S3_V06N0303 +arc: H00R0000 H02E0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00T0000 V02S0601 +arc: V00T0100 S1_V02N0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H02W0601 +arc: S1_V02S0701 W3_H06E0203 +arc: A6 H02W0701 +arc: A7 H02W0501 +arc: B3 H02E0101 +arc: B6 S1_V02N0501 +arc: B7 S1_V02N0501 +arc: C3 E1_H02W0401 +arc: C6 E1_H02W0401 +arc: C7 E1_H02W0401 +arc: CE0 H00R0000 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D2 V02N0201 +arc: D3 V02N0001 +arc: D6 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 Q0 +arc: E1_H02E0701 F7 +arc: E3_H06E0203 Q4 +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0000 +arc: M2 V00T0100 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: V01S0000 F6 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111000010111000 +word: SLICED.K1.INIT 1111000010111000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R27C17:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 N1_V01S0100 +arc: S3_V06S0003 W3_H06E0003 +arc: A0 H02W0501 +arc: A2 E1_H02W0501 +arc: A4 V02S0101 +arc: A5 S1_V02N0101 +arc: A6 V02S0101 +arc: B0 E1_H02W0301 +arc: B1 V00B0000 +arc: B2 E1_H02W0101 +arc: B3 S1_V02N0301 +arc: B4 H00R0000 +arc: B6 V02N0501 +arc: B7 S1_V02N0501 +arc: C0 H02E0401 +arc: C1 S1_V02N0401 +arc: C2 H02E0401 +arc: C3 N1_V01N0001 +arc: C4 H02E0601 +arc: C5 F4 +arc: C6 H02E0601 +arc: C7 F6 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 V02N0601 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0100 +arc: D0 V02S0201 +arc: D1 F0 +arc: D2 V02S0201 +arc: D3 V02N0001 +arc: D4 E1_H01W0100 +arc: D5 S1_V02N0601 +arc: D6 H02E0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q5 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F2 +arc: N1_V02N0501 Q5 +arc: N1_V02N0701 Q7 +arc: S1_V02S0101 Q1 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q5 +arc: V01S0100 Q7 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +word: SLICED.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 1100110000001111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 1010101000001111 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 1100110000001111 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 1100000011001111 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R27C18:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 E1_H01W0100 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0501 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: N1_V02N0401 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: W3_H06W0103 S3_V06N0103 +arc: A5 H02E0701 +arc: C5 V02S0001 +arc: CE0 V02N0201 +arc: CE1 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D5 H02E0001 +arc: E1_H02E0501 Q5 +arc: E3_H06E0303 Q5 +arc: F5 F5_SLICE +arc: H01W0100 Q0 +arc: M0 V00B0000 +arc: M2 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q6 +arc: V01S0000 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111101001010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R27C19:PLC2 +arc: H00R0000 W1_H02E0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 N1_V02S0401 +arc: V00B0100 V02N0101 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V01N0001 +arc: H01W0100 W3_H06E0303 +arc: W1_H02W0301 W3_H06E0003 +arc: A1 V02S0701 +arc: A6 H00L0000 +arc: B6 H02E0101 +arc: C1 N1_V01S0100 +arc: C6 V02N0001 +arc: CE1 H00R0000 +arc: CE2 H02W0101 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0100 +arc: D1 H02E0001 +arc: D6 E1_H02W0001 +arc: E1_H01E0001 Q2 +arc: E1_H02E0001 Q2 +arc: E3_H06E0103 Q1 +arc: F1 F1_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1110101011000000 +word: SLICED.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111010110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R27C20:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 S1_V02N0501 +arc: H00R0000 S1_V02N0601 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0501 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 E1_H01W0100 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: CE0 H00R0000 +arc: CE1 V02N0201 +arc: CE2 S1_V02N0601 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0101 Q4 +arc: E1_H02E0001 Q2 +arc: H01W0100 Q0 +arc: M0 H01E0001 +arc: M2 V00T0100 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0303 Q6 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R27C21:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 N1_V01S0000 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V01S0000 +arc: N1_V02N0401 W3_H06E0203 +arc: W1_H02W0001 W3_H06E0003 +arc: W3_H06W0303 N1_V01S0100 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 N1_V01N0101 +arc: A6 V02N0101 +arc: A7 H02E0501 +arc: B1 E1_H01W0100 +arc: B2 H02W0101 +arc: B3 E1_H02W0301 +arc: B4 H02E0301 +arc: B5 S1_V02N0501 +arc: B6 H01E0101 +arc: C0 H02W0601 +arc: C1 N1_V02S0401 +arc: C2 E1_H02W0601 +arc: C3 E1_H01W0000 +arc: C4 H02W0401 +arc: C5 F4 +arc: C6 H02W0401 +arc: C7 F6 +arc: CE2 V02N0601 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0100 +arc: D0 V00B0100 +arc: D2 H02E0001 +arc: D3 S1_V02N0001 +arc: D4 H02E0201 +arc: D5 V02N0401 +arc: D6 H02E0201 +arc: D7 V02N0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F1 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: S1_V02S0001 F2 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 Q5 +arc: S1_V02S0701 Q7 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q5 +arc: V01S0100 F0 +arc: W3_H06W0003 F0 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 1100110000001111 +word: SLICEB.K0.INIT 1111100001110000 +word: SLICEB.K1.INIT 1101100011110000 +word: SLICED.K0.INIT 0101001101010000 +word: SLICED.K1.INIT 1010101000001111 +word: SLICEA.K0.INIT 0000000000001111 +word: SLICEA.K1.INIT 0000001100000011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET SET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R27C22:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00R0000 V02N0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0101 H06E0103 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 W1_H02E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S1_V02N0701 +arc: E1_H01E0101 W3_H06E0203 +arc: A3 V02S0501 +arc: B7 H02E0101 +arc: C3 H02W0401 +arc: C7 V02N0001 +arc: CE0 H00R0000 +arc: CE2 V02N0601 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D2 V02N0201 +arc: D3 H02W0201 +arc: D7 F2 +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F2 +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V02N0001 Q0 +arc: V01S0100 Q4 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICEB.K1.INIT 0000000000000101 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1100000011110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 + +.tile R27C23:PLC2 +arc: E1_H02E0101 V06S0103 +arc: H00R0000 V02S0601 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 H02E0601 +arc: V00T0100 V02S0701 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 S1_V02N0601 +arc: A6 V02N0101 +arc: A7 N1_V01N0101 +arc: B1 W1_H02E0301 +arc: B3 W1_H02E0101 +arc: C3 F6 +arc: C7 E1_H01E0101 +arc: CE1 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D1 H00R0000 +arc: D3 V02S0001 +arc: D7 V02N0401 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F1 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F6 +arc: M4 V00T0100 +arc: M6 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0101010101010101 +word: SLICED.K1.INIT 0000000000000101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1100111100000011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1100110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R27C24:PLC2 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 V02N0201 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 V02N0701 +arc: CE0 H02E0101 +arc: CE1 H02E0101 +arc: CE2 H02E0101 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0100 +arc: M0 H01E0001 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V02N0001 Q2 +arc: N1_V02N0201 Q0 +arc: N1_V02N0401 Q6 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R27C2:PLC2 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 V02S0001 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0501 +arc: A1 H02E0501 +arc: A3 H02E0501 +arc: A4 S1_V02N0101 +arc: A7 V02N0301 +arc: B5 F1 +arc: B7 F3 +arc: C1 S1_V02N0601 +arc: C3 N1_V02S0601 +arc: C5 E1_H01E0101 +arc: CE0 S1_V02N0201 +arc: CE1 S1_V02N0201 +arc: CE2 H02W0101 +arc: CE3 H02W0101 +arc: CLK0 G_HPBX0100 +arc: D1 V00T0100 +arc: D3 H02E0201 +arc: D5 V02N0601 +arc: D6 V00B0000 +arc: D7 H00L0100 +arc: E1_H01E0101 Q1 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0003 F3 +arc: N3_V06N0103 F1 +arc: S3_V06S0203 Q4 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1110111001000100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111010110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R27C3:PLC2 +arc: H00R0000 H02E0601 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 E3_H06W0203 +arc: S1_V02S0301 N3_V06S0003 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 V02S0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0701 S3_V06N0203 +arc: B1 V02N0301 +arc: C0 S1_V02N0601 +arc: C1 N1_V02S0401 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D1 V00T0100 +arc: E3_H06E0003 Q0 +arc: F0 F5A_SLICE +arc: M0 V00B0000 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 + +.tile R27C4:PLC2 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0701 E1_H02W0701 + +.tile R27C5:PLC2 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 V02S0301 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0401 S1_V02N0401 +arc: A3 S1_V02N0501 +arc: C3 H00R0100 +arc: CE1 H00R0000 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D3 N1_V02S0201 +arc: E1_H02E0101 F3 +arc: E3_H06E0003 Q3 +arc: F3 F3_SLICE +arc: M6 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q6 +arc: N3_V06N0003 F3 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111010110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R27C6:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 N3_V06S0103 +arc: H00L0100 V02N0301 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0203 E1_H02W0401 +arc: W3_H06W0303 E1_H02W0501 +arc: A3 V02S0701 +arc: A4 H02E0501 +arc: B1 N1_V02S0301 +arc: B3 E1_H01W0100 +arc: B5 E1_H02W0301 +arc: C1 V02S0401 +arc: C3 V02N0401 +arc: C5 E1_H01E0101 +arc: CE0 H00L0100 +arc: CE2 H02W0101 +arc: CE3 V02S0601 +arc: CLK0 G_HPBX0100 +arc: D1 S1_V02N0001 +arc: D3 N1_V01S0000 +arc: D5 H01W0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q1 +arc: E1_H02E0201 F2 +arc: E3_H06E0203 Q4 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F1 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q6 +arc: N1_V02N0301 F1 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q4 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1010101010101010 +word: SLICEC.K1.INIT 1111001111000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R27C7:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 H02E0701 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 V02N0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: A1 H00L0100 +arc: A2 V00B0000 +arc: A3 V02S0501 +arc: A4 V00T0000 +arc: A6 V00T0100 +arc: A7 N1_V01S0100 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0101 +arc: B3 V01N0001 +arc: B4 V02S0501 +arc: B5 V01S0000 +arc: B6 V02S0501 +arc: B7 H02E0101 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: C3 E1_H02W0401 +arc: C4 V01N0101 +arc: C6 E1_H02W0401 +arc: C7 E1_H01E0101 +arc: CE1 H00R0000 +arc: CE2 S1_V02N0601 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: D1 S1_V02N0001 +arc: D2 V00B0100 +arc: D3 F2 +arc: D4 F2 +arc: D5 E1_H01W0100 +arc: D6 V01N0001 +arc: D7 H01W0000 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q6 +arc: E1_H02E0601 Q6 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q4 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 F5 +arc: V00T0100 F1 +arc: V01S0000 Q4 +arc: W1_H02W0701 F7 +word: SLICEB.K0.INIT 0000000000000100 +word: SLICEB.K1.INIT 0000010000000000 +word: SLICED.K0.INIT 0000100000000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEC.K0.INIT 0100000000000000 +word: SLICEC.K1.INIT 0011001111111111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R27C8:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 H01E0001 +arc: H00L0100 H02E0301 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0601 S3_V06N0303 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 S3_V06N0303 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0401 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: A3 E1_H02W0501 +arc: A7 N1_V01S0100 +arc: B0 V02S0101 +arc: B2 F3 +arc: B7 V02N0701 +arc: C0 W1_H02E0601 +arc: C1 S1_V02N0401 +arc: C2 W1_H02E0401 +arc: C3 E1_H02W0601 +arc: C6 V02S0201 +arc: CE0 H00R0000 +arc: CE2 H00L0100 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D3 V02N0201 +arc: D6 H02E0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F6 +arc: E1_H02E0501 F7 +arc: E1_H02E0701 F7 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F3 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F3 +arc: N1_V02N0001 Q0 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 Q7 +arc: S3_V06S0203 Q7 +arc: V00T0000 Q0 +arc: V01S0000 F2 +arc: W1_H02W0401 Q4 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F7 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 F6 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 1101110110001000 +word: SLICEB.K0.INIT 1100000011000000 +word: SLICEB.K1.INIT 0000000010100000 +word: SLICEA.K0.INIT 1111000011100010 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R27C9:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E3_H06E0103 H01E0101 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02N0101 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 W1_H02E0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 H01E0001 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0301 W3_H06E0003 +arc: S3_V06S0003 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 E1_H02W0501 +arc: A3 V02N0701 +arc: B0 F3 +arc: B5 H02E0301 +arc: C0 H02W0601 +arc: C2 V02N0601 +arc: C3 H02E0601 +arc: C4 N1_V02S0201 +arc: C5 V00T0100 +arc: CE0 H00R0100 +arc: CE2 S1_V02N0601 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D0 E1_H02W0201 +arc: D1 F2 +arc: D2 H02W0001 +arc: D3 V02S0201 +arc: D5 E1_H02W0001 +arc: E1_H02E0001 Q0 +arc: E1_H02E0601 Q4 +arc: E3_H06E0203 Q4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H01W0100 F3 +arc: M0 V00B0000 +arc: M4 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0001 Q0 +arc: S1_V02S0401 Q6 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q4 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0101000001011111 +word: SLICEB.K1.INIT 0101111100000000 +word: SLICEA.K0.INIT 0011000000111111 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1111110000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 + +.tile R28C10:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A0 H00R0000 +arc: A1 H02W0501 +arc: A2 V02N0701 +arc: A4 F5 +arc: A6 H02E0701 +arc: A7 V02S0101 +arc: B1 E1_H02W0301 +arc: B2 V01N0001 +arc: B4 V02S0701 +arc: B5 V01S0000 +arc: B6 F1 +arc: B7 V00B0100 +arc: C0 E1_H02W0401 +arc: C1 H00R0100 +arc: C2 H02E0401 +arc: C4 H02W0601 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 H02W0601 +arc: CE0 E1_H02W0101 +arc: CE1 S1_V02N0201 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D0 H02W0201 +arc: D1 F0 +arc: D2 H01E0101 +arc: D4 V02N0401 +arc: D5 E1_H02W0201 +arc: D6 V01N0001 +arc: D7 V02N0401 +arc: E1_H01E0001 F5 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: N3_V06N0103 Q2 +arc: N3_V06N0303 Q6 +arc: V00B0000 F4 +arc: V01S0000 Q6 +arc: W1_H02W0001 F0 +word: SLICEC.K0.INIT 0101001100000000 +word: SLICEC.K1.INIT 0011000000111111 +word: SLICEB.K0.INIT 1111010001000100 +word: SLICEB.K1.INIT 1111111111111111 +word: SLICED.K0.INIT 1111101111111010 +word: SLICED.K1.INIT 0011010100000000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 0101100011111101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R28C11:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 V02S0401 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 H06E0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H02W0301 +arc: N3_V06N0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: A0 V02N0701 +arc: A1 H02E0701 +arc: A2 H02E0501 +arc: A3 H02E0701 +arc: A5 V00B0000 +arc: A6 F7 +arc: A7 H00R0000 +arc: B0 E1_H01W0100 +arc: B1 S1_V02N0301 +arc: B2 F3 +arc: B3 S1_V02N0301 +arc: B4 N1_V01S0000 +arc: B6 E1_H02W0301 +arc: C1 E1_H01W0000 +arc: C2 F6 +arc: C3 F4 +arc: C4 V00T0100 +arc: C5 V02S0201 +arc: C6 V00B0100 +arc: C7 V02S0001 +arc: CE0 H00L0000 +arc: CE1 H00R0100 +arc: CE2 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: D0 W1_H02E0201 +arc: D1 F0 +arc: D2 E1_H02W0001 +arc: D3 V02N0001 +arc: D4 S1_V02N0401 +arc: D5 S1_V02N0601 +arc: D7 E1_H01W0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 Q2 +arc: N3_V06N0103 Q2 +arc: N3_V06N0303 F5 +arc: V00B0000 Q4 +arc: V01S0000 F7 +arc: W1_H02W0701 F5 +arc: W3_H06W0303 F5 +word: SLICED.K0.INIT 1011100010111000 +word: SLICED.K1.INIT 0000101001011111 +word: SLICEC.K0.INIT 1100111111000000 +word: SLICEC.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 0000111100010001 +word: SLICEB.K1.INIT 0110111100101011 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 0110001011111011 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C0MUX 1 + +.tile R28C12:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V02S0501 +arc: H00L0000 V02N0201 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: W3_H06W0303 N1_V01S0100 +arc: A1 E1_H01E0001 +arc: A4 V02N0101 +arc: A6 H00L0000 +arc: B0 V02S0301 +arc: B1 H02W0101 +arc: B4 H02W0301 +arc: B6 V02S0701 +arc: B7 V01S0000 +arc: C1 E1_H02W0601 +arc: C4 H02E0401 +arc: C6 H02W0601 +arc: C7 V00T0000 +arc: CE0 H00R0000 +arc: CE2 H00R0100 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: D0 H02E0201 +arc: D1 V00T0100 +arc: D4 V01N0001 +arc: D6 V02S0601 +arc: D7 V00B0000 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 Q0 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0201 Q0 +arc: S1_V02S0401 Q6 +arc: S3_V06S0003 Q0 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q4 +arc: V01S0000 Q6 +arc: V01S0100 Q6 +arc: W1_H02W0701 F7 +word: SLICEC.K0.INIT 1111111100000010 +word: SLICEC.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 1100110000000000 +word: SLICEA.K1.INIT 1001000101111001 +word: SLICED.K0.INIT 1000100011111000 +word: SLICED.K1.INIT 0000001111110011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R28C13:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N3_V06S0203 +arc: E3_H06E0103 N3_V06S0103 +arc: H00L0000 V02N0201 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 E1_H02W0601 +arc: N1_V02N0301 W3_H06E0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 V01N0101 +arc: A2 V02S0701 +arc: A3 S1_V02N0501 +arc: A4 N1_V01S0100 +arc: A5 V00B0000 +arc: A6 H02E0501 +arc: B1 V00T0000 +arc: B2 H02E0101 +arc: B3 N1_V02S0101 +arc: B4 W1_H02E0301 +arc: B5 V02N0701 +arc: B6 W1_H02E0101 +arc: C0 V02N0601 +arc: C1 H02E0401 +arc: C2 H00L0000 +arc: C4 N1_V02S0001 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 V00B0100 +arc: D2 W1_H02E0001 +arc: D3 F2 +arc: D4 V02N0601 +arc: D5 H01W0000 +arc: D6 V02S0401 +arc: E1_H01E0001 F1 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q4 +arc: H01W0100 F5 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0101 F1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0601 Q6 +arc: S3_V06S0003 Q3 +arc: S3_V06S0203 Q4 +arc: V00T0000 Q0 +arc: V01S0000 Q3 +arc: V01S0100 Q3 +arc: W3_H06W0003 Q0 +word: SLICED.K0.INIT 1111100010001000 +word: SLICED.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICEA.K1.INIT 0101001101010011 +word: SLICEC.K0.INIT 1111010001000100 +word: SLICEC.K1.INIT 1001001000101111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0100010011111111 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R28C14:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0601 E1_H01W0000 +arc: E3_H06E0303 N1_V01S0100 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 H02E0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06W0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 H02W0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 S3_V06N0303 +arc: H01W0100 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 H01E0001 +arc: A2 V02N0501 +arc: A3 E1_H02W0701 +arc: A4 V00T0000 +arc: A5 N1_V01N0101 +arc: A7 E1_H02W0501 +arc: B0 H02E0301 +arc: B1 H00R0100 +arc: B4 S1_V02N0701 +arc: B6 H02E0301 +arc: B7 V00B0000 +arc: C0 H02W0601 +arc: C1 V02S0401 +arc: C2 S1_V02N0401 +arc: C3 H00L0000 +arc: C4 E1_H01E0101 +arc: C5 V02N0001 +arc: C6 V02S0201 +arc: C7 V02N0201 +arc: CE1 H00L0100 +arc: CE2 H00R0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D0 H02W0001 +arc: D1 E1_H02W0001 +arc: D2 S1_V02N0001 +arc: D3 V00B0100 +arc: D4 W1_H02E0201 +arc: D5 F0 +arc: D6 V02S0601 +arc: D7 H02W0001 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0100 Q7 +arc: H01W0000 F3 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F4 +arc: N1_V02N0701 Q7 +arc: N3_V06N0303 Q5 +arc: V00B0000 F6 +arc: V01S0000 Q5 +arc: W3_H06W0003 F3 +word: SLICED.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 0011001100000101 +word: SLICEA.K0.INIT 0001110100000000 +word: SLICEA.K1.INIT 0011000000111111 +word: SLICEC.K0.INIT 0010111011001111 +word: SLICEC.K1.INIT 1111111101010000 +word: SLICEB.K0.INIT 1010111110100000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R28C15:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0003 N1_V02S0301 +arc: S3_V06S0303 N1_V01S0100 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 H02W0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 E1_H02W0701 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0000 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0001 Q0 +arc: E1_H02E0601 Q6 +arc: H01W0000 Q4 +arc: M0 V00T0000 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R28C16:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 N3_V06S0203 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02N0401 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 V02S0701 +arc: A2 H01E0001 +arc: A3 V01N0101 +arc: A4 V00T0100 +arc: A6 N1_V02S0101 +arc: B0 E1_H01W0100 +arc: B1 S1_V02N0301 +arc: B4 V00B0100 +arc: B5 S1_V02N0701 +arc: B6 E1_H02W0101 +arc: B7 S1_V02N0701 +arc: C0 N1_V01S0100 +arc: C1 H02W0601 +arc: C2 H02E0401 +arc: C3 H02E0601 +arc: C4 E1_H02W0401 +arc: C5 F4 +arc: C6 W1_H02E0601 +arc: C7 F6 +arc: CE0 S1_V02N0201 +arc: CE2 S1_V02N0601 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: D0 V00B0100 +arc: D1 F0 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 V02S0601 +arc: D5 E1_H02W0001 +arc: D6 V02S0601 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N3_V06N0203 Q7 +arc: V01S0000 Q5 +arc: V01S0100 Q7 +arc: W1_H02W0701 Q5 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 1100111100000011 +word: SLICEA.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 1100000011110011 +word: SLICED.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 1100111100000011 +word: SLICEB.K0.INIT 1010101011110000 +word: SLICEB.K1.INIT 1010000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R28C17:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 N3_V06S0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 H02W0601 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 V02S0201 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E3_H06W0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 N1_V02S0501 +arc: A2 V00T0000 +arc: A3 H01E0001 +arc: A4 S1_V02N0301 +arc: A5 H02W0701 +arc: A6 N1_V02S0301 +arc: A7 S1_V02N0101 +arc: B2 H02E0301 +arc: B3 W1_H02E0101 +arc: B4 H00R0000 +arc: B5 V02N0701 +arc: B6 H02W0301 +arc: B7 V00B0000 +arc: CE2 H00L0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: H01W0100 Q5 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V01S0100 Q6 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R28C18:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V01N0101 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 H02E0401 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0501 E1_H01W0100 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 W1_H02E0601 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 H00L0000 +arc: A1 N1_V02S0701 +arc: A2 H02E0501 +arc: A3 E1_H02W0701 +arc: A4 H02W0701 +arc: A5 H02W0501 +arc: A6 W1_H02E0501 +arc: A7 W1_H02E0701 +arc: B0 V02S0101 +arc: B1 V02S0301 +arc: B2 H00R0000 +arc: B3 W1_H02E0101 +arc: B4 N1_V01S0000 +arc: B5 H02E0301 +arc: B6 V00B0000 +arc: B7 V02S0701 +arc: CE0 S1_V02N0201 +arc: CE1 S1_V02N0201 +arc: CE2 S1_V02N0601 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q2 +arc: W1_H02W0101 Q3 +arc: W1_H02W0401 Q4 +arc: W1_H02W0501 Q7 +arc: W3_H06W0303 Q6 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101010 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R28C19:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 H02W0001 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: S3_V06S0203 W3_H06E0203 +arc: A0 H02W0501 +arc: A1 V01N0101 +arc: A2 V00T0000 +arc: A3 V02S0501 +arc: A4 V00T0100 +arc: A5 V02N0301 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 V01N0001 +arc: B1 S1_V02N0101 +arc: B2 H02W0301 +arc: B3 N1_V02S0301 +arc: B4 V02N0501 +arc: B5 N1_V02S0501 +arc: B6 V00B0000 +arc: B7 E1_H02W0101 +arc: CE0 S1_V02N0201 +arc: CE1 S1_V02N0201 +arc: CE2 H00L0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0101 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q5 +arc: S1_V02S0001 Q2 +arc: S1_V02S0601 Q4 +arc: V01S0100 Q6 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R28C20:PLC2 +arc: E1_H02E0401 V02S0401 +arc: H00L0000 H02E0201 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02N0401 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 W1_H02E0401 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 N3_V06S0203 +arc: N1_V02N0501 W3_H06E0303 +arc: A0 V02N0701 +arc: A1 H00L0100 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 V00T0000 +arc: A5 V00B0000 +arc: A6 E1_H01W0000 +arc: A7 E1_H02W0501 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B2 V02N0301 +arc: B3 H00R0000 +arc: B4 W1_H02E0301 +arc: B5 E1_H02W0101 +arc: B6 V00B0000 +arc: B7 V00B0000 +arc: CE0 H00L0000 +arc: CE1 H00L0000 +arc: CE2 H00L0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0101 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q7 +arc: S1_V02S0101 Q1 +arc: S1_V02S0301 Q3 +arc: S1_V02S0501 Q5 +arc: S1_V02S0601 Q4 +arc: V01S0100 Q6 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R28C21:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 N1_V02S0701 +arc: S3_V06S0303 H01E0101 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 N1_V01S0100 +arc: W1_H02W0601 S1_V02N0601 +arc: E1_H02E0501 W3_H06E0303 +arc: N1_V02N0501 W3_H06E0303 +arc: S3_V06S0003 W3_H06E0003 +arc: W1_H02W0001 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 +arc: A0 V02N0701 +arc: A1 V01N0101 +arc: A6 S1_V02N0101 +arc: A7 H02W0701 +arc: B0 V00B0000 +arc: B1 V02S0101 +arc: B6 V01S0000 +arc: B7 V00B0100 +arc: C6 V02N0201 +arc: C7 V02N0001 +arc: CE0 H00L0000 +arc: CE2 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: D6 H00R0100 +arc: D7 V01N0001 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q0 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0101 Q1 +arc: V01S0000 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1100101010101010 +word: SLICED.K1.INIT 1110110001001100 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R28C22:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 H02E0601 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0501 H02E0501 +arc: V00B0100 V02S0101 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0701 V02N0701 +arc: A2 S1_V02N0701 +arc: A3 V02N0701 +arc: A4 N1_V01S0100 +arc: A5 V02N0101 +arc: B2 H00R0100 +arc: B3 S1_V02N0301 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: C2 S1_V02N0401 +arc: C3 H00L0000 +arc: C4 V02N0201 +arc: C5 V02N0001 +arc: CE0 H00R0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 S1_V02N0601 +arc: D5 V00B0000 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F4 +arc: H01W0100 F5 +arc: M0 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: V00B0000 Q6 +arc: W1_H02W0001 F2 +arc: W1_H02W0101 F3 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1011100011110000 +word: SLICEB.K1.INIT 1110010011001100 +word: SLICEC.K0.INIT 1011111110000000 +word: SLICEC.K1.INIT 1111100001110000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R28C23:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0401 N1_V01S0000 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0000 H02E0601 +arc: V00B0100 V02N0101 +arc: V00T0100 V02N0701 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 S1_V02N0601 +arc: A7 N1_V02S0301 +arc: B0 W1_H02E0301 +arc: B3 H02E0301 +arc: C0 F6 +arc: C1 E1_H01W0000 +arc: C3 F6 +arc: C6 E1_H01E0101 +arc: C7 V02S0201 +arc: CE1 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D1 H00R0000 +arc: D3 V00B0100 +arc: D7 V02S0401 +arc: E1_H01E0101 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F5D_SLICE +arc: M4 V00T0100 +arc: M6 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0301 Q3 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F1 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000111100001111 +word: SLICED.K1.INIT 0000000000000101 +word: SLICEA.K0.INIT 0000001100000011 +word: SLICEA.K1.INIT 0000000000001111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1100110000001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 + +.tile R28C24:PLC2 +arc: H00R0100 H02E0501 +arc: N1_V02N0201 V01N0001 +arc: S1_V02S0501 H06E0303 +arc: V00B0100 H02E0701 +arc: V00T0000 V02N0601 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 S3_V06N0103 +arc: B3 F1 +arc: B7 V02S0701 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0601 +arc: C3 H02E0401 +arc: C7 V02N0201 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D1 V01S0100 +arc: D3 V00B0100 +arc: D7 F2 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: M2 V00T0000 +arc: MUXCLK3 CLK0 +arc: N1_V02N0701 Q7 +word: SLICEB.K0.INIT 0000111100001111 +word: SLICEB.K1.INIT 0000000000000011 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1100000011001111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R28C2:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 S1_V02N0301 +arc: H00R0100 V02S0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 S1_V02N0301 +arc: V00T0100 H02W0301 +arc: A1 H02E0501 +arc: A7 S1_V02N0301 +arc: B1 H02W0101 +arc: B7 F1 +arc: CE0 V02N0201 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D1 V02S0201 +arc: D6 S1_V02N0601 +arc: D7 H01W0000 +arc: E3_H06E0303 Q6 +arc: F1 F1_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q1 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0103 F1 +word: SLICED.K0.INIT 1111111100000000 +word: SLICED.K1.INIT 1110111001000100 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1101110110001000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R28C3:PLC2 +arc: E1_H02E0601 E1_H01W0000 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0701 H02W0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 V02S0301 + +.tile R28C4:PLC2 +arc: E1_H02E0001 V06S0003 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 S3_V06N0203 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 V02S0701 +arc: W1_H02W0701 V06S0203 +arc: B2 E1_H01W0100 +arc: C2 S1_V02N0401 +arc: CE0 H02W0101 +arc: CE1 H00R0100 +arc: CE2 H02W0101 +arc: CLK0 G_HPBX0100 +arc: D2 W1_H02E0001 +arc: D3 S1_V02N0201 +arc: E3_H06E0003 Q0 +arc: F2 F5B_SLICE +arc: H01W0000 Q2 +arc: M0 H02E0601 +arc: M2 V00T0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0001 Q2 +arc: S1_V02S0601 Q4 +arc: S3_V06S0203 Q4 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1100110011110000 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R28C5:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 E1_H02W0101 +arc: A1 V02S0701 +arc: B0 E1_H01W0100 +arc: B1 H02W0101 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: CE0 H00R0100 +arc: CE1 E1_H02W0101 +arc: CE2 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D0 V00T0100 +arc: D1 V01S0100 +arc: E1_H02E0101 Q1 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q4 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0101 Q1 +arc: S3_V06S0103 Q2 +arc: V01S0100 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 1111111000010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R28C6:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0100 E1_H02W0101 +arc: H00R0000 H02W0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0001 W1_H02E0001 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0601 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0501 E1_H02W0501 +arc: A2 H00L0100 +arc: B2 E1_H01W0100 +arc: C2 S1_V02N0601 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D3 E1_H02W0201 +arc: F2 F5B_SLICE +arc: H01W0100 Q6 +arc: M0 V00T0100 +arc: M2 V00T0000 +arc: M4 H02W0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0001 Q2 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q0 +arc: S1_V02S0201 Q0 +arc: S3_V06S0203 Q4 +arc: W1_H02W0201 Q2 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1110010011100100 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R28C7:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 H06E0003 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 N1_V01S0100 +arc: E3_H06E0003 W3_H06E0303 +arc: A0 H00L0100 +arc: A1 N1_V02S0501 +arc: A2 N1_V02S0701 +arc: B0 E1_H02W0101 +arc: B1 F3 +arc: B2 H00R0100 +arc: B3 V02S0301 +arc: C0 H00L0000 +arc: C1 E1_H02W0401 +arc: C2 H02W0401 +arc: C3 H02E0601 +arc: CE0 H00R0000 +arc: CE2 H00R0000 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: D0 S1_V02N0201 +arc: D1 F0 +arc: D2 N1_V02S0201 +arc: D3 F2 +arc: E1_H01E0101 Q4 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q4 +arc: M4 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 F3 +arc: N1_V02N0101 Q1 +arc: S3_V06S0303 Q6 +arc: W1_H02W0401 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000001 +word: SLICEA.K1.INIT 0000010000000000 +word: SLICEB.K0.INIT 0000000000100000 +word: SLICEB.K1.INIT 0000001100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R28C8:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0100 H02E0101 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 E3_H06W0003 +arc: V00B0100 V02N0301 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: E3_H06E0303 W3_H06E0303 +arc: W3_H06W0003 E3_H06W0003 +arc: A1 E1_H01E0001 +arc: A2 H02E0701 +arc: A5 V02S0301 +arc: A7 S1_V02N0101 +arc: B2 H00R0100 +arc: B4 H02E0301 +arc: B5 F1 +arc: B6 H02E0301 +arc: C1 S1_V02N0601 +arc: C2 H02E0601 +arc: C3 S1_V02N0601 +arc: C4 E1_H02W0601 +arc: C5 F6 +arc: C6 E1_H01E0101 +arc: CLK0 G_HPBX0100 +arc: D1 N1_V02S0001 +arc: D2 V00T0100 +arc: D3 F2 +arc: D4 H01W0000 +arc: D5 H00L0100 +arc: D6 V02S0601 +arc: D7 V02S0601 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q5 +arc: E3_H06E0003 Q3 +arc: E3_H06E0203 F4 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q5 +arc: H01W0100 F2 +arc: LSR1 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N3_V06N0103 F2 +word: SLICEC.K0.INIT 1100000000000000 +word: SLICEC.K1.INIT 0100111011001100 +word: SLICEB.K0.INIT 1111100011110000 +word: SLICEB.K1.INIT 0000111100000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000011111010 +word: SLICED.K0.INIT 0011111111111111 +word: SLICED.K1.INIT 1010101000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET SET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R28C9:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0000 V02S0201 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 W1_H02E0701 +arc: N3_V06N0003 E1_H01W0000 +arc: N3_V06N0203 S1_V02N0701 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H06W0303 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 V02S0001 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 W1_H02E0501 +arc: A1 W1_H02E0501 +arc: A7 H00R0000 +arc: B0 V00B0000 +arc: B1 E1_H02W0301 +arc: C0 S1_V02N0401 +arc: C1 H00L0000 +arc: C7 H02W0601 +arc: CE1 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 N1_V01S0000 +arc: D1 F0 +arc: D7 V02N0401 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 F0 +arc: E1_H02E0701 F7 +arc: E3_H06E0003 F0 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: M2 V00T0000 +arc: MUXCLK1 CLK0 +arc: N1_V02N0001 F0 +arc: S1_V02S0201 Q2 +arc: S3_V06S0003 F0 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 F7 +arc: V01S0000 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000010100000 +word: SLICEA.K0.INIT 0100010001000000 +word: SLICEA.K1.INIT 0001001101011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R29C10:PLC2 +arc: E1_H02E0501 V02N0501 +arc: H00L0000 H02W0001 +arc: H00L0100 V02N0301 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 V01N0101 +arc: S1_V02S0201 W1_H02E0201 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 H01E0001 +arc: E3_H06E0303 W3_H06E0303 +arc: A0 V02S0701 +arc: A1 W1_H02E0701 +arc: B2 F3 +arc: C0 H00L0000 +arc: C1 E1_H02W0601 +arc: C2 N1_V02S0601 +arc: C3 H02W0401 +arc: CE0 H00L0100 +arc: CE1 V02N0201 +arc: CE2 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D0 H02E0001 +arc: D1 H02W0001 +arc: D2 E1_H02W0001 +arc: D3 H00R0000 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 Q2 +arc: E1_H02E0301 F3 +arc: E1_H02E0601 Q6 +arc: E3_H06E0003 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 F1 +arc: H01W0100 Q1 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F3 +arc: N3_V06N0003 F0 +arc: N3_V06N0103 Q2 +arc: S1_V02S0401 Q4 +arc: S3_V06S0203 Q4 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F1 +arc: W3_H06W0303 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111000011111100 +word: SLICEB.K1.INIT 0000000000001111 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R29C11:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 N3_V06S0103 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02N0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0103 N1_V02S0101 +arc: V00B0000 H02W0401 +arc: V00B0100 H02W0501 +arc: V00T0000 H02E0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0401 E1_H02W0101 +arc: W1_H02W0601 E1_H02W0301 +arc: W1_H02W0701 N3_V06S0203 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0301 W3_H06E0003 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 E1_H02W0701 +arc: A3 N1_V02S0701 +arc: A5 V00B0000 +arc: A6 V02N0101 +arc: B0 E1_H02W0301 +arc: B1 V00T0000 +arc: B5 H02W0301 +arc: B7 W1_H02E0301 +arc: C0 H00L0100 +arc: C1 S1_V02N0601 +arc: C2 H00L0000 +arc: C3 N1_V01N0001 +arc: C5 E1_H02W0601 +arc: C6 F4 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D0 N1_V01S0000 +arc: D1 H02W0201 +arc: D2 V02N0201 +arc: D3 V02N0001 +arc: D5 E1_H02W0201 +arc: D6 F2 +arc: E1_H01E0101 F3 +arc: E1_H02E0201 F0 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F1 +arc: H01W0100 F3 +arc: M4 V00B0100 +arc: M6 V00T0100 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V02N0301 F1 +arc: W3_H06W0003 F3 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0110101110110000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 0011001100001111 +word: SLICED.K0.INIT 1111101011110000 +word: SLICED.K1.INIT 0011001100110011 +word: SLICEB.K0.INIT 1111010110100000 +word: SLICEB.K1.INIT 1111000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R29C12:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0701 S3_V06N0203 +arc: E3_H06E0303 W1_H02E0601 +arc: H00L0000 H02E0201 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 H02E0601 +arc: H00R0100 V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 S3_V06N0303 +arc: S3_V06S0003 N1_V02S0001 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 V01N0101 +arc: S3_V06S0103 W3_H06E0103 +arc: E3_H06E0003 W3_H06E0303 +arc: A2 W1_H02E0501 +arc: A3 E1_H02W0701 +arc: A4 N1_V01N0101 +arc: A5 V02N0301 +arc: A6 H02W0701 +arc: A7 H02E0501 +arc: B1 N1_V02S0101 +arc: B2 H02W0101 +arc: B3 F1 +arc: B4 E1_H02W0301 +arc: B5 W1_H02E0301 +arc: B7 V00B0100 +arc: C1 H02W0401 +arc: C2 H00L0000 +arc: C3 E1_H02W0601 +arc: C4 E1_H02W0401 +arc: C5 S1_V02N0001 +arc: C6 N1_V02S0201 +arc: C7 F6 +arc: CE0 H00R0000 +arc: CE1 H00R0100 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D1 E1_H02W0001 +arc: D2 V00T0100 +arc: D3 V02N0201 +arc: D4 V02S0401 +arc: D5 V00B0000 +arc: D6 H00L0100 +arc: D7 S1_V02N0601 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F5 +arc: V00B0000 F4 +arc: V00T0100 F3 +arc: W1_H02W0601 Q6 +arc: W1_H02W0701 F7 +arc: W3_H06W0103 Q2 +word: SLICEB.K0.INIT 0000110000011101 +word: SLICEB.K1.INIT 0111001010111011 +word: SLICEC.K0.INIT 1001010001001111 +word: SLICEC.K1.INIT 0000110010001100 +word: SLICED.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 0110111101001101 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1100111111000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 + +.tile R29C13:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 V02N0301 +arc: H00R0000 V02N0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0701 H02E0701 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 V06N0203 +arc: E1_H02E0201 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 +arc: A0 H02E0701 +arc: A1 H00L0000 +arc: A2 S1_V02N0701 +arc: A3 V02N0501 +arc: A5 V02N0301 +arc: A6 V02S0101 +arc: A7 W1_H02E0701 +arc: B0 H02W0301 +arc: B1 H02E0301 +arc: B2 N1_V02S0101 +arc: B3 N1_V02S0301 +arc: B6 H02W0101 +arc: B7 E1_H02W0101 +arc: C0 N1_V01S0100 +arc: C1 H02W0401 +arc: C2 V02S0401 +arc: C4 W1_H02E0401 +arc: C5 E1_H02W0401 +arc: C7 F6 +arc: CE1 H00R0100 +arc: CE2 H00R0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D0 N1_V02S0201 +arc: D1 N1_V01S0000 +arc: D2 H02E0001 +arc: D3 F2 +arc: D5 N1_V02S0601 +arc: D6 H00L0100 +arc: D7 V01N0001 +arc: E1_H02E0101 Q3 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M4 V00T0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q4 +arc: N3_V06N0203 Q4 +arc: V01S0000 Q7 +arc: W1_H02W0001 F0 +word: SLICEA.K0.INIT 1001010001001111 +word: SLICEA.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 0101010100110011 +word: SLICED.K1.INIT 1111001111100010 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 0000010110101111 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 0100010011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 + +.tile R29C14:PLC2 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 N1_V01S0000 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: V00T0000 H02E0001 +arc: V00T0100 V02S0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 V02N0701 +arc: N1_V02N0301 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: A0 H00R0000 +arc: A1 E1_H02W0701 +arc: A2 V00B0000 +arc: A3 H02W0501 +arc: A4 V00T0100 +arc: A5 V02N0301 +arc: A6 V02S0301 +arc: A7 V02N0301 +arc: B0 H02W0301 +arc: B1 V02N0301 +arc: B2 H00R0100 +arc: B3 V02N0301 +arc: B4 S1_V02N0701 +arc: B6 H02E0301 +arc: C0 V02S0401 +arc: C2 V02S0401 +arc: C4 H02W0601 +arc: C5 E1_H02W0401 +arc: C6 V00B0100 +arc: C7 F6 +arc: CE0 V02N0201 +arc: CE1 V02N0201 +arc: CE2 V02N0601 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0100 +arc: D0 E1_H02W0201 +arc: D1 F0 +arc: D2 E1_H02W0201 +arc: D3 F2 +arc: D4 V02S0401 +arc: D5 H01W0000 +arc: D6 S1_V02N0401 +arc: D7 H02W0001 +arc: E1_H01E0101 Q1 +arc: E1_H02E0101 Q3 +arc: E1_H02E0701 Q7 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N3_V06N0203 Q7 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q7 +arc: W3_H06W0303 Q5 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 1010000011110101 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 1000100010111011 +word: SLICEB.K0.INIT 1000110010101111 +word: SLICEB.K1.INIT 1011101110001000 +word: SLICED.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 1010111100000101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R29C15:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0103 V01N0101 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 N1_V01S0000 +arc: S1_V02S0701 W3_H06E0203 +arc: A2 F7 +arc: A5 H02E0501 +arc: A6 W1_H02E0501 +arc: A7 E1_H02W0701 +arc: B2 H02W0301 +arc: B3 S1_V02N0301 +arc: B5 V01S0000 +arc: B7 W1_H02E0101 +arc: C2 H00L0100 +arc: C3 H02E0401 +arc: C4 W1_H02E0401 +arc: C5 V00B0100 +arc: C6 V02N0201 +arc: C7 V00T0100 +arc: CE1 H00R0000 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D2 V02N0001 +arc: D3 V01S0100 +arc: D4 E1_H02W0201 +arc: D5 S1_V02N0401 +arc: D7 V00B0000 +arc: E1_H01E0001 Q6 +arc: E1_H02E0601 Q4 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F2 +arc: H01W0100 Q4 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F5 +arc: V00B0000 Q6 +arc: V01S0000 Q4 +arc: V01S0100 Q6 +arc: W3_H06W0003 Q3 +word: SLICEB.K0.INIT 0010111011001111 +word: SLICEB.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1010000010100000 +word: SLICED.K1.INIT 1001010001110011 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1000011000111011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 + +.tile R29C16:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 V02S0201 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: E1_H02E0301 W3_H06E0003 +arc: S1_V02S0601 W3_H06E0303 +arc: W1_H02W0001 W3_H06E0003 +arc: A0 E1_H02W0701 +arc: A6 E1_H02W0701 +arc: A7 V00T0100 +arc: B0 H01W0100 +arc: B1 H02E0301 +arc: B6 V00B0100 +arc: B7 S1_V02N0501 +arc: C0 H02W0601 +arc: C1 H02E0401 +arc: C6 V00T0000 +arc: C7 H02E0401 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 V00B0100 +arc: D1 H02E0201 +arc: D6 H00L0100 +arc: D7 H02E0201 +arc: E1_H01E0001 Q4 +arc: E3_H06E0003 F0 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q7 +arc: H01W0100 Q1 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q1 +arc: N1_V02N0501 Q7 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q7 +arc: S3_V06S0203 Q7 +arc: V00B0100 Q7 +arc: V00T0000 Q2 +arc: V01S0000 Q7 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1010101011100010 +word: SLICED.K1.INIT 1010000011100100 +word: SLICEA.K0.INIT 1011100010101010 +word: SLICEA.K1.INIT 0000000000110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R29C17:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02E0401 +arc: V00T0000 H02E0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02S0501 +arc: A2 V00T0000 +arc: A3 V02S0701 +arc: A5 V00B0000 +arc: A6 H00L0000 +arc: B2 H00R0100 +arc: B4 W1_H02E0101 +arc: B7 E1_H02W0101 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: N1_V01N0001 F3 +arc: N3_V06N0303 F6 +arc: W1_H02W0001 F2 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R29C18:PLC2 +arc: E1_H02E0301 V01N0101 +arc: H00L0000 N1_V02S0001 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 W1_H02E0601 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0701 N3_V06S0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: A1 W1_H02E0501 +arc: A2 V00B0000 +arc: A3 H02E0501 +arc: A4 H02E0701 +arc: A7 H00L0000 +arc: B0 H02E0101 +arc: B5 H02E0301 +arc: B6 S1_V02N0501 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F7 +arc: N1_V01N0001 F1 +arc: N1_V02N0001 F2 +arc: V01S0000 F6 +arc: W1_H02W0101 F3 +arc: W1_H02W0501 F5 +arc: W3_H06W0203 F4 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R29C19:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V01N0101 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0301 N1_V01S0100 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: W1_H02W0101 E1_H01W0100 +arc: A0 V02N0501 +arc: A4 S1_V02N0301 +arc: A6 V02N0301 +arc: B1 H02E0301 +arc: B2 V01N0001 +arc: B3 N1_V02S0301 +arc: B5 S1_V02N0501 +arc: B7 S1_V02N0701 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: S1_V02S0401 F4 +arc: S1_V02S0501 F7 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F5 +arc: V01S0000 F0 +arc: V01S0100 F2 +arc: W1_H02W0301 F3 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R29C20:PLC2 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0501 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0701 S3_V06N0203 +arc: H01W0100 W3_H06E0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 W3_H06E0203 +arc: W1_H02W0401 W3_H06E0203 +arc: A2 V02N0501 +arc: A3 V01N0101 +arc: A4 H02E0701 +arc: A5 H02W0501 +arc: A6 V02N0301 +arc: A7 H02W0701 +arc: B0 H02E0101 +arc: B1 V01N0001 +arc: E1_H02E0501 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: N1_V02N0501 F7 +arc: S1_V02S0201 F0 +arc: S1_V02S0301 F1 +arc: S1_V02S0601 F6 +arc: V01S0000 F2 +arc: V01S0100 F3 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R29C21:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0000 H02W0401 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0401 W1_H02E0401 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 V02N0301 +arc: V00T0000 V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 N1_V02S0701 +arc: E1_H02E0101 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: E3_H06E0103 W3_H06E0103 +arc: A6 E1_H01W0000 +arc: A7 H00R0000 +arc: B6 V01S0000 +arc: B7 H02W0101 +arc: C6 H02W0401 +arc: C7 V01N0101 +arc: CE1 H00R0100 +arc: CE2 V02N0601 +arc: CLK0 G_HPBX0100 +arc: D6 S1_V02N0601 +arc: D7 V02N0401 +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F6 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q4 +arc: V01S0000 Q2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1101111110000000 +word: SLICED.K1.INIT 1111011110000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R29C22:PLC2 +arc: E1_H02E0601 N3_V06S0303 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 V02N0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0701 V01N0101 +arc: H01W0000 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0701 W3_H06E0203 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S1_V02S0701 W3_H06E0203 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 +arc: A3 H02E0501 +arc: B0 V00B0000 +arc: B1 E1_H01W0100 +arc: B4 H02W0301 +arc: B5 F3 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C5 H02W0401 +arc: C7 V02N0201 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D3 V02N0001 +arc: D5 H02W0201 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: M4 V00B0100 +arc: MUXCLK3 CLK0 +arc: N1_V02N0501 Q7 +arc: V00B0000 F4 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F1 +word: SLICEC.K0.INIT 0011001100110011 +word: SLICEC.K1.INIT 0000000000000011 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1100000011110011 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1010101000000000 +word: SLICEA.K0.INIT 0000001100000011 +word: SLICEA.K1.INIT 0000001100000011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R29C23:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0701 N1_V02S0701 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 V01N0001 +arc: V00B0100 H02W0701 +arc: V00T0100 S1_V02N0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 N1_V02S0401 +arc: A3 N1_V02S0701 +arc: B3 F1 +arc: B7 W1_H02E0101 +arc: C1 E1_H01W0000 +arc: C7 V00T0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D1 V00B0100 +arc: D2 S1_V02N0001 +arc: D3 V02S0201 +arc: D7 F2 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M2 H02E0601 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICEB.K1.INIT 0000000000010001 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1100000011110011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R29C24:PLC2 +arc: H00R0100 V02S0501 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0601 W1_H02E0601 +arc: V00B0000 W1_H02E0601 +arc: W1_H02W0701 N1_V01S0100 +arc: E1_H01E0001 W3_H06E0003 +arc: H01W0000 W3_H06E0103 +arc: A1 E1_H01E0001 +arc: A5 H02E0701 +arc: B3 H02E0101 +arc: B5 F1 +arc: C1 N1_V01S0100 +arc: C3 F4 +arc: C4 S1_V02N0201 +arc: CE1 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D3 V02N0001 +arc: D5 H02E0201 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: M4 V00B0000 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q3 +arc: W1_H02W0401 F4 +word: SLICEC.K0.INIT 0000111100001111 +word: SLICEC.K1.INIT 0000000000010001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1100111100000011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1010000010100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R29C2:PLC2 +arc: H00L0000 S1_V02N0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 V01N0001 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0301 E1_H01W0100 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02N0201 +arc: V00T0000 H02W0201 +arc: A3 V01N0101 +arc: A5 N1_V01N0101 +arc: B3 H01W0100 +arc: B5 S1_V02N0501 +arc: C3 S1_V02N0601 +arc: C5 S1_V02N0201 +arc: CE0 H00L0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D3 S1_V02N0201 +arc: D5 V02N0401 +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: H01W0100 Q0 +arc: M0 H02W0601 +arc: M2 V00B0000 +arc: M4 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q6 +arc: N1_V02N0001 Q2 +arc: N1_V02N0601 Q4 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1110110010100000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1110110010100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R29C3:PLC2 +arc: H00R0100 V02S0701 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0301 N1_V02S0301 +arc: V00B0000 V02N0001 +arc: V00T0000 V02N0401 +arc: CE1 E1_H02W0101 +arc: CE2 H00R0100 +arc: CE3 E1_H02W0101 +arc: CLK0 G_HPBX0100 +arc: E3_H06E0203 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q6 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: M6 H02W0401 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0203 Q4 +arc: W1_H02W0201 Q2 +arc: W1_H02W0601 Q6 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R29C4:PLC2 +arc: E3_H06E0303 V06S0303 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 V01N0001 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0401 V02S0401 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0601 Q4 +arc: LSR0 V00B0100 +arc: M4 H02W0401 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR0 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R29C5:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0601 E3_H06W0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0201 E1_H02W0201 +arc: V00B0100 V02N0101 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 E1_H02W0101 +arc: A1 S1_V02N0501 +arc: B1 S1_V02N0101 +arc: C1 H02E0601 +arc: CE1 S1_V02N0201 +arc: CE2 E1_H02W0101 +arc: CE3 E1_H02W0101 +arc: CLK0 G_HPBX0100 +arc: D1 V01S0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 Q4 +arc: F0 F5A_SLICE +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: M4 E1_H02W0401 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0203 Q4 +arc: V00B0000 Q6 +arc: V01S0100 Q2 +arc: W1_H02W0401 Q6 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1110110010100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R29C6:PLC2 +arc: E1_H02E0001 V02N0001 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0701 E1_H01W0100 +arc: V01S0000 S3_V06N0103 +arc: A2 E1_H01E0001 +arc: A3 E1_H02W0701 +arc: B1 S1_V02N0301 +arc: B2 F3 +arc: B3 S1_V02N0101 +arc: B5 S1_V02N0701 +arc: C1 V02N0401 +arc: C5 V01N0101 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CE2 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D1 H02E0001 +arc: D2 V02N0001 +arc: D3 V02S0001 +arc: D5 S1_V02N0601 +arc: E1_H01E0001 Q3 +arc: E1_H02E0101 Q1 +arc: E1_H02E0301 F1 +arc: E3_H06E0103 F2 +arc: E3_H06E0303 Q6 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0401 Q6 +arc: N3_V06N0103 F1 +arc: N3_V06N0303 F5 +arc: S1_V02S0501 F5 +arc: V00T0100 F3 +arc: V01S0100 Q5 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0101010100110011 +word: SLICEB.K1.INIT 1011101110001000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111001111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 + +.tile R29C7:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 S1_V02N0601 +arc: H00L0100 H02E0101 +arc: H00R0000 V02N0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0401 V01N0001 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 N1_V02S0401 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0501 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 S1_V02N0501 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: B0 V02S0101 +arc: B3 H02E0301 +arc: C1 W1_H02E0601 +arc: C3 H00L0100 +arc: CE0 H00R0000 +arc: CE1 S1_V02N0201 +arc: CE2 H00R0100 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0100 +arc: D0 H02W0201 +arc: D1 V02N0001 +arc: D2 N1_V01S0000 +arc: D3 H02E0001 +arc: E1_H01E0001 F0 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H01W0000 F0 +arc: H01W0100 Q0 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0003 F0 +arc: N3_V06N0103 F1 +arc: N3_V06N0203 Q4 +arc: S1_V02S0001 Q2 +arc: S1_V02S0601 Q6 +arc: S3_V06S0103 Q1 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0401 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 1111010110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R29C8:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0003 N3_V06S0003 +arc: E3_H06E0103 V06S0103 +arc: H00R0100 V02N0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 H01E0001 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 S3_V06N0203 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 S1_V02N0701 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A4 V02N0101 +arc: B2 E1_H01W0100 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V01N0101 +arc: C5 H02E0601 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0100 +arc: D2 V00B0100 +arc: D3 S1_V02N0001 +arc: D4 E1_H01W0100 +arc: E1_H02E0301 Q3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q0 +arc: M0 E1_H02W0601 +arc: M4 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q3 +arc: S3_V06S0003 Q0 +arc: S3_V06S0303 Q6 +arc: V00T0000 Q2 +arc: W1_H02W0601 Q4 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1100110011001010 +word: SLICEB.K1.INIT 1111101000001010 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEC.K1.INIT 1111000011110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R29C9:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 V01N0001 +arc: S1_V02S0401 N1_V01S0000 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0601 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 N3_V06S0203 +arc: A2 V02S0701 +arc: A7 N1_V02S0301 +arc: B2 V02S0101 +arc: B3 W1_H02E0301 +arc: B7 V01S0000 +arc: C2 V02S0401 +arc: C3 H00L0000 +arc: C7 W1_H02E0401 +arc: CE0 H00R0100 +arc: CE2 V02N0601 +arc: CLK0 G_HPBX0100 +arc: D2 S1_V02N0001 +arc: D3 V02S0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q0 +arc: E1_H02E0301 F3 +arc: E3_H06E0203 F7 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q0 +arc: H01W0100 Q4 +arc: M0 V00B0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0301 F3 +arc: W1_H02W0201 Q2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1100100011001100 +word: SLICEB.K0.INIT 1110110010100000 +word: SLICEB.K1.INIT 0000110011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R30C10:PLC2 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 H02E0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06W0003 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 H06E0303 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 E1_H02W0201 +arc: N3_V06N0303 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: A0 V02N0701 +arc: A1 S1_V02N0701 +arc: A5 E1_H02W0701 +arc: B0 V02N0101 +arc: B2 S1_V02N0101 +arc: B3 F1 +arc: B6 V02N0501 +arc: B7 V00B0000 +arc: C0 S1_V02N0401 +arc: C2 E1_H02W0601 +arc: C3 E1_H01W0000 +arc: C4 V02N0201 +arc: C5 V02S0201 +arc: C6 W1_H02E0401 +arc: C7 F6 +arc: CE0 H00R0000 +arc: CE1 H00R0100 +arc: CE2 H00L0100 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D0 H02E0201 +arc: D1 V01S0100 +arc: D2 S1_V02N0001 +arc: D3 F2 +arc: D4 H01W0000 +arc: D5 E1_H01W0100 +arc: D6 V02N0601 +arc: D7 E1_H02W0001 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 F1 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q5 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F5 +arc: N1_V02N0101 F3 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 Q5 +arc: V00B0000 Q6 +arc: V01S0100 Q0 +arc: W1_H02W0501 Q5 +arc: W3_H06W0303 F5 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 0000001100001111 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 0011001100001111 +word: SLICEA.K0.INIT 0100010000000100 +word: SLICEA.K1.INIT 1010101001010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R30C11:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 W1_H02E0601 +arc: H00L0000 H02E0201 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 V02S0401 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 S3_V06N0303 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0303 W3_H06E0303 +arc: W3_H06W0003 S3_V06N0003 +arc: A1 F7 +arc: A2 V02N0701 +arc: A3 W1_H02E0701 +arc: A5 V00T0000 +arc: A7 H00R0000 +arc: B0 E1_H02W0301 +arc: B1 V02N0101 +arc: B2 H02W0301 +arc: B3 W1_H02E0301 +arc: B5 V02N0501 +arc: B7 V02N0501 +arc: C0 H02W0401 +arc: C1 H00L0000 +arc: C2 N1_V02S0601 +arc: C3 W1_H02E0401 +arc: C5 H02W0601 +arc: C7 V02N0001 +arc: CE0 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 E1_H02W0201 +arc: D1 F0 +arc: D2 W1_H02E0001 +arc: D3 V00T0100 +arc: D5 V01N0001 +arc: D7 H00L0100 +arc: E1_H01E0101 F3 +arc: E1_H02E0301 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q0 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F1 +arc: S1_V02S0201 F2 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 0010110011101111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0110101110110000 +word: SLICEB.K0.INIT 0101111100011011 +word: SLICEB.K1.INIT 0000000000000100 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1001010001001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R30C12:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0203 S3_V06N0203 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02E0701 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0501 H06E0303 +arc: V00B0000 V02N0201 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0003 E3_H06W0303 +arc: A1 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A5 E1_H01W0000 +arc: B0 E1_H02W0101 +arc: B1 V00T0000 +arc: B4 E1_H02W0101 +arc: B5 H02E0101 +arc: B7 E1_H02W0301 +arc: C0 N1_V02S0401 +arc: C1 H00L0000 +arc: C4 H02W0401 +arc: C5 F4 +arc: C7 H02E0601 +arc: CE0 H02W0101 +arc: CE2 H00R0000 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0201 +arc: D3 W1_H02E0201 +arc: D4 V00B0000 +arc: D5 E1_H02W0201 +arc: D7 H02E0201 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H01W0000 F3 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F3 +arc: N1_V02N0001 Q0 +arc: N1_V02N0301 F3 +arc: N1_V02N0501 Q7 +arc: V01S0000 F1 +arc: W1_H02W0201 F0 +arc: W3_H06W0203 Q4 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 0011111110001011 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 0110111101001101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0101010100000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1100111111111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 + +.tile R30C13:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 W1_H02E0301 +arc: E3_H06E0103 S3_V06N0103 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0000 H02W0601 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02N0301 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S3_V06N0203 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0701 W3_H06E0203 +arc: N1_V02N0701 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W3_H06W0303 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0203 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02W0501 +arc: A3 H00L0100 +arc: A5 V00T0000 +arc: A6 N1_V01N0101 +arc: A7 E1_H01W0000 +arc: B0 H02E0101 +arc: B1 V00B0000 +arc: B5 V02S0701 +arc: B7 V01S0000 +arc: C0 F4 +arc: C1 E1_H02W0601 +arc: C3 S1_V02N0601 +arc: C5 E1_H02W0401 +arc: C6 V00B0100 +arc: C7 H02E0401 +arc: CE0 H00R0000 +arc: CE1 V02N0201 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 V00T0100 +arc: D1 S1_V02N0201 +arc: D3 V02S0001 +arc: D5 V02N0601 +arc: D7 V02N0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 F7 +arc: H01W0100 F3 +arc: M4 W1_H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F0 +arc: S3_V06S0003 Q3 +arc: V00T0100 F1 +arc: V01S0000 Q6 +arc: V01S0100 Q6 +arc: W1_H02W0401 Q6 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0101010001010000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0110100011011010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1010111110100000 +word: SLICED.K0.INIT 1010000010100000 +word: SLICED.K1.INIT 1001011100011001 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R30C14:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0203 V06S0203 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 H02E0401 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 S1_V02N0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: N1_V02N0101 W3_H06E0103 +arc: W3_H06W0003 S3_V06N0003 +arc: E3_H06E0303 W3_H06E0203 +arc: A1 W1_H02E0701 +arc: A5 V02N0101 +arc: A7 H00L0000 +arc: B1 F3 +arc: B2 F3 +arc: B3 H02W0301 +arc: B4 H02W0301 +arc: B5 H02W0301 +arc: C0 H00L0100 +arc: C3 H02E0601 +arc: C4 H02E0401 +arc: C5 H02E0601 +arc: C6 V00B0100 +arc: C7 F4 +arc: CE0 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 E1_H02W0001 +arc: D1 V02S0201 +arc: D2 V01S0100 +arc: D3 H00R0000 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 E1_H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F3 +arc: E1_H02E0101 Q1 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q1 +arc: H01W0100 F3 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: S1_V02S0201 F0 +arc: S1_V02S0401 F6 +arc: S1_V02S0701 Q7 +arc: V00B0100 Q7 +word: SLICEB.K0.INIT 0011001100000000 +word: SLICEB.K1.INIT 0000111100001100 +word: SLICEC.K0.INIT 1111110011111111 +word: SLICEC.K1.INIT 0000111000001111 +word: SLICEA.K0.INIT 0000111111110000 +word: SLICEA.K1.INIT 0010001011111111 +word: SLICED.K0.INIT 0000111111110000 +word: SLICED.K1.INIT 1010111100001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.B1MUX 1 + +.tile R30C15:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 S3_V06N0303 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 N1_V02S0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0601 S3_V06N0303 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 S1_V02N0601 +arc: E1_H01E0101 W3_H06E0203 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0303 S3_V06N0303 +arc: E3_H06E0203 W3_H06E0203 +arc: A0 V02S0501 +arc: A3 S1_V02N0701 +arc: A4 E1_H02W0501 +arc: A5 V00B0000 +arc: B0 N1_V02S0301 +arc: B3 N1_V02S0101 +arc: B4 H00R0000 +arc: B6 H01E0101 +arc: B7 V01S0000 +arc: C0 W1_H02E0401 +arc: C2 H00L0100 +arc: C4 V02N0201 +arc: C5 V00T0000 +arc: C6 H02E0401 +arc: CE0 S1_V02N0201 +arc: CE1 S1_V02N0201 +arc: CE2 H00L0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D0 N1_V02S0201 +arc: D2 H02W0001 +arc: D3 H01E0101 +arc: D4 E1_H02W0201 +arc: D5 W1_H02E0001 +arc: D6 S1_V02N0401 +arc: D7 H02W0001 +arc: E1_H01E0001 Q3 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0100 Q0 +arc: M0 H01E0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V02N0101 Q3 +arc: S1_V02S0401 Q4 +arc: S1_V02S0501 F7 +arc: V00B0000 Q4 +arc: V01S0000 Q6 +arc: V01S0100 F2 +arc: W1_H02W0201 Q0 +arc: W1_H02W0401 Q4 +arc: W3_H06W0203 Q4 +word: SLICEC.K0.INIT 1110110010100000 +word: SLICEC.K1.INIT 0000010111110101 +word: SLICEA.K0.INIT 1111100010001000 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0000111111110000 +word: SLICEB.K1.INIT 0011001110111011 +word: SLICED.K0.INIT 0011111100001111 +word: SLICED.K1.INIT 0011001111001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R30C16:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0303 H01E0101 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 V02S0701 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 S1_V02N0701 +arc: E1_H01E0001 W3_H06E0003 +arc: S1_V02S0001 W3_H06E0003 +arc: S3_V06S0203 W3_H06E0203 +arc: W3_H06W0303 S3_V06N0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0003 +arc: A0 V02N0501 +arc: A1 H00L0000 +arc: A4 V00T0000 +arc: A5 V00B0000 +arc: B1 E1_H02W0301 +arc: B4 H01E0101 +arc: C0 H02E0401 +arc: C1 N1_V02S0401 +arc: C4 V00T0100 +arc: C5 V02S0001 +arc: CE0 H00R0000 +arc: CE1 S1_V02N0201 +arc: CE2 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D0 H02E0201 +arc: D1 F0 +arc: D4 E1_H02W0201 +arc: D5 W1_H02E0201 +arc: E1_H01E0101 F0 +arc: E1_H02E0301 Q1 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q4 +arc: H01W0100 Q4 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F5 +arc: S1_V02S0701 F5 +arc: S3_V06S0003 F0 +arc: S3_V06S0103 Q2 +arc: V00B0000 Q4 +arc: V00T0000 F0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000101000000000 +word: SLICEA.K1.INIT 1110110010100000 +word: SLICEC.K0.INIT 1111100010001000 +word: SLICEC.K1.INIT 0000111101010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R30C17:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0103 H01E0101 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 E1_H01W0000 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0601 +arc: V00B0100 V02N0101 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 H01E0101 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0303 S3_V06N0303 +arc: A6 F7 +arc: B6 V00B0100 +arc: B7 E1_H02W0101 +arc: C6 H02E0401 +arc: CE1 H00R0100 +arc: CE2 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D6 V02N0401 +arc: D7 H02E0201 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 F6 +arc: E1_H02E0201 Q2 +arc: E1_H02E0501 F7 +arc: E1_H02E0601 F6 +arc: E1_H02E0701 F7 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 F6 +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F7 +arc: M2 V00T0000 +arc: M4 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F6 +arc: N3_V06N0203 F7 +arc: N3_V06N0303 F6 +arc: S3_V06S0203 F7 +arc: V01S0000 F7 +arc: V01S0100 F6 +arc: W1_H02W0601 F6 +arc: W1_H02W0701 F7 +arc: W3_H06W0203 F7 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0100110001000100 +word: SLICED.K1.INIT 0011001100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R30C18:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 V02S0201 +arc: H00L0000 H02E0201 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 W1_H02E0201 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0303 E1_H02W0601 +arc: A4 V00T0000 +arc: A5 H02E0701 +arc: A6 H00L0000 +arc: A7 H02E0701 +arc: B4 E1_H02W0301 +arc: B6 N1_V02S0501 +arc: B7 N1_V01S0000 +arc: C4 N1_V02S0001 +arc: C5 F4 +arc: C6 H02E0401 +arc: CE2 H00R0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D4 V02S0401 +arc: D5 V02S0601 +arc: D6 V02N0401 +arc: D7 V00B0000 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q7 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q5 +arc: S1_V02S0501 Q7 +arc: S3_V06S0303 Q5 +arc: V00B0000 F6 +arc: V01S0100 Q7 +word: SLICED.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 1000100011011101 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 1010111100000101 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R30C19:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 S3_V06N0003 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0401 +arc: W1_H02W0101 S1_V02N0101 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0601 W3_H06E0303 +arc: S1_V02S0401 W3_H06E0203 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0501 W3_H06E0303 +arc: W3_H06W0203 E1_H02W0701 +arc: W3_H06W0303 V06S0303 +arc: E3_H06E0003 W3_H06E0303 +arc: A0 N1_V02S0701 +arc: A1 W1_H02E0501 +arc: A2 H02W0501 +arc: A3 W1_H02E0501 +arc: A4 H02W0701 +arc: A5 W1_H02E0501 +arc: A6 H02W0701 +arc: A7 W1_H02E0501 +arc: B0 V00B0000 +arc: B2 H00R0000 +arc: B4 H00L0000 +arc: B5 N1_V01S0000 +arc: B6 V00B0100 +arc: C0 H02W0401 +arc: C1 V02S0601 +arc: C2 H02W0401 +arc: C3 N1_V01S0100 +arc: C4 V02N0201 +arc: C5 F4 +arc: C6 V02N0201 +arc: C7 V02S0001 +arc: CE0 H02E0101 +arc: CE1 H02E0101 +arc: CE2 H02E0101 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0100 +arc: D0 V02N0201 +arc: D1 F0 +arc: D2 V02N0201 +arc: D3 F2 +arc: D4 E1_H02W0201 +arc: D6 H02E0201 +arc: D7 H02W0001 +arc: E1_H01E0001 F6 +arc: E1_H02E0301 Q3 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q7 +arc: N1_V02N0301 Q1 +arc: N1_V02N0501 Q5 +arc: S1_V02S0501 Q7 +arc: S3_V06S0003 Q3 +arc: S3_V06S0303 Q5 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 1000110110001101 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 1010000011110101 +word: SLICED.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 1010000011110101 +word: SLICEA.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 1010000011110101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R30C20:PLC2 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 V06S0203 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E1_H01W0100 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 V02N0701 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0103 W3_H06E0103 +arc: W3_H06W0203 S3_V06N0203 +arc: A0 N1_V02S0701 +arc: A1 H00R0000 +arc: A2 N1_V02S0501 +arc: A3 H02E0701 +arc: A4 N1_V02S0301 +arc: A5 V02S0301 +arc: A6 V02S0101 +arc: B0 V02S0101 +arc: B2 H00L0000 +arc: B4 S1_V02N0701 +arc: B6 V00T0000 +arc: B7 N1_V01S0000 +arc: C0 E1_H01W0000 +arc: C1 V02N0401 +arc: C2 V02S0401 +arc: C3 N1_V01S0100 +arc: C4 V02N0201 +arc: C5 F4 +arc: C6 V02N0001 +arc: C7 F6 +arc: CE0 W1_H02E0101 +arc: CE1 W1_H02E0101 +arc: CE2 W1_H02E0101 +arc: CE3 W1_H02E0101 +arc: CLK0 G_HPBX0100 +arc: D0 H02E0201 +arc: D1 F0 +arc: D2 V02N0201 +arc: D3 F2 +arc: D4 V02S0401 +arc: D5 H02E0001 +arc: D6 H02E0201 +arc: D7 H02E0001 +arc: E3_H06E0003 Q3 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q3 +arc: N1_V02N0301 Q1 +arc: N1_V02N0501 Q7 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q5 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 1010000011110101 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 1010101000001111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 1100110000001111 +word: SLICEA.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 1010000010101111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R30C21:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0401 V02S0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 W1_H02E0301 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0100 +arc: H01W0000 Q2 +arc: M0 V00T0000 +arc: M2 E1_H02W0601 +arc: M4 V00B0100 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q6 +arc: W1_H02W0201 Q0 +arc: W1_H02W0401 Q4 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R30C22:PLC2 +arc: H00L0000 H02E0001 +arc: H00R0000 H02E0601 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0001 +arc: W1_H02W0401 V06N0203 +arc: N1_V02N0001 W3_H06E0003 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 +arc: A0 E1_H01E0001 +arc: A1 V02S0701 +arc: B0 V02S0101 +arc: B1 V02N0101 +arc: C0 V02S0401 +arc: C1 N1_V01N0001 +arc: CE1 H00L0000 +arc: CE2 H00R0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D0 H02W0201 +arc: D1 V02S0201 +arc: E1_H01E0001 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: M2 V00T0000 +arc: M4 H02E0401 +arc: M6 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 F0 +arc: W1_H02W0101 F1 +arc: W1_H02W0201 Q2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEA.K1.INIT 1110010011001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R30C23:PLC2 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0001 S3_V06N0003 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0601 W3_H06E0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 +arc: CE0 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0001 Q0 +arc: H01W0100 Q6 +arc: M0 H02W0601 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q2 +arc: V01S0100 Q4 +arc: W1_H02W0201 Q0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R30C24:PLC2 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0401 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: W1_H02W0601 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: M4 V00B0000 +arc: MUXCLK2 CLK0 +arc: N1_V02N0601 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R30C25:PLC2 +arc: S3_V06S0103 W3_H06E0103 + +.tile R30C2:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E3_H06E0203 V06S0203 +arc: H00R0000 V02N0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0101 E1_H01W0100 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0301 +arc: CE1 H00R0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: M2 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0401 Q6 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R30C3:PLC2 +arc: H00R0000 V02N0401 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0301 +arc: V00T0000 W1_H02E0201 +arc: A1 W1_H02E0501 +arc: B3 H02E0301 +arc: C1 H02W0601 +arc: C3 H00L0100 +arc: CE0 H02E0101 +arc: CE1 V02N0201 +arc: CE2 H00R0000 +arc: CE3 E1_H02W0101 +arc: CLK0 G_HPBX0100 +arc: D1 S1_V02N0001 +arc: D2 V01S0100 +arc: D3 V00T0100 +arc: E3_H06E0103 Q2 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q6 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0401 Q4 +arc: N3_V06N0103 F1 +arc: V00T0100 F1 +arc: V01S0100 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111010110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R30C4:PLC2 +arc: E1_H02E0401 V02S0401 +arc: E3_H06E0203 N3_V06S0203 +arc: H00L0000 H02W0201 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02N0601 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 S3_V06N0303 +arc: A4 V00T0100 +arc: B0 E1_H02W0301 +arc: B4 V01S0000 +arc: B5 H00L0000 +arc: C0 H00L0000 +arc: C1 V02N0401 +arc: C4 V00T0000 +arc: C5 V00T0000 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H02W0101 +arc: CLK0 G_HPBX0100 +arc: D0 V02N0001 +arc: D4 E1_H01W0100 +arc: D5 S1_V02N0401 +arc: E1_H02E0601 Q6 +arc: E3_H06E0303 Q5 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q4 +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q0 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: S1_V02S0601 Q6 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1111000011110000 +word: SLICEC.K0.INIT 1100110111001000 +word: SLICEC.K1.INIT 1111110000001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R30C5:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0701 V01N0101 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0301 E1_H02W0301 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 V02N0701 +arc: W1_H02W0101 E1_H02W0001 +arc: CE0 H00L0000 +arc: CE1 H00R0000 +arc: CE2 H00R0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 Q0 +arc: E3_H06E0303 Q6 +arc: H01W0000 Q4 +arc: H01W0100 Q2 +arc: M0 V00B0100 +arc: M2 H02W0601 +arc: M4 V00T0100 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V02N0401 Q4 +arc: S3_V06S0003 Q0 +arc: S3_V06S0303 Q6 +arc: W1_H02W0201 Q2 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R30C6:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0000 H02W0001 +arc: H00L0100 E1_H02W0301 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0003 E1_H01W0000 +arc: V00T0000 H02W0201 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 H01E0101 +arc: A1 V02N0701 +arc: A7 H02E0701 +arc: B7 H02E0101 +arc: C1 V02N0401 +arc: C7 E1_H01E0101 +arc: CE0 H00L0100 +arc: CE1 V02N0201 +arc: CE2 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D1 S1_V02N0201 +arc: D7 V01N0001 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 Q2 +arc: E1_H02E0401 Q6 +arc: F1 F1_SLICE +arc: F6 F5D_SLICE +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0101 F1 +arc: V00B0000 Q4 +arc: V01S0000 F1 +arc: V01S0100 Q1 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1110101011000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111101001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R30C7:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 E3_H06W0203 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 H02W0301 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 E1_H02W0501 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0103 E1_H01W0100 +arc: A1 V02N0501 +arc: A3 V02N0501 +arc: A5 H02E0501 +arc: B5 H02E0101 +arc: C1 S1_V02N0401 +arc: C3 N1_V02S0601 +arc: CE0 H00L0100 +arc: CE1 H00L0100 +arc: CE2 E1_H02W0101 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D1 H02W0201 +arc: D3 V02N0001 +arc: D4 H02E0001 +arc: D5 H02W0001 +arc: E1_H02E0401 Q4 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 Q6 +arc: H01W0100 F1 +arc: M4 V00B0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q3 +arc: N3_V06N0003 F3 +arc: S1_V02S0101 F3 +arc: S1_V02S0301 Q1 +arc: S3_V06S0203 Q4 +arc: S3_V06S0303 Q6 +arc: V01S0000 Q4 +arc: V01S0100 F1 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111111100000000 +word: SLICEC.K1.INIT 1100110010101010 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111010110100000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111010110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R30C8:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0103 N3_V06S0103 +arc: H00L0100 H02E0301 +arc: H00R0000 H02W0601 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 H06E0003 +arc: V00T0000 V02N0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0203 E1_H01W0000 +arc: E3_H06E0203 W3_H06E0203 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H02E0501 +arc: A3 H02E0501 +arc: A6 E1_H02W0501 +arc: A7 W1_H02E0701 +arc: B2 V02N0101 +arc: B3 W1_H02E0301 +arc: B6 V02S0501 +arc: C0 V02S0601 +arc: C1 S1_V02N0401 +arc: C2 V02N0601 +arc: C3 V02N0601 +arc: C6 E1_H01E0101 +arc: C7 V02S0001 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0000 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D0 S1_V02N0001 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0101 Q7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: M0 V00T0000 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q4 +arc: N3_V06N0003 Q3 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 F7 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 F6 +arc: W1_H02W0101 Q3 +arc: W1_H02W0401 F6 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011110000 +word: SLICED.K0.INIT 0000000100000000 +word: SLICED.K1.INIT 1010101011110000 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 1010101110101000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R30C9:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0601 E3_H06W0303 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0501 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 E3_H06W0303 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 H02E0601 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 E3_H06W0303 +arc: E1_H02E0201 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A5 S1_V02N0101 +arc: A6 H02E0701 +arc: A7 N1_V01S0100 +arc: B0 E1_H02W0301 +arc: B5 V01S0000 +arc: B7 E1_H02W0301 +arc: C0 E1_H02W0601 +arc: C4 V02N0201 +arc: C5 F4 +arc: C6 H02E0601 +arc: C7 E1_H02W0601 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 H00R0000 +arc: D1 V00B0100 +arc: D4 V02S0401 +arc: D5 E1_H02W0001 +arc: D6 V02S0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F4 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q6 +arc: M0 H02E0601 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q6 +arc: N3_V06N0303 F5 +arc: S3_V06S0203 Q7 +arc: V01S0000 Q2 +arc: V01S0100 Q2 +arc: W1_H02W0201 Q2 +arc: W3_H06W0003 Q0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEC.K1.INIT 0010000000000000 +word: SLICEA.K0.INIT 1111001111000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 1010111110100000 +word: SLICED.K1.INIT 1111000011100010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R31C10:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0100 V02N0301 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S1_V02N0201 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 S3_V06N0203 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 W3_H06E0103 +arc: A1 H02W0701 +arc: A2 S1_V02N0501 +arc: A3 V00B0000 +arc: A7 H00R0000 +arc: B1 H02E0101 +arc: B2 E1_H02W0101 +arc: B6 E1_H02W0101 +arc: C1 H02E0601 +arc: C3 H00L0000 +arc: C6 H02W0401 +arc: C7 F6 +arc: CE1 H00R0100 +arc: CE2 H00L0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D1 V00T0100 +arc: D2 H02W0201 +arc: D3 F2 +arc: D6 H01W0000 +arc: D7 V00B0000 +arc: E3_H06E0003 F3 +arc: E3_H06E0203 F7 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q6 +arc: H01W0000 Q0 +arc: M0 V00T0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0001 F2 +arc: N1_V02N0401 F6 +arc: S3_V06S0003 F3 +arc: S3_V06S0203 F7 +arc: V01S0100 Q4 +arc: W1_H02W0601 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1011101110001000 +word: SLICEB.K1.INIT 0000101001011111 +word: SLICED.K0.INIT 1111110000110000 +word: SLICED.K1.INIT 0101010100001111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111100010001000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R31C11:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0201 H02E0201 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0501 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V01N0101 +arc: H01W0000 W3_H06E0103 +arc: S1_V02S0301 W3_H06E0003 +arc: S1_V02S0501 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0101 W3_H06E0103 +arc: A1 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A5 N1_V01S0100 +arc: A7 N1_V01S0100 +arc: B0 E1_H01W0100 +arc: B1 H02E0301 +arc: B3 F1 +arc: B5 W1_H02E0301 +arc: B6 H02W0301 +arc: B7 W1_H02E0301 +arc: C0 H02W0601 +arc: C1 H00L0000 +arc: C3 H02E0601 +arc: C5 V00B0100 +arc: C6 H02W0601 +arc: C7 E1_H01E0101 +arc: CE2 V02S0601 +arc: CLK0 G_HPBX0100 +arc: D0 V02N0201 +arc: D1 W1_H02E0001 +arc: D3 V02S0001 +arc: D5 N1_V02S0601 +arc: D6 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q6 +arc: E1_H02E0101 F3 +arc: E1_H02E0601 Q4 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: W3_H06W0003 Q0 +arc: W3_H06W0303 Q6 +word: SLICED.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1100110010001100 +word: SLICEC.K0.INIT 1111111111111111 +word: SLICEC.K1.INIT 1110101011000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R31C12:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02N0401 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 V02N0701 +arc: A1 V02N0701 +arc: A2 V02N0701 +arc: A3 V02N0501 +arc: A4 V00T0000 +arc: A5 V02S0101 +arc: A7 V02N0301 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B2 H00L0000 +arc: B3 H00L0000 +arc: B4 H02E0301 +arc: B5 V00B0100 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 E1_H02W0401 +arc: C5 V00T0100 +arc: C7 E1_H01E0101 +arc: CLK1 G_HPBX0100 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D4 N1_V02S0601 +arc: D5 H00R0100 +arc: D7 V02N0601 +arc: E1_H01E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: LSR1 H02W0301 +arc: MUXCLK3 CLK1 +arc: S1_V02S0001 F0 +arc: W1_H02W0301 F1 +arc: W1_H02W0501 Q7 +arc: W3_H06W0203 Q7 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111000010101010 +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 + +.tile R31C13:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 W1_H02E0601 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 V02S0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 N1_V01S0100 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 N1_V01S0000 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0701 W3_H06E0203 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 W3_H06E0203 +arc: S3_V06S0003 W3_H06E0003 +arc: W1_H02W0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: A0 E1_H02W0501 +arc: A1 W1_H02E0701 +arc: A7 V02N0101 +arc: B0 S1_V02N0301 +arc: B1 W1_H02E0101 +arc: B3 V01N0001 +arc: C0 H02E0401 +arc: C3 F6 +arc: C6 W1_H02E0401 +arc: C7 F6 +arc: CE0 H00R0000 +arc: CE2 H00R0100 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D3 V02N0001 +arc: D6 V02N0401 +arc: D7 V00B0000 +arc: E1_H02E0301 Q1 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H01W0000 F0 +arc: H01W0100 Q6 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0303 Q6 +arc: S1_V02S0101 Q1 +arc: S1_V02S0301 Q1 +arc: S1_V02S0401 Q4 +arc: S1_V02S0501 F7 +arc: S3_V06S0303 F6 +arc: V00T0100 Q1 +arc: V01S0100 F6 +arc: W1_H02W0401 Q4 +arc: W3_H06W0303 Q6 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1000011000111011 +word: SLICEA.K1.INIT 1011101100110011 +word: SLICED.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 1111010101010101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0011111100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 + +.tile R31C14:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0003 H01E0001 +arc: H00R0000 H02W0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0303 V06N0303 +arc: A1 H02E0701 +arc: A2 V02S0701 +arc: A7 H02W0701 +arc: B1 V00B0000 +arc: B2 H02E0301 +arc: B5 H02E0301 +arc: B7 V02S0501 +arc: C0 N1_V01N0001 +arc: C1 W1_H02E0601 +arc: C2 H02E0601 +arc: C4 H02E0601 +arc: C6 V00B0100 +arc: CE0 H00R0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D0 E1_H02W0001 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0001 +arc: D6 E1_H02W0001 +arc: D7 H00R0100 +arc: E1_H02E0301 Q1 +arc: E1_H02E0701 Q7 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q7 +arc: H01W0100 Q1 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: S1_V02S0001 F2 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 F0 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 Q7 +arc: S3_V06S0103 Q1 +arc: V00B0100 Q7 +arc: V00T0100 Q1 +arc: V01S0000 F6 +arc: V01S0100 F4 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000111111110000 +word: SLICEA.K1.INIT 0001111100001111 +word: SLICEC.K0.INIT 0000111111110000 +word: SLICEC.K1.INIT 0011001111001100 +word: SLICED.K0.INIT 0000111111110000 +word: SLICED.K1.INIT 1101110101010101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C1MUX 1 + +.tile R31C15:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0601 V01N0001 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02E0601 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0701 N1_V01S0100 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 V06N0003 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 N1_V02S0701 +arc: E1_H02E0701 W3_H06E0203 +arc: E3_H06E0103 W3_H06E0003 +arc: A5 V02S0301 +arc: A7 N1_V02S0101 +arc: B2 V02N0301 +arc: B3 N1_V02S0101 +arc: B5 V02N0501 +arc: B7 V02S0701 +arc: C4 V00B0100 +arc: C7 V02S0201 +arc: CE0 H02W0101 +arc: CE2 V02S0601 +arc: CLK0 G_HPBX0100 +arc: D2 W1_H02E0001 +arc: D3 H02W0201 +arc: D4 H02W0201 +arc: D5 N1_V02S0401 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q5 +arc: E3_H06E0203 F7 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0001 F2 +arc: S1_V02S0101 F3 +arc: S1_V02S0401 F4 +arc: S3_V06S0003 Q0 +arc: V00B0100 Q5 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0011001111001100 +word: SLICEB.K1.INIT 0011001111001100 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 0000111111110000 +word: SLICEC.K1.INIT 0100010011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R31C16:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 H02E0601 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 S1_V02N0701 +arc: S1_V02S0001 W3_H06E0003 +arc: S3_V06S0203 W3_H06E0203 +arc: E3_H06E0203 W3_H06E0103 +arc: A0 H00R0000 +arc: A1 F5 +arc: A5 V02S0101 +arc: A6 E1_H02W0701 +arc: A7 V02S0301 +arc: B0 E1_H01W0100 +arc: B1 N1_V02S0101 +arc: B5 H02E0101 +arc: B6 V02S0501 +arc: B7 H01E0101 +arc: C0 S1_V02N0601 +arc: C1 E1_H01W0000 +arc: C2 V02S0601 +arc: C3 E1_H02W0601 +arc: C5 E1_H02W0401 +arc: C6 H01E0001 +arc: C7 V00T0100 +arc: D0 W1_H02E0001 +arc: D1 F0 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D5 V00B0000 +arc: D6 H02W0001 +arc: D7 H00R0100 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0601 F6 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 F7 +arc: V01S0100 F2 +word: SLICED.K0.INIT 1001011101000011 +word: SLICED.K1.INIT 1000010000100001 +word: SLICEB.K0.INIT 0000111111110000 +word: SLICEB.K1.INIT 0000111111110000 +word: SLICEA.K0.INIT 1000001001000001 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1001000000001001 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R31C17:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0203 N1_V01S0000 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0501 V02N0501 +arc: E1_H02E0401 W3_H06E0203 +arc: A0 H00R0000 +arc: A1 E1_H02W0501 +arc: A2 H02E0501 +arc: A3 F5 +arc: A4 V02S0101 +arc: A5 E1_H02W0501 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B2 F3 +arc: B3 H02E0101 +arc: B4 E1_H02W0101 +arc: B5 V01S0000 +arc: B7 V02N0701 +arc: C0 N1_V02S0601 +arc: C1 V02S0401 +arc: C2 N1_V01N0001 +arc: C3 V02N0401 +arc: C4 N1_V02S0001 +arc: C5 V00B0100 +arc: C7 E1_H02W0601 +arc: CE1 V02N0201 +arc: CE2 V02S0601 +arc: CLK0 G_HPBX0100 +arc: D0 W1_H02E0001 +arc: D1 V00B0100 +arc: D2 H02W0001 +arc: D3 H02E0001 +arc: D4 H02W0201 +arc: D5 S1_V02N0601 +arc: D7 H00R0100 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 Q4 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F7 +arc: N3_V06N0103 Q2 +arc: S1_V02S0401 Q4 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q4 +word: SLICEB.K0.INIT 0000111100010001 +word: SLICEB.K1.INIT 0010111011001111 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1000001101101011 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1111100010001000 +word: SLICEC.K1.INIT 1000011000111011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C18:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 N1_V01S0100 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 +arc: A3 V02N0701 +arc: A4 H02E0501 +arc: A5 H02E0701 +arc: A6 N1_V02S0301 +arc: B3 H00R0100 +arc: B4 H02E0301 +arc: B5 V02N0501 +arc: B6 H02W0301 +arc: B7 V00B0000 +arc: C3 H02W0401 +arc: C4 S1_V02N0201 +arc: C5 V02N0001 +arc: C6 V02N0201 +arc: C7 V00B0100 +arc: CE2 V02S0601 +arc: CE3 E1_H02W0101 +arc: CLK0 G_HPBX0100 +arc: D3 H00R0000 +arc: D4 E1_H02W0001 +arc: D5 S1_V02N0601 +arc: D6 H02E0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F3 +arc: E1_H02E0501 F7 +arc: E1_H02E0601 Q4 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 F5 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q4 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0303 Q6 +arc: S3_V06S0203 F7 +arc: V00B0000 Q6 +arc: W1_H02W0401 Q4 +word: SLICED.K0.INIT 1111111111001110 +word: SLICED.K1.INIT 0011001100001111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1001000000001001 +word: SLICEC.K0.INIT 1111100010001000 +word: SLICEC.K1.INIT 1000010101101101 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R31C19:PLC2 +arc: E1_H02E0301 V02N0301 +arc: H00L0000 H02W0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H06E0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 V02S0001 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H01W0100 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0501 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: S1_V02S0101 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0101 W3_H06E0103 +arc: A0 E1_H02W0501 +arc: A1 V02S0701 +arc: A2 H00L0100 +arc: A3 V02S0701 +arc: A4 H02W0501 +arc: A6 V02S0101 +arc: B0 V01N0001 +arc: B2 E1_H02W0301 +arc: B4 E1_H02W0101 +arc: B5 N1_V02S0701 +arc: B6 H02W0301 +arc: B7 N1_V02S0501 +arc: C0 S1_V02N0401 +arc: C1 H00L0000 +arc: C2 S1_V02N0401 +arc: C3 N1_V02S0401 +arc: C4 V02N0001 +arc: C5 F4 +arc: C6 V02N0001 +arc: C7 F6 +arc: CE0 W1_H02E0101 +arc: CE1 W1_H02E0101 +arc: CE2 V02S0601 +arc: CE3 W1_H02E0101 +arc: CLK0 G_HPBX0100 +arc: D0 V02N0201 +arc: D1 F0 +arc: D2 V02N0001 +arc: D3 F2 +arc: D4 S1_V02N0401 +arc: D5 H00R0100 +arc: D6 S1_V02N0401 +arc: D7 H00R0100 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q3 +arc: N1_V02N0501 Q5 +arc: N1_V02N0701 Q7 +word: SLICEB.K0.INIT 0001001101011111 +word: SLICEB.K1.INIT 1010000011110101 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 1100110000001111 +word: SLICED.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 1100110000001111 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 1010000011110101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R31C20:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 V02N0601 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 V06S0303 +arc: E1_H01E0001 W3_H06E0003 +arc: S3_V06S0103 W3_H06E0103 +arc: A3 E1_H01E0001 +arc: A4 E1_H01W0000 +arc: A6 V02S0101 +arc: A7 W1_H02E0701 +arc: B3 V02S0301 +arc: B4 W1_H02E0301 +arc: B6 H02E0301 +arc: B7 V01S0000 +arc: C3 H02W0401 +arc: C4 H02W0601 +arc: C6 N1_V02S0001 +arc: C7 V01N0101 +arc: CE0 H00R0000 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D3 H02E0201 +arc: D4 S1_V02N0601 +arc: D6 W1_H02E0201 +arc: D7 V02N0601 +arc: E1_H02E0401 Q6 +arc: E1_H02E0501 F7 +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: H01W0100 Q6 +arc: M0 V00B0100 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0401 Q4 +arc: V01S0000 Q6 +arc: V01S0100 Q3 +arc: W1_H02W0601 Q4 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1110101011000000 +word: SLICEC.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0011000010111010 +word: SLICED.K0.INIT 1111100010001000 +word: SLICED.K1.INIT 1001011101000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R31C21:PLC2 +arc: H00L0100 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 V02S0301 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 V06S0303 +arc: H01W0000 W3_H06E0103 +arc: W1_H02W0701 W3_H06E0203 +arc: CE0 H02E0101 +arc: CE1 H00L0100 +arc: CE2 H02E0101 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: H01W0100 Q2 +arc: M0 V00T0100 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0303 Q6 +arc: S3_V06S0103 Q2 +arc: V00B0000 Q4 +arc: V00T0000 Q0 +arc: W1_H02W0601 Q6 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R31C22:PLC2 +arc: E1_H02E0401 W1_H02E0401 +arc: H00L0000 V02S0001 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0401 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 V01N0101 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0701 W3_H06E0203 +arc: A0 V02N0501 +arc: A1 H02W0701 +arc: B0 H02W0101 +arc: B1 V02N0101 +arc: C0 V02S0401 +arc: CE0 H00R0100 +arc: CE1 H00L0000 +arc: CE2 V02S0601 +arc: CE3 V02S0601 +arc: CLK0 G_HPBX0100 +arc: D0 E1_H02W0201 +arc: D1 V01S0100 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0100 Q2 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q4 +arc: N3_V06N0303 Q6 +arc: S1_V02S0101 F1 +arc: V01S0000 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1110101011000000 +word: SLICEA.K1.INIT 0010001001110111 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R31C23:PLC2 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 H06E0303 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0701 S1_V02N0701 +arc: H01W0000 W3_H06E0103 +arc: CLK0 G_HPBX0100 +arc: M2 V00B0100 +arc: MUXCLK1 CLK0 +arc: N1_V02N0001 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R31C24:PLC2 +arc: N1_V02N0001 S1_V02N0501 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0301 W1_H02E0301 +arc: V00B0100 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: S1_V02S0401 W3_H06E0203 +arc: CLK0 G_HPBX0100 +arc: M0 V00B0100 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R31C2:PLC2 +arc: E1_H02E0101 V02S0101 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0001 E1_H01W0000 +arc: V00B0100 V02S0101 +arc: CE1 E1_H02W0101 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0201 Q2 +arc: LSR0 E1_H02W0301 +arc: M2 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R31C3:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 N3_V06S0003 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 V02N0301 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H02W0401 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0000 V02S0401 +arc: V00T0100 H02E0101 +arc: V01S0000 N3_V06S0103 +arc: A7 E1_H02W0501 +arc: B7 E1_H02W0301 +arc: C7 E1_H01E0101 +arc: CE0 H00L0100 +arc: CE1 H00L0100 +arc: CE2 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D7 H02E0201 +arc: E1_H01E0101 Q4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: F6 F5D_SLICE +arc: H01W0000 Q2 +arc: M0 V00B0100 +arc: M2 V00T0000 +arc: M4 V00T0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0303 Q6 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1110101011000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R31C4:PLC2 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V06S0203 +arc: H00L0000 V02N0001 +arc: H00L0100 H02E0301 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 H02E0001 +arc: V00T0000 V02N0601 +arc: V00T0100 V02S0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 N3_V06S0203 +arc: B1 H02W0101 +arc: CE1 H00L0000 +arc: CE2 E1_H02W0101 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D1 V02N0001 +arc: E1_H02E0301 F1 +arc: E1_H02E0401 Q6 +arc: E3_H06E0103 Q2 +arc: F1 F1_SLICE +arc: H01W0000 Q6 +arc: M2 E1_H02W0601 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V01S0000 Q4 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R31C5:PLC2 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 V02N0301 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: V00B0100 V02S0301 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06S0103 +arc: A1 H00L0000 +arc: A4 F5 +arc: A5 V00T0000 +arc: B0 F1 +arc: B1 V00B0000 +arc: B5 H00R0000 +arc: C1 N1_V01N0001 +arc: C4 S1_V02N0001 +arc: C5 N1_V02S0201 +arc: CE1 H00L0100 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D0 S1_V02N0001 +arc: D1 H02W0201 +arc: D5 H02W0201 +arc: E1_H01E0101 F0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 F1 +arc: E1_H02E0201 F0 +arc: E1_H02E0401 F4 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 Q6 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 F0 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q6 +arc: H01W0100 F4 +arc: LSR1 H02E0301 +arc: M2 V00B0100 +arc: M6 V00T0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F5 +arc: N1_V02N0101 F1 +arc: N1_V02N0201 F0 +arc: N1_V02N0501 F5 +arc: S1_V02S0501 F5 +arc: S3_V06S0003 F0 +arc: S3_V06S0103 F1 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F5 +arc: V00B0000 Q6 +arc: V00T0000 Q2 +arc: V01S0000 F1 +arc: W1_H02W0001 F0 +arc: W1_H02W0301 F1 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 F0 +arc: W3_H06W0103 F1 +arc: W3_H06W0203 F4 +arc: W3_H06W0303 F5 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1100110000000000 +word: SLICEA.K1.INIT 0000000100000000 +word: SLICEC.K0.INIT 1010000010100000 +word: SLICEC.K1.INIT 0000000000010000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R31C6:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 V02S0601 +arc: H00R0000 H02E0401 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0101 H06E0103 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 H02E0001 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 E3_H06W0203 +arc: A4 V00T0000 +arc: B4 N1_V02S0701 +arc: C4 H02E0601 +arc: C5 F4 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 Q0 +arc: E3_H06E0203 F4 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: LSR1 H02W0301 +arc: M0 W1_H02E0601 +arc: M2 V00B0100 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F5 +arc: S3_V06S0203 F4 +arc: V01S0000 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1111000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R31C7:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06S0303 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 N1_V02S0001 +arc: V00T0100 V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V02S0401 +arc: W3_H06W0303 E3_H06W0303 +arc: A2 H02E0501 +arc: A6 H00R0000 +arc: B1 V02S0301 +arc: B3 V02S0101 +arc: B5 H02E0301 +arc: B6 N1_V01S0000 +arc: B7 V01S0000 +arc: C0 H02E0401 +arc: C1 N1_V01S0100 +arc: C3 N1_V02S0401 +arc: C4 V01N0101 +arc: C5 V02S0001 +arc: C6 V00T0000 +arc: C7 E1_H01E0101 +arc: CE0 E1_H02W0101 +arc: CE1 E1_H02W0101 +arc: CE2 E1_H02W0101 +arc: CLK0 G_HPBX0100 +arc: D1 V02S0001 +arc: D3 V02S0001 +arc: D5 H02E0201 +arc: D6 H01W0000 +arc: D7 H01W0000 +arc: E1_H01E0101 Q4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 F6 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M4 V00T0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0401 Q4 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: S3_V06S0203 Q4 +arc: V00T0000 Q0 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1010101010101010 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 1111000011110000 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICED.K0.INIT 1100110010001100 +word: SLICED.K1.INIT 1111111111110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R31C8:PLC2 +arc: E1_H02E0601 V02N0601 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0601 S1_V02N0601 +arc: A6 H02E0501 +arc: A7 V02N0101 +arc: B6 V01S0000 +arc: B7 V00B0000 +arc: C6 H02E0401 +arc: C7 F6 +arc: CE0 H00R0000 +arc: CE1 W1_H02E0101 +arc: CE2 V02S0601 +arc: CLK0 G_HPBX0100 +arc: D6 W1_H02E0001 +arc: D7 E1_H02W0001 +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00B0100 +arc: M2 W1_H02E0601 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0401 Q4 +arc: N1_V02N0701 Q7 +arc: V01S0000 Q2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0011101100001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R31C9:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0203 V06S0203 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 H02W0101 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 H02W0601 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: S1_V02S0201 W3_H06E0103 +arc: W3_H06W0103 V06S0103 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H00L0100 +arc: A1 E1_H01E0001 +arc: A6 V02N0101 +arc: B0 V02S0301 +arc: B1 V02N0101 +arc: B3 H02W0101 +arc: B6 F3 +arc: B7 N1_V01S0000 +arc: C0 N1_V01S0100 +arc: C1 V02N0601 +arc: C2 H02E0601 +arc: C3 N1_V01N0001 +arc: C6 E1_H01E0101 +arc: C7 S1_V02N0001 +arc: CE1 H00R0000 +arc: CE2 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D0 S1_V02N0001 +arc: D1 F0 +arc: D2 V02N0001 +arc: D3 V02S0201 +arc: D6 V02N0601 +arc: D7 H02W0201 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F7 +arc: E1_H02E0601 Q4 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M4 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V02N0201 F2 +arc: N3_V06N0103 F1 +arc: N3_V06N0303 F6 +arc: S3_V06S0103 F2 +arc: V01S0100 F7 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0011111000101110 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0000100000000000 +word: SLICED.K1.INIT 0000000000000011 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 1111000011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.A1MUX 1 + +.tile R32C10:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06S0203 +arc: H00L0100 H02W0301 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 W1_H02E0501 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0101 +arc: V00T0000 V02N0601 +arc: V00T0100 V02S0501 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W3_H06W0103 S3_V06N0103 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0303 +arc: A4 H02E0501 +arc: A5 V00T0000 +arc: A6 E1_H01W0000 +arc: A7 V02N0301 +arc: B4 H01E0101 +arc: B5 V02S0701 +arc: B6 V00B0100 +arc: B7 V01S0000 +arc: C4 W1_H02E0601 +arc: C5 F4 +arc: C6 E1_H01E0101 +arc: C7 F6 +arc: CE0 H00L0100 +arc: CE1 H02E0101 +arc: CLK0 G_HPBX0100 +arc: D4 V02S0401 +arc: D5 V01N0001 +arc: D6 V02S0601 +arc: D7 V01N0001 +arc: E1_H01E0101 Q0 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0501 Q7 +arc: N3_V06N0303 Q5 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 1100111000001010 +word: SLICED.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 1010111000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R32C11:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 N3_V06S0303 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 S1_V02N0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 W1_H02E0701 +arc: A1 E1_H02W0501 +arc: B0 E1_H02W0301 +arc: B1 V00T0000 +arc: C0 H02E0401 +arc: C1 H02E0601 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 V01S0100 +arc: D1 S1_V02N0201 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q2 +arc: LSR0 V00B0000 +arc: M2 V00B0100 +arc: M4 V00T0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 Q4 +arc: N3_V06N0003 F0 +arc: N3_V06N0103 F1 +arc: S3_V06S0103 F1 +arc: V01S0100 F1 +arc: W1_H02W0101 F1 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0100000000000000 +word: SLICEA.K1.INIT 0000000010000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R32C12:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V01N0001 +arc: H00L0000 H02E0001 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 H02W0401 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0001 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 E1_H02W0501 +arc: S3_V06S0103 W3_H06E0103 +arc: S3_V06S0203 W3_H06E0203 +arc: A0 S1_V02N0701 +arc: A1 S1_V02N0701 +arc: A2 S1_V02N0701 +arc: A3 S1_V02N0701 +arc: A4 V00B0000 +arc: A5 V02S0101 +arc: A6 V02S0301 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 H00L0000 +arc: B5 V02S0701 +arc: C0 H02W0601 +arc: C1 H02W0601 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: C4 E1_H02W0401 +arc: C5 V00T0100 +arc: C6 S1_V02N0201 +arc: CE3 H00R0000 +arc: CLK1 G_HPBX0100 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 V02S0601 +arc: D5 H00R0100 +arc: D6 V02S0401 +arc: D7 V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F1 +arc: H01W0100 Q7 +arc: LSR0 H02E0501 +arc: LSR1 V00T0000 +arc: MUXCLK3 CLK1 +arc: MUXLSR3 LSR0 +arc: N1_V02N0301 F3 +arc: N3_V06N0203 Q7 +arc: S1_V02S0001 F0 +arc: W1_H02W0201 F2 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111000010100000 +word: SLICED.K1.INIT 0000000011111111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C13:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 H02E0601 +arc: H00R0100 V02S0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0003 S1_V02N0001 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02S0001 +arc: V00T0100 H02W0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 E1_H02W0701 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 H00R0000 +arc: A5 N1_V01S0100 +arc: B1 V02S0301 +arc: B3 H01W0100 +arc: B5 W1_H02E0301 +arc: C1 N1_V02S0401 +arc: C2 H00L0100 +arc: C3 H00L0100 +arc: C6 Q6 +arc: C7 E1_H01E0101 +arc: CE1 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D1 N1_V02S0201 +arc: D2 V00T0100 +arc: D6 H00L0100 +arc: D7 H02E0201 +arc: E1_H01E0101 Q6 +arc: E1_H02E0301 F1 +arc: E3_H06E0003 Q3 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0100 Q6 +arc: LSR1 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V02N0101 F3 +arc: S1_V02S0301 Q3 +arc: S1_V02S0501 Q7 +arc: S1_V02S0701 Q5 +arc: S3_V06S0003 Q3 +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F7 +arc: V01S0000 Q3 +arc: W3_H06W0003 Q3 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 0011111100111111 +word: SLICED.K0.INIT 0000111100000000 +word: SLICED.K1.INIT 0000000011110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001000100010001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1001000000001001 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R32C14:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 V02S0201 +arc: H00R0000 N1_V02S0401 +arc: H01W0000 E3_H06W0103 +arc: H01W0100 E3_H06W0303 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0201 S3_V06N0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 W1_H02E0001 +arc: V01S0000 N3_V06S0103 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: W3_H06W0303 S3_V06N0303 +arc: E3_H06E0103 W3_H06E0103 +arc: A2 H02W0501 +arc: A3 H02E0501 +arc: A4 V00T0000 +arc: A5 N1_V01S0100 +arc: A6 V02N0301 +arc: A7 H02E0701 +arc: B0 E1_H02W0301 +arc: B2 H00R0000 +arc: B3 H00L0000 +arc: B4 V02S0501 +arc: B5 V00B0100 +arc: B6 N1_V01S0000 +arc: B7 V00B0000 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F4 +arc: N1_V02N0401 F6 +arc: W1_H02W0001 F2 +arc: W1_H02W0101 F3 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R32C15:PLC2 +arc: E1_H01E0101 E3_H06W0203 +arc: E1_H02E0501 E3_H06W0303 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 V02N0701 +arc: H00L0000 V02S0001 +arc: H00L0100 V02N0301 +arc: H00R0000 N1_V02S0401 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0401 E3_H06W0203 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 V02S0401 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0501 V02S0501 +arc: A0 H02E0501 +arc: A1 V02S0701 +arc: A2 H00L0100 +arc: A3 N1_V02S0701 +arc: A4 V00B0000 +arc: A5 V02N0101 +arc: A6 H00R0000 +arc: A7 N1_V02S0101 +arc: B0 V00T0000 +arc: B1 V02S0301 +arc: B2 H00L0000 +arc: B3 V02S0101 +arc: B4 N1_V02S0501 +arc: B5 H02E0301 +arc: B6 V02N0501 +arc: B7 S1_V02N0501 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F4 +arc: N1_V01N0101 F3 +arc: N1_V02N0001 F0 +arc: N1_V02N0601 F6 +arc: S3_V06S0203 F7 +arc: W1_H02W0001 F2 +arc: W1_H02W0701 F5 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R32C16:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 S3_V06N0003 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0701 H01E0101 +arc: H00L0000 V02N0001 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 S3_V06N0003 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0201 E3_H06W0103 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 S3_V06N0003 +arc: H01W0100 W3_H06E0303 +arc: S1_V02S0701 W3_H06E0203 +arc: E3_H06E0003 W3_H06E0303 +arc: A0 V01N0101 +arc: A1 E1_H02W0501 +arc: A2 H02W0501 +arc: A3 V00B0000 +arc: A4 V02S0101 +arc: A5 N1_V01S0100 +arc: A6 H02E0701 +arc: A7 H00L0000 +arc: B0 V02S0301 +arc: B1 V01N0001 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 F4 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0501 F5 +arc: S3_V06S0003 F3 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R32C17:PLC2 +arc: H00L0000 V02N0201 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0203 N3_V06S0203 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0501 V01N0101 +arc: A0 V02N0501 +arc: A1 S1_V02N0701 +arc: A2 E1_H02W0701 +arc: A3 S1_V02N0501 +arc: A4 H02W0701 +arc: A5 E1_H01W0000 +arc: A6 H02E0701 +arc: A7 V02S0101 +arc: B0 V02S0301 +arc: B1 S1_V02N0301 +arc: B2 E1_H02W0301 +arc: B3 H00L0000 +arc: B4 V02S0701 +arc: B5 H02E0101 +arc: B6 V02N0701 +arc: B7 V00T0000 +arc: E1_H01E0001 F7 +arc: E1_H02E0001 F0 +arc: E1_H02E0101 F1 +arc: E1_H02E0601 F6 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101010 +word: SLICED.K0.INIT 0110011001101100 +word: SLICED.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101010 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101100 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R32C18:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0701 V02N0701 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N1_V02S0701 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: A0 F5 +arc: A1 H00R0000 +arc: A4 W1_H02E0501 +arc: B0 V02N0301 +arc: B1 N1_V02S0301 +arc: B6 W1_H02E0301 +arc: B7 W1_H02E0301 +arc: C5 V00T0000 +arc: D4 W1_H02E0001 +arc: D5 W1_H02E0001 +arc: D6 E1_H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: W1_H02W0701 F7 +word: SLICEA.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 0110011001101010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEC.K0.INIT 0101010110101010 +word: SLICEC.K1.INIT 0000111111110000 +word: SLICED.K0.INIT 0011001111001100 +word: SLICED.K1.INIT 0011001111001100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R32C19:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 E1_H01W0100 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0103 W1_H02E0101 +arc: H00L0000 V02S0201 +arc: H00L0100 H02E0301 +arc: H00R0000 H02W0601 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N1_V02S0501 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V01N0101 +arc: A1 S1_V02N0501 +arc: A3 V00B0000 +arc: A4 H02W0501 +arc: A5 H02W0501 +arc: A6 H02E0501 +arc: A7 V02S0301 +arc: B0 H00R0100 +arc: B1 H02W0101 +arc: B2 H02E0301 +arc: B3 V02N0101 +arc: B4 H02W0301 +arc: B5 F1 +arc: B6 V02N0501 +arc: B7 V01S0000 +arc: C0 H00L0000 +arc: C1 H00L0100 +arc: C2 S1_V02N0401 +arc: C3 H02E0401 +arc: C4 E1_H01E0101 +arc: C6 V02S0001 +arc: C7 H02W0401 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D0 V02N0201 +arc: D1 F2 +arc: D2 H01E0101 +arc: D3 F2 +arc: D4 F0 +arc: D6 V02S0401 +arc: D7 V01N0001 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 F3 +arc: M4 V00T0000 +arc: MUXCLK1 CLK0 +arc: V01S0000 F6 +arc: V01S0100 F4 +arc: W3_H06W0103 F1 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 0101100011111101 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0100001011100111 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEC.K0.INIT 1110001011010001 +word: SLICEC.K1.INIT 0110011001100110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R32C20:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0501 S3_V06N0303 +arc: H00L0100 H02E0301 +arc: H00R0000 V02S0601 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S3_V06N0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 H02W0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 S3_V06N0203 +arc: E1_H02E0601 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: A0 H02E0501 +arc: A1 F5 +arc: A4 V02N0301 +arc: A6 F5 +arc: B0 H01W0100 +arc: B1 F3 +arc: B2 H00R0000 +arc: B3 H01W0100 +arc: B5 H02E0301 +arc: B6 F3 +arc: B7 H02E0301 +arc: C0 E1_H01W0000 +arc: C1 N1_V01N0001 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C4 H02E0401 +arc: C5 V02S0201 +arc: C6 E1_H01E0101 +arc: C7 H01E0001 +arc: CE1 H00L0100 +arc: CE2 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D1 F0 +arc: D2 W1_H02E0201 +arc: D3 V00B0100 +arc: D4 H02E0201 +arc: D5 V00B0000 +arc: D6 F0 +arc: D7 V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F7 +arc: V00B0000 Q4 +arc: W3_H06W0103 F1 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 0001110100011101 +word: SLICEA.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 0000001111001111 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 0000110000111111 +word: SLICED.K0.INIT 0000100000000000 +word: SLICED.K1.INIT 0000110000111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R32C21:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 N3_V06S0303 +arc: H00L0000 H02W0201 +arc: H00R0000 H02E0601 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02S0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0401 V01N0001 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 H02W0501 +arc: A1 H00L0000 +arc: A3 F5 +arc: A4 V02N0101 +arc: A5 H02E0501 +arc: A6 E1_H02W0701 +arc: B0 F1 +arc: B1 V00T0000 +arc: B2 H01W0100 +arc: B3 H00L0000 +arc: B4 H02W0301 +arc: B5 S1_V02N0701 +arc: B7 V01S0000 +arc: C0 F6 +arc: C1 H02W0401 +arc: C2 W1_H02E0401 +arc: C3 H02W0401 +arc: C4 V00T0100 +arc: C5 E1_H01E0101 +arc: C6 V02N0001 +arc: C7 V01N0101 +arc: CE0 V02N0201 +arc: CE1 H00R0000 +arc: CE2 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: D0 S1_V02N0201 +arc: D1 H02E0001 +arc: D2 V00B0100 +arc: D3 F2 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D6 H00R0100 +arc: D7 V02N0401 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q4 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F7 +arc: H01W0000 Q2 +arc: H01W0100 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0001 Q0 +arc: V01S0000 Q4 +arc: V01S0100 F3 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 0000111100010001 +word: SLICEA.K1.INIT 0101100011111101 +word: SLICEB.K0.INIT 1100111111000000 +word: SLICEB.K1.INIT 0011100011111011 +word: SLICEC.K0.INIT 1110101011000000 +word: SLICEC.K1.INIT 1000001101101011 +word: SLICED.K0.INIT 1111101000001010 +word: SLICED.K1.INIT 0000111100110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.A1MUX 1 + +.tile R32C22:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V02N0601 +arc: H00L0000 V02S0001 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0701 S3_V06N0203 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 V02S0401 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0501 S1_V02N0501 +arc: S1_V02S0401 W3_H06E0203 +arc: S3_V06S0303 W3_H06E0303 +arc: A0 H00L0100 +arc: A1 V02S0501 +arc: A2 V02S0701 +arc: A3 W1_H02E0501 +arc: A4 F5 +arc: A5 E1_H02W0701 +arc: A7 H00L0000 +arc: B0 V00T0000 +arc: B1 V00B0000 +arc: B2 H02W0101 +arc: B3 V02N0301 +arc: B4 V02N0701 +arc: B5 S1_V02N0701 +arc: B6 N1_V01S0000 +arc: B7 V00B0000 +arc: C0 H02W0401 +arc: C1 V02N0401 +arc: C2 H02E0601 +arc: C3 N1_V01N0001 +arc: C4 N1_V02S0201 +arc: C5 V00T0100 +arc: C6 H02E0401 +arc: C7 F6 +arc: CE0 H00R0000 +arc: CE1 H00R0100 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D1 F0 +arc: D2 E1_H02W0201 +arc: D3 V00B0100 +arc: D4 H02E0001 +arc: D5 V02S0601 +arc: D6 S1_V02N0401 +arc: D7 V02N0401 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 F1 +arc: E1_H02E0401 F4 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 Q2 +arc: V01S0000 Q6 +arc: V01S0100 F3 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1101100011011000 +word: SLICEA.K1.INIT 0011100011111011 +word: SLICED.K0.INIT 1100110011110000 +word: SLICED.K1.INIT 0011111110001011 +word: SLICEC.K0.INIT 0010110011101111 +word: SLICEC.K1.INIT 1001011101000011 +word: SLICEB.K0.INIT 1110101011000000 +word: SLICEB.K1.INIT 1000001101101011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R32C23:PLC2 +arc: H00R0000 V02S0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06E0303 +arc: V00B0100 W1_H02E0701 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0501 N3_V06S0303 +arc: H01W0100 W3_H06E0303 +arc: S1_V02S0001 W3_H06E0003 +arc: S1_V02S0201 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 +arc: A0 H02E0501 +arc: A1 E1_H01E0001 +arc: A2 H02E0501 +arc: A3 V02N0501 +arc: A4 H02E0501 +arc: B0 F1 +arc: B1 H02E0301 +arc: B2 V01N0001 +arc: B4 E1_H02W0301 +arc: B5 V02N0501 +arc: B6 H02E0301 +arc: B7 V02N0701 +arc: C0 H02E0601 +arc: C2 H02E0601 +arc: C3 H00L0000 +arc: C4 H02E0401 +arc: C5 V02N0001 +arc: C6 E1_H01E0101 +arc: C7 H02W0401 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 V02N0201 +arc: D1 V00B0100 +arc: D2 H01E0101 +arc: D3 H00R0000 +arc: D4 H01W0000 +arc: D5 V00B0000 +arc: D6 V02S0601 +arc: D7 H02E0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H01W0000 F6 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N3_V06N0203 Q4 +arc: S3_V06S0303 F5 +arc: V00B0000 Q4 +arc: V01S0000 Q0 +arc: V01S0100 F7 +arc: W1_H02W0701 F5 +word: SLICED.K0.INIT 1111001111000000 +word: SLICED.K1.INIT 0000001111001111 +word: SLICEB.K0.INIT 0011000000110101 +word: SLICEB.K1.INIT 0000101001011111 +word: SLICEA.K0.INIT 0011000000110101 +word: SLICEA.K1.INIT 1011101110001000 +word: SLICEC.K0.INIT 0000000111001101 +word: SLICEC.K1.INIT 0000001111001111 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 + +.tile R32C24:PLC2 +arc: N1_V02N0601 S3_V06N0303 +arc: S1_V02S0601 H01E0001 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 V02N0701 +arc: A3 W1_H02E0701 +arc: B3 V02N0301 +arc: C3 V02N0601 +arc: CE1 S1_V02N0201 +arc: CLK0 G_HPBX0100 +arc: D3 V02N0001 +arc: F3 F3_SLICE +arc: MUXCLK1 CLK0 +arc: N1_V02N0101 Q3 +arc: W1_H02W0101 Q3 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0011001100000101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R32C25:PLC2 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 S1_V02N0501 + +.tile R32C2:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0001 E3_H06W0003 +arc: S3_V06S0203 H06W0203 +arc: V00B0000 V02S0001 +arc: CE0 H00L0100 +arc: CLK0 G_HPBX0100 +arc: E3_H06E0003 Q0 +arc: M0 V00B0000 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R32C3:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 N1_V02S0601 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0701 N1_V02S0701 +arc: S3_V06S0003 H06W0003 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 V02N0401 +arc: CE0 H02E0101 +arc: CE1 H02E0101 +arc: CE2 H02E0101 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0100 +arc: M0 V00T0000 +arc: M2 E1_H02W0601 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0601 Q6 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R32C4:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0401 N1_V01S0000 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0100 H02E0301 +arc: H00R0000 H02E0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N3_V06N0003 S3_V06N0003 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0000 V02N0401 +arc: V01S0000 S3_V06N0103 +arc: CE0 W1_H02E0101 +arc: CE1 H00R0000 +arc: CE2 H00L0100 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: E3_H06E0203 Q4 +arc: M0 V00B0100 +arc: M2 E1_H02W0601 +arc: M4 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0201 Q2 +arc: N1_V02N0401 Q6 +arc: N1_V02N0601 Q4 +arc: S3_V06S0003 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R32C5:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 V02S0501 +arc: H00R0100 V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0100 V02N0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 E1_H02W0701 +arc: B1 V01N0001 +arc: C1 V02N0401 +arc: D1 V02N0201 +arc: E3_H06E0003 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M3 E1_H02W0201 +arc: M4 V00B0100 +arc: M5 H00R0100 +arc: M6 V00B0100 +word: SLICEB.K0.INIT 1111111111111111 +word: SLICEB.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 1111111111111111 +word: SLICEA.K1.INIT 1111111111111110 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R32C6:PLC2 +arc: H00L0100 H02W0301 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0401 H02E0401 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0601 S1_V02N0601 +arc: A6 H02E0501 +arc: B6 N1_V01S0000 +arc: B7 W1_H02E0101 +arc: C6 W1_H02E0401 +arc: C7 V02N0001 +arc: CE0 H00L0100 +arc: CE1 H00L0100 +arc: CE2 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D6 H02E0201 +arc: D7 V00B0000 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: H01W0100 Q0 +arc: M0 V00T0000 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0203 Q7 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q2 +arc: V00B0000 F6 +arc: W3_H06W0003 Q0 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 1111000011111100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 + +.tile R32C7:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0203 N1_V01S0000 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0101 +arc: V00T0000 V02S0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 S1_V02N0701 +arc: A4 V02S0101 +arc: A5 V00T0100 +arc: A6 W1_H02E0501 +arc: A7 H00R0000 +arc: B4 V02S0701 +arc: B5 H02W0301 +arc: B6 V01S0000 +arc: B7 H02W0301 +arc: C4 E1_H01E0101 +arc: C5 V02N0001 +arc: C6 V00B0100 +arc: C7 V02N0001 +arc: CE0 V02S0201 +arc: CE1 V02S0201 +arc: CLK0 G_HPBX0100 +arc: D4 E1_H01W0100 +arc: D5 H01W0000 +arc: D6 H02W0201 +arc: D7 V02N0401 +arc: E1_H01E0101 Q2 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F4 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0203 Q7 +arc: N3_V06N0303 Q5 +arc: V01S0000 Q0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0101000011011100 +word: SLICED.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 1111010001000100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R32C8:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 E3_H06W0303 +arc: E3_H06E0103 N3_V06S0103 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0401 V01N0001 +arc: S1_V02S0501 V01N0101 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0601 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 E3_H06W0303 +arc: W1_H02W0601 S3_V06N0303 +arc: W3_H06W0003 S3_V06N0003 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CE2 H00R0000 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0601 Q4 +arc: H01W0100 Q2 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: M0 H02E0601 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: W1_H02W0201 Q0 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R32C9:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0501 W1_H02E0501 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0100 H02E0301 +arc: H00R0000 N1_V02S0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 S3_V06N0203 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 H06E0203 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0701 S1_V02N0701 +arc: CE0 H00R0000 +arc: CE1 H00L0100 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0101 Q2 +arc: H01W0000 Q0 +arc: H01W0100 Q4 +arc: M0 V00T0100 +arc: M2 V00T0000 +arc: M4 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N3_V06N0203 Q4 +arc: V01S0100 Q0 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R33C10:PLC2 +arc: E1_H02E0201 V02N0201 +arc: H00L0100 H02W0301 +arc: H00R0100 V02S0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0203 S1_V02N0401 +arc: S1_V02S0201 H06W0103 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W3_H06W0003 S3_V06N0003 +arc: A0 H02E0501 +arc: A1 E1_H02W0701 +arc: A2 H02E0501 +arc: A4 V02N0101 +arc: A5 E1_H02W0501 +arc: B1 H02E0101 +arc: B4 H01E0101 +arc: B5 N1_V01S0000 +arc: C0 H02E0401 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: C4 N1_V02S0201 +arc: C5 F4 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D0 V00B0100 +arc: D1 V02N0001 +arc: D2 V02N0001 +arc: D3 S1_V02N0201 +arc: D4 V00B0000 +arc: D5 V02S0401 +arc: E1_H01E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q1 +arc: M2 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0201 Q0 +arc: N1_V02N0501 Q5 +arc: N3_V06N0103 Q1 +arc: V00B0000 Q6 +arc: W3_H06W0103 Q2 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 1010111000001100 +word: SLICEA.K0.INIT 1111000010101010 +word: SLICEA.K1.INIT 1111000011100100 +word: SLICEB.K0.INIT 1111000010101010 +word: SLICEB.K1.INIT 1111111100000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R33C11:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 E1_H01W0000 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: A2 V02N0501 +arc: A3 V02S0501 +arc: B2 W1_H02E0301 +arc: B3 V02N0301 +arc: B7 V02N0701 +arc: C2 H02W0401 +arc: C3 E1_H02W0401 +arc: C7 V01N0101 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D2 H02E0201 +arc: D3 F2 +arc: D7 H00R0100 +arc: E3_H06E0203 Q7 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q7 +arc: M0 H01E0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 F2 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000010 +word: SLICEB.K1.INIT 0010000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 + +.tile R33C12:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 H02E0601 +arc: H00R0100 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 H02W0601 +arc: V00B0100 V02N0101 +arc: V00T0000 S1_V02N0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0301 S3_V06N0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 E1_H02W0701 +arc: A0 V02N0501 +arc: A1 V02N0701 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A4 S1_V02N0101 +arc: A5 V02S0101 +arc: A7 Q7 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: B4 H00R0000 +arc: B5 H02E0101 +arc: B7 V02S0701 +arc: C0 S1_V02N0601 +arc: C1 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V00T0000 +arc: C5 S1_V02N0201 +arc: C7 V02N0201 +arc: CLK1 G_HPBX0100 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 H02E0001 +arc: D7 V02S0601 +arc: E1_H01E0001 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0000 +arc: LSR1 V00T0100 +arc: MUXCLK3 CLK1 +arc: MUXLSR3 LSR0 +arc: N1_V02N0301 F1 +arc: N3_V06N0003 F0 +arc: N3_V06N0103 F2 +arc: N3_V06N0203 Q7 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1100111011101110 +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R33C13:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02N0701 +arc: E3_H06E0003 N1_V01S0000 +arc: H00L0100 V02S0301 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0203 H01E0001 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0401 N1_V02S0401 +arc: V00B0100 V02S0101 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 W3_H06E0303 +arc: W3_H06W0103 V06S0103 +arc: E3_H06E0303 W3_H06E0203 +arc: A5 V02N0301 +arc: B1 E1_H01W0100 +arc: B7 H02W0101 +arc: C1 N1_V02S0601 +arc: C5 E1_H02W0401 +arc: C7 E1_H02W0601 +arc: CE1 H00L0100 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D1 S1_V02N0201 +arc: D5 H02E0001 +arc: D7 H02W0001 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F1 +arc: E1_H02E0501 Q7 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q7 +arc: M2 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0303 Q5 +arc: S3_V06S0103 Q2 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 + +.tile R33C14:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0103 S3_V06N0103 +arc: H00L0000 V02S0201 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H01E0101 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 H02E0601 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E3_H06W0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 S1_V02N0701 +arc: A3 E1_H01E0001 +arc: A4 N1_V02S0101 +arc: A5 S1_V02N0301 +arc: A6 N1_V01N0101 +arc: A7 V00T0100 +arc: B1 H02E0101 +arc: B3 F1 +arc: B7 V01S0000 +arc: C0 N1_V02S0401 +arc: C1 S1_V02N0401 +arc: C3 F4 +arc: C6 S1_V02N0201 +arc: C7 F4 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D3 N1_V02S0001 +arc: D4 H00R0100 +arc: D5 S1_V02N0601 +arc: D6 N1_V02S0601 +arc: D7 V01N0001 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 Q7 +arc: E3_H06E0203 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q7 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M4 E1_H01E0101 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q7 +arc: N1_V02N0701 Q7 +arc: N3_V06N0203 Q7 +arc: N3_V06N0303 F6 +arc: S1_V02S0001 F2 +arc: S1_V02S0101 F1 +arc: S3_V06S0103 F2 +arc: V00T0100 F1 +arc: V01S0000 F0 +arc: V01S0100 Q7 +word: SLICED.K0.INIT 0000010110101111 +word: SLICED.K1.INIT 1110111100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000011101111 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEC.K0.INIT 0000000001010101 +word: SLICEC.K1.INIT 0000000001010101 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R33C15:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 W1_H02E0501 +arc: E3_H06E0303 V06N0303 +arc: H00L0100 S1_V02N0101 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0103 N3_V06S0003 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H01W0000 +arc: A5 V02N0101 +arc: A7 H02E0501 +arc: B2 F3 +arc: C2 V02N0601 +arc: C3 H02E0401 +arc: C5 V02N0201 +arc: C6 V00T0000 +arc: CE0 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D3 V02S0001 +arc: D5 E1_H02W0001 +arc: D6 H02W0001 +arc: D7 H02W0001 +arc: E1_H01E0101 F3 +arc: E1_H02E0701 Q5 +arc: E3_H06E0003 F3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q0 +arc: M0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0501 F7 +arc: N3_V06N0003 F3 +arc: N3_V06N0103 F2 +arc: V01S0000 F3 +arc: V01S0100 F6 +arc: W3_H06W0003 F3 +arc: W3_H06W0103 F2 +arc: W3_H06W0303 Q5 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0011111100111111 +word: SLICEB.K1.INIT 1111111100001111 +word: SLICED.K0.INIT 0000111111110000 +word: SLICED.K1.INIT 0101010110101010 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111101000001010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R33C16:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 N1_V01S0000 +arc: E3_H06E0003 V06S0003 +arc: E3_H06E0203 S3_V06N0203 +arc: E3_H06E0303 V06N0303 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N1_V02S0001 +arc: S3_V06S0103 H01E0101 +arc: S3_V06S0203 H01E0001 +arc: S3_V06S0303 N1_V01S0100 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0701 N3_V06S0203 +arc: A2 H00L0100 +arc: A3 V02S0501 +arc: A5 V02N0301 +arc: A6 V02N0101 +arc: A7 F5 +arc: B2 E1_H02W0301 +arc: B5 H02E0301 +arc: B6 N1_V02S0701 +arc: B7 N1_V02S0501 +arc: C0 S1_V02N0601 +arc: C1 E1_H02W0601 +arc: C2 V02S0401 +arc: C3 H02W0401 +arc: C4 V02S0001 +arc: C5 H02E0401 +arc: C6 V02S0201 +arc: C7 F6 +arc: CE1 W1_H02E0101 +arc: CLK0 G_HPBX0100 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V00T0100 +arc: D3 S1_V02N0001 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 H02E0001 +arc: D7 V02S0601 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: H01W0100 F4 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 F1 +arc: S1_V02S0201 F2 +arc: V00T0100 F3 +word: SLICEC.K0.INIT 0000111111110000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEB.K0.INIT 0101100011111101 +word: SLICEB.K1.INIT 1111000010101010 +word: SLICED.K0.INIT 1000010000100001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEA.K0.INIT 0000111111110000 +word: SLICEA.K1.INIT 0000111111110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R33C17:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0203 W1_H02E0701 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H02W0601 +arc: N3_V06N0203 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02S0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 E1_H01W0000 +arc: E3_H06E0303 W3_H06E0203 +arc: A5 V00B0000 +arc: A6 V02S0301 +arc: A7 V02S0301 +arc: B0 H02W0101 +arc: B1 V02S0301 +arc: B3 V02N0101 +arc: B7 V02S0501 +arc: C3 H00R0100 +arc: C5 H02E0601 +arc: C6 V02S0001 +arc: CE1 H00L0000 +arc: CE2 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: D0 V00B0100 +arc: D1 E1_H02W0201 +arc: D3 H02W0001 +arc: D5 N1_V02S0401 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q5 +arc: H01W0100 F0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F1 +arc: N1_V02N0401 F6 +arc: N1_V02N0701 F7 +arc: V01S0000 F3 +arc: W1_H02W0101 Q3 +word: SLICEA.K0.INIT 0011001111001100 +word: SLICEA.K1.INIT 0011001111001100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 0101101001011010 +word: SLICED.K1.INIT 0110011001100110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R33C18:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: H00L0100 H02W0101 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 H06W0003 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 V02S0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 S3_V06N0303 +arc: N1_V02N0501 W3_H06E0303 +arc: A0 E1_H01E0001 +arc: A1 H02W0501 +arc: A2 N1_V02S0701 +arc: A3 E1_H01E0001 +arc: A4 S1_V02N0101 +arc: A5 V02N0101 +arc: B0 H02E0301 +arc: B1 H01W0100 +arc: B2 E1_H01W0100 +arc: B3 W1_H02E0301 +arc: B4 V02N0501 +arc: B5 V02S0501 +arc: C0 H02E0601 +arc: C1 S1_V02N0601 +arc: C2 H00L0100 +arc: C3 E1_H02W0601 +arc: C4 E1_H01E0101 +arc: C5 S1_V02N0001 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 W1_H02E0001 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 W1_H02E0001 +arc: D4 W1_H02E0001 +arc: D5 V00B0000 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 Q3 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0201 F2 +arc: N1_V02N0301 Q3 +arc: N3_V06N0103 F2 +arc: S1_V02S0201 Q0 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 Q4 +arc: S3_V06S0203 Q4 +arc: V00B0000 Q4 +arc: W1_H02W0301 F1 +arc: W3_H06W0103 F2 +word: SLICEA.K0.INIT 1110110010100000 +word: SLICEA.K1.INIT 1001011100011001 +word: SLICEC.K0.INIT 1110110010100000 +word: SLICEC.K1.INIT 1001010001001111 +word: SLICEB.K0.INIT 0001110101010101 +word: SLICEB.K1.INIT 1111100010001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R33C19:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 S3_V06N0303 +arc: E1_H02E0701 S3_V06N0203 +arc: H00L0000 H02W0001 +arc: H00L0100 H02W0101 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0100 V02S0301 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0601 V06S0303 +arc: H01W0100 W3_H06E0303 +arc: W1_H02W0001 W3_H06E0003 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 V02N0501 +arc: A3 V02N0501 +arc: A4 H02E0701 +arc: A5 V00B0000 +arc: A6 H02W0501 +arc: A7 S1_V02N0101 +arc: B2 V02S0301 +arc: B3 H02W0301 +arc: B4 N1_V02S0501 +arc: B5 V02S0501 +arc: B6 V02N0701 +arc: B7 N1_V02S0701 +arc: C2 H00L0000 +arc: C3 H02E0601 +arc: C4 H01E0001 +arc: C5 H02E0601 +arc: C6 E1_H02W0601 +arc: C7 F6 +arc: CE0 W1_H02E0101 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D2 H00R0000 +arc: D3 V00B0100 +arc: D4 H02E0001 +arc: D5 H02W0201 +arc: D6 H00L0100 +arc: D7 V02N0601 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: M0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F2 +arc: N1_V01N0101 F7 +arc: N1_V02N0101 F3 +arc: N3_V06N0003 Q0 +arc: S1_V02S0701 F5 +arc: V00B0000 Q4 +arc: V01S0000 Q4 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 1000011001011101 +word: SLICEC.K0.INIT 1110110010100000 +word: SLICEC.K1.INIT 1000011001011101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R33C20:PLC2 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0003 W1_H02E0301 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 E1_H02W0301 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V02S0601 +arc: E1_H02E0401 W3_H06E0203 +arc: N1_V02N0101 W3_H06E0103 +arc: S1_V02S0701 W3_H06E0203 +arc: S3_V06S0203 W3_H06E0203 +arc: W1_H02W0401 W3_H06E0203 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 S3_V06N0203 +arc: E3_H06E0203 W3_H06E0203 +arc: E3_H06E0303 W3_H06E0203 +arc: A0 H02E0501 +arc: A1 V02S0501 +arc: A2 N1_V02S0501 +arc: A5 E1_H01W0000 +arc: A6 V02S0101 +arc: A7 E1_H01W0000 +arc: B0 E1_H02W0301 +arc: B1 H01W0100 +arc: B2 V02N0101 +arc: B5 W1_H02E0301 +arc: B6 H02W0301 +arc: B7 V02S0501 +arc: C0 H00L0100 +arc: C1 N1_V02S0401 +arc: C2 H02E0401 +arc: C5 S1_V02N0001 +arc: C6 V00B0100 +arc: C7 W1_H02E0601 +arc: CE0 V02N0201 +arc: CE1 V02N0201 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0100 +arc: D0 E1_H02W0201 +arc: D1 H00R0000 +arc: D2 H02W0001 +arc: D5 H01W0000 +arc: D6 H00R0100 +arc: D7 H01W0000 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q0 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F5 +arc: S1_V02S0501 F7 +arc: S3_V06S0003 Q0 +arc: W1_H02W0001 Q2 +arc: W1_H02W0201 Q2 +word: SLICEB.K0.INIT 1111100010001000 +word: SLICEB.K1.INIT 1111111111111111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 1110110010100000 +word: SLICEA.K1.INIT 1000001101101011 +word: SLICED.K0.INIT 1110101011000000 +word: SLICED.K1.INIT 1000011001011101 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R33C21:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: H00L0000 W1_H02E0201 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 H02E0701 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V02N0501 +arc: E1_H02E0501 W3_H06E0303 +arc: N1_V02N0301 W3_H06E0003 +arc: S3_V06S0003 W3_H06E0003 +arc: E3_H06E0103 W3_H06E0003 +arc: A1 H02W0501 +arc: A2 N1_V02S0501 +arc: A4 W1_H02E0501 +arc: A5 V00B0000 +arc: A6 H02E0501 +arc: A7 H00R0000 +arc: B0 V02N0101 +arc: B1 H02W0101 +arc: B2 V02N0301 +arc: B4 H02W0301 +arc: B5 H02E0301 +arc: B6 W1_H02E0301 +arc: B7 S1_V02N0701 +arc: C1 N1_V01S0100 +arc: C2 E1_H02W0401 +arc: C4 E1_H02W0601 +arc: C5 W1_H02E0601 +arc: C6 V00B0100 +arc: C7 V00T0100 +arc: CE0 H00L0000 +arc: CE1 H00R0100 +arc: CE2 V02N0601 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0100 +arc: D0 W1_H02E0001 +arc: D1 F0 +arc: D2 V02N0001 +arc: D4 V02S0401 +arc: D5 S1_V02N0401 +arc: D6 E1_H02W0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 F0 +arc: E1_H02E0401 Q4 +arc: E1_H02E0601 Q6 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q2 +arc: H01W0100 Q6 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q1 +arc: N1_V02N0601 Q4 +arc: N3_V06N0103 Q1 +arc: V00B0000 Q4 +arc: V01S0000 F0 +arc: W1_H02W0201 Q2 +arc: W1_H02W0601 Q4 +arc: W3_H06W0003 F0 +word: SLICEA.K0.INIT 0011001100000000 +word: SLICEA.K1.INIT 0011001100000101 +word: SLICEB.K0.INIT 1111100010001000 +word: SLICEB.K1.INIT 1111111111111111 +word: SLICED.K0.INIT 1110101011000000 +word: SLICED.K1.INIT 1001011100100101 +word: SLICEC.K0.INIT 1110101011000000 +word: SLICEC.K1.INIT 1000010101101101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R33C22:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E3_H06E0003 H01E0001 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 N1_V02S0101 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0501 V02N0501 +arc: E1_H02E0601 W3_H06E0303 +arc: W1_H02W0301 W3_H06E0003 +arc: A0 V02S0501 +arc: A1 S1_V02N0701 +arc: A2 V00T0000 +arc: A3 V00B0000 +arc: A4 V02S0101 +arc: A5 V02S0301 +arc: A6 V02N0101 +arc: A7 V02S0301 +arc: B1 V02S0301 +arc: B3 S1_V02N0101 +arc: B5 H02E0101 +arc: B7 H01E0101 +arc: C0 V02N0401 +arc: C1 N1_V01S0100 +arc: C2 N1_V01N0001 +arc: C3 E1_H01W0000 +arc: C4 W1_H02E0601 +arc: C5 F4 +arc: C6 H02E0601 +arc: C7 F6 +arc: CE0 H00R0100 +arc: CE2 V02S0601 +arc: CE3 V02S0601 +arc: CLK0 G_HPBX0100 +arc: D0 V02S0201 +arc: D1 F0 +arc: D2 V02S0001 +arc: D3 N1_V01S0000 +arc: D4 V02N0401 +arc: D5 S1_V02N0401 +arc: D6 H02W0001 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F2 +arc: E1_H02E0501 F7 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: V00B0000 Q4 +arc: V00T0000 Q0 +arc: V01S0000 F3 +word: SLICED.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 0101111110001101 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 0110001011111011 +word: SLICEB.K0.INIT 0000000000000101 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1111000010101010 +word: SLICEC.K1.INIT 0101111110001101 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B0MUX 1 + +.tile R33C23:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0501 W1_H02E0401 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 H06E0303 +arc: V00B0000 V02S0201 +arc: V00B0100 H02W0501 +arc: V00T0000 V02N0401 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0401 W3_H06E0203 +arc: A0 E1_H01E0001 +arc: A5 W1_H02E0701 +arc: B0 H02E0301 +arc: B1 E1_H02W0301 +arc: B2 H02E0301 +arc: B3 E1_H02W0301 +arc: B4 H02E0101 +arc: B5 H00R0000 +arc: C1 W1_H02E0601 +arc: C2 N1_V01S0100 +arc: C3 V02S0401 +arc: C4 W1_H02E0401 +arc: C5 F4 +arc: CE2 V02S0601 +arc: CLK0 G_HPBX0100 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 V01S0100 +arc: D3 N1_V01S0000 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: E1_H01E0001 F1 +arc: E1_H02E0101 F1 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q4 +arc: H01W0100 F2 +arc: M6 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F0 +arc: N3_V06N0303 Q6 +arc: V00T0100 F3 +arc: V01S0100 F3 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEA.K1.INIT 0000001111001111 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 0000001111001111 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICEC.K1.INIT 0010111011001111 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 + +.tile R33C24:PLC2 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 S1_V02N0701 +arc: S3_V06S0103 H06E0103 +arc: V00B0100 W1_H02E0701 +arc: N1_V02N0201 W3_H06E0103 +arc: A0 V02N0501 +arc: A3 H02E0501 +arc: A5 H02E0701 +arc: A7 W1_H02E0501 +arc: B0 F1 +arc: B1 W1_H02E0301 +arc: B4 H02E0101 +arc: B5 V02N0501 +arc: B6 F3 +arc: B7 V02N0501 +arc: C0 V02N0401 +arc: C1 H00L0100 +arc: C3 E1_H02W0601 +arc: C4 V02N0001 +arc: C5 F4 +arc: C6 V02N0001 +arc: C7 F6 +arc: CE0 V02N0201 +arc: CE2 V02N0601 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0100 +arc: D0 V00B0100 +arc: D1 V00T0100 +arc: D3 V01S0100 +arc: D4 V01N0001 +arc: D5 V02N0401 +arc: D6 V02S0601 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q5 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0501 Q7 +arc: S1_V02S0001 Q0 +arc: V00T0100 F3 +arc: V01S0100 Q5 +arc: W1_H02W0501 Q7 +word: SLICEA.K0.INIT 0011000000110101 +word: SLICEA.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEC.K1.INIT 0000111100010001 +word: SLICED.K0.INIT 1100111111000000 +word: SLICED.K1.INIT 0000111100010001 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000010111110101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R33C25:PLC2 +arc: N1_V02N0301 H06E0003 +arc: W1_H02W0301 E1_H01W0100 + +.tile R33C26:PLC2 +arc: H01W0100 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 + +.tile R33C2:PLC2 +arc: E1_H02E0701 E1_H01W0100 +arc: N1_V02N0001 E3_H06W0003 +arc: A3 V00B0000 +arc: A7 H00R0000 +arc: B0 V02N0301 +arc: B3 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C0 E1_H02W0401 +arc: C1 V02N0601 +arc: C3 V02N0601 +arc: C7 E1_H02W0601 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D0 V02N0001 +arc: D1 F0 +arc: D3 E1_H02W0201 +arc: D7 E1_H02W0201 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 F2 +arc: E1_H02E0601 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F1 +arc: H00R0000 Q6 +arc: LSR0 E1_H02W0301 +arc: M2 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +arc: V00B0000 Q6 +arc: V00T0000 F0 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0010001100110011 +word: SLICEB.K0.INIT 1111111111111111 +word: SLICEB.K1.INIT 0001000000000000 +word: SLICEA.K0.INIT 0011001100111111 +word: SLICEA.K1.INIT 1111000011111111 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R33C3:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 H01E0101 +arc: H00R0100 V02N0501 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0401 N3_V06S0203 +arc: V00T0000 H02E0201 +arc: A0 V02S0701 +arc: A2 H02E0701 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B2 S1_V02N0101 +arc: B3 Q3 +arc: CE1 H00R0100 +arc: CE2 V02N0601 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q2 +arc: E1_H02E0301 Q3 +arc: E3_H06E0003 Q3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: S1_V02S0501 Q7 +arc: S1_V02S0601 Q4 +arc: S3_V06S0303 Q5 +arc: V00B0000 Q4 +arc: V01S0100 Q6 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R33C4:PLC2 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0000 V02N0601 +arc: N1_V02N0401 H01E0001 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0301 H01E0101 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 V02N0601 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 N1_V01N0101 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CE2 V02N0601 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0100 +arc: E3_H06E0003 Q3 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q6 +arc: S1_V02S0001 Q2 +arc: S1_V02S0101 Q3 +arc: S1_V02S0601 Q4 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q7 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q4 +arc: V00T0000 Q0 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R33C5:PLC2 +arc: E1_H02E0201 S3_V06N0103 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06S0303 +arc: H00L0000 W1_H02E0001 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0501 E1_H02W0501 +arc: V00B0000 V02S0001 +arc: W1_H02W0401 N3_V06S0203 +arc: A4 S1_V02N0301 +arc: A5 V02N0101 +arc: A6 V02S0301 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B5 H00L0000 +arc: B6 W1_H02E0101 +arc: C5 H02E0601 +arc: C6 W1_H02E0401 +arc: C7 V02N0001 +arc: CE0 V02N0201 +arc: CLK0 G_HPBX0100 +arc: D4 V02S0601 +arc: D5 S1_V02N0601 +arc: D6 V02N0601 +arc: D7 V00B0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F7 +arc: N1_V02N0401 F4 +arc: N1_V02N0701 F5 +arc: S1_V02S0101 Q1 +arc: S3_V06S0003 Q0 +arc: V00T0000 Q0 +arc: V01S0000 F6 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 1010101000000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R33C6:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 N1_V02S0701 +arc: H00R0000 H02W0601 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0003 H06E0003 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 V02S0401 +arc: V00T0100 E1_H02W0101 +arc: W1_H02W0401 S1_V02N0401 +arc: A7 N1_V01N0101 +arc: B6 V02N0501 +arc: B7 N1_V02S0501 +arc: C7 V01N0101 +arc: CE0 H00R0000 +arc: CE1 H00R0100 +arc: CE2 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D6 E1_H02W0201 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 Q0 +arc: E1_H02E0001 Q2 +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: H01W0100 F7 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M0 V00T0000 +arc: M2 H02E0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q4 +arc: V01S0000 Q4 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1100110000000000 +word: SLICED.K1.INIT 0000011101110111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R33C7:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H06E0003 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0303 H06E0303 +arc: V00B0000 V02S0001 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0501 S3_V06N0303 +arc: A4 F5 +arc: A5 H02W0701 +arc: A6 H02E0501 +arc: A7 F5 +arc: B4 V02N0501 +arc: B5 N1_V02S0501 +arc: B6 V02N0501 +arc: B7 H01E0101 +arc: C5 S1_V02N0201 +arc: C7 V02N0001 +arc: CE0 N1_V02S0201 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D5 V02N0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F4 +arc: E1_H02E0001 Q2 +arc: E1_H02E0601 F6 +arc: E1_H02E0701 F5 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F5 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q0 +arc: W1_H02W0601 F6 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1000100010001000 +word: SLICEC.K1.INIT 0100000000000000 +word: SLICED.K0.INIT 1000100010001000 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R33C8:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0601 E3_H06W0303 +arc: H00R0000 H02E0601 +arc: H00R0100 W1_H02E0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0003 V06N0003 +arc: A0 V02S0501 +arc: A3 H02E0701 +arc: B0 N1_V02S0101 +arc: B1 V02N0101 +arc: B3 H01W0100 +arc: C0 V02N0601 +arc: C3 H00R0100 +arc: CE2 H00R0000 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D0 H02E0201 +arc: D1 F0 +arc: D3 W1_H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: H00L0100 F1 +arc: H01W0000 Q4 +arc: H01W0100 Q4 +arc: LSR1 E1_H02W0301 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: S1_V02S0301 F1 +arc: S1_V02S0601 Q6 +arc: S3_V06S0103 F2 +arc: V01S0000 F0 +arc: V01S0100 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1110101011000000 +word: SLICEA.K0.INIT 0000000001000000 +word: SLICEA.K1.INIT 1100110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R33C9:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 N1_V01S0100 +arc: H00R0000 H02E0401 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S3_V06N0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0201 N1_V02S0201 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N1_V02S0201 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0701 V02N0701 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0101 Q2 +arc: LSR1 H02W0301 +arc: M2 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R34C10:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V06S0203 +arc: H00L0000 E1_H02W0201 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 V02N0301 +arc: A0 V02N0501 +arc: A1 V02N0501 +arc: B1 V00B0000 +arc: B4 V02N0501 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C4 V02N0001 +arc: CE0 H00R0000 +arc: CE1 H00L0000 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 V00B0100 +arc: D1 E1_H02W0001 +arc: D4 E1_H02W0001 +arc: D5 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: M2 H02E0601 +arc: M4 W1_H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q0 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q1 +arc: V01S0000 Q2 +arc: W1_H02W0101 Q1 +arc: W3_H06W0203 Q4 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111111100000000 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEA.K1.INIT 1100110011001010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 + +.tile R34C11:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 E1_H01W0000 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 E1_H01W0000 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0301 +arc: V00T0000 E1_H02W0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S3_V06N0303 +arc: W1_H02W0701 V06S0203 +arc: H01W0100 W3_H06E0303 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A4 V00B0000 +arc: A5 V02N0101 +arc: B0 H00R0100 +arc: B1 H00R0100 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 V02N0501 +arc: B5 V00B0100 +arc: B7 H02W0301 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 H02W0401 +arc: C5 S1_V02N0201 +arc: C7 E1_H01E0101 +arc: CLK1 G_HPBX0100 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 V02N0401 +arc: D5 H02E0201 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F1 +arc: E3_H06E0003 F0 +arc: E3_H06E0203 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q7 +arc: LSR1 V00T0000 +arc: MUXCLK3 CLK1 +arc: N1_V01N0101 F2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK + +.tile R34C12:PLC2 +arc: E1_H02E0401 V02N0401 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 W1_H02E0301 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 V01N0001 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A1 H02E0501 +arc: A5 N1_V02S0301 +arc: B0 F1 +arc: B1 H02E0301 +arc: B3 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 S1_V02N0601 +arc: C3 H00L0100 +arc: C5 S1_V02N0001 +arc: C7 W1_H02E0401 +arc: CLK0 G_HPBX0100 +arc: D0 V02S0001 +arc: D1 S1_V02N0201 +arc: D3 V02S0201 +arc: D5 V02S0601 +arc: D7 V02S0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F3 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 F3 +arc: E1_H02E0301 F1 +arc: E1_H02E0501 F7 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F1 +arc: MUXCLK0 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: N1_V02N0101 F3 +arc: N1_V02N0301 F1 +arc: N3_V06N0003 F3 +arc: N3_V06N0103 F1 +arc: N3_V06N0203 F7 +arc: N3_V06N0303 F5 +arc: V01S0000 F7 +arc: V01S0100 F3 +arc: W1_H02W0101 F3 +arc: W1_H02W0301 F1 +arc: W1_H02W0501 F5 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 0111010101000101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1100110000001111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111000001010101 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1100110000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 + +.tile R34C13:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0401 H01E0001 +arc: E1_H02E0601 H01E0001 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 H02E0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 N1_V02S0501 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 V02N0001 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 E1_H02W0401 +arc: E1_H02E0501 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0203 +arc: A0 F7 +arc: A1 F7 +arc: A2 F7 +arc: A3 F7 +arc: A4 V02N0101 +arc: A5 E1_H02W0701 +arc: B0 H00R0100 +arc: B1 H00R0100 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 V00B0100 +arc: B5 H00L0000 +arc: B7 V02N0501 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: C4 H02E0401 +arc: C5 V00T0100 +arc: C7 E1_H02W0601 +arc: CLK1 G_HPBX0100 +arc: D0 H01E0101 +arc: D1 H01E0101 +arc: D2 H01E0101 +arc: D3 H01E0101 +arc: D4 V02N0401 +arc: D5 E1_H02W0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F0 +arc: E1_H02E0701 F7 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F7 +arc: LSR1 V00B0000 +arc: N3_V06N0203 F7 +arc: V01S0100 F1 +arc: W1_H02W0701 F7 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1100000011001111 +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 + +.tile R34C14:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 V02N0001 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 W1_H02E0701 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0701 N1_V01S0100 +arc: V00B0000 S1_V02N0201 +arc: V00T0100 W1_H02E0101 +arc: V01S0000 S3_V06N0103 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0103 E1_H01W0100 +arc: A0 H01E0001 +arc: A1 H01E0001 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 V00B0000 +arc: A5 S1_V02N0101 +arc: A6 V02N0101 +arc: A7 H00R0000 +arc: B0 H00R0100 +arc: B1 H00R0100 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 V02N0501 +arc: B5 H00L0000 +arc: B6 V00B0100 +arc: B7 V01S0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 V01N0101 +arc: C5 E1_H02W0401 +arc: C6 V02S0201 +arc: C7 S1_V02N0001 +arc: CLK1 G_HPBX0100 +arc: D0 V00T0100 +arc: D1 V00T0100 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 E1_H02W0201 +arc: D5 H00L0100 +arc: D6 N1_V02S0601 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H01W0000 F1 +arc: H01W0100 F2 +arc: LSR0 H02E0501 +arc: LSR1 H02E0301 +arc: MUXCLK3 CLK1 +arc: MUXLSR3 LSR0 +arc: N3_V06N0203 Q7 +arc: S1_V02S0501 Q7 +arc: S3_V06S0203 Q7 +arc: V00B0100 Q7 +word: SLICED.K0.INIT 0100010011101100 +word: SLICED.K1.INIT 1111111110101110 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R34C15:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 W1_H02E0701 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 H02E0001 +arc: H00R0000 H02E0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 H06E0303 +arc: S3_V06S0003 N1_V01S0000 +arc: S3_V06S0203 N1_V01S0000 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V00B0100 E1_H02W0501 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 V02N0501 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0701 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: A4 V02N0301 +arc: A5 V00B0000 +arc: A6 V02S0101 +arc: A7 E1_H01W0000 +arc: B0 H00R0100 +arc: B1 H00R0100 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 V02N0501 +arc: B5 V02S0701 +arc: B6 E1_H02W0101 +arc: C0 H00L0000 +arc: C1 H00L0000 +arc: C2 H00L0000 +arc: C3 H00L0000 +arc: C4 E1_H02W0401 +arc: C5 S1_V02N0001 +arc: C6 V00B0100 +arc: C7 F6 +arc: CLK1 G_HPBX0100 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 H02W0201 +arc: D5 V02N0401 +arc: D6 W1_H02E0001 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: LSR1 W1_H02E0301 +arc: MUXCLK3 CLK1 +arc: V01S0000 F1 +arc: V01S0100 F0 +arc: W1_H02W0401 F6 +arc: W3_H06W0203 Q7 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1010000000000000 +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R34C16:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0301 N1_V02S0301 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0203 N1_V02S0701 +arc: V00B0000 E1_H02W0601 +arc: V00T0000 H02W0201 +arc: V00T0100 E1_H02W0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0203 E3_H06W0203 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 V02N0301 +arc: A5 V00T0000 +arc: A6 H02W0701 +arc: A7 V02N0101 +arc: B0 H00R0100 +arc: B1 V00B0000 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 S1_V02N0501 +arc: B5 H02W0301 +arc: B7 V02S0501 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 V00T0100 +arc: C5 S1_V02N0201 +arc: C6 E1_H01E0101 +arc: C7 W1_H02E0601 +arc: CE3 H00L0100 +arc: CLK1 G_HPBX0100 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 V02S0401 +arc: D5 V01N0001 +arc: D6 V02S0601 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q7 +arc: LSR1 H02E0301 +arc: MUXCLK3 CLK1 +arc: S3_V06S0003 F0 +arc: S3_V06S0103 F1 +arc: W3_H06W0303 F6 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000101 +word: SLICED.K1.INIT 1010110010101100 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R34C17:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0100 H02E0301 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 S3_V06N0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 E3_H06W0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02N0401 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0401 W3_H06E0203 +arc: W3_H06W0103 E3_H06W0103 +arc: W3_H06W0203 E3_H06W0103 +arc: A1 V02N0701 +arc: A2 V02S0501 +arc: A5 V02S0301 +arc: A6 F7 +arc: B2 H02E0301 +arc: B3 V01N0001 +arc: B6 N1_V01S0000 +arc: B7 V02S0701 +arc: C1 N1_V01S0100 +arc: C2 N1_V01N0001 +arc: C3 S1_V02N0601 +arc: C5 V00T0000 +arc: C6 E1_H01E0101 +arc: C7 V02N0201 +arc: CE0 H00L0100 +arc: CE1 H00L0100 +arc: CE2 H00L0100 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D1 S1_V02N0001 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D5 S1_V02N0601 +arc: D6 H01W0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 F3 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: H01W0100 Q5 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: V00T0100 Q3 +arc: W1_H02W0001 F2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0501 Q7 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 Q3 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 0000000000000100 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1010101011110000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111000010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R34C18:PLC2 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 S3_V06N0303 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 H02W0601 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0201 +arc: V00T0100 H02W0101 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0701 V02N0701 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: E1_H02E0401 W3_H06E0203 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: H01W0000 W3_H06E0103 +arc: H01W0100 W3_H06E0303 +arc: S3_V06S0103 W3_H06E0103 +arc: W1_H02W0001 W3_H06E0003 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0601 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0501 +arc: A2 E1_H02W0501 +arc: A3 E1_H02W0501 +arc: A4 V00B0000 +arc: A5 V00T0000 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: B4 V02N0501 +arc: B5 H02E0301 +arc: B7 F3 +arc: C0 H00R0100 +arc: C1 H00R0100 +arc: C2 H00R0100 +arc: C3 H00R0100 +arc: C4 V00B0100 +arc: C5 V02N0201 +arc: C7 H02E0601 +arc: CLK1 G_HPBX0100 +arc: D0 H02W0001 +arc: D1 H02W0201 +arc: D2 H02W0001 +arc: D3 H02W0201 +arc: D4 V02N0401 +arc: D5 W1_H02E0001 +arc: D7 H01W0000 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00T0100 +arc: MUXCLK3 CLK1 +arc: S1_V02S0001 F2 +arc: S1_V02S0101 F1 +arc: S3_V06S0003 F0 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R34C19:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 S3_V06N0003 +arc: H00R0000 H02W0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 N1_V02S0701 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02N0701 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0001 W3_H06E0003 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0601 W3_H06E0303 +arc: E1_H02E0701 W3_H06E0203 +arc: S1_V02S0601 W3_H06E0303 +arc: W3_H06W0003 S3_V06N0003 +arc: W3_H06W0103 S3_V06N0103 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A4 V02S0101 +arc: A5 V00T0000 +arc: B0 H00R0100 +arc: B1 H00R0100 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 V02N0501 +arc: B5 H00R0000 +arc: B7 H02E0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 E1_H02W0401 +arc: C5 V00B0100 +arc: C7 V00T0100 +arc: CLK1 G_HPBX0100 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 V02N0401 +arc: D5 N1_V02S0401 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F0 +arc: E3_H06E0203 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK3 CLK1 +arc: S3_V06S0203 Q7 +arc: V00T0100 F1 +arc: V01S0000 F3 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R34C20:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 H02W0701 +arc: V00T0100 H02W0101 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V01N0101 +arc: E1_H02E0601 W3_H06E0303 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A2 H02E0701 +arc: A3 H02E0701 +arc: A4 V02S0101 +arc: A5 V00T0100 +arc: B0 H00R0100 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: B3 H00R0100 +arc: B4 V02N0501 +arc: B5 N1_V01S0000 +arc: B7 W1_H02E0101 +arc: C0 W1_H02E0401 +arc: C1 W1_H02E0401 +arc: C2 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: C4 V01N0101 +arc: C5 V00B0100 +arc: C7 H01E0001 +arc: CLK1 G_HPBX0100 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D2 W1_H02E0001 +arc: D3 W1_H02E0001 +arc: D4 V02N0401 +arc: D5 N1_V02S0401 +arc: D7 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F1 +arc: LSR1 H02E0301 +arc: MUXCLK3 CLK1 +arc: S1_V02S0101 F3 +arc: S1_V02S0501 Q7 +arc: S3_V06S0203 Q7 +arc: V01S0100 F2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111001111000000 +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 + +.tile R34C21:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 W1_H02E0601 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0203 N1_V01S0000 +arc: H00L0000 V02N0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 V01N0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H06E0203 +arc: S1_V02S0601 N1_V01S0000 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 N3_V06S0003 +arc: V00B0000 V02N0201 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 W1_H02E0701 +arc: A1 W1_H02E0701 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: A4 V02N0301 +arc: A5 V00B0000 +arc: B0 H00R0100 +arc: B1 H00R0100 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B7 H02E0301 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 E1_H02W0401 +arc: C5 V00B0100 +arc: C7 H02E0601 +arc: CLK1 G_HPBX0100 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 S1_V02N0401 +arc: D5 H00L0100 +arc: D7 F0 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: LSR1 W1_H02E0301 +arc: MUXCLK3 CLK1 +arc: S3_V06S0203 Q7 +arc: V01S0000 F1 +arc: V01S0100 F2 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111001111000000 +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 + +.tile R34C22:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 S1_V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 V06S0203 +arc: H00R0100 H02E0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0401 N1_V02S0401 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 V02S0201 +arc: A2 E1_H02W0501 +arc: A6 H02E0701 +arc: B1 H02E0101 +arc: B2 H02E0301 +arc: B6 H02E0301 +arc: C1 E1_H02W0401 +arc: C2 H02E0601 +arc: C6 V00T0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D1 H02E0001 +arc: D2 W1_H02E0201 +arc: D6 H02E0201 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F6 F5D_SLICE +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0001 Q2 +arc: V00T0100 Q1 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q6 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1110110010100000 +word: SLICEB.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111110000001100 +word: SLICED.K0.INIT 1110101011000000 +word: SLICED.K1.INIT 1111111111111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R34C23:PLC2 +arc: E1_H02E0501 V02S0501 +arc: N1_V02N0401 H02E0401 +arc: W1_H02W0401 V02N0401 +arc: W1_H02W0601 V02N0601 +arc: A0 F5 +arc: A1 F5 +arc: A2 F5 +arc: A3 F5 +arc: A5 H02E0701 +arc: A7 V02N0101 +arc: B1 V02S0301 +arc: B4 H02E0301 +arc: B5 H02E0101 +arc: B6 S1_V02N0501 +arc: C0 F4 +arc: C1 F4 +arc: C2 F4 +arc: C3 F4 +arc: C5 H02E0601 +arc: C6 S1_V02N0001 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 H00R0000 +arc: D3 H00R0000 +arc: D4 S1_V02N0601 +arc: D5 E1_H02W0201 +arc: D6 S1_V02N0401 +arc: D7 S1_V02N0601 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: M0 V00B0100 +arc: M1 H02E0001 +arc: M2 V00B0100 +arc: V00B0100 F7 +arc: W3_H06W0103 F1 +word: SLICED.K0.INIT 0000000000000011 +word: SLICED.K1.INIT 0101010100000000 +word: SLICEC.K0.INIT 0000000000110011 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0101111111111111 +word: SLICEA.K1.INIT 0001001100110011 +word: SLICEB.K0.INIT 0101111111111111 +word: SLICEB.K1.INIT 0101111111111111 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R34C24:PLC2 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: V00B0000 V02S0001 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0401 W3_H06E0203 +arc: A4 H02E0501 +arc: A5 V02N0101 +arc: C4 V02S0001 +arc: C5 F4 +arc: CLK0 G_HPBX0100 +arc: D4 V02N0601 +arc: D5 H02W0001 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M2 V00B0000 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F5 +arc: N3_V06N0103 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000101001011111 +word: SLICEC.K1.INIT 1010101011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R34C25:PLC2 +arc: N1_V02N0501 S1_V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0201 S1_V02N0201 + +.tile R34C2:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 H02W0301 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0100 S1_V02N0101 +arc: A3 E1_H01E0001 +arc: D3 V00B0100 +arc: E1_H02E0301 F3 +arc: E3_H06E0003 F3 +arc: F3 F3_SLICE +arc: N1_V02N0101 F3 +arc: S1_V02S0101 F3 +arc: V01S0000 F3 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1010101000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R34C3:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0601 E3_H06W0303 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0601 N1_V02S0601 +arc: S3_V06S0003 H06W0003 +arc: S3_V06S0103 N1_V01S0100 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 E1_H02W0401 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: A0 S1_V02N0701 +arc: A2 V00T0000 +arc: A5 Q5 +arc: A7 Q7 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V01S0000 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0101 Q4 +arc: E1_H02E0301 Q3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: LSR0 V00B0000 +arc: LSR1 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q2 +arc: S1_V02S0701 Q5 +arc: S3_V06S0303 Q6 +arc: V00T0000 Q2 +arc: V01S0000 Q6 +arc: V01S0100 Q7 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R34C4:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 W1_H02E0301 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 H02E0601 +arc: S1_V02S0701 H01E0101 +arc: W1_H02W0601 E1_H02W0601 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0001 Q4 +arc: E1_H02E0301 Q1 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q6 +arc: H01W0000 Q0 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: S1_V02S0101 Q3 +arc: S1_V02S0201 Q2 +arc: S3_V06S0303 Q6 +arc: V00B0000 Q4 +arc: V00T0000 Q0 +arc: V01S0100 Q5 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R34C5:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 W1_H02E0101 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06S0303 +arc: E3_H06E0303 V06S0303 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 H06W0203 +arc: V01S0000 N3_V06S0103 +arc: A4 F5 +arc: A5 H02E0701 +arc: A6 F7 +arc: A7 W1_H02E0501 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B5 H02E0301 +arc: B7 N1_V01S0000 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C6 H02E0601 +arc: C7 F4 +arc: CLK0 G_HPBX0100 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: D6 S1_V02N0601 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F6 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q1 +arc: V00B0000 F6 +arc: V00T0000 Q0 +arc: W1_H02W0401 F6 +word: SLICEC.K0.INIT 1010000000001010 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICED.K0.INIT 1111101011110000 +word: SLICED.K1.INIT 1000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R34C6:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V06S0203 +arc: H00R0000 V02S0601 +arc: H00R0100 H02E0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E3_H06W0303 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 H02E0601 +arc: S3_V06S0003 E1_H01W0000 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H06W0303 +arc: V00B0000 V02N0001 +arc: V00B0100 H02W0701 +arc: V00T0100 V02S0701 +arc: W1_H02W0301 H01E0101 +arc: W3_H06W0003 E1_H01W0000 +arc: A1 H01E0001 +arc: A6 N1_V01N0101 +arc: A7 V00T0100 +arc: B0 F1 +arc: B1 V02N0301 +arc: B6 V01S0000 +arc: B7 W1_H02E0101 +arc: C1 N1_V01S0100 +arc: C6 V02N0201 +arc: C7 F6 +arc: CE1 H00R0000 +arc: CE2 V02S0601 +arc: CLK0 G_HPBX0100 +arc: D0 E1_H02W0201 +arc: D1 N1_V01S0000 +arc: D6 H00R0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0101 F1 +arc: E1_H02E0301 F1 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: LSR1 V00B0000 +arc: M2 V00B0100 +arc: M4 H02E0401 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q4 +arc: S3_V06S0103 F1 +arc: V01S0000 Q2 +arc: W1_H02W0601 F6 +arc: W3_H06W0303 F6 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1110101010101010 +word: SLICED.K1.INIT 1111111100010000 +word: SLICEA.K0.INIT 1100110011111111 +word: SLICEA.K1.INIT 1111111110000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R34C7:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0301 N3_V06S0003 +arc: E3_H06E0203 V06S0203 +arc: E3_H06E0303 W1_H02E0501 +arc: H00L0000 H02W0001 +arc: H00L0100 H02W0301 +arc: H00R0000 V02S0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0101 V01N0101 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0103 E1_H01W0100 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 V02N0701 +arc: A1 H00L0000 +arc: A2 N1_V02S0501 +arc: A6 H02E0701 +arc: A7 E1_H02W0701 +arc: B1 H02E0301 +arc: B2 E1_H01W0100 +arc: B6 V02N0701 +arc: B7 V00B0100 +arc: C1 V02S0401 +arc: C3 W1_H02E0601 +arc: C6 E1_H02W0601 +arc: C7 H02W0401 +arc: CE2 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D1 V02S0201 +arc: D2 V00T0100 +arc: D3 H00R0000 +arc: D6 E1_H01W0100 +arc: D7 E1_H02W0001 +arc: E1_H01E0001 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: H01W0100 F6 +arc: M0 V00T0000 +arc: M4 V00B0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0203 Q7 +arc: S3_V06S0003 F3 +arc: V00T0000 F2 +arc: V00T0100 F3 +arc: V01S0000 F3 +arc: V01S0100 Q4 +arc: W1_H02W0101 F3 +arc: W3_H06W0203 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1111111111111111 +word: SLICEA.K1.INIT 0000000001000000 +word: SLICED.K0.INIT 0010101010101010 +word: SLICED.K1.INIT 1110110010100000 +word: SLICEB.K0.INIT 0011001101110111 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R34C8:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 V01N0001 +arc: E1_H02E0701 S1_V02N0701 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 S1_V02N0301 +arc: S1_V02S0401 H02W0401 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 S1_V02N0601 +arc: S3_V06S0003 W3_H06E0003 +arc: W1_H02W0301 W3_H06E0003 +arc: W3_H06W0203 E1_H01W0000 +arc: A1 H00L0000 +arc: A2 E1_H01E0001 +arc: A4 V00T0000 +arc: A5 N1_V01N0101 +arc: A6 V02N0101 +arc: A7 W1_H02E0701 +arc: B1 W1_H02E0101 +arc: B2 F3 +arc: B4 W1_H02E0101 +arc: B5 N1_V01S0000 +arc: B6 V02S0701 +arc: B7 N1_V01S0000 +arc: C1 N1_V01S0100 +arc: C2 N1_V01N0001 +arc: C3 V02N0601 +arc: C4 S1_V02N0201 +arc: C5 F6 +arc: C6 W1_H02E0401 +arc: C7 F6 +arc: CE0 H02E0101 +arc: CLK0 G_HPBX0100 +arc: D1 S1_V02N0201 +arc: D2 W1_H02E0201 +arc: D3 H02E0001 +arc: D4 F2 +arc: D5 V02S0601 +arc: D6 S1_V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F3 +arc: LSR0 E1_H02W0301 +arc: LSR1 E1_H02W0301 +arc: M0 H01E0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q4 +arc: N1_V02N0101 F3 +arc: S1_V02S0501 F7 +arc: V00T0000 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000010111111 +word: SLICEC.K0.INIT 1111111100000100 +word: SLICEC.K1.INIT 1110110000000000 +word: SLICEB.K0.INIT 0111000011110000 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICED.K0.INIT 0001000000000000 +word: SLICED.K1.INIT 1110110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R34C9:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0601 E3_H06W0303 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 H02E0701 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 E3_H06W0203 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0301 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 E3_H06W0203 +arc: W1_H02W0601 H01E0001 +arc: W1_H02W0701 H01E0101 +arc: W3_H06W0303 E3_H06W0203 +arc: CE0 H00R0100 +arc: CE1 H00L0000 +arc: CE2 H00L0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: H01W0000 Q2 +arc: H01W0100 Q4 +arc: M0 V00B0100 +arc: M2 H02E0601 +arc: M4 V00B0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0001 Q0 +arc: S3_V06S0103 Q2 +arc: S3_V06S0303 Q6 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R35C10:PLC2 +arc: E1_H02E0101 E3_H06W0103 +arc: E1_H02E0301 S1_V02N0301 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 H02E0501 +arc: N3_V06N0103 S3_V06N0003 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0001 S1_V02N0001 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0100 +arc: H01W0000 Q4 +arc: LSR1 V00B0000 +arc: M4 V00B0100 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R35C11:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0601 E1_H01W0000 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 S3_V06N0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0303 V06N0303 +arc: CE0 H00R0100 +arc: CLK0 G_HPBX0100 +arc: LSR1 H02E0301 +arc: M0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R35C12:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 S3_V06N0203 +arc: H00R0000 V02S0401 +arc: H00R0100 V02N0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 N1_V01S0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 S3_V06N0203 +arc: V00T0000 V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0401 S3_V06N0203 +arc: CE0 H00R0000 +arc: CE1 H02W0101 +arc: CE2 H00R0000 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 Q4 +arc: H01W0000 Q6 +arc: H01W0100 Q6 +arc: M0 V00B0000 +arc: M2 H02E0601 +arc: M4 H02W0401 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: S1_V02S0001 Q0 +arc: V00B0000 Q4 +arc: V01S0100 Q2 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R35C13:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E3_H06E0103 N1_V01S0100 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0601 H06W0303 +arc: V00B0100 V02N0101 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0401 N1_V02S0401 +arc: A0 S1_V02N0501 +arc: A5 F7 +arc: A7 N1_V01N0101 +arc: B0 H02E0101 +arc: B1 V00T0000 +arc: B5 E1_H02W0101 +arc: B6 E1_H02W0101 +arc: B7 V02S0501 +arc: C0 V02N0601 +arc: C4 E1_H01E0101 +arc: C5 N1_V02S0201 +arc: C6 V00T0100 +arc: C7 V02S0201 +arc: CE0 H00R0000 +arc: CE1 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D0 N1_V02S0201 +arc: D1 V01S0100 +arc: D5 S1_V02N0601 +arc: D6 V02N0601 +arc: D7 V00B0000 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0000 F4 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M2 H02W0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q0 +arc: S1_V02S0201 Q2 +arc: S1_V02S0301 F1 +arc: S1_V02S0701 F7 +arc: S3_V06S0103 F1 +arc: S3_V06S0203 F7 +arc: V00B0000 Q6 +arc: V00T0000 Q0 +arc: V01S0000 Q2 +arc: V01S0100 F7 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0011000000000000 +word: SLICED.K1.INIT 0000000000010011 +word: SLICEA.K0.INIT 0001000000110000 +word: SLICEA.K1.INIT 1100110000000000 +word: SLICEC.K0.INIT 0000111100001111 +word: SLICEC.K1.INIT 0101011101110111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R35C14:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0303 V06N0303 +arc: H00R0000 S1_V02N0401 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0303 E3_H06W0303 +arc: V00B0000 V02S0201 +arc: V01S0100 S3_V06N0303 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V02N0601 +arc: W3_H06W0003 N3_V06S0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A4 N1_V02S0101 +arc: A5 V00B0000 +arc: A6 N1_V02S0301 +arc: B0 S1_V02N0301 +arc: B2 E1_H01W0100 +arc: B3 E1_H02W0101 +arc: CE1 H00R0000 +arc: CE2 S1_V02N0601 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0001 Q3 +arc: E1_H02E0201 Q2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q6 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 Q4 +arc: N1_V02N0601 Q6 +arc: N1_V02N0701 Q5 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 0101010101011010 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R35C15:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0303 S3_V06N0303 +arc: H00R0100 H02E0701 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 H02W0601 +arc: S3_V06S0003 H06E0003 +arc: S3_V06S0203 H06E0203 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0501 S3_V06N0303 +arc: A5 N1_V01S0100 +arc: A7 H02E0701 +arc: B3 V02S0101 +arc: B6 H02E0101 +arc: C3 E1_H01W0000 +arc: C5 V02S0201 +arc: C6 H01E0001 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0100 +arc: D3 N1_V01S0000 +arc: D5 H02W0201 +arc: D6 H00R0100 +arc: D7 H02E0201 +arc: E1_H01E0101 F6 +arc: E1_H02E0301 Q3 +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F7 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q5 +arc: N3_V06N0303 Q5 +word: SLICED.K0.INIT 1111000011001100 +word: SLICED.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111001111000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 + +.tile R35C16:PLC2 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0103 V06N0103 +arc: E3_H06E0203 V06N0203 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S3_V06N0103 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 E3_H06W0303 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 S3_V06N0203 +arc: S1_V02S0501 S3_V06N0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0101 +arc: V00T0100 H02W0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 N1_V01S0000 +arc: W3_H06W0103 S3_V06N0103 +arc: W3_H06W0303 S3_V06N0303 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A2 V02S0701 +arc: A3 V02S0701 +arc: A4 V00T0100 +arc: A5 N1_V02S0101 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B4 V02N0501 +arc: B5 N1_V02S0701 +arc: B7 F3 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 E1_H02W0401 +arc: C5 V02N0001 +arc: C7 V02S0201 +arc: CLK1 G_HPBX0100 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D2 H02E0001 +arc: D3 V02S0001 +arc: D4 N1_V02S0401 +arc: D5 H00R0100 +arc: D7 V02S0401 +arc: E1_H01E0001 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: LSR1 V00B0100 +arc: MUXCLK3 CLK1 +arc: S3_V06S0203 Q7 +arc: V01S0100 F2 +arc: W1_H02W0201 F0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C17:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0501 S3_V06N0303 +arc: E1_H02E0601 H01E0001 +arc: E3_H06E0303 S3_V06N0303 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 W1_H02E0301 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0203 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0303 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 S3_V06N0303 +arc: V00B0000 S1_V02N0001 +arc: V00T0000 E1_H02W0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 S3_V06N0303 +arc: W1_H02W0701 N3_V06S0203 +arc: W3_H06W0303 S3_V06N0303 +arc: A5 V00T0000 +arc: A6 V02N0101 +arc: B1 V02S0101 +arc: B3 H02E0301 +arc: B5 V02N0701 +arc: B6 H02W0301 +arc: C1 N1_V02S0401 +arc: C3 H00L0000 +arc: C6 E1_H02W0601 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CE2 V02N0601 +arc: CE3 W1_H02E0101 +arc: CLK0 G_HPBX0100 +arc: D1 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D5 V02S0401 +arc: D6 H00L0100 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F1 +arc: E1_H02E0401 Q6 +arc: E1_H02E0701 F5 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q3 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V02N0701 Q5 +arc: W1_H02W0601 Q6 +word: SLICED.K0.INIT 1110110010100000 +word: SLICED.K1.INIT 1111111111111111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1101110110001000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111000011001100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111000011001100 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 + +.tile R35C18:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0601 N1_V02S0601 +arc: E1_H02E0701 N3_V06S0203 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0401 S3_V06N0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0701 S3_V06N0203 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0001 H01E0001 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 W1_H02E0701 +arc: A1 F5 +arc: A5 N1_V01N0101 +arc: A6 H02E0701 +arc: A7 W1_H02E0701 +arc: B0 V01N0001 +arc: B1 F3 +arc: B3 V02N0101 +arc: B4 H02W0301 +arc: B5 V02N0701 +arc: B6 N1_V02S0501 +arc: B7 V00B0100 +arc: C0 N1_V01N0001 +arc: C1 W1_H02E0601 +arc: C3 V02N0401 +arc: C4 V01N0101 +arc: C5 H02E0401 +arc: C6 V02N0201 +arc: C7 F6 +arc: CE0 E1_H02W0101 +arc: CE1 H00R0100 +arc: CE2 V02N0601 +arc: CE3 E1_H02W0101 +arc: CLK0 G_HPBX0100 +arc: D0 N1_V02S0001 +arc: D1 V02N0201 +arc: D3 H02E0201 +arc: D5 V02N0401 +arc: D6 V00B0000 +arc: D7 S1_V02N0601 +arc: E1_H01E0101 Q4 +arc: E1_H02E0501 Q7 +arc: E3_H06E0203 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q3 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F1 +arc: N1_V01N0101 Q4 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q0 +arc: N3_V06N0203 Q7 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 0011001100000101 +word: SLICEA.K1.INIT 0011101011110011 +word: SLICED.K0.INIT 0101111111000101 +word: SLICED.K1.INIT 0000000111001101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEC.K0.INIT 0011000000110000 +word: SLICEC.K1.INIT 1001010001001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R35C19:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 V01N0101 +arc: E3_H06E0103 S3_V06N0103 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0203 N3_V06S0103 +arc: V00B0100 H02W0701 +arc: V00T0000 H02W0201 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0201 S3_V06N0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V02S0601 +arc: E1_H02E0101 W3_H06E0103 +arc: A0 V01N0101 +arc: A1 H02E0501 +arc: A3 V00B0000 +arc: A5 E1_H02W0701 +arc: A6 H02E0701 +arc: B0 E1_H02W0101 +arc: B3 E1_H01W0100 +arc: B5 N1_V02S0501 +arc: B6 H02E0301 +arc: C1 H02E0601 +arc: C3 H02E0601 +arc: C5 E1_H02W0601 +arc: C6 W1_H02E0601 +arc: CE3 W1_H02E0101 +arc: CLK0 G_HPBX0100 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D3 S1_V02N0001 +arc: D5 H02E0201 +arc: D6 V02S0601 +arc: E1_H01E0001 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q6 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V02N0101 F3 +arc: N1_V02N0301 F1 +arc: V00B0000 Q6 +arc: V00T0100 F1 +word: SLICED.K0.INIT 1110101011000000 +word: SLICED.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 1110111001000100 +word: SLICEA.K1.INIT 0101010100001111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000010000100001 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R35C20:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N1_V02S0701 +arc: E3_H06E0203 S3_V06N0203 +arc: H00L0100 V02N0101 +arc: H00R0100 V02N0701 +arc: N1_V01N0101 S3_V06N0203 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H06E0303 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0203 S3_V06N0203 +arc: S1_V02S0201 N1_V02S0701 +arc: V00B0100 H02W0501 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0103 V06N0103 +arc: A0 H01E0001 +arc: A1 N1_V02S0501 +arc: A3 H02E0501 +arc: A5 V02S0101 +arc: A6 N1_V02S0301 +arc: A7 S1_V02N0101 +arc: B0 F1 +arc: B1 W1_H02E0101 +arc: B6 V00B0100 +arc: B7 H02E0301 +arc: C0 V02N0601 +arc: C1 E1_H02W0401 +arc: C3 N1_V01S0100 +arc: C5 V02S0201 +arc: C6 V00T0000 +arc: C7 V00T0100 +arc: CE0 H00L0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 V02S0001 +arc: D1 E1_H02W0201 +arc: D3 V02S0201 +arc: D5 H02E0001 +arc: D6 H02E0201 +arc: D7 V00B0000 +arc: E1_H01E0101 F7 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q6 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0601 Q6 +arc: N3_V06N0003 Q0 +arc: S1_V02S0101 Q3 +arc: S3_V06S0303 Q5 +arc: V00B0000 Q6 +arc: V01S0100 Q0 +arc: W3_H06W0303 Q5 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111101000001010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1010101011110000 +word: SLICEA.K0.INIT 0101010100000011 +word: SLICEA.K1.INIT 0011101011110011 +word: SLICED.K0.INIT 1111100010001000 +word: SLICED.K1.INIT 1001001001110101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R35C21:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 V02S0101 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 H06E0203 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 N1_V02S0201 +arc: W1_H02W0701 V01N0101 +arc: W1_H02W0501 W3_H06E0303 +arc: A2 W1_H02E0701 +arc: A3 H02E0701 +arc: A4 V02N0301 +arc: A5 H02E0501 +arc: A7 N1_V01S0100 +arc: B1 W1_H02E0101 +arc: B4 V00B0100 +arc: B5 W1_H02E0301 +arc: B7 V02S0701 +arc: C1 V02S0401 +arc: C2 E1_H01W0000 +arc: C3 W1_H02E0401 +arc: C4 N1_V02S0201 +arc: C5 V01N0101 +arc: CE2 V02N0601 +arc: CLK0 G_HPBX0100 +arc: D1 N1_V01S0000 +arc: D2 V01S0100 +arc: D3 V02S0201 +arc: D4 H02E0201 +arc: D5 V00B0000 +arc: D7 H00L0100 +arc: E1_H01E0001 Q4 +arc: E1_H02E0401 Q4 +arc: E1_H02E0501 F5 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 F2 +arc: S1_V02S0301 Q1 +arc: V00B0000 Q4 +arc: V01S0000 Q7 +arc: V01S0100 F3 +arc: W1_H02W0101 F3 +arc: W1_H02W0601 Q4 +arc: W3_H06W0203 Q4 +word: SLICEB.K0.INIT 1111101001010000 +word: SLICEB.K1.INIT 0000101001011111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1110111000100010 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1100111111000000 +word: SLICEC.K0.INIT 1111100010001000 +word: SLICEC.K1.INIT 1001001000101111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R35C22:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 V06S0303 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 H02E0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 V01N0001 +arc: V00T0000 H02E0201 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V02N0401 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 W3_H06E0203 +arc: A1 V02N0701 +arc: A2 F7 +arc: A4 H02W0701 +arc: A5 N1_V01N0101 +arc: A6 N1_V02S0101 +arc: A7 E1_H02W0701 +arc: B0 F1 +arc: B2 F3 +arc: B3 V02N0101 +arc: B5 V02N0501 +arc: B6 H02W0301 +arc: B7 V00B0000 +arc: C0 E1_H01W0000 +arc: C1 H00R0100 +arc: C2 V02N0401 +arc: C3 V02S0401 +arc: C4 V02N0001 +arc: C5 N1_V02S0001 +arc: C6 V00T0000 +arc: C7 W1_H02E0401 +arc: CE1 H00L0000 +arc: CE2 E1_H02W0101 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D0 V02N0001 +arc: D1 H02E0001 +arc: D2 V02N0201 +arc: D3 V01S0100 +arc: D4 N1_V02S0401 +arc: D5 F2 +arc: D6 H02W0201 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F0 +arc: E1_H02E0401 Q6 +arc: E1_H02E0701 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 F4 +arc: N1_V02N0101 Q3 +arc: V00B0000 Q6 +arc: V01S0100 Q6 +arc: W3_H06W0303 Q6 +word: SLICEA.K0.INIT 1100110011110000 +word: SLICEA.K1.INIT 0101000001011111 +word: SLICEB.K0.INIT 0011101011110011 +word: SLICEB.K1.INIT 1111110000110000 +word: SLICEC.K0.INIT 1010111110100000 +word: SLICEC.K1.INIT 0101000001010011 +word: SLICED.K0.INIT 1110110010100000 +word: SLICED.K1.INIT 1001010001110011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R35C23:PLC2 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02N0601 +arc: N1_V02N0401 H06E0203 +arc: S1_V02S0201 V01N0001 +arc: V00B0100 H02E0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V06S0303 +arc: N1_V02N0601 W3_H06E0303 +arc: A0 W1_H02E0501 +arc: A3 N1_V02S0501 +arc: A4 H02E0501 +arc: B0 F1 +arc: B1 H02E0101 +arc: B4 H00L0000 +arc: B5 N1_V02S0501 +arc: C0 S1_V02N0401 +arc: C1 H02E0601 +arc: C3 H02E0401 +arc: C4 H01E0001 +arc: C5 W1_H02E0401 +arc: CE0 H00R0000 +arc: CE2 H02W0101 +arc: CLK0 G_HPBX0100 +arc: D0 H02E0201 +arc: D1 H02E0001 +arc: D3 V00B0100 +arc: D4 F0 +arc: D5 V00B0000 +arc: E1_H02E0101 F3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F3 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0101 Q1 +arc: N3_V06N0303 Q6 +arc: S1_V02S0501 F5 +arc: V00B0000 Q4 +arc: W1_H02W0701 F5 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000110000011101 +word: SLICEC.K1.INIT 0000001111001111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000010110101111 +word: SLICEA.K0.INIT 0011101011110011 +word: SLICEA.K1.INIT 1111110000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R35C24:PLC2 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: W1_H02W0101 V02N0101 +arc: N1_V02N0701 W3_H06E0203 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0003 E1_H01W0000 + +.tile R35C25:PLC2 +arc: H01W0000 W3_H06E0103 + +.tile R35C26:PLC2 +arc: W1_H02W0601 W3_H06E0303 + +.tile R35C2:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V01N0001 +arc: H00L0100 V02S0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0203 N1_V01S0000 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0000 E1_H02W0201 +arc: CE0 H00L0100 +arc: CE1 V02N0201 +arc: CE2 H00L0100 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q0 +arc: E1_H02E0601 Q4 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R35C3:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V01S0100 +arc: H00R0000 V02N0601 +arc: N1_V02N0101 E1_H01W0100 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0601 +arc: S1_V02S0701 H06W0203 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 N1_V02S0501 +arc: A2 V02S0701 +arc: A3 V02N0501 +arc: A5 V00T0100 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B4 N1_V02S0501 +arc: B5 H02E0301 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C4 H02E0401 +arc: C5 V02N0001 +arc: CE0 H00R0000 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0100 +arc: D2 V02S0001 +arc: D3 V02N0201 +arc: D5 E1_H02W0001 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 F4 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 F3 +arc: E1_H02E0601 F4 +arc: E1_H02E0701 F5 +arc: E3_H06E0303 Q6 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M0 V00T0000 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F2 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0011000000110000 +word: SLICEC.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 1000010000100001 +word: SLICEB.K1.INIT 0000100010001000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R35C4:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0701 H01E0101 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 N1_V02S0601 +arc: N1_V02N0301 S1_V02N0301 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0401 N1_V02S0101 +arc: V00B0000 V02S0201 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0201 E1_H02W0201 +arc: A1 H00R0000 +arc: A2 V00T0000 +arc: A3 V02N0501 +arc: A5 H02E0701 +arc: A6 H02E0501 +arc: A7 V02S0101 +arc: B1 V02N0101 +arc: B2 N1_V02S0301 +arc: B3 E1_H01W0100 +arc: B4 H02E0101 +arc: B5 H00L0000 +arc: B6 V02S0701 +arc: B7 V00B0000 +arc: C1 E1_H02W0401 +arc: C2 N1_V02S0601 +arc: C3 N1_V01N0001 +arc: C5 V02N0201 +arc: C6 H02E0401 +arc: C7 W1_H02E0601 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 S1_V02N0001 +arc: D4 W1_H02E0201 +arc: D5 V01N0001 +arc: D6 W1_H02E0201 +arc: D7 V02S0401 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F1 +arc: E1_H02E0501 F7 +arc: E1_H02E0601 F4 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F3 +arc: N1_V01N0001 F2 +arc: N1_V02N0101 F3 +arc: S1_V02S0701 F5 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 0111111111111111 +word: SLICEC.K0.INIT 0011001100000000 +word: SLICEC.K1.INIT 0010101000000000 +word: SLICED.K0.INIT 1100001101000001 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001001101011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R35C5:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 W1_H02E0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0100 S1_V02N0301 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H06E0203 +arc: S3_V06S0003 N1_V01S0000 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 N1_V02S0101 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0401 N3_V06S0203 +arc: A1 H02E0501 +arc: A2 H02E0701 +arc: A3 S1_V02N0701 +arc: A4 V02S0101 +arc: A5 V02N0301 +arc: A6 V02S0301 +arc: A7 V02S0301 +arc: B1 H02E0101 +arc: B2 N1_V02S0301 +arc: B3 N1_V02S0301 +arc: B4 V02N0701 +arc: B5 H01E0101 +arc: B6 H02E0301 +arc: B7 H02E0301 +arc: C1 F6 +arc: C2 S1_V02N0601 +arc: C3 W1_H02E0601 +arc: C4 S1_V02N0001 +arc: C5 F4 +arc: C6 H02E0601 +arc: C7 H02E0601 +arc: D1 S1_V02N0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 H00L0100 +arc: D5 N1_V02S0401 +arc: D6 H02W0001 +arc: D7 E1_H01W0100 +arc: E1_H01E0101 F0 +arc: E1_H02E0201 F0 +arc: E1_H02E0501 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F2 +arc: M0 H01E0001 +arc: M2 V00B0100 +arc: M6 V00B0000 +arc: V01S0000 F0 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0100000011000000 +word: SLICEB.K0.INIT 0000010000000001 +word: SLICEB.K1.INIT 0000100000000010 +word: SLICED.K0.INIT 0000000000001001 +word: SLICED.K1.INIT 0000100100000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000000000100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R35C6:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H01E0101 +arc: S1_V02S0401 E1_H01W0000 +arc: V00B0100 V02N0301 +arc: V00T0000 N1_V02S0401 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V06S0003 +arc: A1 V02S0501 +arc: A4 V00T0000 +arc: A5 N1_V01N0101 +arc: A6 V02N0101 +arc: A7 F5 +arc: B1 H02E0301 +arc: B4 H02W0101 +arc: B5 H02E0101 +arc: B6 S1_V02N0501 +arc: B7 V02N0501 +arc: C4 E1_H02W0601 +arc: C5 V02N0001 +arc: C6 H02W0401 +arc: C7 F6 +arc: CE1 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D1 V02N0201 +arc: D4 V02S0601 +arc: D5 V00B0000 +arc: D6 H02W0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F4 +arc: E1_H02E0701 F7 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 Q2 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0401 F4 +arc: N3_V06N0103 Q1 +arc: S3_V06S0203 F4 +arc: V00B0000 F4 +arc: W1_H02W0001 Q2 +arc: W1_H02W0401 F4 +arc: W3_H06W0203 F4 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0010000010100000 +word: SLICEC.K0.INIT 0100000000000000 +word: SLICEC.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0010001011111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R35C7:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 S1_V02N0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 W1_H02E0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0100 V02N0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 S1_V02N0401 +arc: A0 H00L0000 +arc: A1 W1_H02E0501 +arc: A2 V02N0701 +arc: A3 E1_H02W0501 +arc: A7 V02N0301 +arc: B0 S1_V02N0301 +arc: B1 V00B0000 +arc: B7 N1_V01S0000 +arc: C0 V02S0601 +arc: C1 V02S0401 +arc: C6 S1_V02N0001 +arc: C7 H01E0001 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 V02S0201 +arc: D1 F0 +arc: D2 H02E0001 +arc: D3 V00T0100 +arc: D6 H01W0000 +arc: D7 V02N0601 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 F3 +arc: E1_H02E0401 F6 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: W3_H06W0103 Q1 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0001010100111111 +word: SLICEA.K1.INIT 0101000001010011 +word: SLICEB.K0.INIT 1010101000000000 +word: SLICEB.K1.INIT 1010101000000000 +word: SLICED.K0.INIT 1111000000000000 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R35C8:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0701 W1_H02E0701 +arc: H00L0000 N1_V02S0201 +arc: H00R0000 V02S0401 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0601 H06W0303 +arc: N3_V06N0003 S3_V06N0303 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 S3_V06N0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 N3_V06S0203 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0601 N1_V02S0301 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0601 V01N0001 +arc: N1_V02N0201 W3_H06E0103 +arc: A1 V02S0501 +arc: B1 H02E0301 +arc: C1 H02E0401 +arc: D1 H01E0101 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H01E0001 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: M3 H00R0000 +arc: M4 V00B0100 +arc: M5 H00L0000 +arc: M6 V00B0100 +word: SLICEA.K0.INIT 1111111111111111 +word: SLICEA.K1.INIT 1111111111111110 +word: SLICEB.K0.INIT 1111111111111111 +word: SLICEB.K1.INIT 1111111111111111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R35C9:PLC2 +arc: E1_H02E0501 N3_V06S0303 +arc: H00L0000 V02S0001 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0501 S3_V06N0303 +arc: S1_V02S0701 H01E0101 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 S3_V06N0003 +arc: W1_H02W0101 S3_V06N0103 +arc: W1_H02W0501 W3_H06E0303 +arc: A0 E1_H02W0501 +arc: A1 V02N0501 +arc: A7 H02E0701 +arc: B0 H02E0101 +arc: B1 H02E0301 +arc: B7 V02S0701 +arc: C0 E1_H01W0000 +arc: C1 V02N0401 +arc: CE1 H00L0000 +arc: CE2 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D0 V01S0100 +arc: D1 F0 +arc: D7 V02S0601 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0103 Q1 +arc: N3_V06N0203 Q7 +arc: V01S0100 Q2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0001001101011111 +word: SLICEA.K1.INIT 1111110011111110 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0100010011111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.C1MUX 1 + +.tile R36C10:PLC2 +arc: H00R0000 H02W0601 +arc: N1_V02N0101 H02E0101 +arc: N3_V06N0003 S3_V06N0003 +arc: N3_V06N0103 S3_V06N0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0601 N3_V06S0303 +arc: W1_H02W0701 S1_V02N0701 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: M6 V00T0100 +arc: MUXCLK3 CLK0 +arc: S1_V02S0401 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R36C11:PLC2 +arc: E1_H02E0001 E3_H06W0003 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0100 V02N0301 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0501 H06W0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0501 E1_H02W0501 +arc: V00B0000 S1_V02N0201 +arc: V00B0100 V02N0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0601 V01N0001 +arc: A3 V02N0501 +arc: B3 H00R0000 +arc: C3 N1_V01S0100 +arc: CE2 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D3 V02N0201 +arc: F2 F5B_SLICE +arc: H00R0000 Q4 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: MUXCLK2 CLK0 +arc: W1_H02W0201 F2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1110110010100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R36C12:PLC2 +arc: E1_H02E0701 N1_V01S0100 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 H06W0303 +arc: V00B0000 V02S0001 +arc: CE0 H02W0101 +arc: CE1 H02W0101 +arc: CE2 H02W0101 +arc: CE3 H02W0101 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0101 Q0 +arc: E3_H06E0003 Q0 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: H01W0000 Q6 +arc: M0 H02E0601 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0203 Q4 +arc: V00T0000 Q2 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R36C13:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E3_H06W0203 +arc: N3_V06N0003 E3_H06W0003 +arc: S3_V06S0003 N1_V01S0000 +arc: V00B0000 V02N0001 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 E1_H02W0701 +arc: A1 S1_V02N0501 +arc: A2 V02S0701 +arc: A5 H02W0501 +arc: A6 H02E0701 +arc: A7 E1_H02W0501 +arc: B3 H01W0100 +arc: B5 H00R0000 +arc: B6 S1_V02N0701 +arc: B7 N1_V01S0000 +arc: C2 F6 +arc: C4 V00T0100 +arc: C5 V02S0001 +arc: C7 F6 +arc: CE0 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D1 S1_V02N0001 +arc: D2 V02S0201 +arc: D3 S1_V02N0201 +arc: D4 S1_V02N0401 +arc: D5 H02W0001 +arc: D6 V02S0601 +arc: D7 H00R0100 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 F2 +arc: E1_H02E0501 F7 +arc: E3_H06E0103 F2 +arc: E3_H06E0203 F7 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F3 +arc: H00R0000 Q4 +arc: H01W0100 F2 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 F2 +arc: N3_V06N0103 F2 +arc: N3_V06N0203 F7 +arc: N3_V06N0303 F5 +arc: S3_V06S0103 F2 +arc: S3_V06S0303 F5 +arc: V00T0100 Q1 +arc: W3_H06W0103 F2 +arc: W3_H06W0303 F5 +word: SLICED.K0.INIT 0100010000000000 +word: SLICED.K1.INIT 0000010101000101 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 0000010000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1010101000000000 +word: SLICEB.K0.INIT 1010000011110000 +word: SLICEB.K1.INIT 0011001111111111 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R36C14:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 S1_V02N0301 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0501 N1_V02S0501 +arc: W3_H06W0203 V06N0203 +arc: W3_H06W0303 E3_H06W0303 +arc: A1 N1_V02S0501 +arc: A4 N1_V01S0100 +arc: A7 H02E0501 +arc: B0 S1_V02N0101 +arc: B1 V02S0301 +arc: B3 Q3 +arc: B4 H02W0101 +arc: B5 V02S0501 +arc: B7 F1 +arc: C0 H02W0401 +arc: C1 H00L0000 +arc: C2 V02S0401 +arc: C4 V02N0201 +arc: C5 V02N0201 +arc: C7 V02S0001 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D0 H02W0001 +arc: D1 F0 +arc: D2 H02E0201 +arc: D3 F2 +arc: D4 E1_H02W0201 +arc: D5 E1_H02W0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F2 +arc: E3_H06E0003 F0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 F4 +arc: LSR1 E1_H02W0301 +arc: M4 V00T0100 +arc: M6 E1_H02W0401 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: N1_V02N0001 F0 +arc: N1_V02N0301 F3 +arc: N1_V02N0401 F6 +arc: N3_V06N0003 Q3 +arc: N3_V06N0303 F6 +arc: S1_V02S0301 F1 +arc: S1_V02S0601 F6 +arc: S3_V06S0003 Q3 +arc: S3_V06S0303 F6 +arc: V00T0100 Q3 +arc: V01S0000 F0 +arc: W1_H02W0601 F6 +arc: W3_H06W0003 F3 +word: SLICEB.K0.INIT 0000000000001111 +word: SLICEB.K1.INIT 0011001100000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000001000000000 +word: SLICEC.K0.INIT 1100000001000000 +word: SLICEC.K1.INIT 0000111111001111 +word: SLICEA.K0.INIT 0011000000110011 +word: SLICEA.K1.INIT 0000000000010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 + +.tile R36C15:PLC2 +arc: H00L0100 V02N0301 +arc: H00R0000 H02W0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N3_V06N0103 E1_H01W0100 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 V02S0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 N3_V06S0203 +arc: W3_H06W0103 E3_H06W0103 +arc: A0 H02W0501 +arc: A1 V02S0501 +arc: A3 H00L0100 +arc: A4 F5 +arc: A5 W1_H02E0501 +arc: B0 F1 +arc: B2 V02N0301 +arc: B3 H00R0000 +arc: B4 H02E0301 +arc: C0 S1_V02N0601 +arc: C1 N1_V01N0001 +arc: C2 H02W0601 +arc: C3 V02S0601 +arc: C5 S1_V02N0201 +arc: C6 E1_H01E0101 +arc: C7 V00T0100 +arc: CE1 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 V02N0001 +arc: D1 V01S0100 +arc: D2 S1_V02N0001 +arc: D3 S1_V02N0001 +arc: D5 H02E0201 +arc: D6 V00B0000 +arc: D7 V02N0601 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 Q2 +arc: E1_H02E0501 F5 +arc: E3_H06E0203 F7 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: H01W0000 F7 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 F5 +arc: N1_V02N0601 F6 +arc: N1_V02N0701 F5 +arc: N3_V06N0203 F7 +arc: N3_V06N0303 F5 +arc: S1_V02S0501 F5 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 F5 +arc: V00T0100 Q3 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F5 +arc: W3_H06W0203 F7 +arc: W3_H06W0303 F6 +word: SLICED.K0.INIT 1111111111110000 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 0111011101110111 +word: SLICEC.K1.INIT 1111111101011111 +word: SLICEB.K0.INIT 1111110000000000 +word: SLICEB.K1.INIT 0001000000000000 +word: SLICEA.K0.INIT 0001001100000000 +word: SLICEA.K1.INIT 0000000000001010 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R36C16:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S3_V06N0003 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 S3_V06N0003 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0103 H06E0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 V02S0001 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N3_V06S0303 +arc: A4 F5 +arc: A7 V02N0101 +arc: B1 H01W0100 +arc: B3 N1_V02S0301 +arc: B4 E1_H02W0101 +arc: C1 V02N0401 +arc: C3 N1_V01S0100 +arc: C4 V02S0201 +arc: C5 S1_V02N0201 +arc: C7 H02W0401 +arc: CE2 W1_H02E0101 +arc: CLK0 G_HPBX0100 +arc: D0 V02N0201 +arc: D1 H00R0000 +arc: D3 N1_V02S0201 +arc: D4 V00B0000 +arc: D5 H02E0201 +arc: D7 V02S0401 +arc: E1_H02E0201 Q0 +arc: E1_H02E0701 F5 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 F5 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: M0 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 F5 +arc: N3_V06N0303 F5 +arc: S1_V02S0301 Q3 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: S3_V06S0003 Q0 +arc: V01S0100 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1100000011001111 +word: SLICEC.K0.INIT 0011001100000101 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000111110101111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 + +.tile R36C17:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 N1_V02S0201 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0301 H06E0003 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0601 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: A1 E1_H01E0001 +arc: A3 E1_H02W0501 +arc: A5 V00B0000 +arc: B1 H02E0101 +arc: B4 H02W0301 +arc: B5 N1_V02S0501 +arc: C2 V02N0401 +arc: C4 V00T0000 +arc: C5 S1_V02N0201 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 H02W0201 +arc: D1 H02W0001 +arc: D2 H02E0001 +arc: D3 H02E0001 +arc: D4 S1_V02N0401 +arc: D5 H02E0201 +arc: E1_H01E0001 Q0 +arc: E3_H06E0003 Q0 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M0 V00T0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F3 +arc: N1_V02N0201 F2 +arc: N3_V06N0003 Q0 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 F5 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 Q0 +arc: S3_V06S0003 Q0 +arc: S3_V06S0203 Q4 +arc: V00B0000 Q4 +arc: V01S0100 Q4 +arc: W3_H06W0003 Q0 +arc: W3_H06W0303 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1010101000110011 +word: SLICEC.K0.INIT 0000110011111100 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEB.K0.INIT 0000111111110000 +word: SLICEB.K1.INIT 0101010110101010 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R36C18:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 W1_H02E0701 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06E0303 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0203 H06E0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 E1_H02W0601 +arc: S3_V06S0003 N1_V02S0301 +arc: V00T0000 H02E0201 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0701 V06S0203 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0301 W3_H06E0003 +arc: A1 V02N0701 +arc: A7 S1_V02N0101 +arc: B0 F1 +arc: B3 V02N0101 +arc: B5 F1 +arc: B7 E1_H02W0301 +arc: C0 E1_H01W0000 +arc: C1 E1_H02W0401 +arc: C2 V02N0401 +arc: C5 V00T0000 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 H02W0001 +arc: D1 V02N0201 +arc: D2 W1_H02E0001 +arc: D3 W1_H02E0001 +arc: D5 E1_H01W0100 +arc: D7 N1_V02S0601 +arc: E1_H01E0101 F2 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q7 +arc: H01W0100 F3 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F5 +arc: V01S0000 F0 +word: SLICEA.K0.INIT 1100111111000000 +word: SLICEA.K1.INIT 0000010111110101 +word: SLICEB.K0.INIT 0000111111110000 +word: SLICEB.K1.INIT 0011001111001100 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111000011001100 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1101110110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.C1MUX 1 + +.tile R36C19:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0701 V06S0203 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0003 N3_V06S0303 +arc: V00T0100 S1_V02N0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 E1_H01W0100 +arc: E1_H01E0101 W3_H06E0203 +arc: E1_H02E0401 W3_H06E0203 +arc: N1_V02N0701 W3_H06E0203 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: S3_V06S0103 W3_H06E0103 +arc: E3_H06E0303 W3_H06E0203 +arc: A1 V02N0701 +arc: A3 V00B0000 +arc: A4 V00T0100 +arc: A5 E1_H02W0701 +arc: A6 V02S0301 +arc: B1 V00T0000 +arc: B4 V01S0000 +arc: B5 H00L0000 +arc: B7 V00B0000 +arc: C1 E1_H02W0601 +arc: C2 S1_V02N0601 +arc: C4 V02S0201 +arc: C5 F4 +arc: C6 V02N0201 +arc: C7 V00T0000 +arc: CE1 H00R0100 +arc: CE2 H02W0101 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D1 N1_V02S0001 +arc: D2 V02N0201 +arc: D3 V01S0100 +arc: D4 H02E0001 +arc: D5 H02E0201 +arc: D6 S1_V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 F3 +arc: E3_H06E0003 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: H01W0100 F3 +arc: M0 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 F3 +arc: N1_V02N0501 F7 +arc: N3_V06N0003 F0 +arc: N3_V06N0303 Q5 +arc: V00B0000 Q6 +arc: V00T0000 Q2 +arc: V01S0100 Q2 +arc: W1_H02W0301 F3 +arc: W3_H06W0003 F3 +arc: W3_H06W0203 F7 +word: SLICEC.K0.INIT 0110001011111011 +word: SLICEC.K1.INIT 0100010001000111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0100011100000000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 0000000010101010 +word: SLICED.K0.INIT 1010111100000000 +word: SLICED.K1.INIT 1111110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.A1MUX 1 + +.tile R36C20:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 E1_H01W0100 +arc: E1_H02E0201 N3_V06S0103 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E3_H06E0203 N3_V06S0203 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0303 H01E0101 +arc: S1_V02S0101 N3_V06S0103 +arc: S3_V06S0003 N3_V06S0303 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 H01E0001 +arc: A1 V02N0701 +arc: A2 H01E0001 +arc: A3 H02E0701 +arc: A4 E1_H02W0501 +arc: B0 F1 +arc: B2 F3 +arc: B4 H02W0301 +arc: C1 V02N0601 +arc: C3 N1_V01S0100 +arc: C4 V00B0100 +arc: CE2 H02E0101 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0100 +arc: D0 H02W0001 +arc: D1 H02W0201 +arc: D2 V00T0100 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: H01W0000 F3 +arc: H01W0100 Q4 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0203 Q4 +arc: V00T0100 F1 +arc: W1_H02W0001 F0 +arc: W3_H06W0303 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1110101011000000 +word: SLICEC.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1101110110001000 +word: SLICEB.K1.INIT 0000111101010101 +word: SLICEA.K0.INIT 1101110110001000 +word: SLICEA.K1.INIT 0000010110101111 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R36C21:PLC2 +arc: E1_H02E0001 V06S0003 +arc: H00L0000 V02S0201 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 V02N0501 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 H02E0201 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02E0501 +arc: V00T0000 H02E0201 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 H01E0101 +arc: E1_H02E0501 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: N3_V06N0203 W3_H06E0203 +arc: N3_V06N0303 W3_H06E0303 +arc: S1_V02S0501 W3_H06E0303 +arc: S3_V06S0303 W3_H06E0303 +arc: W1_H02W0501 W3_H06E0303 +arc: A0 H00L0000 +arc: A1 V02S0701 +arc: A4 N1_V02S0301 +arc: A6 N1_V02S0301 +arc: B0 H02E0301 +arc: B1 H02W0101 +arc: B4 N1_V01S0000 +arc: B6 V02N0501 +arc: C0 N1_V02S0601 +arc: C1 H02W0401 +arc: C4 E1_H02W0401 +arc: C6 V00B0100 +arc: CE0 H00R0000 +arc: CE1 H02E0101 +arc: CE2 H02E0101 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0100 +arc: D0 V00T0100 +arc: D1 H02E0001 +arc: D4 H00R0100 +arc: D6 E1_H01W0100 +arc: E1_H02E0601 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q6 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q6 +arc: N3_V06N0003 Q0 +arc: V00T0100 F1 +arc: W1_H02W0201 Q0 +arc: W1_H02W0401 Q4 +arc: W3_H06W0103 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111100010001000 +word: SLICEC.K1.INIT 1111111111111111 +word: SLICED.K0.INIT 1110110010100000 +word: SLICED.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0101000001010011 +word: SLICEA.K1.INIT 0011100011111011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R36C22:PLC2 +arc: E1_H02E0601 E1_H01W0000 +arc: H00L0000 H02E0001 +arc: H00R0000 W1_H02E0401 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 H02E0601 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0203 S3_V06N0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0501 H02E0501 +arc: V00B0100 V02N0301 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 E1_H02W0401 +arc: N1_V02N0501 W3_H06E0303 +arc: N1_V02N0701 W3_H06E0203 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0601 W3_H06E0303 +arc: CE2 H00R0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: H01W0100 Q6 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: V00B0000 Q4 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R36C23:PLC2 +arc: H00L0000 W1_H02E0001 +arc: H00R0100 V02N0501 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 H06E0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0000 V02S0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 V02S0501 +arc: N1_V02N0301 W3_H06E0003 +arc: CE0 H00L0000 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0101 Q0 +arc: H01W0000 Q4 +arc: M0 H02E0601 +arc: M4 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: N3_V06N0003 Q0 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R36C24:PLC2 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 + +.tile R36C25:PLC2 +arc: N1_V02N0201 N3_V06S0103 +arc: S1_V02S0201 N3_V06S0103 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0501 W3_H06E0303 + +.tile R36C2:PLC2 +arc: E1_H02E0201 E3_H06W0103 +arc: E1_H02E0601 V02S0601 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: S3_V06S0103 E3_H06W0103 +arc: V00B0000 V02S0201 +arc: V00B0100 V02N0301 +arc: CE1 S1_V02N0201 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0001 Q2 +arc: E1_H02E0401 Q6 +arc: M2 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R36C3:PLC2 +arc: H00L0100 S1_V02N0301 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 S3_V06N0003 +arc: N3_V06N0303 H06W0303 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02W0501 +arc: A1 V02S0501 +arc: A7 H00R0000 +arc: B1 H01W0100 +arc: B7 V02S0701 +arc: C1 V02S0601 +arc: C7 V02N0201 +arc: CE1 H00L0100 +arc: CE2 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D1 H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0501 F7 +arc: E3_H06E0103 Q2 +arc: F0 F5A_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q4 +arc: M0 V00B0100 +arc: M2 H02E0601 +arc: M4 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: V01S0000 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000011101110111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1100001101000001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R36C4:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 E1_H02W0001 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0201 W1_H02E0201 +arc: N1_V02N0501 H01E0101 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0303 S3_V06N0203 +arc: S1_V02S0301 H06W0003 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 H02W0101 +arc: A1 E1_H02W0701 +arc: A3 E1_H02W0701 +arc: A5 V02S0101 +arc: A7 E1_H02W0501 +arc: B1 H02W0101 +arc: B3 V02N0101 +arc: B4 E1_H02W0101 +arc: B5 H00R0000 +arc: C1 V02N0601 +arc: C3 H00L0000 +arc: C4 W1_H02E0401 +arc: C5 W1_H02E0401 +arc: C7 V00T0000 +arc: CLK0 G_HPBX0100 +arc: D1 S1_V02N0201 +arc: D3 V00T0100 +arc: D5 H02E0001 +arc: D7 H00R0100 +arc: E1_H02E0601 F4 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F1 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F3 +arc: N3_V06N0203 Q7 +arc: W1_H02W0501 F5 +word: SLICEC.K0.INIT 1100000011000000 +word: SLICEC.K1.INIT 1000010000100001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0001010100111111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0101010111110101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 + +.tile R36C5:PLC2 +arc: E3_H06E0103 V06N0103 +arc: H00L0000 S1_V02N0201 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0101 S3_V06N0103 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 H06W0003 +arc: N3_V06N0303 S3_V06N0203 +arc: S3_V06S0003 N3_V06S0003 +arc: S3_V06S0103 H06W0103 +arc: S3_V06S0203 H06W0203 +arc: V00B0100 V02S0301 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0101 N1_V02S0101 +arc: A0 V02S0701 +arc: A1 H00L0000 +arc: A4 N1_V02S0101 +arc: A5 W1_H02E0501 +arc: A7 S1_V02N0101 +arc: B0 E1_H02W0301 +arc: B1 N1_V02S0101 +arc: B4 V01S0000 +arc: B5 E1_H02W0301 +arc: B7 F1 +arc: C1 V02S0601 +arc: C4 H02E0401 +arc: C5 F4 +arc: C7 H02E0601 +arc: CE1 E1_H02W0101 +arc: CLK0 G_HPBX0100 +arc: D1 H02E0001 +arc: D4 H00R0100 +arc: D5 V02S0401 +arc: D7 F0 +arc: E1_H02E0601 F6 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: M2 V00B0100 +arc: M6 V00T0100 +arc: MUXCLK1 CLK0 +arc: S1_V02S0201 Q2 +arc: V01S0000 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1000100010001000 +word: SLICEA.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0010000010100000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111111111111011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R36C6:PLC2 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V01N0101 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 E1_H02W0501 +arc: N3_V06N0203 S3_V06N0203 +arc: S3_V06S0303 E1_H01W0100 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0501 E1_H02W0401 +arc: W1_H02W0701 S1_V02N0701 +arc: A0 W1_H02E0701 +arc: A4 E1_H01W0000 +arc: A5 V02N0301 +arc: A7 H02E0701 +arc: B0 S1_V02N0101 +arc: B1 W1_H02E0301 +arc: B4 V02N0701 +arc: B5 W1_H02E0101 +arc: C0 H00L0000 +arc: C1 V02S0401 +arc: C4 V02N0201 +arc: C5 H02E0601 +arc: C7 H02W0401 +arc: CE1 S1_V02N0201 +arc: CLK0 G_HPBX0100 +arc: D0 V02N0001 +arc: D1 F0 +arc: D4 V02N0601 +arc: D5 V00B0000 +arc: D7 H00R0100 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: M2 H02W0601 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0701 Q7 +arc: S3_V06S0103 F1 +arc: V00B0000 F4 +arc: V01S0100 Q2 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0101000011111111 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 1111010111111101 +word: SLICEA.K0.INIT 1000001011000011 +word: SLICEA.K1.INIT 1100001100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R36C7:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0100 V02S0301 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0501 H02W0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S3_V06S0203 N1_V02S0401 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 N3_V06S0303 +arc: A2 H00L0100 +arc: A3 E1_H02W0501 +arc: A7 E1_H01W0000 +arc: B2 E1_H02W0101 +arc: B3 V02S0101 +arc: B7 V02S0501 +arc: C2 N1_V01N0001 +arc: C3 H02W0601 +arc: C7 E1_H01E0101 +arc: CE0 H00R0100 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D2 V02S0001 +arc: D3 V02N0201 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 F2 +arc: E1_H02E0601 F6 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q4 +arc: H01W0100 F3 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M0 V00B0100 +arc: M4 H02E0401 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F3 +arc: S3_V06S0003 F3 +arc: V01S0100 Q0 +arc: W3_H06W0003 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0001010100111111 +word: SLICEB.K1.INIT 0000100000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1000111111111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R36C8:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V06N0203 +arc: H00R0000 V02S0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0601 N3_V06S0303 +arc: S3_V06S0003 N3_V06S0003 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02S0401 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0401 S3_V06N0203 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0003 E3_H06W0003 +arc: A3 V02S0501 +arc: A4 V02N0101 +arc: A5 V02S0101 +arc: A6 N1_V01N0101 +arc: A7 V02N0101 +arc: B3 V02S0301 +arc: B4 V02N0501 +arc: B5 V02N0701 +arc: B7 V02S0501 +arc: C3 E1_H02W0601 +arc: C4 V02S0001 +arc: C5 S1_V02N0001 +arc: C6 E1_H02W0601 +arc: C7 F6 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D3 H02E0001 +arc: D4 E1_H01W0100 +arc: D5 V00B0000 +arc: D7 H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 F6 +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F2 +arc: LSR1 E1_H02W0301 +arc: M0 V00T0000 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F6 +arc: N1_V02N0001 Q0 +arc: N1_V02N0501 F7 +arc: N1_V02N0601 F6 +arc: S3_V06S0103 F2 +arc: S3_V06S0203 F7 +arc: V00B0000 F4 +arc: W1_H02W0001 F2 +arc: W1_H02W0501 F7 +arc: W1_H02W0701 F5 +arc: W3_H06W0103 F2 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0101000001010000 +word: SLICED.K1.INIT 0010000000000000 +word: SLICEC.K0.INIT 0001001101011111 +word: SLICEC.K1.INIT 0111011100000111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R36C9:PLC2 +arc: E1_H02E0101 V06S0103 +arc: H00L0000 E1_H02W0201 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 E3_H06W0103 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N3_V06N0103 S1_V02N0101 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0601 W1_H02E0601 +arc: S1_V02S0701 W1_H02E0701 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0501 H01E0101 +arc: W1_H02W0101 W3_H06E0103 +arc: A3 V02N0501 +arc: B3 H00L0000 +arc: C3 V02N0401 +arc: CE0 H02E0101 +arc: CLK0 G_HPBX0100 +arc: D3 H02E0201 +arc: F3 F3_SLICE +arc: H01W0100 Q0 +arc: LSR0 H02W0301 +arc: M0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: S1_V02S0101 F3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000010011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R38C10:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 V01N0001 +arc: H00L0000 V02S0001 +arc: H00R0000 V02N0401 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 H02W0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0401 V01N0001 +arc: A1 V02S0701 +arc: A3 V01N0101 +arc: A6 H00R0000 +arc: A7 V02N0101 +arc: B1 V00B0000 +arc: B2 V02N0301 +arc: B3 E1_H01W0100 +arc: B6 V02S0501 +arc: B7 V02N0501 +arc: C1 E1_H01W0000 +arc: C2 H02E0401 +arc: C3 S1_V02N0401 +arc: C6 H02W0601 +arc: C7 F6 +arc: CE2 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D1 H02W0201 +arc: D3 F2 +arc: D6 N1_V02S0401 +arc: D7 F2 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F2 +arc: E1_H02E0201 F2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 F0 +arc: M0 V00T0000 +arc: M4 H02W0401 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0701 F7 +arc: N3_V06N0103 F2 +arc: S3_V06S0103 F2 +arc: V00B0000 Q4 +arc: V00T0000 F2 +arc: V01S0000 F2 +arc: W1_H02W0001 F2 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 F2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1110110010100000 +word: SLICED.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 0111000001110111 +word: SLICEB.K0.INIT 0000001100000011 +word: SLICEB.K1.INIT 1011001110100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 + +.tile R38C11:PLC2 +arc: E1_H02E0301 V02S0301 +arc: H00R0100 V02S0701 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E3_H06W0003 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 N1_V02S0501 +arc: S1_V02S0601 N1_V02S0301 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0003 N3_V06S0303 +arc: V00B0100 V02N0301 +arc: V00T0100 V02S0501 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V06S0203 +arc: A4 F5 +arc: A7 E1_H01W0000 +arc: B4 V02N0701 +arc: B7 V00T0000 +arc: C4 H02E0601 +arc: C5 H02W0601 +arc: C7 V02S0201 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D4 V01N0001 +arc: D5 H02W0001 +arc: D7 V02S0601 +arc: E1_H02E0401 F4 +arc: E1_H02E0701 F5 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q0 +arc: H01W0100 F7 +arc: LSR0 H02E0301 +arc: M0 V00T0100 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N3_V06N0303 F5 +arc: V00T0000 Q2 +arc: V01S0000 F5 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R38C12:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: H00L0100 H02E0301 +arc: S1_V02S0701 H02E0701 +arc: S3_V06S0103 N3_V06S0103 +arc: S3_V06S0203 N3_V06S0203 +arc: V00B0100 V02N0301 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0601 N3_V06S0303 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: H01W0000 Q6 +arc: M6 V00B0100 +arc: MUXCLK3 CLK0 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R38C13:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06N0103 +arc: E1_H02E0301 V02S0301 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 S1_V02N0601 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 H06W0203 +arc: N3_V06N0303 S1_V02N0601 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 H02W0601 +arc: V01S0000 S3_V06N0103 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0701 N3_V06S0203 +arc: A7 V02N0301 +arc: B7 S1_V02N0701 +arc: C7 E1_H02W0401 +arc: D7 V02N0401 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: M0 H02W0601 +arc: M1 E1_H02W0001 +arc: M2 H02W0601 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 E1_H02W0001 +arc: M6 V00B0000 +arc: N1_V02N0101 F3 +arc: N1_V02N0301 F3 +arc: N3_V06N0003 F3 +arc: W3_H06W0003 F3 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000010 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111111111111111 +word: SLICEC.K1.INIT 1111111111111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R38C14:PLC2 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E3_H06W0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 H02E0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0601 N1_V02S0601 +arc: W3_H06W0003 E3_H06W0303 +arc: W3_H06W0103 E3_H06W0003 +arc: A1 S1_V02N0701 +arc: A5 N1_V02S0301 +arc: A7 V00T0100 +arc: B1 N1_V02S0101 +arc: B2 F3 +arc: B4 H02W0101 +arc: B7 V01S0000 +arc: C1 V02N0601 +arc: C3 V02N0401 +arc: C5 F4 +arc: C7 V02S0201 +arc: CE2 S1_V02N0601 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 N1_V02S0001 +arc: D4 N1_V02S0401 +arc: D5 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 Q6 +arc: E1_H02E0601 Q6 +arc: E3_H06E0303 Q6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F0 +arc: H01W0000 F5 +arc: H01W0100 Q5 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M0 V00B0000 +arc: M6 N1_V01N0101 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 Q6 +arc: N1_V02N0601 Q6 +arc: N3_V06N0103 F2 +arc: N3_V06N0203 F4 +arc: N3_V06N0303 Q6 +arc: S1_V02S0701 F5 +arc: S3_V06S0203 F4 +arc: S3_V06S0303 Q6 +arc: V00B0000 F6 +arc: V01S0100 F4 +arc: W3_H06W0303 Q6 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICEC.K1.INIT 0000101000000000 +word: SLICEB.K0.INIT 1100110011111111 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 1111111111111111 +word: SLICEA.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 1111111111111111 +word: SLICED.K1.INIT 1010111010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R38C15:PLC2 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 N1_V02S0501 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0201 N3_V06S0103 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 V02N0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 E1_H02W0101 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0201 W3_H06E0103 +arc: N1_V02N0001 W3_H06E0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A0 H02W0501 +arc: A4 V02S0301 +arc: A5 V00T0000 +arc: B0 S1_V02N0101 +arc: B1 S1_V02N0301 +arc: B4 S1_V02N0701 +arc: B5 H00R0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C4 H02W0601 +arc: C5 V02N0201 +arc: CE2 H00R0100 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D0 V02N0001 +arc: D1 V02N0001 +arc: D4 H02W0201 +arc: D5 V02N0401 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00R0000 Q4 +arc: H01W0000 F0 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: M6 N1_V01N0101 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q4 +arc: N1_V02N0201 F0 +arc: N1_V02N0601 Q6 +arc: V00B0000 Q6 +arc: V00T0000 Q2 +arc: V01S0100 Q2 +arc: W3_H06W0103 Q2 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0001010101010101 +word: SLICEA.K1.INIT 0011111111111111 +word: SLICEC.K0.INIT 0000000100000000 +word: SLICEC.K1.INIT 0001010100111111 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R38C16:PLC2 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0601 N3_V06S0303 +arc: H00R0100 H02E0501 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0301 E3_H06W0003 +arc: N1_V02N0401 N3_V06S0203 +arc: S1_V02S0201 N1_V02S0701 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0601 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 N1_V02S0601 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H02W0501 +arc: A4 N1_V01S0100 +arc: A5 N1_V01S0100 +arc: B0 H02E0301 +arc: B3 H01W0100 +arc: B4 N1_V01S0000 +arc: B5 H02E0301 +arc: C0 N1_V02S0601 +arc: C3 H02E0401 +arc: C5 V02S0001 +arc: CE0 H00R0100 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 H02W0201 +arc: D2 V00B0100 +arc: D3 H02W0001 +arc: D4 N1_V02S0601 +arc: D5 V00B0000 +arc: E1_H01E0101 F0 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q2 +arc: E1_H02E0701 F5 +arc: E3_H06E0203 Q4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q2 +arc: M0 V00T0000 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0601 Q4 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: S1_V02S0001 Q2 +arc: S3_V06S0103 Q2 +arc: V00B0000 F4 +arc: V01S0000 Q2 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 1111111011001100 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1100000011001111 +word: SLICEC.K0.INIT 0001000100000000 +word: SLICEC.K1.INIT 0000000011100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C0MUX 1 + +.tile R38C17:PLC2 +arc: E1_H02E0101 H01E0101 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 H02E0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0501 E1_H02W0501 +arc: A4 S1_V02N0301 +arc: A6 S1_V02N0301 +arc: B4 V02N0501 +arc: C4 V01N0101 +arc: C5 V01N0101 +arc: D4 V02N0601 +arc: D5 V02N0601 +arc: D6 V02N0401 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F3 +arc: M0 V00B0100 +arc: M1 H00L0000 +arc: M2 V00B0100 +arc: M3 H00L0100 +arc: M4 V00B0100 +arc: M5 H00L0000 +arc: M6 V00B0100 +arc: N3_V06N0003 F3 +arc: S3_V06S0003 F3 +arc: W1_H02W0101 F3 +arc: W3_H06W0003 F3 +word: SLICEC.K0.INIT 0111111111111111 +word: SLICEC.K1.INIT 0000111111111111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0101010111111111 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R38C18:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 V02N0501 +arc: E3_H06E0203 V06N0203 +arc: H00L0000 S1_V02N0201 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0000 V02S0001 +arc: A5 S1_V02N0101 +arc: A7 S1_V02N0101 +arc: B1 E1_H02W0101 +arc: B3 N1_V02S0301 +arc: C0 N1_V02S0601 +arc: C3 H00L0000 +arc: C5 V02S0201 +arc: C7 S1_V02N0001 +arc: CLK0 G_HPBX0100 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D3 N1_V02S0001 +arc: D5 N1_V02S0401 +arc: D7 V00B0000 +arc: E1_H01E0001 Q3 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0003 F0 +arc: N3_V06N0103 F1 +arc: V01S0000 Q5 +arc: V01S0100 Q7 +word: SLICEA.K0.INIT 0000111111110000 +word: SLICEA.K1.INIT 0011001111001100 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111010110100000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1111110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 + +.tile R38C19:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0601 H01E0001 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H06E0203 +arc: N3_V06N0003 S1_V02N0001 +arc: S1_V02S0401 N3_V06S0203 +arc: S3_V06S0303 N3_V06S0303 +arc: V00T0100 W1_H02E0101 +arc: A1 V02N0501 +arc: A2 H02E0501 +arc: B0 V02N0101 +arc: B2 V01N0001 +arc: B5 H02W0301 +arc: C0 V02S0401 +arc: C2 N1_V01S0100 +arc: C5 V02S0201 +arc: CE0 N1_V02S0201 +arc: CE1 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 V02N0201 +arc: D1 V01S0100 +arc: D2 H02E0201 +arc: D5 H02E0201 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q2 +arc: M2 V00T0100 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0001 Q2 +arc: N3_V06N0103 F1 +arc: N3_V06N0303 Q6 +arc: S3_V06S0103 F1 +arc: V01S0100 Q0 +arc: W1_H02W0501 F5 +arc: W3_H06W0103 Q2 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1101110011001100 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1111001111110000 +word: SLICEA.K1.INIT 1010101000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000110000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 + +.tile R38C20:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 H02W0501 +arc: S1_V02S0101 N1_V02S0101 +arc: V00B0000 H02E0401 +arc: V00B0100 N1_V02S0101 +arc: V00T0100 H02E0301 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 N3_V06S0003 +arc: N1_V02N0501 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: A4 V02S0301 +arc: B4 H02E0101 +arc: C4 V02N0201 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D4 H00L0100 +arc: F4 F5C_SLICE +arc: M0 H02E0601 +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0401 Q6 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q6 +arc: W1_H02W0601 Q6 +arc: W3_H06W0003 Q0 +arc: W3_H06W0303 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1110101011000000 +word: SLICEC.K1.INIT 1111111111111111 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R38C21:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0401 V01N0001 +arc: H00R0000 S1_V02N0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0401 H06E0203 +arc: S1_V02S0601 V01N0001 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0501 N1_V02S0501 +arc: A0 V01N0101 +arc: A6 H00R0000 +arc: B0 V02S0301 +arc: B6 W1_H02E0101 +arc: C0 V02S0601 +arc: C6 S1_V02N0001 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 S1_V02N0201 +arc: D6 V02N0401 +arc: F0 F5A_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0601 Q6 +arc: N3_V06N0003 Q0 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q6 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +arc: W3_H06W0303 Q6 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1110110010100000 +word: SLICED.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 1110110010100000 +word: SLICEA.K1.INIT 1111111111111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R38C22:PLC2 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0000 V02N0601 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0101 H06E0103 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 V02S0401 +arc: N1_V02N0401 W3_H06E0203 +arc: A0 S1_V02N0701 +arc: B0 E1_H01W0100 +arc: C0 V02S0601 +arc: CE0 H00R0100 +arc: CE1 H00R0000 +arc: CE2 H00R0100 +arc: CE3 W1_H02E0101 +arc: CLK0 G_HPBX0100 +arc: D0 H02E0001 +arc: E1_H02E0401 Q6 +arc: F0 F5A_SLICE +arc: M0 V00B0000 +arc: M2 H02W0601 +arc: M4 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: W1_H02W0001 Q0 +arc: W3_H06W0003 Q0 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1110101011000000 +word: SLICEA.K1.INIT 1111111111111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R38C23:PLC2 +arc: E1_H02E0101 V02N0101 +arc: H00L0000 V02N0001 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0601 H06E0303 +arc: V00B0100 H02E0701 +arc: CE0 H00R0100 +arc: CE1 V02N0201 +arc: CE2 H00L0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: H01W0100 Q4 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0401 Q6 +arc: N3_V06N0003 Q0 +arc: N3_V06N0303 Q6 +arc: V00B0000 Q4 +arc: V00T0000 Q2 +arc: W1_H02W0601 Q4 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R38C24:PLC2 +arc: V00T0000 H02W0201 +arc: CE2 H02E0101 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0401 Q6 +arc: N3_V06N0303 Q6 +arc: V00B0000 Q4 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R38C25:PLC2 +arc: W1_H02W0201 N1_V02S0201 + +.tile R38C2:PLC2 +arc: E1_H02E0401 V06S0203 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0401 N3_V06S0203 +arc: V01S0100 S3_V06N0303 + +.tile R38C3:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0401 H02E0401 +arc: V00B0000 V02S0201 +arc: V01S0000 N3_V06S0103 +arc: A3 E1_H01E0001 +arc: A7 V02N0301 +arc: B1 H02W0301 +arc: B3 H02W0301 +arc: B7 V01S0000 +arc: C3 V02N0601 +arc: C7 V02N0201 +arc: CE2 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D1 V02S0001 +arc: D3 H02W0201 +arc: D7 H02W0201 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 F1 +arc: E1_H02E0501 F7 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H01W0000 F1 +arc: H01W0100 F1 +arc: M4 V00B0000 +arc: MUXCLK2 CLK0 +arc: N1_V02N0101 F3 +arc: N1_V02N0301 F1 +arc: S1_V02S0301 F1 +arc: S3_V06S0103 F1 +arc: V01S0100 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1100110000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R38C4:PLC2 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 S1_V02N0201 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0601 V01N0001 +arc: S1_V02S0701 H01E0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0301 N1_V02S0301 +arc: A2 V02N0701 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 V02N0301 +arc: B2 H01W0100 +arc: B3 Q3 +arc: CE1 V02S0201 +arc: CE2 E1_H02W0101 +arc: CE3 E1_H02W0101 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0101 Q2 +arc: E1_H02E0601 Q4 +arc: E1_H02E0701 Q7 +arc: E3_H06E0003 Q3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0100 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q7 +arc: N1_V02N0301 Q3 +arc: N1_V02N0401 Q4 +arc: N1_V02N0701 Q7 +arc: N3_V06N0103 Q2 +arc: S1_V02S0401 Q6 +arc: V00B0000 Q4 +arc: V01S0000 Q6 +arc: V01S0100 Q5 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R38C5:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 E1_H02W0701 +arc: S3_V06S0303 N3_V06S0203 +arc: A4 V00B0000 +arc: A5 Q5 +arc: A6 H00R0000 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H01W0100 +arc: B3 Q3 +arc: CE0 H02W0101 +arc: CE1 H02W0101 +arc: CE2 H02W0101 +arc: CE3 H02W0101 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0001 Q2 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0100 Q2 +arc: LSR0 W1_H02E0301 +arc: LSR1 W1_H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q4 +arc: N1_V02N0201 Q2 +arc: S1_V02S0001 Q0 +arc: S1_V02S0601 Q6 +arc: S3_V06S0103 Q1 +arc: S3_V06S0203 Q7 +arc: V00B0000 Q4 +arc: V00T0000 Q0 +arc: V01S0000 Q5 +arc: V01S0100 Q4 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICED.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R38C6:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: H00L0000 H02E0201 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0601 E1_H01W0000 +arc: S3_V06S0103 E1_H01W0100 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 E1_H01W0100 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0701 V06S0203 +arc: A5 W1_H02E0701 +arc: A6 V02N0101 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B5 H00L0000 +arc: B6 H02E0301 +arc: C5 W1_H02E0601 +arc: C6 V02N0201 +arc: C7 V02N0201 +arc: CE0 S1_V02N0201 +arc: CLK0 G_HPBX0100 +arc: D5 V01N0001 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: H01W0100 F7 +arc: LSR0 V00B0100 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0101 Q1 +arc: S1_V02S0001 Q0 +arc: V00T0000 Q0 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1100001101000001 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1111000000000000 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R38C7:PLC2 +arc: H00R0100 V02S0701 +arc: N1_V02N0301 H06E0003 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0203 S1_V02N0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 H02E0101 +arc: V00B0000 H02W0601 +arc: V00B0100 V02S0301 +arc: V00T0000 H02W0201 +arc: A3 F5 +arc: A4 F5 +arc: B4 W1_H02E0301 +arc: C4 S1_V02N0001 +arc: C5 H02W0401 +arc: CE0 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D3 S1_V02N0201 +arc: D4 V02N0401 +arc: D5 V00B0000 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 F3 +arc: H01W0100 F3 +arc: LSR0 V00B0100 +arc: M0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F3 +arc: N1_V02N0101 F3 +arc: N1_V02N0401 F4 +arc: N3_V06N0303 F5 +arc: S1_V02S0201 Q0 +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: S3_V06S0003 F3 +arc: S3_V06S0303 F5 +arc: W1_H02W0101 F3 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1010101000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R38C8:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0601 V02S0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0601 E3_H06W0303 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0601 N1_V01S0000 +arc: V00B0000 V02S0001 +arc: V00B0100 V02N0101 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 N1_V02S0601 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0101 Q4 +arc: LSR1 V00B0000 +arc: M4 V00B0100 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R38C9:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0100 H02E0301 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 E1_H02W0501 +arc: S3_V06S0203 N3_V06S0103 +arc: S3_V06S0303 N3_V06S0203 +arc: V00T0000 H02E0001 +arc: V00T0100 N1_V02S0701 +arc: S3_V06S0103 W3_H06E0103 +arc: A0 V02N0701 +arc: A2 V02S0701 +arc: A4 V00B0000 +arc: A5 V02N0301 +arc: B0 E1_H01W0100 +arc: B1 V01N0001 +arc: B2 F3 +arc: B4 H01E0101 +arc: B5 E1_H02W0301 +arc: C0 H02W0401 +arc: C1 H00L0000 +arc: C3 V02N0601 +arc: C4 H02E0601 +arc: C5 F4 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D0 H02W0201 +arc: D1 V02S0201 +arc: D2 V02N0001 +arc: D3 V00T0100 +arc: D4 H02E0201 +arc: D5 N1_V02S0601 +arc: E3_H06E0003 F3 +arc: E3_H06E0103 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F0 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0101 Q1 +arc: V00B0000 Q6 +arc: W3_H06W0303 Q5 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0001010100111111 +word: SLICEC.K1.INIT 1111111101011101 +word: SLICEB.K0.INIT 0001000100000000 +word: SLICEB.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 0001001100110011 +word: SLICEA.K1.INIT 1111111100111111 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 + +.tile R39C10:PLC2 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 V02N0601 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0701 E1_H02W0701 +arc: S1_V02S0201 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V06S0303 +arc: W3_H06W0103 E1_H01W0100 +arc: A4 F5 +arc: B0 F1 +arc: B1 V02N0101 +arc: B2 E1_H01W0100 +arc: B4 V02S0701 +arc: B5 V02N0501 +arc: B6 V02N0501 +arc: C2 H02E0401 +arc: C3 H00L0000 +arc: C4 H02E0601 +arc: C5 V02S0001 +arc: C7 F6 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D0 H02E0201 +arc: D1 S1_V02N0001 +arc: D3 V02S0201 +arc: D4 F0 +arc: D6 V00B0000 +arc: D7 F2 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 F3 +arc: E1_H02E0401 F6 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 F4 +arc: H01W0000 F3 +arc: H01W0100 F2 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F3 +arc: N1_V02N0201 Q0 +arc: N1_V02N0501 F7 +arc: N3_V06N0003 F3 +arc: S1_V02S0301 F1 +arc: S1_V02S0501 F7 +arc: S1_V02S0701 F5 +arc: S3_V06S0203 F7 +arc: V01S0000 F1 +arc: V01S0100 F6 +arc: W1_H02W0001 F2 +arc: W1_H02W0101 F3 +arc: W1_H02W0201 F2 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F7 +arc: W3_H06W0303 F5 +word: SLICEA.K0.INIT 1100110000000000 +word: SLICEA.K1.INIT 1100110000000000 +word: SLICEC.K0.INIT 1111111110000000 +word: SLICEC.K1.INIT 1100000011000000 +word: SLICED.K0.INIT 0000000011001100 +word: SLICED.K1.INIT 1111000000000000 +word: SLICEB.K0.INIT 0000110000001100 +word: SLICEB.K1.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 + +.tile R39C11:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: H00L0000 E1_H02W0001 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0103 H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0201 N1_V02S0201 +arc: S1_V02S0401 H01E0001 +arc: V00B0000 V02S0201 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 E1_H02W0201 +arc: V01S0000 N3_V06S0103 +arc: A2 V02S0701 +arc: A5 H02E0701 +arc: A6 H00L0000 +arc: A7 E1_H01W0000 +arc: B2 V02S0101 +arc: B4 V01S0000 +arc: B5 N1_V01S0000 +arc: B6 V00B0100 +arc: B7 H02E0101 +arc: C2 V02N0601 +arc: C5 F4 +arc: C6 E1_H01E0101 +arc: C7 F6 +arc: CE0 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D2 H01E0101 +arc: D4 V00B0000 +arc: D5 V02S0601 +arc: D6 N1_V02S0601 +arc: D7 H02E0201 +arc: E1_H01E0101 Q0 +arc: E1_H02E0501 F5 +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q4 +arc: M0 V00T0000 +arc: M2 H02E0601 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F4 +arc: N3_V06N0203 Q7 +arc: V01S0100 F4 +arc: W1_H02W0201 F2 +arc: W1_H02W0401 F4 +arc: W3_H06W0203 Q4 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0111111111111111 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1100110000000000 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 1000111110001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R39C12:PLC2 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 H02E0301 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 S1_V02N0201 +arc: A2 V01N0101 +arc: A3 E1_H02W0501 +arc: A5 V00B0000 +arc: A6 V02N0101 +arc: B0 E1_H02W0301 +arc: B4 H00R0000 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F4 +arc: H01W0100 F2 +arc: N3_V06N0003 F3 +arc: N3_V06N0303 F6 +arc: W1_H02W0701 F5 +word: SLICEC.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0101010101010000 +word: SLICEB.K1.INIT 0101010101010000 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1111111111110000 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R39C13:PLC2 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0301 N1_V02S0301 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 V02S0601 +arc: E3_H06E0303 V06S0303 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 V02N0201 +arc: V00B0100 N1_V02S0301 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 +arc: A7 W1_H02E0501 +arc: B6 N1_V01S0000 +arc: C7 E1_H01E0101 +arc: CE1 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D6 H01W0000 +arc: D7 V02S0401 +arc: E1_H01E0101 Q7 +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q7 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M2 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: S3_V06S0203 Q7 +arc: W1_H02W0001 Q2 +arc: W3_H06W0303 Q6 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +word: SLICED.K0.INIT 0000000000110011 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET SET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.B1MUX 1 + +.tile R39C14:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 N3_V06S0203 +arc: H00R0100 V02S0701 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0601 E1_H02W0601 +arc: S1_V02S0701 N1_V01S0100 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0301 +arc: W1_H02W0501 S1_V02N0501 +arc: W3_H06W0303 E3_H06W0203 +arc: B0 V02N0301 +arc: B1 S1_V02N0301 +arc: B2 V02N0101 +arc: B7 V02N0501 +arc: C1 V02S0601 +arc: C2 V02N0401 +arc: C5 H02W0601 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0100 +arc: D0 V01S0100 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D5 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F2 +arc: E1_H02E0301 F1 +arc: E1_H02E0701 F7 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0301 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F3 +arc: N3_V06N0003 F3 +arc: N3_V06N0103 F1 +arc: S1_V02S0201 F0 +arc: S3_V06S0003 F3 +arc: V00T0100 Q3 +arc: V01S0000 F5 +arc: V01S0100 F1 +arc: W1_H02W0301 F3 +arc: W3_H06W0003 F3 +arc: W3_H06W0103 F1 +word: SLICEA.K0.INIT 1111111100110011 +word: SLICEA.K1.INIT 0000000000110000 +word: SLICEB.K0.INIT 0000001100000000 +word: SLICEB.K1.INIT 1111111111111111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000111111111111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 + +.tile R39C15:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0303 V06S0303 +arc: H00L0000 V02S0001 +arc: H00L0100 N1_V02S0301 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0701 N3_V06S0203 +arc: V00B0000 H02E0401 +arc: V00T0000 V02S0601 +arc: V00T0100 V02S0701 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0601 V06S0303 +arc: A1 V02N0701 +arc: A5 N1_V01N0101 +arc: A6 N1_V01N0101 +arc: A7 H02E0701 +arc: B1 V01N0001 +arc: B5 H02E0101 +arc: B6 V01S0000 +arc: B7 N1_V01S0000 +arc: C1 E1_H02W0401 +arc: C5 V00T0000 +arc: C6 V00T0100 +arc: C7 V02S0001 +arc: CE2 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D1 W1_H02E0201 +arc: D5 H00L0100 +arc: D6 N1_V02S0401 +arc: D7 V00B0000 +arc: E1_H01E0101 F6 +arc: E1_H02E0101 F1 +arc: E1_H02E0401 Q4 +arc: E3_H06E0203 Q4 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: LSR1 V00B0100 +arc: M0 H02W0601 +arc: M1 H00R0000 +arc: M2 H02W0601 +arc: M4 E1_H01E0101 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: V00B0100 F7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1101000000001101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0101010100001100 +word: SLICED.K1.INIT 0000000000000010 +word: SLICEC.K0.INIT 1111111111111111 +word: SLICEC.K1.INIT 1100110011000100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R39C16:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V02S0601 +arc: H00L0000 V02S0201 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 N3_V06S0103 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 N1_V01S0000 +arc: V00T0000 S1_V02N0601 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 N3_V06S0203 +arc: A1 V01N0101 +arc: A2 V01N0101 +arc: A5 H02E0501 +arc: A6 V02N0101 +arc: A7 H00R0000 +arc: B1 H02W0301 +arc: B2 H02W0301 +arc: B4 H02E0301 +arc: B5 S1_V02N0501 +arc: B7 N1_V01S0000 +arc: C1 E1_H02W0401 +arc: C2 E1_H02W0601 +arc: C4 S1_V02N0201 +arc: C5 F4 +arc: C6 V02N0001 +arc: C7 H02E0401 +arc: CE2 H00L0000 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D1 S1_V02N0001 +arc: D2 S1_V02N0001 +arc: D4 H02E0001 +arc: D5 H02E0201 +arc: D6 V02N0401 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: E1_H02E0101 F1 +arc: E3_H06E0203 F4 +arc: E3_H06E0303 Q6 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q6 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M0 H02E0601 +arc: M1 E1_H02W0001 +arc: M2 H02E0601 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: N3_V06N0203 F4 +arc: N3_V06N0303 Q5 +arc: S1_V02S0401 F4 +arc: S3_V06S0303 Q6 +arc: V01S0000 F7 +arc: W1_H02W0601 Q6 +word: SLICEC.K0.INIT 0000000000111111 +word: SLICEC.K1.INIT 0010000000000000 +word: SLICEB.K0.INIT 1010001001010001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000001010 +word: SLICED.K1.INIT 1000000000100000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1010001001010001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R39C17:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0000 H02W0201 +arc: H00R0000 H02W0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0401 S1_V02N0401 +arc: N1_V02N0501 S1_V02N0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 H06E0003 +arc: N3_V06N0103 H06E0103 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 H01E0101 +arc: S3_V06S0303 E1_H01W0100 +arc: V00T0100 W1_H02E0101 +arc: W1_H02W0301 V06S0003 +arc: A0 F7 +arc: A1 V02N0701 +arc: A2 H01E0001 +arc: A3 H01E0001 +arc: A4 V02S0101 +arc: A5 V02S0301 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B6 V02N0501 +arc: B7 H02E0301 +arc: C0 F4 +arc: C1 F4 +arc: C2 F4 +arc: C3 F4 +arc: C4 S1_V02N0001 +arc: C5 W1_H02E0601 +arc: C6 V02N0201 +arc: C7 E1_H02W0601 +arc: CLK0 G_HPBX0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H02E0201 +arc: D5 V02N0601 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E3_H06E0303 Q6 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: M1 V01S0100 +arc: M2 V00T0100 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F1 +arc: S1_V02S0401 Q6 +arc: S1_V02S0601 Q6 +arc: V00B0000 Q6 +arc: V00B0100 F7 +arc: V01S0100 F5 +arc: W1_H02W0401 Q6 +arc: W3_H06W0303 Q6 +word: SLICEC.K0.INIT 1011000000001011 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 0011111100001100 +word: SLICED.K1.INIT 1100000000001100 +word: SLICEB.K0.INIT 0101111111111111 +word: SLICEB.K1.INIT 0101111111111111 +word: SLICEA.K0.INIT 0111111101111111 +word: SLICEA.K1.INIT 0001010101010101 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D0MUX 1 + +.tile R39C18:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 N1_V01S0100 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 N3_V06S0303 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0401 H02E0401 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 H02E0701 +arc: V00T0100 H02E0101 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0301 N3_V06S0003 +arc: A6 H02W0501 +arc: B6 V02N0501 +arc: C6 W1_H02E0601 +arc: CE0 E1_H02W0101 +arc: CE1 E1_H02W0101 +arc: CE3 E1_H02W0101 +arc: CLK0 G_HPBX0100 +arc: D6 V02N0601 +arc: F6 F5D_SLICE +arc: H01W0100 Q2 +arc: M0 W1_H02E0601 +arc: M2 V00B0100 +arc: M4 V00B0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0303 Q6 +arc: S3_V06S0103 Q2 +arc: V01S0000 Q4 +arc: W1_H02W0201 Q2 +arc: W1_H02W0401 Q4 +arc: W1_H02W0601 Q4 +arc: W3_H06W0003 Q0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111100010001000 +word: SLICED.K1.INIT 1111111111111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R39C19:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: H00L0100 N1_V02S0301 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 H06E0303 +arc: N3_V06N0103 S1_V02N0201 +arc: N3_V06N0203 H06E0203 +arc: S1_V02S0301 H02W0301 +arc: V00B0100 H02E0701 +arc: V00T0000 V02S0401 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V01N0001 +arc: E1_H02E0601 W3_H06E0303 +arc: S1_V02S0601 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: A5 H02E0501 +arc: A6 H02E0701 +arc: B5 N1_V02S0501 +arc: B6 H02W0301 +arc: C5 E1_H02W0401 +arc: C6 V00T0100 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D5 H00L0100 +arc: D6 H02E0001 +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q6 +arc: M0 H02E0601 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F4 +arc: N3_V06N0303 Q6 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000100000000 +word: SLICED.K0.INIT 1110101011000000 +word: SLICED.K1.INIT 1111111111111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R39C20:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0000 H02E0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0701 N3_V06S0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0601 H02E0601 +arc: V00B0100 V02S0101 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 E1_H02W0301 +arc: W1_H02W0401 V06S0203 +arc: E1_H02E0101 W3_H06E0103 +arc: E1_H02E0201 W3_H06E0103 +arc: N1_V02N0101 W3_H06E0103 +arc: S1_V02S0101 W3_H06E0103 +arc: S1_V02S0201 W3_H06E0103 +arc: E3_H06E0103 W3_H06E0103 +arc: E3_H06E0203 W3_H06E0103 +arc: A0 H02E0501 +arc: A2 H02E0501 +arc: B0 V02N0101 +arc: B2 V02N0101 +arc: C0 S1_V02N0601 +arc: C2 W1_H02E0401 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D0 E1_H02W0001 +arc: D2 V02N0001 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: H01W0000 Q0 +arc: M0 V00B0100 +arc: M2 V00B0100 +arc: M4 H02W0401 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0001 Q0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q6 +arc: W1_H02W0001 Q2 +arc: W3_H06W0203 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1110101011000000 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1110101011000000 +word: SLICEB.K1.INIT 1111111111111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R39C21:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 V01N0001 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 H02E0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 N3_V06S0003 +arc: V00B0100 V02N0101 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06S0303 +arc: E1_H02E0501 W3_H06E0303 +arc: E1_H02E0601 W3_H06E0303 +arc: H01W0100 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 +arc: CE0 H00R0100 +arc: CE1 H00R0000 +arc: CE2 V02S0601 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0101 Q6 +arc: M0 V00B0000 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q4 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: V00B0000 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R39C22:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0401 W1_H02E0401 +arc: H00L0000 H02E0001 +arc: H00R0000 H02E0601 +arc: H00R0100 H02E0501 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02N0601 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0301 E1_H01W0100 +arc: N1_V02N0401 W3_H06E0203 +arc: CE0 H00L0000 +arc: CE1 H00R0000 +arc: CE2 H00R0100 +arc: CE3 W1_H02E0101 +arc: CLK0 G_HPBX0100 +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: M4 H02E0401 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: V00B0000 Q6 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R39C23:PLC2 +arc: H00L0100 W1_H02E0301 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0201 H06E0103 +arc: N1_V02N0401 H06E0203 +arc: V00B0000 H02E0401 +arc: V00T0000 H02E0201 +arc: N3_V06N0303 W3_H06E0303 +arc: CE0 H00R0100 +arc: CE1 H02E0101 +arc: CE2 H00L0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0101 Q2 +arc: H01W0100 Q4 +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: M4 E1_H01E0101 +arc: M6 N1_V01N0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0601 Q6 +arc: N3_V06N0003 Q0 +arc: W1_H02W0601 Q6 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R39C24:PLC2 +arc: V01S0000 N3_V06S0103 + +.tile R39C2:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V02S0401 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 E3_H06W0203 +arc: H00R0000 S1_V02N0401 +arc: V00B0000 V02N0201 +arc: A0 S1_V02N0501 +arc: A1 H00R0000 +arc: A4 N1_V01N0101 +arc: A6 V02N0101 +arc: A7 H02E0701 +arc: B1 Q1 +arc: B6 V00B0000 +arc: B7 V00B0100 +arc: C0 S1_V02N0601 +arc: C1 F6 +arc: C4 Q4 +arc: C5 V00B0100 +arc: C6 V01N0101 +arc: C7 F6 +arc: CLK0 G_HPBX0100 +arc: D0 S1_V02N0201 +arc: D1 F0 +arc: D4 F0 +arc: D5 H01W0000 +arc: D6 F0 +arc: D7 F0 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F0 +arc: E1_H02E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: H01W0100 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 F6 +arc: S1_V02S0001 F0 +arc: S1_V02S0201 F0 +arc: S1_V02S0301 Q1 +arc: S1_V02S0501 Q7 +arc: S1_V02S0701 F5 +arc: V00B0100 Q7 +arc: V01S0000 F0 +arc: V01S0100 Q4 +word: SLICEC.K0.INIT 0000101011111010 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 0000000001010000 +word: SLICEA.K1.INIT 0110000011101100 +word: SLICED.K0.INIT 1010101100000000 +word: SLICED.K1.INIT 0110000011101100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R39C3:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 V06S0003 +arc: E1_H02E0501 N3_V06S0303 +arc: H00L0100 V02S0301 +arc: H00R0000 V02S0401 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0101 N1_V02S0101 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0401 E3_H06W0203 +arc: S1_V02S0501 H02W0501 +arc: V00B0000 H02E0401 +arc: V00T0000 W1_H02E0201 +arc: A6 N1_V01N0101 +arc: A7 H02E0501 +arc: B6 H01E0101 +arc: B7 H02E0301 +arc: C6 V02N0001 +arc: C7 H01E0001 +arc: CE0 H00R0000 +arc: CE1 H00L0100 +arc: CE2 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D6 V02N0401 +arc: D7 H01W0000 +arc: E1_H01E0001 Q2 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q2 +arc: E1_H02E0601 Q4 +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q6 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q6 +arc: S1_V02S0601 Q6 +arc: V01S0100 F7 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0010001001101010 +word: SLICED.K1.INIT 1000000000100000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R39C4:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0701 N3_V06S0203 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 N3_V06S0203 +arc: S3_V06S0103 N3_V06S0103 +arc: V00T0000 H02E0001 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 E3_H06W0303 +arc: A1 H02W0701 +arc: A2 V02N0501 +arc: A3 V00T0000 +arc: A4 V02N0101 +arc: A5 W1_H02E0701 +arc: A6 H02E0501 +arc: A7 H00R0000 +arc: B1 H02W0101 +arc: B2 V02N0301 +arc: B3 V02N0101 +arc: B4 V02N0701 +arc: B5 F3 +arc: B6 H02E0101 +arc: B7 E1_H02W0301 +arc: C1 V02S0401 +arc: C2 V02N0601 +arc: C3 E1_H02W0401 +arc: C4 H02E0601 +arc: C5 H02E0601 +arc: C6 H01E0001 +arc: C7 F6 +arc: D1 V02N0001 +arc: D2 H02E0001 +arc: D3 H02W0201 +arc: D4 V01N0001 +arc: D5 H00L0100 +arc: D6 V02S0601 +arc: D7 S1_V02N0601 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H00R0000 F4 +arc: N1_V02N0501 F7 +arc: N3_V06N0103 F2 +arc: S3_V06S0303 F5 +word: SLICEC.K0.INIT 1000010000100001 +word: SLICEC.K1.INIT 0100110000000000 +word: SLICED.K0.INIT 1001000000001001 +word: SLICED.K1.INIT 1000000000000000 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 0001010100111111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000011101110111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R39C5:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 V02N0601 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E3_H06W0203 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 N1_V01S0000 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 V01N0001 +arc: S3_V06S0203 E3_H06W0203 +arc: V00B0000 V02S0001 +arc: V00T0000 V02S0601 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0701 V02S0701 +arc: A0 V02N0701 +arc: A1 V01N0101 +arc: A3 F5 +arc: A4 V02N0301 +arc: A5 S1_V02N0101 +arc: A6 H00R0000 +arc: A7 H00L0000 +arc: B0 V02S0301 +arc: B1 V00T0000 +arc: B3 F1 +arc: B4 N1_V01S0000 +arc: B5 H02E0101 +arc: B6 V02S0701 +arc: B7 V02S0501 +arc: C0 N1_V01S0100 +arc: C1 H02E0401 +arc: C3 F4 +arc: C4 V02S0201 +arc: C5 V02S0001 +arc: C6 V02N0001 +arc: C7 F6 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0001 +arc: D3 S1_V02N0001 +arc: D4 H02W0201 +arc: D5 V02N0601 +arc: D6 V00B0000 +arc: D7 H02E0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F2 +arc: M2 N1_V01N0001 +arc: N1_V01N0001 F0 +arc: N3_V06N0103 F2 +arc: S1_V02S0701 F7 +word: SLICED.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 0100000011000000 +word: SLICEC.K0.INIT 1001000000000000 +word: SLICEC.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1111111111111111 +word: SLICEB.K1.INIT 0111111111111111 +word: SLICEA.K0.INIT 1001000000001001 +word: SLICEA.K1.INIT 1001000000001001 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R39C6:PLC2 +arc: H00L0000 H02E0001 +arc: H00L0100 V02S0101 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 E1_H01W0100 +arc: S1_V02S0101 N1_V01S0100 +arc: S1_V02S0601 H02W0601 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02W0501 +arc: V00T0100 H02W0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CE2 H00L0100 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: H01W0100 Q4 +arc: M0 V00B0000 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V02N0001 Q2 +arc: N1_V02N0201 Q0 +arc: N1_V02N0401 Q4 +arc: N1_V02N0601 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R39C7:PLC2 +arc: E1_H02E0001 V02S0001 +arc: H00L0100 V02S0301 +arc: H00R0000 H02W0401 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0201 H06W0103 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 V02N0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0101 V02S0101 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 N3_V06S0303 +arc: W3_H06W0103 E1_H01W0100 +arc: W3_H06W0303 E3_H06W0303 +arc: CE0 H00L0100 +arc: CE1 H00L0100 +arc: CE2 H00L0100 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: H01W0100 Q4 +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: M4 V00B0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0401 Q4 +arc: N3_V06N0303 Q6 +arc: V01S0000 Q6 +arc: W1_H02W0001 Q2 +arc: W1_H02W0201 Q0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R39C8:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: H00L0000 H02E0001 +arc: H00R0000 H02W0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0003 S1_V02N0301 +arc: N3_V06N0103 E3_H06W0103 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0701 N1_V02S0701 +arc: V00B0100 H02W0701 +arc: V00T0100 V02S0501 +arc: W1_H02W0401 V01N0001 +arc: W3_H06W0203 V06S0203 +arc: A0 E1_H02W0501 +arc: A1 H00R0000 +arc: A6 V02N0301 +arc: A7 H00R0000 +arc: B1 E1_H02W0101 +arc: B6 E1_H02W0301 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C1 V02N0401 +arc: C6 H02W0401 +arc: C7 E1_H02W0401 +arc: CE1 H00L0000 +arc: CE2 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D0 E1_H02W0001 +arc: D1 F0 +arc: D6 H00R0100 +arc: D7 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q2 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0301 F1 +arc: N3_V06N0203 F7 +arc: S3_V06S0103 Q2 +arc: S3_V06S0203 Q4 +arc: V00B0000 F6 +arc: W1_H02W0201 Q2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1010000000000000 +word: SLICEA.K1.INIT 0000000001111111 +word: SLICED.K0.INIT 0100111101111111 +word: SLICED.K1.INIT 1011001100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R39C9:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0401 V02N0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0100 H02W0701 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 V02N0601 +arc: W1_H02W0701 V06S0203 +arc: A0 H02W0501 +arc: A1 V01N0101 +arc: A3 V01N0101 +arc: A6 V02N0101 +arc: A7 H02W0701 +arc: B0 V01N0001 +arc: B1 H02W0101 +arc: B3 H02W0101 +arc: B6 S1_V02N0501 +arc: C1 F6 +arc: C3 S1_V02N0601 +arc: C4 E1_H02W0401 +arc: C5 H02W0601 +arc: C6 V02N0001 +arc: C7 F6 +arc: CLK0 G_HPBX0100 +arc: D0 H02W0001 +arc: D1 F0 +arc: D3 V00B0100 +arc: D4 H00R0100 +arc: D5 V00B0000 +arc: D6 S1_V02N0401 +arc: D7 V02S0401 +arc: E1_H02E0601 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F3 +arc: N1_V02N0301 F1 +arc: N3_V06N0203 Q7 +arc: N3_V06N0303 F6 +arc: S1_V02S0701 F5 +arc: V00B0000 F4 +arc: V01S0000 F4 +arc: W3_H06W0203 F4 +word: SLICEC.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1111000000000000 +word: SLICEA.K0.INIT 1000100000000000 +word: SLICEA.K1.INIT 0000000001111111 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICED.K0.INIT 0000101000000011 +word: SLICED.K1.INIT 1010000011111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R40C10:PLC2 +arc: E1_H02E0301 E1_H01W0100 +arc: H00R0000 H02W0601 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0601 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 H01E0001 +arc: V00B0100 V02N0301 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 S1_V02N0601 +arc: W1_H02W0701 V02S0701 +arc: W1_H02W0001 W3_H06E0003 +arc: B0 F1 +arc: B2 F3 +arc: B3 V02S0301 +arc: C0 N1_V01S0100 +arc: C1 H02E0601 +arc: C2 H02E0401 +arc: CE0 H00R0100 +arc: CE1 H00L0000 +arc: CE2 H00R0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D0 H02E0001 +arc: D1 E1_H02W0001 +arc: D2 V02S0201 +arc: D3 H02E0201 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F1 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 F1 +arc: E1_H02E0601 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00L0000 F2 +arc: H01W0000 Q0 +arc: H01W0100 Q3 +arc: LSR0 V00B0100 +arc: M4 V00T0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q4 +arc: N1_V02N0101 Q3 +arc: S1_V02S0101 F3 +arc: S1_V02S0301 F3 +arc: V01S0100 F0 +arc: W1_H02W0101 F3 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1100110011000011 +word: SLICEB.K1.INIT 0011001100000000 +word: SLICEA.K0.INIT 0011000000000000 +word: SLICEA.K1.INIT 1111000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R40C11:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 H01E0101 +arc: H00L0000 N1_V02S0001 +arc: N1_V02N0601 N1_V01S0000 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0601 H01E0001 +arc: V00B0000 H02E0601 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0601 V06S0303 +arc: H01W0100 W3_H06E0303 +arc: A4 E1_H01W0000 +arc: A5 F7 +arc: A7 N1_V01N0101 +arc: B5 H00L0000 +arc: B7 H02E0301 +arc: C4 E1_H02W0401 +arc: C5 F4 +arc: C7 V02S0201 +arc: CE1 V02N0201 +arc: CLK0 G_HPBX0100 +arc: D4 H02E0001 +arc: D5 V02S0401 +arc: D7 V00B0000 +arc: E1_H02E0401 F4 +arc: E1_H02E0601 F4 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F4 +arc: M2 V00T0100 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q2 +arc: N3_V06N0203 F4 +arc: N3_V06N0303 F5 +arc: S3_V06S0203 F4 +arc: V01S0100 F4 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000101011111010 +word: SLICEC.K1.INIT 1011000010111011 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001001101011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R40C12:PLC2 +arc: H00L0100 V02N0301 +arc: N1_V02N0101 W1_H02E0101 +arc: V00T0000 H02W0201 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0701 V02N0701 +arc: A1 F5 +arc: A3 V01N0101 +arc: A6 H02E0501 +arc: A7 Q7 +arc: B1 V01N0001 +arc: B3 V02N0101 +arc: B6 H02E0101 +arc: C1 H00L0100 +arc: C3 S1_V02N0601 +arc: C5 V00B0100 +arc: C6 V00T0100 +arc: C7 F6 +arc: CLK0 G_HPBX0100 +arc: D1 V02N0001 +arc: D3 V02N0001 +arc: D5 V02N0601 +arc: D6 V02S0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F6 +arc: E1_H02E0701 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M0 H02W0601 +arc: M2 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 F5 +arc: S1_V02S0701 Q7 +arc: V00B0100 Q7 +arc: V01S0000 F6 +arc: V01S0100 Q7 +arc: W1_H02W0001 F0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000100001100001 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000111111110000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000001000001 +word: SLICED.K0.INIT 0100000000000000 +word: SLICED.K1.INIT 0101101001011010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R40C13:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 N3_V06S0303 +arc: H00L0100 S1_V02N0101 +arc: H00R0100 H02E0701 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0401 W1_H02E0401 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0000 V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0100 E1_H02W0301 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0203 E3_H06W0103 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0601 +arc: CE2 V02S0601 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: E3_H06E0203 Q4 +arc: F2 F5B_SLICE +arc: M2 V00B0000 +arc: M4 V00B0100 +arc: M6 V00T0100 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V02N0601 Q6 +arc: N3_V06N0203 Q4 +arc: W1_H02W0201 F2 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0010001000101000 +word: SLICEB.K1.INIT 1000100010000001 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R40C14:PLC2 +arc: E1_H02E0001 V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 E1_H01W0100 +arc: V00B0000 S1_V02N0201 +arc: V00T0000 H02E0001 +arc: A0 S1_V02N0701 +arc: A1 V01N0101 +arc: A7 V02N0101 +arc: B0 V01N0001 +arc: B1 H01W0100 +arc: B2 F3 +arc: B3 V02S0101 +arc: B7 V00T0000 +arc: C0 V02N0401 +arc: C1 V02N0601 +arc: C3 S1_V02N0401 +arc: C7 N1_V02S0201 +arc: CE0 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D0 V02S0001 +arc: D1 N1_V02S0001 +arc: D2 V02S0001 +arc: D7 H02W0201 +arc: E1_H01E0001 F3 +arc: E1_H02E0101 F3 +arc: E1_H02E0601 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 F2 +arc: H01W0100 Q0 +arc: LSR0 H02E0301 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0101 F1 +arc: N1_V02N0301 F3 +arc: N3_V06N0003 F3 +arc: N3_V06N0103 F1 +arc: S1_V02S0101 F3 +arc: V01S0000 F6 +arc: V01S0100 F3 +word: SLICEA.K0.INIT 0000000001000000 +word: SLICEA.K1.INIT 1111111000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0101010100010101 +word: SLICEB.K0.INIT 0011001111111111 +word: SLICEB.K1.INIT 0011000000110000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R40C15:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 N3_V06S0303 +arc: H00R0000 S1_V02N0601 +arc: H00R0100 N1_V02S0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0401 H01E0001 +arc: S1_V02S0601 N3_V06S0303 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 V02S0401 +arc: V00T0100 V02N0701 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0201 E1_H02W0201 +arc: A3 V02S0701 +arc: A7 N1_V01N0101 +arc: B3 V02S0101 +arc: C6 H02W0401 +arc: C7 E1_H01E0101 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CE2 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: D3 S1_V02N0201 +arc: D7 H00R0100 +arc: E1_H01E0001 Q6 +arc: E1_H01E0101 Q6 +arc: E1_H02E0001 Q0 +arc: E1_H02E0201 Q0 +arc: E1_H02E0601 Q4 +arc: E3_H06E0003 Q0 +arc: E3_H06E0203 Q4 +arc: E3_H06E0303 Q6 +arc: F3 F3_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q3 +arc: M0 V00T0000 +arc: M4 V00B0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q3 +arc: N3_V06N0003 Q0 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q6 +arc: S1_V02S0201 Q0 +arc: W1_H02W0301 Q3 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1111000011110000 +word: SLICED.K1.INIT 1010000011110101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000010001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R40C16:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0601 V02S0601 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H02E0401 +arc: N3_V06N0003 H06W0003 +arc: S1_V02S0101 W1_H02E0101 +arc: S1_V02S0301 N1_V01S0100 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: S3_V06S0203 H06E0203 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0301 +arc: V00T0100 V02N0701 +arc: W1_H02W0401 N3_V06S0203 +arc: A1 H01E0001 +arc: A2 H01E0001 +arc: A7 S1_V02N0301 +arc: B1 E1_H01W0100 +arc: B2 E1_H01W0100 +arc: B7 V01S0000 +arc: C1 H02E0601 +arc: C2 H02E0601 +arc: C7 N1_V02S0001 +arc: CLK0 G_HPBX0100 +arc: D1 H02E0201 +arc: D2 H02E0001 +arc: D7 H02W0001 +arc: E1_H01E0101 F6 +arc: E1_H02E0301 F1 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F6 F5D_SLICE +arc: M0 V00B0000 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK2 CLK0 +arc: N1_V01N0101 Q4 +arc: V01S0000 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000101001000101 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1001000010011001 +word: SLICEB.K0.INIT 1000101001000101 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R40C17:PLC2 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0601 S1_V02N0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 W1_H02E0601 +arc: N1_V02N0701 H02E0701 +arc: S1_V02S0101 H02W0101 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0201 N3_V06S0103 +arc: A1 V02S0701 +arc: A4 E1_H02W0701 +arc: A5 E1_H01W0000 +arc: A7 V02S0301 +arc: B0 H02E0301 +arc: B1 H02E0301 +arc: B2 H02E0301 +arc: B3 H02E0301 +arc: B4 H00R0000 +arc: B5 S1_V02N0701 +arc: B6 W1_H02E0101 +arc: B7 V01S0000 +arc: C0 F4 +arc: C1 F4 +arc: C2 F4 +arc: C3 F4 +arc: C4 W1_H02E0601 +arc: C5 H02E0601 +arc: CLK0 G_HPBX0100 +arc: D0 H02E0201 +arc: D1 H01E0101 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 S1_V02N0401 +arc: D5 H02E0001 +arc: D7 N1_V02S0601 +arc: E1_H01E0001 Q6 +arc: E1_H02E0401 Q6 +arc: E3_H06E0303 Q6 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 Q6 +arc: H01W0100 Q6 +arc: M0 V00B0100 +arc: M1 H00R0100 +arc: M2 V00B0100 +arc: M6 V00T0100 +arc: MUXCLK3 CLK0 +arc: N1_V02N0301 F1 +arc: N3_V06N0303 Q6 +arc: V00B0100 F5 +arc: V01S0000 Q6 +word: SLICEB.K0.INIT 0011111111111111 +word: SLICEB.K1.INIT 0011111111111111 +word: SLICEA.K0.INIT 0011111111111111 +word: SLICEA.K1.INIT 0000000001111111 +word: SLICED.K0.INIT 1100110011001100 +word: SLICED.K1.INIT 1000100011011101 +word: SLICEC.K0.INIT 1010001001010001 +word: SLICEC.K1.INIT 1000110000100011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R40C18:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 V06S0303 +arc: H00R0000 H02W0401 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H02W0601 +arc: V00B0000 N1_V02S0201 +arc: V00T0000 S1_V02N0601 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: A1 H01E0001 +arc: A2 H01E0001 +arc: A5 E1_H01W0000 +arc: B1 E1_H01W0100 +arc: B2 E1_H01W0100 +arc: B5 N1_V01S0000 +arc: C1 V02N0601 +arc: C2 V02N0601 +arc: C5 H02E0401 +arc: CLK0 G_HPBX0100 +arc: D1 V02S0001 +arc: D2 V02S0001 +arc: D5 V02S0401 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q6 +arc: M0 V00B0000 +arc: M1 H00R0000 +arc: M2 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: S1_V02S0101 F1 +arc: W1_H02W0701 F5 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1001000000001001 +word: SLICEB.K0.INIT 1001000000001001 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1000001001000001 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R40C19:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 V02S0601 +arc: N1_V02N0401 N3_V06S0203 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0301 E1_H02W0301 +arc: V00B0000 W1_H02E0601 +arc: V00B0100 V02S0301 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0701 W3_H06E0203 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0601 +arc: CE0 H00R0000 +arc: CE2 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q4 +arc: M0 V00B0100 +arc: M4 E1_H02W0401 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V02N0001 Q0 +arc: N1_V02N0201 F2 +arc: N3_V06N0003 F3 +arc: N3_V06N0103 F2 +arc: V01S0100 Q4 +arc: W1_H02W0601 Q4 +arc: W3_H06W0003 F3 +arc: W3_H06W0103 F2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111111100001100 +word: SLICEB.K1.INIT 0000000011000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.A1MUX 1 + +.tile R40C20:PLC2 +arc: E1_H02E0101 V02S0101 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0101 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0701 N3_V06S0203 +arc: N3_V06N0303 H06E0303 +arc: S1_V02S0201 H02W0201 +arc: V00B0000 H02W0601 +arc: V00B0100 W1_H02E0501 +arc: CE0 H00R0000 +arc: CE1 H00L0000 +arc: CE2 V02S0601 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: M0 E1_H02W0601 +arc: M2 N1_V01N0001 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R40C21:PLC2 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 N3_V06S0203 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 W3_H06E0003 +arc: W1_H02W0401 W3_H06E0203 +arc: CE0 H00L0100 +arc: CE1 V02S0201 +arc: CE2 H00L0100 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0100 +arc: H01W0000 Q4 +arc: M0 V00B0000 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: N3_V06N0003 Q0 +arc: V00B0000 Q6 +arc: V00T0000 Q2 +arc: W1_H02W0601 Q4 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R40C22:PLC2 +arc: H00L0100 V02S0301 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0701 N3_V06S0203 +arc: V00T0100 V02S0701 +arc: CE1 V02S0201 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: M2 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V02N0601 Q6 +arc: V00T0000 Q2 +arc: W1_H02W0601 Q6 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R40C24:PLC2 +arc: N1_V02N0601 N1_V01S0000 + +.tile R40C2:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 N1_V01S0000 +arc: S1_V02S0201 N1_V01S0000 +arc: V00B0000 V02N0001 +arc: A0 H00L0100 +arc: A1 S1_V02N0501 +arc: A3 S1_V02N0501 +arc: A5 V00T0000 +arc: B0 V02S0301 +arc: B1 V00T0000 +arc: B2 V02N0301 +arc: B3 H01W0100 +arc: B5 V01S0000 +arc: C0 V02N0401 +arc: C1 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 E1_H01W0000 +arc: C4 V02S0201 +arc: C5 E1_H01E0101 +arc: CLK0 G_HPBX0100 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 H01W0000 +arc: D5 E1_H01W0100 +arc: E1_H01E0001 Q2 +arc: E1_H01E0101 Q4 +arc: E1_H02E0101 F3 +arc: E1_H02E0701 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 F0 +arc: H00L0100 Q1 +arc: H01W0000 Q4 +arc: H01W0100 Q2 +arc: LSR1 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q4 +arc: N1_V02N0101 Q1 +arc: N1_V02N0201 Q2 +arc: V00T0000 Q2 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +word: SLICEB.K0.INIT 1100110011111100 +word: SLICEB.K1.INIT 0000011100001111 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICEA.K0.INIT 0010101010101010 +word: SLICEA.K1.INIT 1111010011110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R40C3:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0601 N3_V06S0303 +arc: E1_H02E0701 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H01E0001 +arc: V00B0000 V02N0001 +arc: V00T0000 H02E0001 +arc: V00T0100 H02E0301 +arc: A0 S1_V02N0501 +arc: A1 H02E0701 +arc: A2 V02N0701 +arc: A4 V00T0100 +arc: A5 N1_V01N0101 +arc: A7 V02S0101 +arc: B0 V02S0301 +arc: B1 V00T0000 +arc: B2 V02N0101 +arc: B3 Q3 +arc: B4 S1_V02N0501 +arc: B5 H02E0101 +arc: B7 V02S0501 +arc: C0 V02S0601 +arc: C1 H02E0601 +arc: C2 N1_V01S0100 +arc: C3 F4 +arc: C4 H02E0401 +arc: C5 S1_V02N0001 +arc: C7 E1_H01E0101 +arc: CE0 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 H01E0101 +arc: D1 F0 +arc: D2 V00T0100 +arc: D3 F2 +arc: D4 E1_H01W0100 +arc: D5 H00L0100 +arc: D7 V02S0401 +arc: E1_H01E0101 F1 +arc: E1_H02E0301 Q1 +arc: E3_H06E0103 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0100 F7 +arc: H01W0000 F0 +arc: H01W0100 Q5 +arc: LSR0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0101 F4 +arc: S1_V02S0701 Q5 +word: SLICEC.K0.INIT 0111000000110000 +word: SLICEC.K1.INIT 1111101111110011 +word: SLICEA.K0.INIT 0100100000000000 +word: SLICEA.K1.INIT 1111111100100000 +word: SLICEB.K0.INIT 1111100011110000 +word: SLICEB.K1.INIT 1111111100001100 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111100011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET SET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R40C4:PLC2 +arc: E1_H02E0601 S1_V02N0601 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 H02E0201 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 H02E0601 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0100 H02E0701 +arc: V00T0000 W1_H02E0001 +arc: A1 V02S0501 +arc: A3 V00T0000 +arc: A6 W1_H02E0501 +arc: A7 V02S0101 +arc: B1 E1_H02W0101 +arc: B3 V02S0101 +arc: B6 V02N0501 +arc: B7 V01S0000 +arc: C1 V02S0401 +arc: C3 F6 +arc: C7 F6 +arc: CE1 V02N0201 +arc: CE2 H00R0100 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D1 V01S0100 +arc: D3 V00T0100 +arc: D7 W1_H02E0001 +arc: E1_H02E0101 F1 +arc: E3_H06E0003 Q3 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 F6 +arc: M4 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: V00T0100 Q3 +arc: V01S0000 Q7 +arc: V01S0100 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0001000100010001 +word: SLICED.K1.INIT 1110110001001100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 1110111100100000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000011101110111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R40C5:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 V06S0303 +arc: E3_H06E0003 W1_H02E0301 +arc: E3_H06E0303 V06S0303 +arc: H00L0100 N1_V02S0101 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 V01N0101 +arc: N3_V06N0103 S1_V02N0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 N3_V06S0203 +arc: V00B0000 H02W0401 +arc: V00B0100 V02N0301 +arc: V00T0000 N1_V02S0601 +arc: A4 N1_V01N0101 +arc: A5 H02E0701 +arc: B4 N1_V02S0701 +arc: B5 H02E0101 +arc: C4 V00T0000 +arc: C5 F4 +arc: CE0 H00L0100 +arc: CE1 H00L0100 +arc: CE3 V02S0601 +arc: CLK0 G_HPBX0100 +arc: D4 E1_H02W0001 +arc: D5 E1_H02W0201 +arc: E1_H02E0701 F5 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q6 +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q2 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0100000011000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R40C6:PLC2 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0100 H02W0301 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0101 N1_V02S0001 +arc: S1_V02S0501 N3_V06S0303 +arc: S1_V02S0701 E1_H02W0701 +arc: V00B0000 S1_V02N0001 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0401 N3_V06S0203 +arc: A2 V01N0101 +arc: A3 H02W0701 +arc: A5 V02S0101 +arc: A7 H02W0501 +arc: B2 H00R0000 +arc: B3 H02E0301 +arc: B5 H02E0301 +arc: B7 V01S0000 +arc: C2 H00L0100 +arc: C3 H00L0000 +arc: C5 V00T0100 +arc: C7 S1_V02N0201 +arc: CE0 N1_V02S0201 +arc: CLK0 G_HPBX0100 +arc: D2 H02E0001 +arc: D3 V02N0201 +arc: D5 V02N0401 +arc: D7 S1_V02N0601 +arc: E1_H02E0701 F5 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q0 +arc: M0 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: N1_V01N0101 F3 +arc: S1_V02S0601 F6 +arc: V00T0000 F2 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001001101011111 +word: SLICEB.K0.INIT 0000011101110111 +word: SLICEB.K1.INIT 1000010000100001 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R40C7:PLC2 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 H02W0001 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 E1_H02W0501 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0701 +arc: V00T0100 H02W0101 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 N1_V01S0100 +arc: W3_H06W0003 N3_V06S0003 +arc: A3 N1_V02S0501 +arc: A5 E1_H01W0000 +arc: A6 W1_H02E0501 +arc: A7 W1_H02E0701 +arc: B3 V01N0001 +arc: B6 V01S0000 +arc: B7 V00B0000 +arc: C3 S1_V02N0401 +arc: C4 V02S0201 +arc: C6 N1_V02S0201 +arc: C7 F6 +arc: CE0 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D3 S1_V02N0001 +arc: D4 E1_H01W0100 +arc: D5 F2 +arc: D6 H02W0201 +arc: D7 H00R0100 +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 V00T0100 +arc: M2 V00B0100 +arc: M4 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0701 Q7 +arc: N3_V06N0203 Q4 +arc: V01S0000 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000011101110111 +word: SLICEC.K0.INIT 0000000000001111 +word: SLICEC.K1.INIT 1010101011111111 +word: SLICED.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0101010100000011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R40C8:PLC2 +arc: E1_H02E0601 V02N0601 +arc: E1_H02E0701 W1_H02E0601 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H06E0003 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 V01N0101 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0501 H02W0501 +arc: V00B0100 H02W0501 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0701 N3_V06S0203 +arc: A3 E1_H02W0501 +arc: B3 V01N0001 +arc: C2 H02E0601 +arc: C3 N1_V02S0601 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D2 S1_V02N0201 +arc: D3 H00R0000 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F2 +arc: H01W0100 F3 +arc: LSR0 E1_H02W0301 +arc: M6 V00B0100 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR0 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111000000000000 +word: SLICEB.K1.INIT 0001010100111111 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 + +.tile R40C9:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E1_H01W0000 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0401 N3_V06S0203 +arc: S1_V02S0201 N3_V06S0103 +arc: S3_V06S0103 N3_V06S0103 +arc: V00B0100 V02S0101 +arc: V00T0100 N1_V02S0501 +arc: V01S0100 N3_V06S0303 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0501 N3_V06S0303 +arc: W1_H02W0701 N3_V06S0203 +arc: E1_H02E0201 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: A0 H02W0701 +arc: A1 H02E0701 +arc: A7 Q7 +arc: B0 V02N0301 +arc: B1 S1_V02N0101 +arc: B6 V02N0701 +arc: B7 V00B0000 +arc: C0 V02S0401 +arc: C1 H00L0100 +arc: C6 V02N0201 +arc: C7 V02S0201 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 V00T0100 +arc: D1 F0 +arc: D6 E1_H01W0100 +arc: D7 V01N0001 +arc: E1_H01E0001 F6 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 F7 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M2 H02E0601 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 Q2 +arc: N1_V02N0601 Q4 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q4 +arc: S1_V02S0501 Q7 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F7 +arc: V00B0000 F6 +arc: V01S0000 F6 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000110011111100 +word: SLICED.K1.INIT 1010100110101010 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0000000011110100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R41C10:PLC2 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0501 N1_V01S0100 +arc: N1_V02N0301 S1_V02N0201 +arc: N3_V06N0003 E3_H06W0003 +arc: S1_V02S0501 N1_V02S0501 +arc: V00T0000 H02E0001 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0501 W3_H06E0303 +arc: A1 V02N0501 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A7 V02N0301 +arc: B1 V02N0301 +arc: B2 V02S0101 +arc: B4 V02N0701 +arc: B5 V02N0701 +arc: B7 H01E0101 +arc: C1 N1_V01N0001 +arc: C3 H00L0000 +arc: C4 N1_V02S0201 +arc: C5 N1_V02S0201 +arc: C7 H02E0401 +arc: CLK0 G_HPBX0100 +arc: D1 H01E0101 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D4 V02S0601 +arc: D5 V02S0401 +arc: D7 V01N0001 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H01W0000 F0 +arc: H01W0100 Q6 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M0 H02E0601 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F3 +arc: N1_V01N0101 Q2 +arc: N1_V02N0001 F0 +arc: V00B0000 F4 +arc: V01S0000 Q2 +arc: W1_H02W0001 Q2 +arc: W1_H02W0301 F3 +word: SLICEB.K0.INIT 0011001111001100 +word: SLICEB.K1.INIT 1111000000001111 +word: SLICEC.K0.INIT 0100010001001000 +word: SLICEC.K1.INIT 1000100010000001 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0001010010000001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0010000000010000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R41C11:PLC2 +arc: E1_H02E0701 N1_V01S0100 +arc: H00L0100 V02S0301 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 H02W0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H02W0301 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0101 H02W0101 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 H02W0501 +arc: S1_V02S0601 E1_H01W0000 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 E1_H02W0501 +arc: V00T0000 E1_H02W0001 +arc: V00T0100 W1_H02E0101 +arc: W3_H06W0003 E3_H06W0003 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 V00T0000 +arc: A5 N1_V01N0101 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B4 E1_H02W0101 +arc: B5 N1_V01S0000 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 V00B0100 +arc: C5 V00T0100 +arc: CLK1 G_HPBX0100 +arc: D0 E1_H02W0201 +arc: D1 E1_H02W0201 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0201 +arc: D4 H00R0100 +arc: D5 H00L0100 +arc: E1_H01E0101 Q3 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: LSR1 H02E0501 +arc: MUXCLK0 CLK1 +arc: MUXCLK1 CLK1 +arc: V01S0000 Q1 +arc: V01S0100 Q0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK + +.tile R41C12:PLC2 +arc: E1_H02E0001 E1_H01W0000 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0701 N1_V01S0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0203 E3_H06W0203 +arc: N3_V06N0303 H06W0303 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 H01E0101 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0501 N1_V01S0100 +arc: A0 F7 +arc: A1 V02S0701 +arc: A3 H02E0701 +arc: A5 Q5 +arc: A6 F7 +arc: A7 E1_H01W0000 +arc: B0 V00B0000 +arc: B1 Q1 +arc: B3 E1_H01W0100 +arc: B4 F3 +arc: B5 F3 +arc: B7 V02S0701 +arc: C0 H00L0100 +arc: C1 V02N0401 +arc: C2 H00R0100 +arc: C3 H02W0601 +arc: C4 Q4 +arc: C6 V00T0100 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0100 +arc: D0 F2 +arc: D1 N1_V01S0000 +arc: D2 H02W0001 +arc: D3 S1_V02N0201 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: D7 V02N0401 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H00R0100 Q5 +arc: H01W0000 F4 +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q4 +arc: N1_V02N0001 F2 +arc: N1_V02N0101 F3 +arc: N1_V02N0201 F0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 F6 +arc: S1_V02S0701 F5 +arc: V00B0000 Q4 +arc: V00T0100 Q1 +arc: V01S0000 Q1 +arc: W1_H02W0701 F5 +word: SLICEB.K0.INIT 0000111111110000 +word: SLICEB.K1.INIT 0000000001000000 +word: SLICEC.K0.INIT 0011110000111100 +word: SLICEC.K1.INIT 0110011010101010 +word: SLICEA.K0.INIT 0111000110001110 +word: SLICEA.K1.INIT 0110110011001100 +word: SLICED.K0.INIT 1010010101011010 +word: SLICED.K1.INIT 0010000011110010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R41C13:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0401 N3_V06S0203 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 N1_V01S0100 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0701 H02E0701 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 H01E0101 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A3 H02E0701 +arc: A5 V02S0101 +arc: A6 H00L0000 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B4 S1_V02N0501 +arc: B6 S1_V02N0701 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 F4 +arc: C3 H00R0100 +arc: C5 F4 +arc: C6 Q6 +arc: C7 S1_V02N0201 +arc: CLK0 G_HPBX0100 +arc: D0 H01E0101 +arc: D1 H01E0101 +arc: D2 Q2 +arc: D3 H02E0001 +arc: D4 V02S0601 +arc: D6 V02S0401 +arc: D7 V00B0000 +arc: E1_H01E0101 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0100 F7 +arc: H01W0000 Q2 +arc: H01W0100 Q2 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M0 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V02N0001 Q2 +arc: N1_V02N0701 F7 +arc: V00B0000 Q6 +arc: V00T0000 Q0 +arc: V01S0100 F6 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 F2 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 Q6 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 1000000000000000 +word: SLICEA.K1.INIT 0111111111111111 +word: SLICEC.K0.INIT 0000000000110011 +word: SLICEC.K1.INIT 0101101001011010 +word: SLICEB.K0.INIT 0000111111110000 +word: SLICEB.K1.INIT 0101101000001111 +word: SLICED.K0.INIT 1111000011010010 +word: SLICED.K1.INIT 1111000000001111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 + +.tile R41C14:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0201 N1_V01S0000 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 N3_V06S0303 +arc: H00L0000 N1_V02S0201 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 E1_H02W0601 +arc: N3_V06N0203 E3_H06W0203 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0401 E1_H01W0000 +arc: V00T0000 N1_V02S0601 +arc: W3_H06W0303 E3_H06W0203 +arc: A0 N1_V02S0701 +arc: A1 H00R0000 +arc: A2 S1_V02N0701 +arc: A4 V00B0000 +arc: A6 N1_V01S0100 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 S1_V02N0301 +arc: B3 V02N0301 +arc: B4 V02N0501 +arc: B7 V00T0000 +arc: C0 E1_H02W0401 +arc: C2 V02N0601 +arc: C3 H02E0401 +arc: C4 H02W0601 +arc: C7 E1_H02W0601 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D0 H02W0201 +arc: D1 V00T0100 +arc: D2 V01S0100 +arc: D3 V02N0001 +arc: D4 F0 +arc: D6 E1_H01W0100 +arc: D7 V00B0000 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F2 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0100 F1 +arc: LSR1 E1_H02W0301 +arc: M4 V00T0100 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 Q6 +arc: N1_V02N0201 F0 +arc: N1_V02N0301 F1 +arc: N1_V02N0401 Q6 +arc: N3_V06N0303 Q6 +arc: S1_V02S0101 F3 +arc: S1_V02S0601 F4 +arc: V00B0000 Q6 +arc: V00T0100 F3 +arc: V01S0000 F4 +arc: V01S0100 F3 +word: SLICEC.K0.INIT 0000100011111111 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111000011100000 +word: SLICEB.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 1010101000000000 +word: SLICED.K1.INIT 0000000000000011 +word: SLICEA.K0.INIT 0000000001000000 +word: SLICEA.K1.INIT 1010101000100010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 + +.tile R41C15:PLC2 +arc: E1_H02E0501 N1_V01S0100 +arc: H00R0100 V02N0501 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 N1_V01S0100 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H01E0101 +arc: V00B0000 H02W0601 +arc: V00B0100 H02W0701 +arc: V00T0000 V02S0601 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0601 E1_H02W0301 +arc: A0 H02E0701 +arc: A5 H02E0501 +arc: A6 N1_V01N0101 +arc: A7 H00R0000 +arc: B0 F1 +arc: B5 E1_H02W0301 +arc: C1 E1_H01W0000 +arc: C5 H01E0001 +arc: C7 V02S0001 +arc: CE1 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 H02E0001 +arc: D1 V00B0100 +arc: D5 H02E0201 +arc: D7 V02N0401 +arc: E1_H02E0401 Q6 +arc: E3_H06E0303 Q6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F4 +arc: H01W0100 F4 +arc: M2 H02E0601 +arc: M4 V00B0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0101 F1 +arc: N1_V02N0601 Q6 +arc: N3_V06N0003 Q0 +arc: N3_V06N0303 Q6 +arc: S1_V02S0401 F4 +arc: S1_V02S0601 F4 +arc: V01S0000 F4 +arc: V01S0100 F4 +arc: W3_H06W0103 Q2 +arc: W3_H06W0303 Q6 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1010101010101010 +word: SLICED.K1.INIT 1010000010101111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000001000000000 +word: SLICEA.K0.INIT 0111011111111111 +word: SLICEA.K1.INIT 0000000000001111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R41C16:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 V06S0103 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H02W0701 +arc: N3_V06N0103 H06W0103 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0501 N3_V06S0303 +arc: S3_V06S0303 N3_V06S0303 +arc: V00B0100 S1_V02N0301 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0401 N1_V02S0401 +arc: A0 E1_H01E0001 +arc: A3 F7 +arc: A5 V02S0101 +arc: A6 N1_V02S0301 +arc: B0 V02N0101 +arc: B3 N1_V02S0301 +arc: B5 V02N0501 +arc: B6 N1_V02S0501 +arc: B7 V00B0000 +arc: C0 N1_V02S0401 +arc: C1 H00L0000 +arc: C4 S1_V02N0001 +arc: C6 E1_H01E0101 +arc: CE2 H00R0000 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D1 E1_H02W0001 +arc: D3 V00T0100 +arc: D4 N1_V02S0401 +arc: D5 S1_V02N0601 +arc: D6 N1_V02S0401 +arc: D7 V02S0601 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 F7 +arc: E1_H02E0001 Q0 +arc: E1_H02E0501 Q5 +arc: E3_H06E0103 F1 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00L0100 F3 +arc: H00R0000 F4 +arc: H01W0000 Q0 +arc: H01W0100 Q6 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V02N0201 Q0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0501 F7 +arc: N3_V06N0003 Q0 +arc: N3_V06N0203 F7 +arc: N3_V06N0303 Q5 +arc: V00B0000 Q6 +arc: V01S0000 Q5 +arc: V01S0100 Q0 +arc: W1_H02W0601 Q6 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0010000000100000 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICED.K0.INIT 0000100000000000 +word: SLICED.K1.INIT 0000000011001100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0100010011111111 +word: SLICEC.K0.INIT 0000111111111111 +word: SLICEC.K1.INIT 0010001000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C1MUX 1 + +.tile R41C17:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0203 H06W0203 +arc: S1_V02S0401 N1_V02S0401 +arc: S1_V02S0501 N1_V02S0401 +arc: S1_V02S0701 N1_V02S0601 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0301 V06S0003 +arc: W3_H06W0003 E3_H06W0303 +arc: A0 F7 +arc: A1 F7 +arc: A2 F7 +arc: A3 F7 +arc: A4 V02N0301 +arc: A5 E1_H02W0701 +arc: A6 V02S0101 +arc: A7 H00R0000 +arc: B0 V02N0101 +arc: B1 V02N0101 +arc: B2 V02N0101 +arc: B3 V02N0101 +arc: B4 E1_H02W0301 +arc: B5 H02E0101 +arc: B7 S1_V02N0701 +arc: C1 S1_V02N0601 +arc: C4 W1_H02E0401 +arc: C5 E1_H02W0401 +arc: C7 V02N0001 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 H02W0201 +arc: D5 V01N0001 +arc: D6 E1_H02W0001 +arc: D7 E1_H02W0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: M0 V00B0000 +arc: M1 H00R0100 +arc: M2 V00B0000 +arc: N1_V02N0301 F1 +arc: N3_V06N0303 F6 +arc: V00B0000 F4 +arc: W3_H06W0303 F6 +word: SLICEB.K0.INIT 0111011111111111 +word: SLICEB.K1.INIT 0111011111111111 +word: SLICEA.K0.INIT 0111011111111111 +word: SLICEA.K1.INIT 0000011100001111 +word: SLICEC.K0.INIT 1000001001000001 +word: SLICEC.K1.INIT 1000001001000001 +word: SLICED.K0.INIT 0101010100000000 +word: SLICED.K1.INIT 1011000000001011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R41C18:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0601 V02S0601 +arc: H00L0100 V02S0101 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 H06E0303 +arc: S1_V02S0601 H06E0303 +arc: V00T0000 W1_H02E0001 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0701 V01N0101 +arc: A0 F5 +arc: A1 F5 +arc: A2 F5 +arc: A3 F5 +arc: A5 V00T0000 +arc: A6 V02N0101 +arc: A7 W1_H02E0501 +arc: B1 H02W0101 +arc: B5 V02N0501 +arc: B6 S1_V02N0701 +arc: B7 V02S0501 +arc: C0 F6 +arc: C1 F6 +arc: C2 F6 +arc: C3 F6 +arc: C4 S1_V02N0201 +arc: C5 V00T0100 +arc: C6 V02N0001 +arc: C7 S1_V02N0001 +arc: D0 E1_H02W0201 +arc: D1 V02N0201 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 H00R0100 +arc: D5 V01N0001 +arc: D6 V02N0401 +arc: D7 E1_H01W0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: M0 V00B0100 +arc: M1 H00L0100 +arc: M2 V00B0100 +arc: N3_V06N0203 F4 +arc: V00B0100 F7 +arc: W3_H06W0203 F4 +word: SLICEA.K0.INIT 0101111111111111 +word: SLICEA.K1.INIT 0000000001111111 +word: SLICEC.K0.INIT 0000111100000000 +word: SLICEC.K1.INIT 1000001000000000 +word: SLICEB.K0.INIT 0101111111111111 +word: SLICEB.K1.INIT 0101111111111111 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 1000000000100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R41C19:PLC2 +arc: E1_H02E0601 V06S0303 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 N3_V06S0203 +arc: V00B0100 V02S0301 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0701 N1_V01S0100 +arc: A3 V00T0000 +arc: B2 V01N0001 +arc: B3 V01N0001 +arc: C3 W1_H02E0401 +arc: CE2 S1_V02N0601 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: D2 V02S0201 +arc: D3 H02E0201 +arc: E1_H01E0001 F3 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q4 +arc: H01W0100 Q6 +arc: M0 H02E0601 +arc: M4 V00T0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0201 F2 +arc: N3_V06N0103 F2 +arc: S1_V02S0401 Q6 +arc: V00T0000 Q0 +arc: W1_H02W0001 Q0 +arc: W1_H02W0101 F3 +arc: W1_H02W0401 Q6 +arc: W1_H02W0601 Q4 +arc: W3_H06W0103 F2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000011001100 +word: SLICEB.K1.INIT 1000010000100001 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 + +.tile R41C20:PLC2 +arc: H00L0100 H02W0301 +arc: H00R0100 V02N0501 +arc: N1_V02N0601 N3_V06S0303 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 H01E0001 +arc: B7 W1_H02E0301 +arc: C7 V02S0201 +arc: CE0 N1_V02S0201 +arc: CE1 H00R0100 +arc: CE2 H00L0100 +arc: CLK0 G_HPBX0100 +arc: F7 F7_SLICE +arc: M0 H02E0601 +arc: M2 V00B0000 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0401 Q4 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 F7 +arc: V00B0000 Q4 +arc: V00T0000 Q0 +arc: W3_H06W0203 F7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000110000001100 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R41C21:PLC2 +arc: W1_H02W0301 N1_V02S0301 + +.tile R41C22:PLC2 +arc: E1_H02E0301 S1_V02N0301 + +.tile R41C23:PLC2 +arc: A1 F5 +arc: A4 E1_H01W0000 +arc: A5 V02N0101 +arc: A7 F5 +arc: B4 V00B0100 +arc: B5 S1_V02N0701 +arc: C4 E1_H01E0101 +arc: C5 F4 +arc: CLK0 G_HPBX0100 +arc: D1 S1_V02N0201 +arc: D4 E1_H01W0100 +arc: D5 E1_H02W0001 +arc: D7 V01N0001 +arc: E1_H01E0101 Q1 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F5 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 Q7 +arc: V00B0100 Q7 +arc: V01S0000 Q1 +arc: W3_H06W0303 Q5 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111111110101010 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0101010100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R41C24:PLC2 +arc: A1 H02E0701 +arc: A5 H02E0501 +arc: A7 H02E0501 +arc: CLK0 G_HPBX0100 +arc: D1 V02N0001 +arc: D5 V01N0001 +arc: D7 S1_V02N0601 +arc: F1 F1_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 Q5 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: S1_V02S0301 Q1 +arc: S1_V02S0501 Q7 +arc: S1_V02S0701 Q5 +arc: V01S0000 Q7 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0101010100000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0101010100000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0101010100000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R41C25:PLC2 +arc: H00R0100 W1_H02E0701 +arc: S1_V02S0501 W1_H02E0501 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 S1_V02N0301 +arc: W1_H02W0301 S1_V02N0301 +arc: A1 W1_H02E0701 +arc: A2 E1_H01E0001 +arc: A3 W1_H02E0701 +arc: B1 V02N0101 +arc: B2 S1_V02N0101 +arc: C2 H00L0100 +arc: C5 V01N0101 +arc: CLK0 G_HPBX0100 +arc: D2 V01S0100 +arc: D3 V02N0001 +arc: D5 H00R0100 +arc: E1_H01E0001 Q5 +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q3 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: S1_V02S0101 Q1 +arc: S1_V02S0301 Q3 +arc: V01S0000 Q5 +arc: V01S0100 Q1 +arc: W1_H02W0001 F2 +word: SLICEB.K0.INIT 0000000000000001 +word: SLICEB.K1.INIT 0101010100000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000011110000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0100010001000100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R41C2:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0401 E1_H02W0401 +arc: V00T0000 H02W0201 +arc: A0 V02N0501 +arc: A2 H02E0501 +arc: A3 H02W0701 +arc: A5 N1_V01N0101 +arc: A6 E1_H01W0000 +arc: A7 Q7 +arc: B0 N1_V02S0301 +arc: B2 F3 +arc: B3 E1_H01W0100 +arc: B4 F3 +arc: B5 F3 +arc: B7 F3 +arc: C0 E1_H02W0401 +arc: C1 N1_V01S0100 +arc: C2 N1_V01N0001 +arc: C3 V02N0401 +arc: C4 Q4 +arc: C5 V00B0100 +arc: C7 F6 +arc: CE0 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D0 Q0 +arc: D1 V02S0201 +arc: D2 H00R0000 +arc: D3 V02N0001 +arc: D5 V00B0000 +arc: D6 V00B0000 +arc: D7 H01W0000 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F1 +arc: E1_H02E0101 F1 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 F1 +arc: H00R0000 F6 +arc: H01W0000 Q2 +arc: H01W0100 Q7 +arc: M4 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q2 +arc: N1_V02N0201 Q2 +arc: N1_V02N0301 F3 +arc: N1_V02N0501 Q7 +arc: N1_V02N0601 F6 +arc: V00B0000 Q4 +arc: V00B0100 Q7 +word: SLICEA.K0.INIT 1011111110000000 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 1111110011111100 +word: SLICEC.K1.INIT 1100110011111110 +word: SLICED.K0.INIT 0000000010101010 +word: SLICED.K1.INIT 0001001000000010 +word: SLICEB.K0.INIT 0010000100110000 +word: SLICEB.K1.INIT 0000000000001000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R41C3:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 H01E0001 +arc: E1_H02E0601 E1_H01W0000 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0201 V01N0001 +arc: V00T0000 H02W0001 +arc: V00T0100 E1_H02W0301 +arc: W1_H02W0701 V02S0701 +arc: A7 V02N0101 +arc: C1 V02N0601 +arc: CE0 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D1 H02E0001 +arc: D7 H02E0001 +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q2 +arc: LSR1 V00T0000 +arc: M2 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR1 +arc: S1_V02S0501 Q7 +arc: V01S0000 Q1 +arc: V01S0100 Q2 +arc: W1_H02W0201 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000011110000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R41C4:PLC2 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 W1_H02E0001 +arc: H00L0100 N1_V02S0101 +arc: H00R0100 V02S0501 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0501 W1_H02E0501 +arc: N1_V02N0601 E1_H01W0000 +arc: V00B0100 W1_H02E0501 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 S1_V02N0001 +arc: A0 V02S0501 +arc: A1 V02N0501 +arc: A2 W1_H02E0701 +arc: A3 W1_H02E0701 +arc: A5 N1_V02S0101 +arc: A6 W1_H02E0501 +arc: A7 Q7 +arc: B1 N1_V02S0101 +arc: B2 N1_V02S0101 +arc: B3 N1_V02S0101 +arc: B5 V02N0501 +arc: B7 V02N0501 +arc: C1 H02E0601 +arc: C2 N1_V01N0001 +arc: C3 H00L0000 +arc: C5 E1_H01E0101 +arc: C7 F6 +arc: CE0 W1_H02E0101 +arc: CE1 W1_H02E0101 +arc: CE2 W1_H02E0101 +arc: CE3 W1_H02E0101 +arc: CLK0 G_HPBX0100 +arc: D0 V00B0100 +arc: D1 F0 +arc: D2 V00T0100 +arc: D3 V01S0100 +arc: D5 F0 +arc: D6 H00R0100 +arc: D7 H00L0100 +arc: E1_H01E0101 Q5 +arc: E1_H02E0201 Q2 +arc: E3_H06E0003 Q3 +arc: E3_H06E0103 Q1 +arc: E3_H06E0203 Q7 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q1 +arc: H01W0100 F6 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: V01S0100 Q3 +arc: W1_H02W0401 F6 +word: SLICED.K0.INIT 1010101000000000 +word: SLICED.K1.INIT 1010101011001010 +word: SLICEA.K0.INIT 0000000010101010 +word: SLICEA.K1.INIT 1011100011110000 +word: SLICEB.K0.INIT 1111001011010000 +word: SLICEB.K1.INIT 1111011110000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1110010011110000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R41C5:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 V06S0203 +arc: H00L0100 E1_H02W0301 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 N1_V01S0100 +arc: N1_V02N0301 N3_V06S0003 +arc: S1_V02S0201 N1_V02S0701 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 V02S0201 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 E3_H06W0003 +arc: A5 H02W0701 +arc: A6 H02E0701 +arc: A7 F5 +arc: B5 S1_V02N0701 +arc: B6 V01S0000 +arc: B7 V01S0000 +arc: C5 V02N0201 +arc: C6 V02N0201 +arc: C7 E1_H02W0601 +arc: CE0 H00L0100 +arc: CE1 W1_H02E0101 +arc: CLK0 G_HPBX0100 +arc: D5 E1_H02W0201 +arc: D6 E1_H02W0001 +arc: D7 V02N0401 +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F6 +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q0 +arc: N3_V06N0003 Q0 +arc: V01S0000 Q2 +arc: V01S0100 F7 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 1000001001000001 +word: SLICED.K1.INIT 0010000010100000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001001101011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R41C6:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 V06S0203 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0401 N3_V06S0203 +arc: S1_V02S0401 W1_H02E0401 +arc: V00B0000 V02S0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0701 N3_V06S0203 +arc: A0 H02E0701 +arc: A1 H02E0701 +arc: A2 V01N0101 +arc: A3 H02W0501 +arc: A5 N1_V01N0101 +arc: A6 H02W0501 +arc: A7 F5 +arc: B0 V02N0101 +arc: B1 V02N0301 +arc: B3 H02E0101 +arc: B5 N1_V02S0701 +arc: B6 V02N0501 +arc: B7 E1_H02W0101 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C3 S1_V02N0601 +arc: C5 E1_H02W0401 +arc: C6 H02E0401 +arc: C7 F6 +arc: D0 F2 +arc: D1 F2 +arc: D2 H02E0201 +arc: D3 V02S0001 +arc: D5 E1_H01W0100 +arc: D6 V00B0000 +arc: D7 E1_H02W0201 +arc: E1_H01E0001 F3 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F0 +arc: M0 V00B0100 +arc: V01S0000 F7 +word: SLICED.K0.INIT 0000011101110111 +word: SLICED.K1.INIT 0010000010100000 +word: SLICEB.K0.INIT 0101010110101010 +word: SLICEB.K1.INIT 0001001101011111 +word: SLICEA.K0.INIT 0000000000001001 +word: SLICEA.K1.INIT 0000000010010000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000011101110111 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R41C7:PLC2 +arc: H00L0100 V02S0301 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0601 E1_H02W0601 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0401 H02E0401 +arc: V00B0100 E1_H02W0701 +arc: V00T0100 V02N0701 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0501 V06S0303 +arc: W1_H02W0601 H01E0001 +arc: CE0 H00L0100 +arc: CE1 E1_H02W0101 +arc: CE2 E1_H02W0101 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0100 +arc: E1_H01E0101 Q0 +arc: H01W0000 Q4 +arc: H01W0100 Q2 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N3_V06N0003 Q0 +arc: V01S0000 Q4 +arc: W1_H02W0001 Q2 +arc: W1_H02W0401 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R41C8:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0601 N3_V06S0303 +arc: N3_V06N0303 E3_H06W0303 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0501 E1_H01W0100 +arc: S1_V02S0701 E1_H01W0100 +arc: V00B0100 V02S0101 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V02N0401 +arc: S1_V02S0001 W3_H06E0003 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A4 V02N0101 +arc: A5 E1_H02W0501 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 H02W0301 +arc: B5 H00R0000 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 E1_H02W0601 +arc: C5 V02S0001 +arc: CE3 V02N0601 +arc: CLK1 G_HPBX0100 +arc: D0 H02W0201 +arc: D1 H02W0201 +arc: D2 H02W0201 +arc: D3 H02W0201 +arc: D4 E1_H02W0001 +arc: D5 W1_H02E0201 +arc: E1_H01E0001 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: LSR1 V00B0100 +arc: M6 V00T0100 +arc: MUXCLK0 CLK1 +arc: MUXCLK1 CLK1 +arc: MUXCLK3 CLK1 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 Q3 +arc: N3_V06N0103 Q2 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R41C9:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0601 V01N0001 +arc: H00R0100 V02S0501 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 H02W0001 +arc: V00B0100 S1_V02N0101 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 E3_H06W0303 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 H00L0000 +arc: A2 V01N0101 +arc: A3 E1_H01E0001 +arc: A5 V02N0301 +arc: A6 H00L0000 +arc: A7 H00R0000 +arc: B1 V01N0001 +arc: B2 H00L0000 +arc: B3 H00R0000 +arc: B5 H00R0000 +arc: B6 N1_V01S0000 +arc: B7 V01S0000 +arc: C0 V02S0601 +arc: C1 H00L0000 +arc: C2 H00R0100 +arc: C3 V02N0401 +arc: C4 Q4 +arc: C5 V02N0001 +arc: C6 N1_V02S0201 +arc: C7 F6 +arc: CLK0 G_HPBX0100 +arc: D0 N1_V02S0201 +arc: D1 H02W0001 +arc: D2 H02W0001 +arc: D3 N1_V02S0001 +arc: D4 V00B0000 +arc: D5 F2 +arc: D6 H00R0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q4 +arc: E1_H02E0001 Q0 +arc: E1_H02E0401 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H00R0000 Q4 +arc: H01W0000 F4 +arc: H01W0100 F7 +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q0 +arc: N3_V06N0003 F3 +arc: N3_V06N0103 F1 +arc: N3_V06N0303 F5 +arc: V00B0000 F6 +arc: V01S0000 Q7 +arc: W1_H02W0201 F0 +arc: W1_H02W0501 F7 +word: SLICEB.K0.INIT 0101000011010100 +word: SLICEB.K1.INIT 1001011000000000 +word: SLICEA.K0.INIT 1010101010100101 +word: SLICEA.K1.INIT 0011001111000011 +word: SLICEC.K0.INIT 0000111111110000 +word: SLICEC.K1.INIT 1001101001011001 +word: SLICED.K0.INIT 0000001000000000 +word: SLICED.K1.INIT 0110110001101100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.D1MUX 1 + +.tile R42C10:PLC2 +arc: H00R0000 V02N0601 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0003 E3_H06W0003 +arc: N3_V06N0103 E3_H06W0103 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0401 V06S0203 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0601 W3_H06E0303 +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0303 W3_H06E0303 +arc: A4 V00T0000 +arc: A5 S1_V02N0101 +arc: A7 N1_V02S0301 +arc: B4 V02N0501 +arc: B5 V02S0501 +arc: B7 N1_V01S0000 +arc: C4 H02W0401 +arc: C5 F4 +arc: C7 H02E0401 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D4 V02N0401 +arc: D5 W1_H02E0201 +arc: D7 H00R0100 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q7 +arc: H01W0000 Q7 +arc: LSR0 H02E0501 +arc: LSR1 H02E0501 +arc: M2 H02E0601 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q7 +arc: N1_V02N0501 Q7 +arc: V00T0000 Q2 +arc: W3_H06W0303 F5 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0011000111110101 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0111111110000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R42C11:PLC2 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 W1_H02E0201 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0501 +arc: V00B0000 V02S0001 +arc: V00T0000 N1_V02S0601 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 V00B0000 +arc: A5 V02S0101 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0301 +arc: B2 H00R0000 +arc: B3 H00R0000 +arc: B4 H02W0301 +arc: B5 H00L0000 +arc: C0 V02S0601 +arc: C1 V02S0601 +arc: C2 V02S0601 +arc: C3 V02S0601 +arc: C4 H02W0601 +arc: C5 E1_H02W0401 +arc: CE3 S1_V02N0601 +arc: CLK1 G_HPBX0100 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: E1_H01E0001 Q1 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q0 +arc: E1_H02E0301 Q3 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: LSR1 V00T0000 +arc: M6 H02W0401 +arc: MUXCLK0 CLK1 +arc: MUXCLK1 CLK1 +arc: MUXCLK3 CLK1 +arc: W1_H02W0401 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R42C12:PLC2 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 N1_V01S0000 +arc: V00T0000 H02E0201 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 V02S0701 +arc: A0 H01E0001 +arc: A1 V01N0101 +arc: A2 V02N0701 +arc: A3 V02S0501 +arc: A4 H02E0501 +arc: A5 V02N0301 +arc: A6 N1_V01N0101 +arc: A7 V02N0101 +arc: B0 H02E0301 +arc: B1 V00T0000 +arc: B2 H00R0100 +arc: B3 V01N0001 +arc: B4 V00B0100 +arc: B5 V00B0100 +arc: B6 V02N0501 +arc: C0 H00R0100 +arc: C1 F6 +arc: C2 H02E0601 +arc: C3 F4 +arc: C4 V02S0201 +arc: C5 V02N0001 +arc: C6 E1_H01E0101 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0100 +arc: D0 V00B0100 +arc: D1 F0 +arc: D2 V00B0100 +arc: D3 F2 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E1_H01E0101 Q7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q7 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q5 +arc: S1_V02S0101 F3 +arc: S1_V02S0301 F1 +arc: V00B0100 Q5 +arc: V01S0000 Q5 +arc: V01S0100 Q7 +word: SLICEC.K0.INIT 1111111100011101 +word: SLICEC.K1.INIT 0100011001001100 +word: SLICED.K0.INIT 1100010011001100 +word: SLICED.K1.INIT 0101010100001010 +word: SLICEA.K0.INIT 0011111101011111 +word: SLICEA.K1.INIT 0111000000000000 +word: SLICEB.K0.INIT 0101010100010101 +word: SLICEB.K1.INIT 0111000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R42C13:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0301 V02N0301 +arc: E3_H06E0103 N3_V06S0103 +arc: E3_H06E0303 N3_V06S0303 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 H06E0003 +arc: S1_V02S0601 H06E0303 +arc: V00B0000 V02N0001 +arc: V00B0100 N1_V02S0101 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0301 N1_V01S0100 +arc: W1_H02W0401 E1_H01W0000 +arc: A3 V02S0701 +arc: B3 Q3 +arc: CLK0 G_HPBX0100 +arc: D3 V00B0100 +arc: F3 F3_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q3 +arc: LSR0 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q3 +arc: V01S0000 Q3 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0110011011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R42C14:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 N3_V06S0103 +arc: E3_H06E0003 V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0401 N1_V02S0101 +arc: V00B0100 V02S0301 +arc: H01W0000 W3_H06E0103 +arc: A1 F5 +arc: A3 V02N0501 +arc: A4 N1_V01S0100 +arc: A5 V02N0101 +arc: A6 N1_V02S0101 +arc: B1 V02S0101 +arc: B2 F3 +arc: B4 H02W0101 +arc: B5 H02W0101 +arc: B6 N1_V01S0000 +arc: C1 S1_V02N0401 +arc: C2 S1_V02N0601 +arc: C3 V02N0601 +arc: C4 S1_V02N0201 +arc: C6 V02N0201 +arc: CLK0 G_HPBX0100 +arc: D1 V01S0100 +arc: D3 H02W0201 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: D6 V02S0401 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 F3 +arc: LSR1 H02E0301 +arc: M0 V00B0100 +arc: M6 V00T0000 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V02N0201 F2 +arc: V00B0000 Q6 +arc: V00T0000 F0 +arc: V01S0000 F4 +arc: V01S0100 Q6 +word: SLICED.K0.INIT 1110101110111110 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000001100000011 +word: SLICEB.K1.INIT 1010000000000000 +word: SLICEC.K0.INIT 0000111101011011 +word: SLICEC.K1.INIT 0000000000010001 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000001100001110 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R42C15:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0501 N3_V06S0303 +arc: E1_H02E0701 E1_H01W0100 +arc: E3_H06E0303 N3_V06S0303 +arc: H00L0100 V02N0101 +arc: H00R0000 N1_V02S0401 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 N3_V06S0303 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 H02E0001 +arc: V00B0000 V02N0201 +arc: V00B0100 V02S0301 +arc: W1_H02W0201 V01N0001 +arc: A6 N1_V01S0100 +arc: A7 N1_V01S0100 +arc: B4 N1_V01S0000 +arc: B5 N1_V01S0000 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 V02N0001 +arc: C7 V02N0001 +arc: CLK0 G_HPBX0100 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D6 H02E0001 +arc: D7 H02E0001 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q3 +arc: LSR1 H02W0301 +arc: M0 V00B0000 +arc: M1 H00L0100 +arc: M2 V00B0000 +arc: M3 H00R0000 +arc: M4 V00B0000 +arc: M5 H00L0100 +arc: M6 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: W1_H02W0101 Q3 +word: SLICEA.K0.INIT 1111111100000000 +word: SLICEA.K1.INIT 1111111100000000 +word: SLICED.K0.INIT 0000010100000000 +word: SLICED.K1.INIT 1111101011111111 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1111111100000000 +word: SLICEC.K0.INIT 0000000011000000 +word: SLICEC.K1.INIT 1111111100111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.A1MUX 1 + +.tile R42C16:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 N1_V01S0000 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 H02E0501 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 N1_V02S0501 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 N3_V06S0203 +arc: A3 V00T0000 +arc: A7 H00L0000 +arc: B1 H01W0100 +arc: B7 V00B0000 +arc: C0 E1_H02W0601 +arc: C1 V02S0401 +arc: C3 V02N0401 +arc: C7 V00T0000 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D1 V02S0001 +arc: D2 H02E0001 +arc: D3 H00R0000 +arc: D7 H02E0201 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q2 +arc: E1_H02E0201 Q2 +arc: E3_H06E0103 Q2 +arc: E3_H06E0203 Q4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0100 Q0 +arc: M0 V00T0100 +arc: M2 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 Q0 +arc: N1_V02N0401 Q4 +arc: N1_V02N0701 F7 +arc: N3_V06N0003 Q0 +arc: N3_V06N0103 Q2 +arc: V00B0000 Q4 +arc: V00T0000 Q2 +arc: V01S0100 Q4 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 1010101000001111 +word: SLICEA.K0.INIT 1111000011110000 +word: SLICEA.K1.INIT 1100000011001111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1000001011000011 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 + +.tile R42C17:PLC2 +arc: E1_H02E0401 N3_V06S0203 +arc: H00R0000 E1_H02W0601 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0701 V01N0101 +arc: S1_V02S0201 H02E0201 +arc: S1_V02S0501 W1_H02E0501 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02N0401 +arc: A1 V02S0701 +arc: A2 V00B0000 +arc: A6 N1_V01N0101 +arc: A7 V02N0301 +arc: B1 V00B0000 +arc: B2 E1_H01W0100 +arc: B7 V02S0501 +arc: C1 H02W0401 +arc: C2 V02S0401 +arc: C7 H02E0601 +arc: CLK0 G_HPBX0100 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D6 V02N0401 +arc: D7 V01N0001 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 Q4 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: M0 H01E0001 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: MUXCLK2 CLK0 +arc: N1_V02N0101 F1 +arc: N1_V02N0601 Q4 +arc: V00B0000 Q4 +arc: V01S0000 F7 +arc: V01S0100 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1010111100100011 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1101110100001101 +word: SLICED.K0.INIT 1010101001010101 +word: SLICED.K1.INIT 1000000000100000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 + +.tile R42C18:PLC2 +arc: E1_H02E0101 V06S0103 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0401 H02E0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0601 H06E0303 +arc: V00B0100 W1_H02E0501 +arc: V00T0000 V02S0401 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0601 N3_V06S0303 +arc: A1 V02S0501 +arc: B1 V00B0000 +arc: C1 E1_H01W0000 +arc: CLK0 G_HPBX0100 +arc: D1 W1_H02E0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: H00R0000 Q6 +arc: H01W0000 F1 +arc: H01W0100 Q4 +arc: M0 V00B0100 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M4 V00T0000 +arc: M6 V00T0100 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q4 +arc: V00B0000 Q4 +arc: V01S0100 Q4 +arc: W1_H02W0401 Q4 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1000010010100101 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R42C19:PLC2 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0701 H06E0203 +arc: V00T0000 V02S0401 +arc: V00T0100 H02E0101 +arc: V01S0000 N3_V06S0103 +arc: E1_H02E0501 W3_H06E0303 +arc: CE2 V02N0601 +arc: CLK0 G_HPBX0100 +arc: H01W0000 Q2 +arc: H01W0100 Q6 +arc: M2 V00B0000 +arc: M4 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 Q4 +arc: N1_V02N0401 Q4 +arc: V00B0000 Q4 +arc: V01S0100 Q6 +arc: W1_H02W0601 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R42C20:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: N1_V02N0501 H02E0501 +arc: E1_H02E0001 W3_H06E0003 + +.tile R42C21:PLC2 +arc: N1_V02N0301 H02E0301 + +.tile R42C22:PLC2 +arc: E1_H02E0001 W1_H02E0001 +arc: H00R0100 H02W0501 +arc: V00B0100 V02N0301 +arc: N3_V06N0103 W3_H06E0103 +arc: A1 H02W0501 +arc: A3 H02W0501 +arc: A4 N1_V01N0101 +arc: B1 E1_H01W0100 +arc: B4 V01S0000 +arc: B5 E1_H02W0301 +arc: C3 E1_H01W0000 +arc: C4 V00T0100 +arc: C7 E1_H02W0401 +arc: CLK0 G_HPBX0100 +arc: D4 H01W0000 +arc: D5 H00R0100 +arc: D7 H00R0100 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q1 +arc: E1_H02E0501 Q5 +arc: E1_H02E0701 Q7 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q7 +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q5 +arc: V00T0100 Q3 +arc: V01S0000 Q1 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEC.K1.INIT 1111111111001100 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1111111111110000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0100010001000100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0101000001010000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R42C23:PLC2 +arc: N1_V02N0101 H01E0101 +arc: S1_V02S0001 E1_H01W0000 +arc: V00T0000 H02E0001 +arc: W1_H02W0501 V02S0501 +arc: A2 H02E0501 +arc: A3 H02E0701 +arc: B0 V00T0000 +arc: B4 H02E0301 +arc: B5 H02E0101 +arc: B6 V02S0701 +arc: B7 N1_V01S0000 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 F4 +arc: N1_V01N0001 F6 +arc: V01S0000 F7 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEB.K1.INIT 0101010101011010 +word: SLICEC.K0.INIT 0011001100111100 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 0011001100111100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R42C24:PLC2 +arc: V00B0000 V02N0201 +arc: W1_H02W0301 H01E0101 +arc: W1_H02W0401 H01E0001 +arc: A1 V02S0701 +arc: A3 V02N0701 +arc: A4 V02N0101 +arc: A5 V02N0301 +arc: B0 V02S0301 +arc: B2 V01N0001 +arc: B6 V00B0000 +arc: B7 N1_V01S0000 +arc: E1_H01E0001 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F3 +arc: N1_V01N0001 F1 +arc: N1_V02N0001 F0 +arc: S1_V02S0201 F2 +arc: S1_V02S0701 F5 +arc: V01S0000 F7 +arc: V01S0100 F4 +word: SLICEA.K0.INIT 0011001100111100 +word: SLICEA.K1.INIT 0101010101011010 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0101010101011010 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0101010101011010 +word: SLICED.K0.INIT 0011001100111100 +word: SLICED.K1.INIT 0011001100111100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R42C25:PLC2 +arc: S1_V02S0401 H01E0001 +arc: A0 V02N0701 +arc: A1 V01N0101 +arc: A4 V02N0101 +arc: B2 V02S0301 +arc: B3 V02S0101 +arc: B5 N1_V01S0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: N1_V01N0101 F5 +arc: N1_V02N0001 F2 +arc: N1_V02N0101 F3 +arc: S1_V02S0001 F0 +arc: V01S0000 F1 +arc: V01S0100 F4 +word: SLICEC.K0.INIT 0101010101011010 +word: SLICEC.K1.INIT 0011001100111100 +word: SLICEA.K0.INIT 0101010101011010 +word: SLICEA.K1.INIT 0101010101011010 +word: SLICEB.K0.INIT 0011001100111100 +word: SLICEB.K1.INIT 0011001100111100 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000001110 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R42C2:PLC2 +arc: E1_H02E0501 S1_V02N0501 +arc: N1_V02N0001 S1_V02N0501 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 S1_V02N0501 + +.tile R42C3:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 N1_V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0501 H02E0501 +arc: N3_V06N0003 H06W0003 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0401 H02W0401 +arc: V00B0000 V02S0201 +arc: A3 V02N0501 +arc: A4 V02N0101 +arc: A7 S1_V02N0101 +arc: B0 V00B0000 +arc: B2 V01N0001 +arc: B5 S1_V02N0701 +arc: B6 N1_V01S0000 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: N1_V02N0601 F6 +arc: S1_V02S0201 F2 +arc: S1_V02S0501 F5 +arc: S1_V02S0701 F7 +arc: V01S0000 F4 +arc: V01S0100 F3 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R42C4:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0501 V06S0303 +arc: E1_H02E0601 E3_H06W0303 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0203 H06W0203 +arc: A0 H02E0501 +arc: A6 V02N0301 +arc: A7 H02E0701 +arc: B6 H02E0101 +arc: B7 H02E0301 +arc: C6 H02E0401 +arc: C7 F6 +arc: CLK0 G_HPBX0100 +arc: D6 H02E0001 +arc: D7 H00R0100 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0601 Q6 +arc: W1_H02W0401 F6 +word: SLICED.K0.INIT 0000000000100000 +word: SLICED.K1.INIT 1010101010100010 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R42C5:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0701 V06S0203 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 N1_V02S0301 +arc: N1_V02N0201 H02E0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 H06W0203 +arc: S1_V02S0301 N3_V06S0003 +arc: S1_V02S0601 N1_V02S0301 +arc: V00B0000 V02S0201 +arc: V00T0000 N1_V02S0401 +arc: V00T0100 S1_V02N0501 +arc: A1 H02W0501 +arc: A7 H02W0501 +arc: C1 N1_V01S0100 +arc: C7 H02E0601 +arc: CE1 H00L0100 +arc: CE2 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D1 V02N0001 +arc: D7 V00B0000 +arc: F1 F1_SLICE +arc: F7 F7_SLICE +arc: M2 V00T0000 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0601 Q4 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 Q7 +arc: V01S0100 Q2 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000111110101111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000101011111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R42C6:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0401 V02S0401 +arc: H00R0100 W1_H02E0501 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 N3_V06S0303 +arc: S1_V02S0001 H02E0001 +arc: S1_V02S0201 E1_H02W0201 +arc: V00B0000 H02W0401 +arc: V00T0000 H02E0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0501 N1_V02S0501 +arc: B7 V02N0501 +arc: C0 H02E0401 +arc: C1 N1_V02S0601 +arc: C7 H02W0401 +arc: CE1 S1_V02N0201 +arc: CE2 S1_V02N0601 +arc: CLK0 G_HPBX0100 +arc: D0 S1_V02N0001 +arc: D1 V02N0201 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q2 +arc: M0 V00B0000 +arc: M2 V00T0000 +arc: M4 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0201 Q2 +arc: N3_V06N0203 Q7 +arc: V01S0000 Q4 +arc: W3_H06W0003 Q0 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000001111 +word: SLICEA.K1.INIT 1111111100001111 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0011001111110011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 + +.tile R42C7:PLC2 +arc: E1_H02E0001 V02S0001 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 H02W0601 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 H02W0701 +arc: S1_V02S0301 H02W0301 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 H02W0401 +arc: V00B0100 W1_H02E0701 +arc: V00T0000 V02S0401 +arc: W1_H02W0401 N1_V02S0401 +arc: A6 V02N0301 +arc: A7 N1_V01N0101 +arc: B6 V02N0501 +arc: B7 V00B0100 +arc: C6 V02N0201 +arc: C7 F6 +arc: CE0 H00R0000 +arc: CE1 H00R0000 +arc: CE2 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D6 V01N0001 +arc: D7 H02E0001 +arc: E1_H01E0101 Q0 +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q4 +arc: M0 V00T0000 +arc: M2 V00B0000 +arc: M4 H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V01S0100 Q2 +arc: W3_H06W0203 Q7 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0001001101011111 +word: SLICED.K1.INIT 0000000110101011 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R42C8:PLC2 +arc: E1_H02E0101 V01N0101 +arc: E3_H06E0103 V06S0103 +arc: H00L0000 V02S0001 +arc: H00R0000 H02W0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 V01N0001 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0401 E1_H02W0401 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02W0201 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 V06S0203 +arc: W3_H06W0203 N3_V06S0203 +arc: A0 V02S0701 +arc: A1 V02S0501 +arc: A2 V02S0701 +arc: A3 V02S0501 +arc: A4 V00T0000 +arc: A5 V02S0101 +arc: A6 E1_H01W0000 +arc: A7 V00T0100 +arc: B0 H00R0100 +arc: B1 H00R0100 +arc: B2 H00R0100 +arc: B3 H00R0100 +arc: B4 H00R0000 +arc: B5 H00L0000 +arc: B6 H01E0101 +arc: B7 V00B0000 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 H02W0401 +arc: C5 W1_H02E0401 +arc: C6 V02N0201 +arc: C7 E1_H02W0401 +arc: CLK1 G_HPBX0100 +arc: D0 V02S0201 +arc: D1 V02S0201 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: D4 E1_H02W0001 +arc: D5 H02E0001 +arc: D6 V02N0601 +arc: D7 E1_H02W0201 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR1 V00B0100 +arc: MUXCLK0 CLK1 +arc: MUXCLK1 CLK1 +arc: N3_V06N0203 F7 +arc: S1_V02S0001 Q0 +arc: V00B0000 F6 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0100110001011111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEA.MODE DPRAM +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.WREMUX WRE +enum: CLK1.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE RAMW +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE DPRAM +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK1.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R42C9:PLC2 +arc: E1_H02E0201 N1_V02S0201 +arc: E1_H02E0501 V02N0501 +arc: E1_H02E0601 S1_V02N0601 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: S1_V02S0201 N1_V02S0201 +arc: V00B0100 V02N0101 +arc: V00T0100 S1_V02N0701 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0701 N1_V02S0701 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: B4 H02W0301 +arc: B5 N1_V02S0501 +arc: C1 H00L0000 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 V02S0001 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0100 +arc: D1 N1_V01S0000 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 V00B0000 +arc: D5 V00B0000 +arc: E1_H02E0301 F1 +arc: E1_H02E0401 Q4 +arc: E1_H02E0701 F5 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q2 +arc: H01W0000 Q6 +arc: H01W0100 Q2 +arc: LSR1 V00B0100 +arc: M2 V00T0000 +arc: M6 V00T0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q4 +arc: N1_V02N0301 F1 +arc: V00B0000 Q4 +arc: V00T0000 Q2 +arc: W1_H02W0201 Q2 +arc: W1_H02W0601 Q4 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 1000000000000000 +word: SLICEB.K1.INIT 0111111111111111 +word: SLICEC.K0.INIT 0011111111000000 +word: SLICEC.K1.INIT 1100110000110011 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000111111110000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R43C10:PLC2 +arc: N1_V02N0401 H02W0401 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H02W0601 +arc: V00B0000 V02N0001 +arc: V00B0100 H02E0701 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 E1_H01W0100 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0201 Q0 +arc: E3_H06E0003 Q0 +arc: H01W0100 Q0 +arc: LSR0 V00B0000 +arc: M0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q0 +arc: W1_H02W0001 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R43C11:PLC2 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0401 H02W0401 +arc: V00T0000 W1_H02E0201 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0401 N3_V06S0203 +arc: W1_H02W0601 N3_V06S0303 +arc: H01W0100 W3_H06E0303 +arc: CE0 V02N0201 +arc: CLK0 G_HPBX0100 +arc: H01W0000 Q0 +arc: M0 V00T0000 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R43C12:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 W1_H02E0201 +arc: H00L0100 V02S0301 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 E1_H01W0100 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0701 E1_H01W0100 +arc: V00T0000 H02W0001 +arc: W1_H02W0401 V02N0401 +arc: A1 H00L0100 +arc: A3 V00T0000 +arc: A5 Q5 +arc: A6 N1_V01S0100 +arc: B0 V01N0001 +arc: B1 V02S0101 +arc: B3 E1_H01W0100 +arc: B5 H00L0000 +arc: B6 N1_V01S0000 +arc: B7 V00B0000 +arc: C0 H02W0401 +arc: C1 H02W0401 +arc: C2 N1_V01S0100 +arc: C3 H00R0100 +arc: C5 F6 +arc: C7 H02W0601 +arc: CLK0 G_HPBX0100 +arc: D0 S1_V02N0001 +arc: D1 F0 +arc: D2 N1_V01S0000 +arc: D3 F2 +arc: D5 E1_H01W0100 +arc: D7 H00R0100 +arc: E1_H01E0001 F3 +arc: E1_H02E0501 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: H00R0100 Q5 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 F2 +arc: N1_V02N0001 F0 +arc: N1_V02N0501 Q5 +arc: N1_V02N0701 Q5 +arc: S1_V02S0501 Q5 +arc: V00B0000 F6 +arc: V01S0000 F1 +arc: V01S0100 F2 +word: SLICED.K0.INIT 1000100010001000 +word: SLICED.K1.INIT 1100000000000000 +word: SLICEB.K0.INIT 0000000000001111 +word: SLICEB.K1.INIT 1010001010101010 +word: SLICEA.K0.INIT 0000111100001100 +word: SLICEA.K1.INIT 0000000000011111 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0001001010101010 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 + +.tile R43C13:PLC2 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 H06E0003 +arc: N3_V06N0003 H06E0003 +arc: A0 H02E0501 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 V00T0100 +arc: A6 H02E0501 +arc: A7 H02E0501 +arc: B0 V00B0000 +arc: B3 Q3 +arc: B4 V00B0100 +arc: B5 V00B0100 +arc: B6 V02N0501 +arc: B7 V00B0000 +arc: C0 F4 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C4 E1_H01E0101 +arc: C5 F4 +arc: C6 F4 +arc: C7 V02S0001 +arc: CLK0 G_HPBX0100 +arc: D0 H02E0001 +arc: D2 H02W0001 +arc: D3 H02W0001 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 V00B0000 +arc: D7 S1_V02N0401 +arc: E1_H01E0101 Q2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: H01W0100 F4 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M0 H01E0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q5 +arc: N1_V02N0501 F7 +arc: N1_V02N0701 F7 +arc: S1_V02S0401 F4 +arc: V00B0000 Q6 +arc: V00B0100 Q5 +arc: V00T0000 Q2 +arc: V00T0100 Q3 +arc: W1_H02W0001 Q0 +arc: W1_H02W0401 Q6 +arc: W1_H02W0601 F4 +word: SLICEB.K0.INIT 0101101010101010 +word: SLICEB.K1.INIT 0110100011001100 +word: SLICEC.K0.INIT 0000001000000000 +word: SLICEC.K1.INIT 0000001100001100 +word: SLICEA.K0.INIT 1111100010001000 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICED.K0.INIT 1101010111000000 +word: SLICED.K1.INIT 0000000000000111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ + +.tile R43C14:PLC2 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0601 N1_V02S0601 +arc: H00R0000 V02S0401 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 E1_H01W0000 +arc: N1_V02N0701 N1_V01S0100 +arc: V00T0000 H02W0001 +arc: W1_H02W0001 N1_V02S0001 +arc: B2 H02W0301 +arc: B3 H02W0301 +arc: C2 H02W0601 +arc: C3 H02W0601 +arc: CLK0 G_HPBX0100 +arc: D0 N1_V01S0000 +arc: D1 N1_V01S0000 +arc: D2 V02S0201 +arc: D3 V02S0201 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: LSR0 E1_H02W0301 +arc: M0 V00T0000 +arc: M1 H00R0000 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q1 +arc: V01S0000 Q1 +word: SLICEB.K0.INIT 1100001111001100 +word: SLICEB.K1.INIT 1100110000111100 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICEA.K1.INIT 0000000011111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 + +.tile R43C15:PLC2 +arc: H00R0000 N1_V02S0401 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 E1_H01E0001 +arc: A1 E1_H01E0001 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B3 Q3 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C2 N1_V02S0601 +arc: C3 N1_V02S0401 +arc: CLK0 G_HPBX0100 +arc: D0 H00R0000 +arc: D1 H00R0000 +arc: D2 V02S0001 +arc: D3 H02E0201 +arc: E1_H01E0001 Q2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: H01W0000 Q2 +arc: H01W0100 Q0 +arc: LSR1 H02W0301 +arc: M0 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 Q3 +arc: N1_V02N0001 Q2 +arc: N1_V02N0101 Q3 +arc: N1_V02N0201 Q0 +arc: V00T0000 Q0 +arc: V00T0100 Q3 +arc: W1_H02W0001 Q2 +arc: W1_H02W0301 Q3 +word: SLICEB.K0.INIT 1010010101011010 +word: SLICEB.K1.INIT 1100100101101100 +word: SLICEA.K0.INIT 1100110010011100 +word: SLICEA.K1.INIT 1100011011001100 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R43C16:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V02S0501 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0301 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 +arc: W1_H02W0301 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 + +.tile R43C17:PLC2 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 V02S0501 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 N1_V01S0100 +arc: V00B0000 V02S0201 +arc: V00B0100 E1_H02W0701 +arc: A5 H02E0501 +arc: B4 H02E0101 +arc: C4 V00T0000 +arc: C5 H02W0601 +arc: CE1 H00R0100 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D4 V02N0601 +arc: D5 S1_V02N0601 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M0 V00B0100 +arc: M2 V00B0000 +arc: M6 H02E0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q0 +arc: N1_V02N0001 Q0 +arc: N1_V02N0401 Q6 +arc: N3_V06N0203 F4 +arc: N3_V06N0303 F5 +arc: V00T0000 Q2 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1111000011001100 +word: SLICEC.K1.INIT 1111010110100000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R43C18:PLC2 +arc: E3_H06E0003 S3_V06N0003 +arc: H00R0000 H02W0401 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0701 N1_V01S0100 +arc: V00T0000 N1_V02S0601 +arc: V00T0100 S1_V02N0701 +arc: CE1 H00R0000 +arc: CE3 V02S0601 +arc: CLK0 G_HPBX0100 +arc: H01W0100 Q2 +arc: M2 V00T0100 +arc: M6 V00T0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0001 Q2 +arc: V01S0100 Q2 +arc: W1_H02W0601 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R43C19:PLC2 +arc: N1_V02N0601 N1_V01S0000 +arc: N3_V06N0003 H06E0003 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0701 N1_V01S0100 + +.tile R43C22:PLC2 +arc: E1_H02E0301 W3_H06E0003 +arc: N1_V02N0301 W3_H06E0003 +arc: N3_V06N0003 W3_H06E0003 +arc: E3_H06E0003 W3_H06E0003 + +.tile R43C23:PLC2 +arc: E1_H02E0501 N1_V02S0501 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0701 E1_H01W0100 +arc: C5 V02S0001 +arc: CLK0 G_HPBX0100 +arc: D5 H00R0100 +arc: E1_H02E0701 Q5 +arc: F5 F5_SLICE +arc: LSR1 H02E0301 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 + +.tile R43C24:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 H02E0701 +arc: N3_V06N0103 S3_V06N0003 +arc: V00B0000 V02S0201 +arc: V00B0100 H02E0501 +arc: N3_V06N0003 W3_H06E0003 +arc: A3 V02S0701 +arc: A5 E1_H01W0000 +arc: A6 H02E0701 +arc: A7 H02E0501 +arc: B5 N1_V02S0501 +arc: B6 V01S0000 +arc: C1 N1_V01S0100 +arc: C5 E1_H02W0601 +arc: C6 V00T0100 +arc: CLK0 G_HPBX0100 +arc: D1 V00B0100 +arc: D3 V00B0100 +arc: D5 E1_H01W0100 +arc: D6 H00R0100 +arc: D7 V00B0000 +arc: E1_H01E0101 F6 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q7 +arc: H01W0100 F4 +arc: LSR0 W1_H02E0301 +arc: LSR1 W1_H02E0301 +arc: M4 E1_H01E0101 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V02N0101 Q1 +arc: N1_V02N0301 Q3 +arc: V00T0100 Q1 +arc: V01S0000 Q3 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000001 +word: SLICED.K0.INIT 0000000000000001 +word: SLICED.K1.INIT 0101010100000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000011110000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000010101010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R43C25:PLC2 +arc: N1_V02N0301 H06E0003 +arc: V00B0000 V02S0001 +arc: V00T0100 N1_V02S0701 +arc: A3 N1_V02S0501 +arc: B5 N1_V02S0701 +arc: B7 N1_V02S0701 +arc: C1 N1_V01S0100 +arc: CLK0 G_HPBX0100 +arc: D1 V00T0100 +arc: D3 N1_V01S0000 +arc: D5 V02S0401 +arc: D7 V00B0000 +arc: E1_H01E0001 Q7 +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q5 +arc: H01W0100 Q3 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q1 +arc: N1_V02N0701 Q7 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0011001100000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0011001100000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0101010100000000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000011110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 + +.tile R43C26:PLC2 +arc: W1_H02W0601 H01E0001 + +.tile R43C2:PLC2 +arc: E1_H02E0501 V02N0501 +arc: S1_V02S0001 E1_H02W0001 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0401 Q4 +arc: M4 V00B0000 +arc: M6 H02E0401 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V00B0000 Q6 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R43C3:PLC2 +arc: H00R0000 V02S0401 +arc: S1_V02S0001 H02W0001 +arc: V00B0000 V02S0201 +arc: A0 V02S0501 +arc: A1 N1_V02S0501 +arc: A3 H02E0501 +arc: A4 H02E0501 +arc: A5 H02E0501 +arc: A7 N1_V01S0100 +arc: B1 V00T0000 +arc: B5 H00R0000 +arc: C1 H00L0100 +arc: C5 N1_V02S0001 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D0 V02N0001 +arc: D1 V00B0100 +arc: D3 N1_V01S0000 +arc: D4 V00B0000 +arc: D7 V02N0401 +arc: E1_H02E0301 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0100 F5 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V02N0101 Q3 +arc: N1_V02N0501 Q7 +arc: N1_V02N0701 F5 +arc: S1_V02S0701 F5 +arc: V00B0100 Q7 +arc: V00T0000 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0000000010101010 +word: SLICEA.K1.INIT 0000000000000010 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0101010100000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000010101010 +word: SLICEC.K0.INIT 0101010100000000 +word: SLICEC.K1.INIT 1011101010111010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R43C4:PLC2 +arc: H00R0100 H02W0501 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0301 H02E0301 +arc: N3_V06N0003 E3_H06W0003 +arc: V00B0000 W1_H02E0401 +arc: W1_H02W0001 E3_H06W0003 +arc: W1_H02W0301 E3_H06W0003 +arc: A2 V00T0000 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V02N0301 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V01S0000 +arc: CE1 H00R0100 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: E1_H02E0001 Q2 +arc: E1_H02E0301 Q3 +arc: E1_H02E0401 Q4 +arc: E1_H02E0501 Q7 +arc: E1_H02E0601 Q6 +arc: E1_H02E0701 Q5 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: LSR0 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: V00T0000 Q2 +arc: V01S0000 Q6 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1010101010100000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R43C5:PLC2 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0401 N3_V06S0203 +arc: E1_H02E0501 N3_V06S0303 +arc: E3_H06E0303 N3_V06S0303 +arc: H00R0000 V02S0601 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0701 N1_V01S0100 +arc: V00B0000 H02E0601 +arc: V00B0100 V02S0301 +arc: A4 H02E0501 +arc: A5 H02E0701 +arc: B4 H02E0301 +arc: C4 H02E0401 +arc: C5 F4 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0100 +arc: D4 V00B0000 +arc: D5 H02E0001 +arc: E1_H01E0001 Q2 +arc: E1_H02E0701 F5 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: M2 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0303 Q5 +arc: W1_H02W0501 F5 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 0101111111111111 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 + +.tile R43C6:PLC2 +arc: H00L0100 H02E0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 N1_V01S0000 +arc: V00B0000 V02S0001 +arc: A0 H01E0001 +arc: A1 H02E0501 +arc: B1 E1_H01W0100 +arc: C1 H02E0401 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0100 +arc: D0 V02S0201 +arc: D1 H00R0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00R0000 Q6 +arc: M6 V00B0000 +arc: MUXCLK3 CLK0 +arc: N1_V02N0201 F0 +arc: V01S0000 F1 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 1010101000000000 +word: SLICEA.K1.INIT 0000011101110111 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 + +.tile R43C7:PLC2 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 H02W0201 +arc: N1_V02N0301 N1_V01S0100 +arc: N1_V02N0501 W1_H02E0501 +arc: N3_V06N0003 H06W0003 +arc: V00B0100 V02S0301 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 E1_H01W0000 +arc: CE0 H00R0100 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0100 +arc: H01W0100 Q4 +arc: LSR0 E1_H02W0501 +arc: M0 V00T0100 +arc: M4 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 Q0 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R43C8:PLC2 +arc: E1_H02E0701 N3_V06S0203 +arc: H00L0000 V02S0001 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V01N0101 N3_V06S0203 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0601 N3_V06S0303 +arc: V00B0100 S1_V02N0101 +arc: V01S0000 N3_V06S0103 +arc: W1_H02W0201 N3_V06S0103 +arc: W1_H02W0701 N3_V06S0203 +arc: A4 E1_H01W0000 +arc: A5 V02N0101 +arc: A6 E1_H02W0701 +arc: A7 V02N0101 +arc: B4 E1_H02W0301 +arc: B5 H00L0000 +arc: B6 V01S0000 +arc: B7 N1_V01S0000 +arc: C4 V00T0000 +arc: C5 F4 +arc: C6 E1_H02W0601 +arc: C7 E1_H02W0401 +arc: CE0 V02S0201 +arc: CLK0 G_HPBX0100 +arc: D4 V02N0601 +arc: D5 V02S0401 +arc: D6 E1_H01W0100 +arc: D7 V00B0000 +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F7 +arc: M0 V00B0100 +arc: MUXCLK0 CLK0 +arc: V00B0000 F6 +arc: V00T0000 Q0 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0001010100111111 +word: SLICED.K1.INIT 0011111100010101 +word: SLICEC.K0.INIT 0000011101110111 +word: SLICEC.K1.INIT 0011000111110101 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R43C9:PLC2 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0701 W1_H02E0701 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 E1_H01W0100 +arc: V00B0000 V02S0201 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 H02W0001 +arc: W1_H02W0501 E1_H01W0100 +arc: CE2 H00R0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0100 +arc: H01W0000 Q6 +arc: H01W0100 Q4 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 V00B0000 +arc: M6 V00B0100 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE ASYNC +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R44C10:PLC2 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0201 N3_V06S0103 +arc: V00T0100 H02W0301 +arc: W1_H02W0101 N3_V06S0103 +arc: CLK0 G_HPBX0100 +arc: M0 V00B0000 +arc: M6 V00T0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0001 Q0 +arc: V00B0000 Q6 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R44C11:PLC2 +arc: E1_H02E0701 S1_V02N0701 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0601 N1_V01S0000 +arc: W1_H02W0301 N3_V06S0003 + +.tile R44C12:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: H00L0000 V02S0001 +arc: H00R0100 V02S0701 +arc: N1_V02N0401 N3_V06S0203 +arc: V00B0000 V02S0201 +arc: A2 V02S0501 +arc: A3 V02S0701 +arc: A5 Q5 +arc: A6 H02E0701 +arc: A7 Q7 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B7 V02S0701 +arc: C2 N1_V01S0100 +arc: C3 F6 +arc: C6 H02W0601 +arc: C7 F6 +arc: CLK0 G_HPBX0100 +arc: D2 V00T0100 +arc: D3 F2 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 F2 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 Q5 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: V00T0100 Q3 +arc: V01S0000 Q5 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000010101010 +word: SLICEB.K0.INIT 0000000010111111 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICED.K0.INIT 0000010100000000 +word: SLICED.K1.INIT 0010001011110010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET SET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B0MUX 1 + +.tile R44C13:PLC2 +arc: N1_V02N0501 H02E0501 +arc: W1_H02W0601 N1_V02S0601 +arc: A0 H02E0501 +arc: A1 H02E0701 +arc: B0 F1 +arc: C0 V02S0401 +arc: C1 H00L0000 +arc: CLK0 G_HPBX0100 +arc: D0 Q0 +arc: D1 H02E0001 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H00L0000 Q0 +arc: MUXCLK0 CLK0 +arc: N3_V06N0103 F1 +word: SLICEA.K0.INIT 0100111100010000 +word: SLICEA.K1.INIT 0000000001011111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.B1MUX 1 + +.tile R44C14:PLC2 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 N3_V06S0203 +arc: N1_V02N0601 N3_V06S0303 + +.tile R44C16:PLC2 +arc: E1_H02E0601 V06S0303 + +.tile R44C17:PLC2 +arc: N1_V02N0601 H02E0601 + +.tile R44C18:PLC2 +arc: N1_V02N0701 N1_V01S0100 + +.tile R44C2:PLC2 +arc: V00B0000 V02S0001 +arc: V00B0100 S1_V02N0301 +arc: B5 V01S0000 +arc: C5 V02N0201 +arc: CE1 H02W0101 +arc: CE3 H02W0101 +arc: CLK0 G_HPBX0100 +arc: D5 H01W0000 +arc: E1_H01E0001 Q5 +arc: E1_H02E0501 Q5 +arc: F5 F5_SLICE +arc: H01W0000 Q6 +arc: LSR0 V00B0000 +arc: M2 H02E0601 +arc: M6 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V02N0501 Q5 +arc: N3_V06N0303 Q5 +arc: V01S0000 Q2 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1111110011000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET SET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET SET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG1.REGSET SET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.A1MUX 1 + +.tile R44C3:PLC2 +arc: E1_H02E0301 N1_V02S0301 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0701 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 E1_H02W0001 +arc: A3 H02E0501 +arc: CE1 H00R0100 +arc: CLK0 G_HPBX0100 +arc: D3 V00T0100 +arc: F3 F3_SLICE +arc: LSR0 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR0 +arc: N1_V02N0101 Q3 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0101010100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 + +.tile R44C4:PLC2 +arc: N1_V02N0301 H02E0301 + +.tile R44C5:PLC2 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0501 N3_V06S0303 +arc: W1_H02W0001 V06S0003 + +.tile R44C6:PLC2 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0601 N3_V06S0303 + +.tile R44C7:PLC2 +arc: N1_V02N0001 N3_V06S0003 +arc: N1_V02N0301 N3_V06S0003 +arc: W1_H02W0001 N3_V06S0003 + +.tile R44C8:PLC2 +arc: N1_V02N0101 E1_H02W0101 +arc: N1_V02N0601 N1_V01S0000 + +.tile R44C9:PLC2 +arc: N1_V02N0601 N3_V06S0303 +arc: N1_V02N0701 N3_V06S0203 + +.tile R45C10:PLC2 +arc: N1_V02N0401 N3_V06S0203 + +.tile R45C12:PLC2 +arc: N1_V02N0001 N1_V01S0000 + +.tile R45C13:PLC2 +arc: N1_V02N0401 N3_V06S0203 + +.tile R45C16:PLC2 +arc: N1_V02N0601 N3_V06S0303 + +.tile R45C17:PLC2 +arc: N1_V02N0601 N3_V06S0303 + +.tile R45C18:PLC2 +arc: N1_V02N0701 N3_V06S0203 + +.tile R45C2:PLC2 +arc: V00B0000 N1_V02S0001 +arc: V00B0100 H02E0701 +arc: CLK0 G_HPBX0100 +arc: LSR0 V00B0000 +arc: M2 N1_V01N0001 +arc: M6 V00B0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q6 +arc: N1_V02N0201 Q2 +arc: V01S0100 Q2 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICED.MODE LOGIC +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG1.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE ASYNC +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R45C8:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: N1_V02N0101 N3_V06S0103 + +.tile R45C9:PLC2 +arc: N1_V02N0101 H02E0101 + +.tile R46C11:PLC2 +arc: N1_V02N0701 N3_V06S0203 + +.tile R46C2:PLC2 +arc: N1_V02N0301 N1_V01S0100 + +.tile TAP_R15C22:TAP_DRIVE +arc: L_HPBX0100 G_VPTX0100 + +.tile TAP_R16C22:TAP_DRIVE +arc: L_HPBX0100 G_VPTX0100 + +.tile TAP_R16C4:TAP_DRIVE +arc: R_HPBX0100 G_VPTX0100 + +.tile TAP_R17C22:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: L_HPBX0100 G_VPTX0100 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R17C4:TAP_DRIVE +arc: R_HPBX0100 G_VPTX0100 + +.tile TAP_R18C22:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: L_HPBX0100 G_VPTX0100 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R18C4:TAP_DRIVE +arc: R_HPBX0100 G_VPTX0100 + +.tile TAP_R19C22:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: L_HPBX0100 G_VPTX0100 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R19C4:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 +arc: R_HPBX0100 G_VPTX0100 + +.tile TAP_R20C22:TAP_DRIVE +arc: L_HPBX0000 G_VPTX0000 +arc: L_HPBX0100 G_VPTX0100 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R20C4:TAP_DRIVE +arc: R_HPBX0100 G_VPTX0100 + +.tile TAP_R21C22:TAP_DRIVE +arc: L_HPBX0100 G_VPTX0100 +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R21C4:TAP_DRIVE +arc: L_HPBX0100 G_VPTX0100 +arc: R_HPBX0100 G_VPTX0100 + +.tile TAP_R22C22:TAP_DRIVE +arc: L_HPBX0100 G_VPTX0100 +arc: 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+ +YOSYS_COARSE=true +YOSYS_GLOBRST=false +YOSYS_SPLITNETS=false +TOP="Murax" + +mkdir -p gen +rm -rf gen/* + +{ + echo "read_verilog ${SOC}" + + if test -n "$TOP"; then + echo "hierarchy -check -top $TOP" + else + echo "hierarchy -check" + fi + if $YOSYS_GLOBRST; then + # insertation of global reset (e.g. for FPGA cores) + echo "add -global_input globrst 1" + echo "proc -global_arst globrst" + fi + echo "synth -run coarse; opt -fine" + # echo "tee -o gen/brams.log memory_bram -rules scripts/brams.txt;;" + if ! $YOSYS_COARSE; then + echo "memory_map; techmap; opt; abc -dff; clean" + fi + if $YOSYS_SPLITNETS; then + # icarus verilog has a performance problems when there are + # dependencies between the bits of a long vector + echo "splitnets; clean" + fi + if $YOSYS_COARSE; then + echo "write_verilog -noexpr -noattr gen/synth.v" + else + echo "select -assert-none t:\$[!_]" + echo "write_verilog -noattr gen/synth.v" + fi + echo "synth_ecp5 -top $TOP -json gen/soc.json" + # echo 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