Merge pull request #75 from olofk/snapshot_dir
Adapt FuseSoC SweRV config generator wrt new snapshot dir
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commit
1e8c6e3813
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@ -14,14 +14,14 @@ class SwervConfigGenerator(Generator):
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def run(self):
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def run(self):
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script_root = os.path.abspath(os.path.join(os.path.dirname(sys.argv[0]), '..'))
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script_root = os.path.abspath(os.path.join(os.path.dirname(sys.argv[0]), '..'))
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files = [
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files = [
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{"configs/snapshots/default/common_defines.vh" : {
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{"snapshots/default/common_defines.vh" : {
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"copyto" : "config/common_defines.vh",
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"copyto" : "config/common_defines.vh",
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"file_type" : "systemVerilogSource"}},
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"file_type" : "systemVerilogSource"}},
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{"configs/snapshots/default/pic_ctrl_verilator_unroll.sv" : {
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{"snapshots/default/pic_ctrl_verilator_unroll.sv" : {
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"copyto" : "config/pic_ctrl_verilator_unroll.sv",
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"copyto" : "config/pic_ctrl_verilator_unroll.sv",
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"is_include_file" : True,
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"is_include_file" : True,
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"file_type" : "systemVerilogSource"}},
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"file_type" : "systemVerilogSource"}},
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{"configs/snapshots/default/pic_map_auto.h" : {
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{"snapshots/default/pic_map_auto.h" : {
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"copyto" : "config/pic_map_auto.h",
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"copyto" : "config/pic_map_auto.h",
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"is_include_file" : True,
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"is_include_file" : True,
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"file_type" : "systemVerilogSource"}}]
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"file_type" : "systemVerilogSource"}}]
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