diff --git a/VexRiscv/demo/.gitignore b/VexRiscv/demo/.gitignore new file mode 100644 index 0000000..c795b05 --- /dev/null +++ b/VexRiscv/demo/.gitignore @@ -0,0 +1 @@ +build \ No newline at end of file diff --git a/VexRiscv/demo/gcc.mk b/VexRiscv/demo/gcc.mk new file mode 100644 index 0000000..cb3828b --- /dev/null +++ b/VexRiscv/demo/gcc.mk @@ -0,0 +1,26 @@ +# Set it to yes if you are using the sifive precompiled GCC pack +SIFIVE_GCC_PACK ?= yes + +ifeq ($(SIFIVE_GCC_PACK),yes) + RISCV_NAME ?= riscv64-unknown-elf + RISCV_PATH ?= /opt/riscv/ +else + RISCV_NAME ?= riscv32-unknown-elf + ifeq ($(MULDIV),yes) + RISCV_PATH ?= /opt/riscv32im/ + else + RISCV_PATH ?= /opt/riscv32i/ + endif +endif + +MABI=ilp32 +MARCH := rv32i_zicsr +ifeq ($(MULDIV),yes) + MARCH := $(MARCH)m +endif +ifeq ($(COMPRESSED),yes) + MARCH := $(MARCH)ac +endif + +CFLAGS += -march=$(MARCH) -mabi=$(MABI) +LDFLAGS += -march=$(MARCH) -mabi=$(MABI) diff --git a/VexRiscv/demo/libs/gpio.h b/VexRiscv/demo/libs/gpio.h new file mode 100755 index 0000000..34348fe --- /dev/null +++ b/VexRiscv/demo/libs/gpio.h @@ -0,0 +1,15 @@ +#ifndef GPIO_H_ +#define GPIO_H_ + + +typedef struct +{ + volatile uint32_t INPUT; + volatile uint32_t OUTPUT; + volatile uint32_t OUTPUT_ENABLE; +} Gpio_Reg; + + +#endif /* GPIO_H_ */ + + diff --git a/VexRiscv/demo/libs/interrupt.h b/VexRiscv/demo/libs/interrupt.h new file mode 100644 index 0000000..23b7d27 --- /dev/null +++ b/VexRiscv/demo/libs/interrupt.h @@ -0,0 +1,17 @@ +#ifndef INTERRUPTCTRL_H_ +#define INTERRUPTCTRL_H_ + +#include + +typedef struct +{ + volatile uint32_t PENDINGS; + volatile uint32_t MASKS; +} InterruptCtrl_Reg; + +static void interruptCtrl_init(InterruptCtrl_Reg* reg){ + reg->MASKS = 0; + reg->PENDINGS = 0xFFFFFFFF; +} + +#endif /* INTERRUPTCTRL_H_ */ diff --git a/VexRiscv/demo/libs/linker.ld b/VexRiscv/demo/libs/linker.ld new file mode 100755 index 0000000..ad708d0 --- /dev/null +++ b/VexRiscv/demo/libs/linker.ld @@ -0,0 +1,109 @@ +/* +This is free and unencumbered software released into the public domain. + +Anyone is free to copy, modify, publish, use, compile, sell, or +distribute this software, either in source code form or as a compiled +binary, for any purpose, commercial or non-commercial, and by any +means. +*/ +OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv") +OUTPUT_ARCH(riscv) +ENTRY(crtStart) + +MEMORY { + onChipRam : ORIGIN = 0x80000000, LENGTH = 8k +} + +_stack_size = DEFINED(_stack_size) ? _stack_size : 512; +_heap_size = DEFINED(_heap_size) ? _heap_size : 0; + +SECTIONS { + + .vector : { + *crt.o(.text); + } > onChipRam + + .memory : { + *(.text); + end = .; + } > onChipRam + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } > onChipRam + + .ctors : + { + . = ALIGN(4); + _ctors_start = .; + KEEP(*(.init_array*)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + . = ALIGN(4); + _ctors_end = .; + } > onChipRam + + .data : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } > onChipRam + + .bss (NOLOAD) : { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _bss_start = .; + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > onChipRam + + .noinit (NOLOAD) : { + . = ALIGN(4); + *(.noinit .noinit.*) + . = ALIGN(4); + } > onChipRam + + + ._user_heap (NOLOAD): + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + PROVIDE ( _heap_start = .); + . = . + _heap_size; + . = ALIGN(8); + PROVIDE ( _heap_end = .); + } > onChipRam + + ._stack (NOLOAD): + { + . = ALIGN(16); + PROVIDE (_stack_end = .); + . = . + _stack_size; + . = ALIGN(16); + PROVIDE (_stack_start = .); + } > onChipRam + +} + diff --git a/VexRiscv/demo/libs/murax.h b/VexRiscv/demo/libs/murax.h new file mode 100644 index 0000000..7a91cfc --- /dev/null +++ b/VexRiscv/demo/libs/murax.h @@ -0,0 +1,28 @@ +/* + * briey.h + * + * Created on: Aug 24, 2016 + * Author: clp + */ + +#ifndef BRIEY_H_ +#define BRIEY_H_ + +#include "timer.h" +#include "prescaler.h" +#include "interrupt.h" +#include "gpio.h" +#include "uart.h" + +#define CORE_HZ 12000000 + +#define GPIO_A ((Gpio_Reg*)(0xF0000000)) +#define TIMER_PRESCALER ((Prescaler_Reg*)0xF0020000) +#define TIMER_INTERRUPT ((InterruptCtrl_Reg*)0xF0020010) +#define TIMER_A ((Timer_Reg*)0xF0020040) +#define TIMER_B ((Timer_Reg*)0xF0020050) +#define UART ((Uart_Reg*)(0xF0010000)) +#define UART_SAMPLE_PER_BAUD 5 + + +#endif /* BRIEY_H_ */ diff --git a/VexRiscv/demo/libs/prescaler.h b/VexRiscv/demo/libs/prescaler.h new file mode 100644 index 0000000..6bd9694 --- /dev/null +++ b/VexRiscv/demo/libs/prescaler.h @@ -0,0 +1,16 @@ +#ifndef PRESCALERCTRL_H_ +#define PRESCALERCTRL_H_ + +#include + + +typedef struct +{ + volatile uint32_t LIMIT; +} Prescaler_Reg; + +static void prescaler_init(Prescaler_Reg* reg){ + +} + +#endif /* PRESCALERCTRL_H_ */ diff --git a/VexRiscv/demo/libs/timer.h b/VexRiscv/demo/libs/timer.h new file mode 100644 index 0000000..1577535 --- /dev/null +++ b/VexRiscv/demo/libs/timer.h @@ -0,0 +1,20 @@ +#ifndef TIMERCTRL_H_ +#define TIMERCTRL_H_ + +#include + + +typedef struct +{ + volatile uint32_t CLEARS_TICKS; + volatile uint32_t LIMIT; + volatile uint32_t VALUE; +} Timer_Reg; + +static void timer_init(Timer_Reg *reg){ + reg->CLEARS_TICKS = 0; + reg->VALUE = 0; +} + + +#endif /* TIMERCTRL_H_ */ diff --git a/VexRiscv/demo/libs/uart.h b/VexRiscv/demo/libs/uart.h new file mode 100755 index 0000000..c3a30a5 --- /dev/null +++ b/VexRiscv/demo/libs/uart.h @@ -0,0 +1,42 @@ +#ifndef UART_H_ +#define UART_H_ + + +typedef struct +{ + volatile uint32_t DATA; + volatile uint32_t STATUS; + volatile uint32_t CLOCK_DIVIDER; + volatile uint32_t FRAME_CONFIG; +} Uart_Reg; + +enum UartParity {NONE = 0,EVEN = 1,ODD = 2}; +enum UartStop {ONE = 0,TWO = 1}; + +typedef struct { + uint32_t dataLength; + enum UartParity parity; + enum UartStop stop; + uint32_t clockDivider; +} Uart_Config; + +static uint32_t uart_writeAvailability(Uart_Reg *reg){ + return (reg->STATUS >> 16) & 0xFF; +} +static uint32_t uart_readOccupancy(Uart_Reg *reg){ + return reg->STATUS >> 24; +} + +static void uart_write(Uart_Reg *reg, uint32_t data){ + while(uart_writeAvailability(reg) == 0); + reg->DATA = data; +} + +static void uart_applyConfig(Uart_Reg *reg, Uart_Config *config){ + reg->CLOCK_DIVIDER = config->clockDivider; + reg->FRAME_CONFIG = ((config->dataLength-1) << 0) | (config->parity << 8) | (config->stop << 16); +} + +#endif /* UART_H_ */ + + diff --git a/VexRiscv/demo/libs/vga.h b/VexRiscv/demo/libs/vga.h new file mode 100644 index 0000000..182b968 --- /dev/null +++ b/VexRiscv/demo/libs/vga.h @@ -0,0 +1,78 @@ +/* + * vga.h + * + * Created on: Jul 8, 2017 + * Author: spinalvm + */ + +#ifndef VGA_H_ +#define VGA_H_ +#include + +typedef struct { + uint32_t hSyncStart ,hSyncEnd; + uint32_t hColorStart,hColorEnd; + + uint32_t vSyncStart ,vSyncEnd; + uint32_t vColorStart,vColorEnd; +}Vga_Timing; + +static const Vga_Timing vga_h640_v480_r60 = { + .hSyncStart = 96, + .hSyncEnd = 800, + .hColorStart = 96 + 16, + .hColorEnd = 800 - 48, + .vSyncStart = 2, + .vSyncEnd = 525, + .vColorStart = 2 + 10, + .vColorEnd = 525 - 33 +}; + +static const Vga_Timing vga_simRes = { + .hSyncStart = 8, + .hSyncEnd = 70, + .hColorStart = 16, + .hColorEnd = 64, + .vSyncStart = 2, + .vSyncEnd = 48, + .vColorStart = 8, + .vColorEnd = 40 +}; + +static const Vga_Timing vga_simRes_h160_v120 = { + .hSyncStart = 8, + .hSyncEnd = 24+160, + .hColorStart = 16, + .hColorEnd = 16+160, + .vSyncStart = 2, + .vSyncEnd = 10+120, + .vColorStart = 6, + .vColorEnd = 6+120 +}; + +typedef struct +{ + volatile uint32_t STATUS; + volatile uint32_t FRAME_SIZE; + volatile uint32_t FRAME_BASE; + volatile uint32_t DUMMY0[13]; + volatile Vga_Timing TIMING; +} Vga_Reg; + +static uint32_t vga_isBusy(Vga_Reg *reg){ + return (reg->STATUS & 2) != 0; +} + +static void vga_run(Vga_Reg *reg){ + reg->STATUS = 1; +} + +static void vga_stop(Vga_Reg *reg){ + reg->STATUS = 0; + while(vga_isBusy(reg)); +} + + +#endif /* VGA_H_ */ + + diff --git a/VexRiscv/demo/makefile b/VexRiscv/demo/makefile new file mode 100755 index 0000000..a7de200 --- /dev/null +++ b/VexRiscv/demo/makefile @@ -0,0 +1,20 @@ +PROJ_NAME=demo +DEBUG=yes +BENCH=no +MULDIV=no + + +SRCS = $(wildcard src/*.c) \ + $(wildcard src/*.cpp) \ + $(wildcard src/*.S) + + +INC += -I./libs/ +INC += -I./libs/ +LDSCRIPT = ./libs/linker.ld + +include ./gcc.mk +include ./subproject.mk + + + diff --git a/VexRiscv/demo/src/crt.S b/VexRiscv/demo/src/crt.S new file mode 100755 index 0000000..0a98a6e --- /dev/null +++ b/VexRiscv/demo/src/crt.S @@ -0,0 +1,97 @@ +.global crtStart +.global main +.global irqCallback + +crtStart: + j crtInit + nop + nop + nop + nop + nop + nop + nop + +.global trap_entry +trap_entry: + sw x1, - 1*4(sp) + sw x5, - 2*4(sp) + sw x6, - 3*4(sp) + sw x7, - 4*4(sp) + sw x10, - 5*4(sp) + sw x11, - 6*4(sp) + sw x12, - 7*4(sp) + sw x13, - 8*4(sp) + sw x14, - 9*4(sp) + sw x15, -10*4(sp) + sw x16, -11*4(sp) + sw x17, -12*4(sp) + sw x28, -13*4(sp) + sw x29, -14*4(sp) + sw x30, -15*4(sp) + sw x31, -16*4(sp) + addi sp,sp,-16*4 + call irqCallback + lw x1 , 15*4(sp) + lw x5, 14*4(sp) + lw x6, 13*4(sp) + lw x7, 12*4(sp) + lw x10, 11*4(sp) + lw x11, 10*4(sp) + lw x12, 9*4(sp) + lw x13, 8*4(sp) + lw x14, 7*4(sp) + lw x15, 6*4(sp) + lw x16, 5*4(sp) + lw x17, 4*4(sp) + lw x28, 3*4(sp) + lw x29, 2*4(sp) + lw x30, 1*4(sp) + lw x31, 0*4(sp) + addi sp,sp,16*4 + mret + .text + + +crtInit: + .option push + .option norelax + la gp, __global_pointer$ + .option pop + la sp, _stack_start + +bss_init: + la a0, _bss_start + la a1, _bss_end +bss_loop: + beq a0,a1,bss_done + sw zero,0(a0) + add a0,a0,4 + j bss_loop +bss_done: + +ctors_init: + la a0, _ctors_start + addi sp,sp,-4 +ctors_loop: + la a1, _ctors_end + beq a0,a1,ctors_done + lw a3,0(a0) + add a0,a0,4 + sw a0,0(sp) + jalr a3 + lw a0,0(sp) + j ctors_loop +ctors_done: + addi sp,sp,4 + + + li a0, 0x880 //880 enable timer + external interrupts + csrw mie,a0 + li a0, 0x1808 //1808 enable interrupts + csrw mstatus,a0 + + call main +infinitLoop: + j infinitLoop + diff --git a/VexRiscv/demo/src/main.c b/VexRiscv/demo/src/main.c new file mode 100755 index 0000000..23abc10 --- /dev/null +++ b/VexRiscv/demo/src/main.c @@ -0,0 +1,47 @@ +#include + +#include + + +void main() { + volatile uint32_t a = 1, b = 2, c = 3; + uint32_t result = 0; + + interruptCtrl_init(TIMER_INTERRUPT); + prescaler_init(TIMER_PRESCALER); + timer_init(TIMER_A); + + TIMER_PRESCALER->LIMIT = 12000-1; //1 ms rate + + TIMER_A->LIMIT = 1000-1; //1 second rate + TIMER_A->CLEARS_TICKS = 0x00010002; + + TIMER_INTERRUPT->PENDINGS = 0xF; + TIMER_INTERRUPT->MASKS = 0x1; + + GPIO_A->OUTPUT_ENABLE = 0x000000FF; + GPIO_A->OUTPUT = 0x00000000; + + UART->STATUS = 2; //Enable RX interrupts + UART->DATA = 'A'; + + while(1){ + result += a; + result += b + c; + for(uint32_t idx = 0;idx < 50000;idx++) asm volatile(""); + GPIO_A->OUTPUT = (GPIO_A->OUTPUT & ~0x3F) | ((GPIO_A->OUTPUT + 1) & 0x3F); //Counter on LED[5:0] + } +} + +void irqCallback(){ + if(TIMER_INTERRUPT->PENDINGS & 1){ //Timer A interrupt + GPIO_A->OUTPUT ^= 0x80; //Toogle led 7 + TIMER_INTERRUPT->PENDINGS = 1; + } + while(UART->STATUS & (1 << 9)){ //UART RX interrupt + UART->DATA = (UART->DATA) & 0xFF; + } +} + + + diff --git a/VexRiscv/demo/subproject.mk b/VexRiscv/demo/subproject.mk new file mode 100755 index 0000000..3aba0d6 --- /dev/null +++ b/VexRiscv/demo/subproject.mk @@ -0,0 +1,87 @@ + + +ifeq ($(DEBUG),yes) + CFLAGS += -g3 -O0 +endif + +ifeq ($(DEBUG),no) + CFLAGS += -g -O3 +endif + +ifeq ($(BENCH),yes) + CFLAGS += -fno-inline +endif + +ifeq ($(SIFIVE_GCC_PACK),yes) + RISCV_CLIB=$(RISCV_PATH)/$(RISCV_NAME)/lib/$(MARCH)/$(MABI)/ +else + RISCV_CLIB=$(RISCV_PATH)/$(RISCV_NAME)/lib/ +endif + + + + + +RISCV_OBJCOPY = $(RISCV_PATH)/bin/$(RISCV_NAME)-objcopy +RISCV_OBJDUMP = $(RISCV_PATH)/bin/$(RISCV_NAME)-objdump +RISCV_CC=$(RISCV_PATH)/bin/$(RISCV_NAME)-gcc + +CFLAGS += -MD -fstrict-volatile-bitfields +LDFLAGS += -nostdlib -lgcc -mcmodel=medany -nostartfiles -ffreestanding -Wl,-Bstatic,-T,$(LDSCRIPT),-Map,$(OBJDIR)/$(PROJ_NAME).map,--print-memory-usage +#LDFLAGS += -lgcc -lc -lg -nostdlib -lgcc -msave-restore --strip-debug, + +OBJDIR = build +OBJS := $(SRCS) +OBJS := $(OBJS:.c=.o) +OBJS := $(OBJS:.cpp=.o) +OBJS := $(OBJS:.S=.o) +OBJS := $(OBJS:..=miaou) +OBJS := $(addprefix $(OBJDIR)/,$(OBJS)) + + +all: $(OBJDIR)/$(PROJ_NAME).elf $(OBJDIR)/$(PROJ_NAME).hex $(OBJDIR)/$(PROJ_NAME).asm $(OBJDIR)/$(PROJ_NAME).v + +$(OBJDIR)/%.elf: $(OBJS) | $(OBJDIR) + $(RISCV_CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) $(LIBS) + +%.hex: %.elf + $(RISCV_OBJCOPY) -O ihex $^ $@ + +%.bin: %.elf + $(RISCV_OBJCOPY) -O binary $^ $@ + +%.v: %.elf + $(RISCV_OBJCOPY) -O verilog $^ $@ + + + +%.asm: %.elf + $(RISCV_OBJDUMP) -S -d $^ > $@ + +$(OBJDIR)/%.o: %.c + mkdir -p $(dir $@) + $(RISCV_CC) -c $(CFLAGS) $(INC) -o $@ $^ + +$(OBJDIR)/%.o: %.cpp + mkdir -p $(dir $@) + $(RISCV_CC) -c $(CFLAGS) $(INC) -o $@ $^ + +$(OBJDIR)/%.o: %.S + mkdir -p $(dir $@) + $(RISCV_CC) -c $(CFLAGS) -o $@ $^ -D__ASSEMBLY__=1 + +$(OBJDIR): + mkdir -p $@ + +clean: + rm -f $(OBJDIR)/$(PROJ_NAME).elf + rm -f $(OBJDIR)/$(PROJ_NAME).hex + rm -f $(OBJDIR)/$(PROJ_NAME).map + rm -f $(OBJDIR)/$(PROJ_NAME).v + rm -f $(OBJDIR)/$(PROJ_NAME).asm + find $(OBJDIR) -type f -name '*.o' -print0 | xargs -0 -r rm + +.SECONDARY: $(OBJS) + + + diff --git a/VexRiscv/murax/.gitignore b/VexRiscv/murax/.gitignore new file mode 100644 index 0000000..511a421 --- /dev/null +++ b/VexRiscv/murax/.gitignore @@ -0,0 +1 @@ +obj_dir \ No newline at end of file diff --git a/VexRiscv/murax/Murax.logTrace b/VexRiscv/murax/Murax.logTrace new file mode 100644 index 0000000..e69de29 diff --git a/VexRiscv/murax/Murax.v b/VexRiscv/murax/Murax.v new file mode 100644 index 0000000..8efdfa9 --- /dev/null +++ b/VexRiscv/murax/Murax.v @@ -0,0 +1,7319 @@ +// Generator : SpinalHDL v1.10.2a git head : a348a60b7e8b6a455c72e1536ec3d74a2ea16935 +// Component : Murax +// Git hash : 229fecd4a1e51f50b2722d02dd5f39f6fb163ce5 + +`timescale 1ns/1ps + +module Murax ( + input wire io_asyncReset, + input wire io_mainClk, + input wire io_jtag_tms, + input wire io_jtag_tdi, + output wire io_jtag_tdo, + input wire io_jtag_tck, + input wire [31:0] io_gpioA_read, + output wire [31:0] io_gpioA_write, + output wire [31:0] io_gpioA_writeEnable, + output wire io_uart_txd, + input wire io_uart_rxd +); + + wire [7:0] system_cpu_debug_bus_cmd_payload_address; + wire system_cpu_dBus_cmd_ready; + reg system_ram_io_bus_cmd_valid; + reg system_apbBridge_io_pipelinedMemoryBus_cmd_valid; + wire [3:0] system_gpioACtrl_io_apb_PADDR; + wire [4:0] system_uartCtrl_io_apb_PADDR; + wire [7:0] system_timer_io_apb_PADDR; + wire io_asyncReset_buffercc_io_dataOut; + wire system_mainBusArbiter_io_iBus_cmd_ready; + wire system_mainBusArbiter_io_iBus_rsp_valid; + wire system_mainBusArbiter_io_iBus_rsp_payload_error; + wire [31:0] system_mainBusArbiter_io_iBus_rsp_payload_inst; + wire system_mainBusArbiter_io_dBus_cmd_ready; + wire system_mainBusArbiter_io_dBus_rsp_ready; + wire system_mainBusArbiter_io_dBus_rsp_error; + wire [31:0] system_mainBusArbiter_io_dBus_rsp_data; + wire system_mainBusArbiter_io_masterBus_cmd_valid; + wire system_mainBusArbiter_io_masterBus_cmd_payload_write; + wire [31:0] system_mainBusArbiter_io_masterBus_cmd_payload_address; + wire [31:0] system_mainBusArbiter_io_masterBus_cmd_payload_data; + wire [3:0] system_mainBusArbiter_io_masterBus_cmd_payload_mask; + wire system_cpu_iBus_cmd_valid; + wire [31:0] system_cpu_iBus_cmd_payload_pc; + wire system_cpu_debug_bus_cmd_ready; + wire [31:0] system_cpu_debug_bus_rsp_data; + wire system_cpu_debug_resetOut; + wire system_cpu_dBus_cmd_valid; + wire system_cpu_dBus_cmd_payload_wr; + wire [3:0] system_cpu_dBus_cmd_payload_mask; + wire [31:0] system_cpu_dBus_cmd_payload_address; + wire [31:0] system_cpu_dBus_cmd_payload_data; + wire [1:0] system_cpu_dBus_cmd_payload_size; + wire jtagBridge_1_io_jtag_tdo; + wire jtagBridge_1_io_remote_cmd_valid; + wire jtagBridge_1_io_remote_cmd_payload_last; + wire [0:0] jtagBridge_1_io_remote_cmd_payload_fragment; + wire jtagBridge_1_io_remote_rsp_ready; + wire systemDebugger_1_io_remote_cmd_ready; + wire systemDebugger_1_io_remote_rsp_valid; + wire systemDebugger_1_io_remote_rsp_payload_error; + wire [31:0] systemDebugger_1_io_remote_rsp_payload_data; + wire systemDebugger_1_io_mem_cmd_valid; + wire [31:0] systemDebugger_1_io_mem_cmd_payload_address; + wire [31:0] systemDebugger_1_io_mem_cmd_payload_data; + wire systemDebugger_1_io_mem_cmd_payload_wr; + wire [1:0] systemDebugger_1_io_mem_cmd_payload_size; + wire system_ram_io_bus_cmd_ready; + wire system_ram_io_bus_rsp_valid; + wire [31:0] system_ram_io_bus_rsp_payload_data; + wire system_apbBridge_io_pipelinedMemoryBus_cmd_ready; + wire system_apbBridge_io_pipelinedMemoryBus_rsp_valid; + wire [31:0] system_apbBridge_io_pipelinedMemoryBus_rsp_payload_data; + wire [19:0] system_apbBridge_io_apb_PADDR; + wire [0:0] system_apbBridge_io_apb_PSEL; + wire system_apbBridge_io_apb_PENABLE; + wire system_apbBridge_io_apb_PWRITE; + wire [31:0] system_apbBridge_io_apb_PWDATA; + wire system_gpioACtrl_io_apb_PREADY; + wire [31:0] system_gpioACtrl_io_apb_PRDATA; + wire system_gpioACtrl_io_apb_PSLVERROR; + wire [31:0] system_gpioACtrl_io_gpio_write; + wire [31:0] system_gpioACtrl_io_gpio_writeEnable; + wire [31:0] system_gpioACtrl_io_value; + wire system_uartCtrl_io_apb_PREADY; + wire [31:0] system_uartCtrl_io_apb_PRDATA; + wire system_uartCtrl_io_uart_txd; + wire system_uartCtrl_io_interrupt; + wire system_timer_io_apb_PREADY; + wire [31:0] system_timer_io_apb_PRDATA; + wire system_timer_io_apb_PSLVERROR; + wire system_timer_io_interrupt; + wire io_apb_decoder_io_input_PREADY; + wire [31:0] io_apb_decoder_io_input_PRDATA; + wire io_apb_decoder_io_input_PSLVERROR; + wire [19:0] io_apb_decoder_io_output_PADDR; + wire [2:0] io_apb_decoder_io_output_PSEL; + wire io_apb_decoder_io_output_PENABLE; + wire io_apb_decoder_io_output_PWRITE; + wire [31:0] io_apb_decoder_io_output_PWDATA; + wire apb3Router_1_io_input_PREADY; + wire [31:0] apb3Router_1_io_input_PRDATA; + wire apb3Router_1_io_input_PSLVERROR; + wire [19:0] apb3Router_1_io_outputs_0_PADDR; + wire [0:0] apb3Router_1_io_outputs_0_PSEL; + wire apb3Router_1_io_outputs_0_PENABLE; + wire apb3Router_1_io_outputs_0_PWRITE; + wire [31:0] apb3Router_1_io_outputs_0_PWDATA; + wire [19:0] apb3Router_1_io_outputs_1_PADDR; + wire [0:0] apb3Router_1_io_outputs_1_PSEL; + wire apb3Router_1_io_outputs_1_PENABLE; + wire apb3Router_1_io_outputs_1_PWRITE; + wire [31:0] apb3Router_1_io_outputs_1_PWDATA; + wire [19:0] apb3Router_1_io_outputs_2_PADDR; + wire [0:0] apb3Router_1_io_outputs_2_PSEL; + wire apb3Router_1_io_outputs_2_PENABLE; + wire apb3Router_1_io_outputs_2_PWRITE; + wire [31:0] apb3Router_1_io_outputs_2_PWDATA; + reg [31:0] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data; + reg resetCtrl_mainClkResetUnbuffered; + reg [5:0] resetCtrl_systemClkResetCounter; + wire [5:0] _zz_when_Murax_l196; + wire when_Murax_l196; + wire when_Murax_l200; + reg resetCtrl_mainClkReset; + reg resetCtrl_systemReset; + reg system_timerInterrupt; + reg system_externalInterrupt; + wire toplevel_system_cpu_dBus_cmd_halfPipe_valid; + wire toplevel_system_cpu_dBus_cmd_halfPipe_ready; + wire toplevel_system_cpu_dBus_cmd_halfPipe_payload_wr; + wire [3:0] toplevel_system_cpu_dBus_cmd_halfPipe_payload_mask; + wire [31:0] toplevel_system_cpu_dBus_cmd_halfPipe_payload_address; + wire [31:0] toplevel_system_cpu_dBus_cmd_halfPipe_payload_data; + wire [1:0] toplevel_system_cpu_dBus_cmd_halfPipe_payload_size; + reg toplevel_system_cpu_dBus_cmd_rValid; + wire toplevel_system_cpu_dBus_cmd_halfPipe_fire; + reg toplevel_system_cpu_dBus_cmd_rData_wr; + reg [3:0] toplevel_system_cpu_dBus_cmd_rData_mask; + reg [31:0] toplevel_system_cpu_dBus_cmd_rData_address; + reg [31:0] toplevel_system_cpu_dBus_cmd_rData_data; + reg [1:0] toplevel_system_cpu_dBus_cmd_rData_size; + reg toplevel_system_cpu_debug_resetOut_regNext; + wire toplevel_system_cpu_debug_bus_cmd_fire; + reg toplevel_system_cpu_debug_bus_cmd_fire_regNext; + wire system_mainBusDecoder_logic_masterPipelined_cmd_valid; + reg system_mainBusDecoder_logic_masterPipelined_cmd_ready; + wire system_mainBusDecoder_logic_masterPipelined_cmd_payload_write; + wire [31:0] system_mainBusDecoder_logic_masterPipelined_cmd_payload_address; + wire [31:0] system_mainBusDecoder_logic_masterPipelined_cmd_payload_data; + wire [3:0] system_mainBusDecoder_logic_masterPipelined_cmd_payload_mask; + wire system_mainBusDecoder_logic_masterPipelined_rsp_valid; + wire [31:0] system_mainBusDecoder_logic_masterPipelined_rsp_payload_data; + wire system_mainBusDecoder_logic_hits_0; + wire _zz_io_bus_cmd_payload_write; + wire system_mainBusDecoder_logic_hits_1; + wire _zz_io_pipelinedMemoryBus_cmd_payload_write; + wire system_mainBusDecoder_logic_noHit; + reg system_mainBusDecoder_logic_rspPending; + wire system_mainBusDecoder_logic_masterPipelined_cmd_fire; + wire when_MuraxUtiles_l127; + reg system_mainBusDecoder_logic_rspNoHit; + reg [0:0] system_mainBusDecoder_logic_rspSourceId; + wire when_MuraxUtiles_l133; + + (* keep_hierarchy = "TRUE" *) BufferCC io_asyncReset_buffercc ( + .io_dataIn (io_asyncReset ), //i + .io_dataOut (io_asyncReset_buffercc_io_dataOut), //o + .io_mainClk (io_mainClk ) //i + ); + MuraxMasterArbiter system_mainBusArbiter ( + .io_iBus_cmd_valid (system_cpu_iBus_cmd_valid ), //i + .io_iBus_cmd_ready (system_mainBusArbiter_io_iBus_cmd_ready ), //o + .io_iBus_cmd_payload_pc (system_cpu_iBus_cmd_payload_pc[31:0] ), //i + .io_iBus_rsp_valid (system_mainBusArbiter_io_iBus_rsp_valid ), //o + .io_iBus_rsp_payload_error (system_mainBusArbiter_io_iBus_rsp_payload_error ), //o + .io_iBus_rsp_payload_inst (system_mainBusArbiter_io_iBus_rsp_payload_inst[31:0] ), //o + .io_dBus_cmd_valid (toplevel_system_cpu_dBus_cmd_halfPipe_valid ), //i + .io_dBus_cmd_ready (system_mainBusArbiter_io_dBus_cmd_ready ), //o + .io_dBus_cmd_payload_wr (toplevel_system_cpu_dBus_cmd_halfPipe_payload_wr ), //i + .io_dBus_cmd_payload_mask (toplevel_system_cpu_dBus_cmd_halfPipe_payload_mask[3:0] ), //i + .io_dBus_cmd_payload_address (toplevel_system_cpu_dBus_cmd_halfPipe_payload_address[31:0] ), //i + .io_dBus_cmd_payload_data (toplevel_system_cpu_dBus_cmd_halfPipe_payload_data[31:0] ), //i + .io_dBus_cmd_payload_size (toplevel_system_cpu_dBus_cmd_halfPipe_payload_size[1:0] ), //i + .io_dBus_rsp_ready (system_mainBusArbiter_io_dBus_rsp_ready ), //o + .io_dBus_rsp_error (system_mainBusArbiter_io_dBus_rsp_error ), //o + .io_dBus_rsp_data (system_mainBusArbiter_io_dBus_rsp_data[31:0] ), //o + .io_masterBus_cmd_valid (system_mainBusArbiter_io_masterBus_cmd_valid ), //o + .io_masterBus_cmd_ready (system_mainBusDecoder_logic_masterPipelined_cmd_ready ), //i + .io_masterBus_cmd_payload_write (system_mainBusArbiter_io_masterBus_cmd_payload_write ), //o + .io_masterBus_cmd_payload_address (system_mainBusArbiter_io_masterBus_cmd_payload_address[31:0] ), //o + .io_masterBus_cmd_payload_data (system_mainBusArbiter_io_masterBus_cmd_payload_data[31:0] ), //o + .io_masterBus_cmd_payload_mask (system_mainBusArbiter_io_masterBus_cmd_payload_mask[3:0] ), //o + .io_masterBus_rsp_valid (system_mainBusDecoder_logic_masterPipelined_rsp_valid ), //i + .io_masterBus_rsp_payload_data (system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[31:0]), //i + .io_mainClk (io_mainClk ), //i + .resetCtrl_systemReset (resetCtrl_systemReset ) //i + ); + VexRiscv system_cpu ( + .iBus_cmd_valid (system_cpu_iBus_cmd_valid ), //o + .iBus_cmd_ready (system_mainBusArbiter_io_iBus_cmd_ready ), //i + .iBus_cmd_payload_pc (system_cpu_iBus_cmd_payload_pc[31:0] ), //o + .iBus_rsp_valid (system_mainBusArbiter_io_iBus_rsp_valid ), //i + .iBus_rsp_payload_error (system_mainBusArbiter_io_iBus_rsp_payload_error ), //i + .iBus_rsp_payload_inst (system_mainBusArbiter_io_iBus_rsp_payload_inst[31:0]), //i + .timerInterrupt (system_timerInterrupt ), //i + .externalInterrupt (system_externalInterrupt ), //i + .softwareInterrupt (1'b0 ), //i + .debug_bus_cmd_valid (systemDebugger_1_io_mem_cmd_valid ), //i + .debug_bus_cmd_ready (system_cpu_debug_bus_cmd_ready ), //o + .debug_bus_cmd_payload_wr (systemDebugger_1_io_mem_cmd_payload_wr ), //i + .debug_bus_cmd_payload_address (system_cpu_debug_bus_cmd_payload_address[7:0] ), //i + .debug_bus_cmd_payload_data (systemDebugger_1_io_mem_cmd_payload_data[31:0] ), //i + .debug_bus_rsp_data (system_cpu_debug_bus_rsp_data[31:0] ), //o + .debug_resetOut (system_cpu_debug_resetOut ), //o + .dBus_cmd_valid (system_cpu_dBus_cmd_valid ), //o + .dBus_cmd_ready (system_cpu_dBus_cmd_ready ), //i + .dBus_cmd_payload_wr (system_cpu_dBus_cmd_payload_wr ), //o + .dBus_cmd_payload_mask (system_cpu_dBus_cmd_payload_mask[3:0] ), //o + .dBus_cmd_payload_address (system_cpu_dBus_cmd_payload_address[31:0] ), //o + .dBus_cmd_payload_data (system_cpu_dBus_cmd_payload_data[31:0] ), //o + .dBus_cmd_payload_size (system_cpu_dBus_cmd_payload_size[1:0] ), //o + .dBus_rsp_ready (system_mainBusArbiter_io_dBus_rsp_ready ), //i + .dBus_rsp_error (system_mainBusArbiter_io_dBus_rsp_error ), //i + .dBus_rsp_data (system_mainBusArbiter_io_dBus_rsp_data[31:0] ), //i + .io_mainClk (io_mainClk ), //i + .resetCtrl_systemReset (resetCtrl_systemReset ), //i + .resetCtrl_mainClkReset (resetCtrl_mainClkReset ) //i + ); + JtagBridge jtagBridge_1 ( + .io_jtag_tms (io_jtag_tms ), //i + .io_jtag_tdi (io_jtag_tdi ), //i + .io_jtag_tdo (jtagBridge_1_io_jtag_tdo ), //o + .io_jtag_tck (io_jtag_tck ), //i + .io_remote_cmd_valid (jtagBridge_1_io_remote_cmd_valid ), //o + .io_remote_cmd_ready (systemDebugger_1_io_remote_cmd_ready ), //i + .io_remote_cmd_payload_last (jtagBridge_1_io_remote_cmd_payload_last ), //o + .io_remote_cmd_payload_fragment (jtagBridge_1_io_remote_cmd_payload_fragment ), //o + .io_remote_rsp_valid (systemDebugger_1_io_remote_rsp_valid ), //i + .io_remote_rsp_ready (jtagBridge_1_io_remote_rsp_ready ), //o + .io_remote_rsp_payload_error (systemDebugger_1_io_remote_rsp_payload_error ), //i + .io_remote_rsp_payload_data (systemDebugger_1_io_remote_rsp_payload_data[31:0]), //i + .io_mainClk (io_mainClk ), //i + .resetCtrl_mainClkReset (resetCtrl_mainClkReset ) //i + ); + SystemDebugger systemDebugger_1 ( + .io_remote_cmd_valid (jtagBridge_1_io_remote_cmd_valid ), //i + .io_remote_cmd_ready (systemDebugger_1_io_remote_cmd_ready ), //o + .io_remote_cmd_payload_last (jtagBridge_1_io_remote_cmd_payload_last ), //i + .io_remote_cmd_payload_fragment (jtagBridge_1_io_remote_cmd_payload_fragment ), //i + .io_remote_rsp_valid (systemDebugger_1_io_remote_rsp_valid ), //o + .io_remote_rsp_ready (jtagBridge_1_io_remote_rsp_ready ), //i + .io_remote_rsp_payload_error (systemDebugger_1_io_remote_rsp_payload_error ), //o + .io_remote_rsp_payload_data (systemDebugger_1_io_remote_rsp_payload_data[31:0]), //o + .io_mem_cmd_valid (systemDebugger_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (system_cpu_debug_bus_cmd_ready ), //i + .io_mem_cmd_payload_address (systemDebugger_1_io_mem_cmd_payload_address[31:0]), //o + .io_mem_cmd_payload_data (systemDebugger_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_wr (systemDebugger_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_size (systemDebugger_1_io_mem_cmd_payload_size[1:0] ), //o + .io_mem_rsp_valid (toplevel_system_cpu_debug_bus_cmd_fire_regNext ), //i + .io_mem_rsp_payload (system_cpu_debug_bus_rsp_data[31:0] ), //i + .io_mainClk (io_mainClk ), //i + .resetCtrl_mainClkReset (resetCtrl_mainClkReset ) //i + ); + MuraxPipelinedMemoryBusRam system_ram ( + .io_bus_cmd_valid (system_ram_io_bus_cmd_valid ), //i + .io_bus_cmd_ready (system_ram_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_write (_zz_io_bus_cmd_payload_write ), //i + .io_bus_cmd_payload_address (system_mainBusDecoder_logic_masterPipelined_cmd_payload_address[31:0]), //i + .io_bus_cmd_payload_data (system_mainBusDecoder_logic_masterPipelined_cmd_payload_data[31:0] ), //i + .io_bus_cmd_payload_mask (system_mainBusDecoder_logic_masterPipelined_cmd_payload_mask[3:0] ), //i + .io_bus_rsp_valid (system_ram_io_bus_rsp_valid ), //o + .io_bus_rsp_payload_data (system_ram_io_bus_rsp_payload_data[31:0] ), //o + .io_mainClk (io_mainClk ), //i + .resetCtrl_systemReset (resetCtrl_systemReset ) //i + ); + PipelinedMemoryBusToApbBridge system_apbBridge ( + .io_pipelinedMemoryBus_cmd_valid (system_apbBridge_io_pipelinedMemoryBus_cmd_valid ), //i + .io_pipelinedMemoryBus_cmd_ready (system_apbBridge_io_pipelinedMemoryBus_cmd_ready ), //o + .io_pipelinedMemoryBus_cmd_payload_write (_zz_io_pipelinedMemoryBus_cmd_payload_write ), //i + .io_pipelinedMemoryBus_cmd_payload_address (system_mainBusDecoder_logic_masterPipelined_cmd_payload_address[31:0]), //i + .io_pipelinedMemoryBus_cmd_payload_data (system_mainBusDecoder_logic_masterPipelined_cmd_payload_data[31:0] ), //i + .io_pipelinedMemoryBus_cmd_payload_mask (system_mainBusDecoder_logic_masterPipelined_cmd_payload_mask[3:0] ), //i + .io_pipelinedMemoryBus_rsp_valid (system_apbBridge_io_pipelinedMemoryBus_rsp_valid ), //o + .io_pipelinedMemoryBus_rsp_payload_data (system_apbBridge_io_pipelinedMemoryBus_rsp_payload_data[31:0] ), //o + .io_apb_PADDR (system_apbBridge_io_apb_PADDR[19:0] ), //o + .io_apb_PSEL (system_apbBridge_io_apb_PSEL ), //o + .io_apb_PENABLE (system_apbBridge_io_apb_PENABLE ), //o + .io_apb_PREADY (io_apb_decoder_io_input_PREADY ), //i + .io_apb_PWRITE (system_apbBridge_io_apb_PWRITE ), //o + .io_apb_PWDATA (system_apbBridge_io_apb_PWDATA[31:0] ), //o + .io_apb_PRDATA (io_apb_decoder_io_input_PRDATA[31:0] ), //i + .io_apb_PSLVERROR (io_apb_decoder_io_input_PSLVERROR ), //i + .io_mainClk (io_mainClk ), //i + .resetCtrl_systemReset (resetCtrl_systemReset ) //i + ); + Apb3Gpio system_gpioACtrl ( + .io_apb_PADDR (system_gpioACtrl_io_apb_PADDR[3:0] ), //i + .io_apb_PSEL (apb3Router_1_io_outputs_0_PSEL ), //i + .io_apb_PENABLE (apb3Router_1_io_outputs_0_PENABLE ), //i + .io_apb_PREADY (system_gpioACtrl_io_apb_PREADY ), //o + .io_apb_PWRITE (apb3Router_1_io_outputs_0_PWRITE ), //i + .io_apb_PWDATA (apb3Router_1_io_outputs_0_PWDATA[31:0] ), //i + .io_apb_PRDATA (system_gpioACtrl_io_apb_PRDATA[31:0] ), //o + .io_apb_PSLVERROR (system_gpioACtrl_io_apb_PSLVERROR ), //o + .io_gpio_read (io_gpioA_read[31:0] ), //i + .io_gpio_write (system_gpioACtrl_io_gpio_write[31:0] ), //o + .io_gpio_writeEnable (system_gpioACtrl_io_gpio_writeEnable[31:0]), //o + .io_value (system_gpioACtrl_io_value[31:0] ), //o + .io_mainClk (io_mainClk ), //i + .resetCtrl_systemReset (resetCtrl_systemReset ) //i + ); + Apb3UartCtrl system_uartCtrl ( + .io_apb_PADDR (system_uartCtrl_io_apb_PADDR[4:0] ), //i + .io_apb_PSEL (apb3Router_1_io_outputs_1_PSEL ), //i + .io_apb_PENABLE (apb3Router_1_io_outputs_1_PENABLE ), //i + .io_apb_PREADY (system_uartCtrl_io_apb_PREADY ), //o + .io_apb_PWRITE (apb3Router_1_io_outputs_1_PWRITE ), //i + .io_apb_PWDATA (apb3Router_1_io_outputs_1_PWDATA[31:0]), //i + .io_apb_PRDATA (system_uartCtrl_io_apb_PRDATA[31:0] ), //o + .io_uart_txd (system_uartCtrl_io_uart_txd ), //o + .io_uart_rxd (io_uart_rxd ), //i + .io_interrupt (system_uartCtrl_io_interrupt ), //o + .io_mainClk (io_mainClk ), //i + .resetCtrl_systemReset (resetCtrl_systemReset ) //i + ); + MuraxApb3Timer system_timer ( + .io_apb_PADDR (system_timer_io_apb_PADDR[7:0] ), //i + .io_apb_PSEL (apb3Router_1_io_outputs_2_PSEL ), //i + .io_apb_PENABLE (apb3Router_1_io_outputs_2_PENABLE ), //i + .io_apb_PREADY (system_timer_io_apb_PREADY ), //o + .io_apb_PWRITE (apb3Router_1_io_outputs_2_PWRITE ), //i + .io_apb_PWDATA (apb3Router_1_io_outputs_2_PWDATA[31:0]), //i + .io_apb_PRDATA (system_timer_io_apb_PRDATA[31:0] ), //o + .io_apb_PSLVERROR (system_timer_io_apb_PSLVERROR ), //o + .io_interrupt (system_timer_io_interrupt ), //o + .io_mainClk (io_mainClk ), //i + .resetCtrl_systemReset (resetCtrl_systemReset ) //i + ); + Apb3Decoder io_apb_decoder ( + .io_input_PADDR (system_apbBridge_io_apb_PADDR[19:0] ), //i + .io_input_PSEL (system_apbBridge_io_apb_PSEL ), //i + .io_input_PENABLE (system_apbBridge_io_apb_PENABLE ), //i + .io_input_PREADY (io_apb_decoder_io_input_PREADY ), //o + .io_input_PWRITE (system_apbBridge_io_apb_PWRITE ), //i + .io_input_PWDATA (system_apbBridge_io_apb_PWDATA[31:0] ), //i + .io_input_PRDATA (io_apb_decoder_io_input_PRDATA[31:0] ), //o + .io_input_PSLVERROR (io_apb_decoder_io_input_PSLVERROR ), //o + .io_output_PADDR (io_apb_decoder_io_output_PADDR[19:0] ), //o + .io_output_PSEL (io_apb_decoder_io_output_PSEL[2:0] ), //o + .io_output_PENABLE (io_apb_decoder_io_output_PENABLE ), //o + .io_output_PREADY (apb3Router_1_io_input_PREADY ), //i + .io_output_PWRITE (io_apb_decoder_io_output_PWRITE ), //o + .io_output_PWDATA (io_apb_decoder_io_output_PWDATA[31:0]), //o + .io_output_PRDATA (apb3Router_1_io_input_PRDATA[31:0] ), //i + .io_output_PSLVERROR (apb3Router_1_io_input_PSLVERROR ) //i + ); + Apb3Router apb3Router_1 ( + .io_input_PADDR (io_apb_decoder_io_output_PADDR[19:0] ), //i + .io_input_PSEL (io_apb_decoder_io_output_PSEL[2:0] ), //i + .io_input_PENABLE (io_apb_decoder_io_output_PENABLE ), //i + .io_input_PREADY (apb3Router_1_io_input_PREADY ), //o + .io_input_PWRITE (io_apb_decoder_io_output_PWRITE ), //i + .io_input_PWDATA (io_apb_decoder_io_output_PWDATA[31:0] ), //i + .io_input_PRDATA (apb3Router_1_io_input_PRDATA[31:0] ), //o + .io_input_PSLVERROR (apb3Router_1_io_input_PSLVERROR ), //o + .io_outputs_0_PADDR (apb3Router_1_io_outputs_0_PADDR[19:0] ), //o + .io_outputs_0_PSEL (apb3Router_1_io_outputs_0_PSEL ), //o + .io_outputs_0_PENABLE (apb3Router_1_io_outputs_0_PENABLE ), //o + .io_outputs_0_PREADY (system_gpioACtrl_io_apb_PREADY ), //i + .io_outputs_0_PWRITE (apb3Router_1_io_outputs_0_PWRITE ), //o + .io_outputs_0_PWDATA (apb3Router_1_io_outputs_0_PWDATA[31:0]), //o + .io_outputs_0_PRDATA (system_gpioACtrl_io_apb_PRDATA[31:0] ), //i + .io_outputs_0_PSLVERROR (system_gpioACtrl_io_apb_PSLVERROR ), //i + .io_outputs_1_PADDR (apb3Router_1_io_outputs_1_PADDR[19:0] ), //o + .io_outputs_1_PSEL (apb3Router_1_io_outputs_1_PSEL ), //o + .io_outputs_1_PENABLE (apb3Router_1_io_outputs_1_PENABLE ), //o + .io_outputs_1_PREADY (system_uartCtrl_io_apb_PREADY ), //i + .io_outputs_1_PWRITE (apb3Router_1_io_outputs_1_PWRITE ), //o + .io_outputs_1_PWDATA (apb3Router_1_io_outputs_1_PWDATA[31:0]), //o + .io_outputs_1_PRDATA (system_uartCtrl_io_apb_PRDATA[31:0] ), //i + .io_outputs_1_PSLVERROR (1'b0 ), //i + .io_outputs_2_PADDR (apb3Router_1_io_outputs_2_PADDR[19:0] ), //o + .io_outputs_2_PSEL (apb3Router_1_io_outputs_2_PSEL ), //o + .io_outputs_2_PENABLE (apb3Router_1_io_outputs_2_PENABLE ), //o + .io_outputs_2_PREADY (system_timer_io_apb_PREADY ), //i + .io_outputs_2_PWRITE (apb3Router_1_io_outputs_2_PWRITE ), //o + .io_outputs_2_PWDATA (apb3Router_1_io_outputs_2_PWDATA[31:0]), //o + .io_outputs_2_PRDATA (system_timer_io_apb_PRDATA[31:0] ), //i + .io_outputs_2_PSLVERROR (system_timer_io_apb_PSLVERROR ), //i + .io_mainClk (io_mainClk ), //i + .resetCtrl_systemReset (resetCtrl_systemReset ) //i + ); + initial begin + resetCtrl_systemClkResetCounter = 6'h0; + end + + always @(*) begin + case(system_mainBusDecoder_logic_rspSourceId) + 1'b0 : _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data = system_ram_io_bus_rsp_payload_data; + default : _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data = system_apbBridge_io_pipelinedMemoryBus_rsp_payload_data; + endcase + end + + always @(*) begin + resetCtrl_mainClkResetUnbuffered = 1'b0; + if(when_Murax_l196) begin + resetCtrl_mainClkResetUnbuffered = 1'b1; + end + end + + assign _zz_when_Murax_l196[5 : 0] = 6'h3f; + assign when_Murax_l196 = (resetCtrl_systemClkResetCounter != _zz_when_Murax_l196); + assign when_Murax_l200 = io_asyncReset_buffercc_io_dataOut; + always @(*) begin + system_timerInterrupt = 1'b0; + if(system_timer_io_interrupt) begin + system_timerInterrupt = 1'b1; + end + end + + always @(*) begin + system_externalInterrupt = 1'b0; + if(system_uartCtrl_io_interrupt) begin + system_externalInterrupt = 1'b1; + end + end + + assign toplevel_system_cpu_dBus_cmd_halfPipe_fire = (toplevel_system_cpu_dBus_cmd_halfPipe_valid && toplevel_system_cpu_dBus_cmd_halfPipe_ready); + assign system_cpu_dBus_cmd_ready = (! toplevel_system_cpu_dBus_cmd_rValid); + assign toplevel_system_cpu_dBus_cmd_halfPipe_valid = toplevel_system_cpu_dBus_cmd_rValid; + assign toplevel_system_cpu_dBus_cmd_halfPipe_payload_wr = toplevel_system_cpu_dBus_cmd_rData_wr; + assign toplevel_system_cpu_dBus_cmd_halfPipe_payload_mask = toplevel_system_cpu_dBus_cmd_rData_mask; + assign toplevel_system_cpu_dBus_cmd_halfPipe_payload_address = toplevel_system_cpu_dBus_cmd_rData_address; + assign toplevel_system_cpu_dBus_cmd_halfPipe_payload_data = toplevel_system_cpu_dBus_cmd_rData_data; + assign toplevel_system_cpu_dBus_cmd_halfPipe_payload_size = toplevel_system_cpu_dBus_cmd_rData_size; + assign toplevel_system_cpu_dBus_cmd_halfPipe_ready = system_mainBusArbiter_io_dBus_cmd_ready; + assign system_cpu_debug_bus_cmd_payload_address = systemDebugger_1_io_mem_cmd_payload_address[7:0]; + assign toplevel_system_cpu_debug_bus_cmd_fire = (systemDebugger_1_io_mem_cmd_valid && system_cpu_debug_bus_cmd_ready); + assign io_jtag_tdo = jtagBridge_1_io_jtag_tdo; + assign io_gpioA_write = system_gpioACtrl_io_gpio_write; + assign io_gpioA_writeEnable = system_gpioACtrl_io_gpio_writeEnable; + assign io_uart_txd = system_uartCtrl_io_uart_txd; + assign system_gpioACtrl_io_apb_PADDR = apb3Router_1_io_outputs_0_PADDR[3:0]; + assign system_uartCtrl_io_apb_PADDR = apb3Router_1_io_outputs_1_PADDR[4:0]; + assign system_timer_io_apb_PADDR = apb3Router_1_io_outputs_2_PADDR[7:0]; + assign system_mainBusDecoder_logic_masterPipelined_cmd_valid = system_mainBusArbiter_io_masterBus_cmd_valid; + assign system_mainBusDecoder_logic_masterPipelined_cmd_payload_write = system_mainBusArbiter_io_masterBus_cmd_payload_write; + assign system_mainBusDecoder_logic_masterPipelined_cmd_payload_address = system_mainBusArbiter_io_masterBus_cmd_payload_address; + assign system_mainBusDecoder_logic_masterPipelined_cmd_payload_data = system_mainBusArbiter_io_masterBus_cmd_payload_data; + assign system_mainBusDecoder_logic_masterPipelined_cmd_payload_mask = system_mainBusArbiter_io_masterBus_cmd_payload_mask; + assign system_mainBusDecoder_logic_hits_0 = ((system_mainBusDecoder_logic_masterPipelined_cmd_payload_address & (~ 32'h00000fff)) == 32'h80000000); + always @(*) begin + system_ram_io_bus_cmd_valid = (system_mainBusDecoder_logic_masterPipelined_cmd_valid && system_mainBusDecoder_logic_hits_0); + if(when_MuraxUtiles_l133) begin + system_ram_io_bus_cmd_valid = 1'b0; + end + end + + assign _zz_io_bus_cmd_payload_write = system_mainBusDecoder_logic_masterPipelined_cmd_payload_write; + assign system_mainBusDecoder_logic_hits_1 = ((system_mainBusDecoder_logic_masterPipelined_cmd_payload_address & (~ 32'h000fffff)) == 32'hf0000000); + always @(*) begin + system_apbBridge_io_pipelinedMemoryBus_cmd_valid = (system_mainBusDecoder_logic_masterPipelined_cmd_valid && system_mainBusDecoder_logic_hits_1); + if(when_MuraxUtiles_l133) begin + system_apbBridge_io_pipelinedMemoryBus_cmd_valid = 1'b0; + end + end + + assign _zz_io_pipelinedMemoryBus_cmd_payload_write = system_mainBusDecoder_logic_masterPipelined_cmd_payload_write; + assign system_mainBusDecoder_logic_noHit = (! (|{system_mainBusDecoder_logic_hits_1,system_mainBusDecoder_logic_hits_0})); + always @(*) begin + system_mainBusDecoder_logic_masterPipelined_cmd_ready = ((|{(system_mainBusDecoder_logic_hits_1 && system_apbBridge_io_pipelinedMemoryBus_cmd_ready),(system_mainBusDecoder_logic_hits_0 && system_ram_io_bus_cmd_ready)}) || system_mainBusDecoder_logic_noHit); + if(when_MuraxUtiles_l133) begin + system_mainBusDecoder_logic_masterPipelined_cmd_ready = 1'b0; + end + end + + assign system_mainBusDecoder_logic_masterPipelined_cmd_fire = (system_mainBusDecoder_logic_masterPipelined_cmd_valid && system_mainBusDecoder_logic_masterPipelined_cmd_ready); + assign when_MuraxUtiles_l127 = (system_mainBusDecoder_logic_masterPipelined_cmd_fire && (! system_mainBusDecoder_logic_masterPipelined_cmd_payload_write)); + assign system_mainBusDecoder_logic_masterPipelined_rsp_valid = ((|{system_apbBridge_io_pipelinedMemoryBus_rsp_valid,system_ram_io_bus_rsp_valid}) || (system_mainBusDecoder_logic_rspPending && system_mainBusDecoder_logic_rspNoHit)); + assign system_mainBusDecoder_logic_masterPipelined_rsp_payload_data = _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data; + assign when_MuraxUtiles_l133 = (system_mainBusDecoder_logic_rspPending && (! system_mainBusDecoder_logic_masterPipelined_rsp_valid)); + always @(posedge io_mainClk) begin + if(when_Murax_l196) begin + resetCtrl_systemClkResetCounter <= (resetCtrl_systemClkResetCounter + 6'h01); + end + if(when_Murax_l200) begin + resetCtrl_systemClkResetCounter <= 6'h0; + end + end + + always @(posedge io_mainClk) begin + resetCtrl_mainClkReset <= resetCtrl_mainClkResetUnbuffered; + resetCtrl_systemReset <= resetCtrl_mainClkResetUnbuffered; + if(toplevel_system_cpu_debug_resetOut_regNext) begin + resetCtrl_systemReset <= 1'b1; + end + end + + always @(posedge io_mainClk or posedge resetCtrl_systemReset) begin + if(resetCtrl_systemReset) begin + toplevel_system_cpu_dBus_cmd_rValid <= 1'b0; + system_mainBusDecoder_logic_rspPending <= 1'b0; + system_mainBusDecoder_logic_rspNoHit <= 1'b0; + end else begin + if(system_cpu_dBus_cmd_valid) begin + toplevel_system_cpu_dBus_cmd_rValid <= 1'b1; + end + if(toplevel_system_cpu_dBus_cmd_halfPipe_fire) begin + toplevel_system_cpu_dBus_cmd_rValid <= 1'b0; + end + if(system_mainBusDecoder_logic_masterPipelined_rsp_valid) begin + system_mainBusDecoder_logic_rspPending <= 1'b0; + end + if(when_MuraxUtiles_l127) begin + system_mainBusDecoder_logic_rspPending <= 1'b1; + end + system_mainBusDecoder_logic_rspNoHit <= 1'b0; + if(system_mainBusDecoder_logic_noHit) begin + system_mainBusDecoder_logic_rspNoHit <= 1'b1; + end + end + end + + always @(posedge io_mainClk) begin + if(system_cpu_dBus_cmd_ready) begin + toplevel_system_cpu_dBus_cmd_rData_wr <= system_cpu_dBus_cmd_payload_wr; + toplevel_system_cpu_dBus_cmd_rData_mask <= system_cpu_dBus_cmd_payload_mask; + toplevel_system_cpu_dBus_cmd_rData_address <= system_cpu_dBus_cmd_payload_address; + toplevel_system_cpu_dBus_cmd_rData_data <= system_cpu_dBus_cmd_payload_data; + toplevel_system_cpu_dBus_cmd_rData_size <= system_cpu_dBus_cmd_payload_size; + end + if(system_mainBusDecoder_logic_masterPipelined_cmd_fire) begin + system_mainBusDecoder_logic_rspSourceId <= system_mainBusDecoder_logic_hits_1; + end + end + + always @(posedge io_mainClk) begin + toplevel_system_cpu_debug_resetOut_regNext <= system_cpu_debug_resetOut; + end + + always @(posedge io_mainClk or posedge resetCtrl_mainClkReset) begin + if(resetCtrl_mainClkReset) begin + toplevel_system_cpu_debug_bus_cmd_fire_regNext <= 1'b0; + end else begin + toplevel_system_cpu_debug_bus_cmd_fire_regNext <= toplevel_system_cpu_debug_bus_cmd_fire; + end + end + + +endmodule + +module Apb3Router ( + input wire [19:0] io_input_PADDR, + input wire [2:0] io_input_PSEL, + input wire io_input_PENABLE, + output wire io_input_PREADY, + input wire io_input_PWRITE, + input wire [31:0] io_input_PWDATA, + output wire [31:0] io_input_PRDATA, + output wire io_input_PSLVERROR, + output wire [19:0] io_outputs_0_PADDR, + output wire [0:0] io_outputs_0_PSEL, + output wire io_outputs_0_PENABLE, + input wire io_outputs_0_PREADY, + output wire io_outputs_0_PWRITE, + output wire [31:0] io_outputs_0_PWDATA, + input wire [31:0] io_outputs_0_PRDATA, + input wire io_outputs_0_PSLVERROR, + output wire [19:0] io_outputs_1_PADDR, + output wire [0:0] io_outputs_1_PSEL, + output wire io_outputs_1_PENABLE, + input wire io_outputs_1_PREADY, + output wire io_outputs_1_PWRITE, + output wire [31:0] io_outputs_1_PWDATA, + input wire [31:0] io_outputs_1_PRDATA, + input wire io_outputs_1_PSLVERROR, + output wire [19:0] io_outputs_2_PADDR, + output wire [0:0] io_outputs_2_PSEL, + output wire io_outputs_2_PENABLE, + input wire io_outputs_2_PREADY, + output wire io_outputs_2_PWRITE, + output wire [31:0] io_outputs_2_PWDATA, + input wire [31:0] io_outputs_2_PRDATA, + input wire io_outputs_2_PSLVERROR, + input wire io_mainClk, + input wire resetCtrl_systemReset +); + + reg _zz_io_input_PREADY; + reg [31:0] _zz_io_input_PRDATA; + reg _zz_io_input_PSLVERROR; + wire _zz_selIndex; + wire _zz_selIndex_1; + reg [1:0] selIndex; + + always @(*) begin + case(selIndex) + 2'b00 : begin + _zz_io_input_PREADY = io_outputs_0_PREADY; + _zz_io_input_PRDATA = io_outputs_0_PRDATA; + _zz_io_input_PSLVERROR = io_outputs_0_PSLVERROR; + end + 2'b01 : begin + _zz_io_input_PREADY = io_outputs_1_PREADY; + _zz_io_input_PRDATA = io_outputs_1_PRDATA; + _zz_io_input_PSLVERROR = io_outputs_1_PSLVERROR; + end + default : begin + _zz_io_input_PREADY = io_outputs_2_PREADY; + _zz_io_input_PRDATA = io_outputs_2_PRDATA; + _zz_io_input_PSLVERROR = io_outputs_2_PSLVERROR; + end + endcase + end + + assign io_outputs_0_PADDR = io_input_PADDR; + assign io_outputs_0_PENABLE = io_input_PENABLE; + assign io_outputs_0_PSEL[0] = io_input_PSEL[0]; + assign io_outputs_0_PWRITE = io_input_PWRITE; + assign io_outputs_0_PWDATA = io_input_PWDATA; + assign io_outputs_1_PADDR = io_input_PADDR; + assign io_outputs_1_PENABLE = io_input_PENABLE; + assign io_outputs_1_PSEL[0] = io_input_PSEL[1]; + assign io_outputs_1_PWRITE = io_input_PWRITE; + assign io_outputs_1_PWDATA = io_input_PWDATA; + assign io_outputs_2_PADDR = io_input_PADDR; + assign io_outputs_2_PENABLE = io_input_PENABLE; + assign io_outputs_2_PSEL[0] = io_input_PSEL[2]; + assign io_outputs_2_PWRITE = io_input_PWRITE; + assign io_outputs_2_PWDATA = io_input_PWDATA; + assign _zz_selIndex = io_input_PSEL[1]; + assign _zz_selIndex_1 = io_input_PSEL[2]; + assign io_input_PREADY = _zz_io_input_PREADY; + assign io_input_PRDATA = _zz_io_input_PRDATA; + assign io_input_PSLVERROR = _zz_io_input_PSLVERROR; + always @(posedge io_mainClk) begin + selIndex <= {_zz_selIndex_1,_zz_selIndex}; + end + + +endmodule + +module Apb3Decoder ( + input wire [19:0] io_input_PADDR, + input wire [0:0] io_input_PSEL, + input wire io_input_PENABLE, + output reg io_input_PREADY, + input wire io_input_PWRITE, + input wire [31:0] io_input_PWDATA, + output wire [31:0] io_input_PRDATA, + output reg io_input_PSLVERROR, + output wire [19:0] io_output_PADDR, + output reg [2:0] io_output_PSEL, + output wire io_output_PENABLE, + input wire io_output_PREADY, + output wire io_output_PWRITE, + output wire [31:0] io_output_PWDATA, + input wire [31:0] io_output_PRDATA, + input wire io_output_PSLVERROR +); + + wire when_Apb3Decoder_l88; + + assign io_output_PADDR = io_input_PADDR; + assign io_output_PENABLE = io_input_PENABLE; + assign io_output_PWRITE = io_input_PWRITE; + assign io_output_PWDATA = io_input_PWDATA; + always @(*) begin + io_output_PSEL[0] = (((io_input_PADDR & (~ 20'h00fff)) == 20'h0) && io_input_PSEL[0]); + io_output_PSEL[1] = (((io_input_PADDR & (~ 20'h00fff)) == 20'h10000) && io_input_PSEL[0]); + io_output_PSEL[2] = (((io_input_PADDR & (~ 20'h00fff)) == 20'h20000) && io_input_PSEL[0]); + end + + always @(*) begin + io_input_PREADY = io_output_PREADY; + if(when_Apb3Decoder_l88) begin + io_input_PREADY = 1'b1; + end + end + + assign io_input_PRDATA = io_output_PRDATA; + always @(*) begin + io_input_PSLVERROR = io_output_PSLVERROR; + if(when_Apb3Decoder_l88) begin + io_input_PSLVERROR = 1'b1; + end + end + + assign when_Apb3Decoder_l88 = (io_input_PSEL[0] && (io_output_PSEL == 3'b000)); + +endmodule + +module MuraxApb3Timer ( + input wire [7:0] io_apb_PADDR, + input wire [0:0] io_apb_PSEL, + input wire io_apb_PENABLE, + output wire io_apb_PREADY, + input wire io_apb_PWRITE, + input wire [31:0] io_apb_PWDATA, + output reg [31:0] io_apb_PRDATA, + output wire io_apb_PSLVERROR, + output wire io_interrupt, + input wire io_mainClk, + input wire resetCtrl_systemReset +); + + wire timerA_io_tick; + wire timerA_io_clear; + wire timerB_io_tick; + wire timerB_io_clear; + reg [1:0] interruptCtrl_1_io_inputs; + reg [1:0] interruptCtrl_1_io_clears; + wire prescaler_1_io_overflow; + wire timerA_io_full; + wire [15:0] timerA_io_value; + wire timerB_io_full; + wire [15:0] timerB_io_value; + wire [1:0] interruptCtrl_1_io_pendings; + wire busCtrl_readErrorFlag; + wire busCtrl_writeErrorFlag; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire busCtrl_doWrite; + wire busCtrl_doRead; + reg [15:0] _zz_io_limit; + reg _zz_io_clear; + reg [1:0] timerABridge_ticksEnable; + reg [0:0] timerABridge_clearsEnable; + reg timerABridge_busClearing; + reg [15:0] system_timer_timerA_io_limit_driver; + reg when_Timer_l40; + reg when_Timer_l44; + reg [1:0] timerBBridge_ticksEnable; + reg [0:0] timerBBridge_clearsEnable; + reg timerBBridge_busClearing; + reg [15:0] system_timer_timerB_io_limit_driver; + reg when_Timer_l40_1; + reg when_Timer_l44_1; + reg [1:0] system_timer_interruptCtrl_1_io_masks_driver; + + Prescaler prescaler_1 ( + .io_clear (_zz_io_clear ), //i + .io_limit (_zz_io_limit[15:0] ), //i + .io_overflow (prescaler_1_io_overflow), //o + .io_mainClk (io_mainClk ), //i + .resetCtrl_systemReset (resetCtrl_systemReset ) //i + ); + Timer timerA ( + .io_tick (timerA_io_tick ), //i + .io_clear (timerA_io_clear ), //i + .io_limit (system_timer_timerA_io_limit_driver[15:0]), //i + .io_full (timerA_io_full ), //o + .io_value (timerA_io_value[15:0] ), //o + .io_mainClk (io_mainClk ), //i + .resetCtrl_systemReset (resetCtrl_systemReset ) //i + ); + Timer timerB ( + .io_tick (timerB_io_tick ), //i + .io_clear (timerB_io_clear ), //i + .io_limit (system_timer_timerB_io_limit_driver[15:0]), //i + .io_full (timerB_io_full ), //o + .io_value (timerB_io_value[15:0] ), //o + .io_mainClk (io_mainClk ), //i + .resetCtrl_systemReset (resetCtrl_systemReset ) //i + ); + InterruptCtrl interruptCtrl_1 ( + .io_inputs (interruptCtrl_1_io_inputs[1:0] ), //i + .io_clears (interruptCtrl_1_io_clears[1:0] ), //i + .io_masks (system_timer_interruptCtrl_1_io_masks_driver[1:0]), //i + .io_pendings (interruptCtrl_1_io_pendings[1:0] ), //o + .io_mainClk (io_mainClk ), //i + .resetCtrl_systemReset (resetCtrl_systemReset ) //i + ); + assign busCtrl_readErrorFlag = 1'b0; + assign busCtrl_writeErrorFlag = 1'b0; + assign io_apb_PREADY = 1'b1; + always @(*) begin + io_apb_PRDATA = 32'h0; + case(io_apb_PADDR) + 8'h0 : begin + io_apb_PRDATA[15 : 0] = _zz_io_limit; + end + 8'h40 : begin + io_apb_PRDATA[1 : 0] = timerABridge_ticksEnable; + io_apb_PRDATA[16 : 16] = timerABridge_clearsEnable; + end + 8'h44 : begin + io_apb_PRDATA[15 : 0] = system_timer_timerA_io_limit_driver; + end + 8'h48 : begin + io_apb_PRDATA[15 : 0] = timerA_io_value; + end + 8'h50 : begin + io_apb_PRDATA[1 : 0] = timerBBridge_ticksEnable; + io_apb_PRDATA[16 : 16] = timerBBridge_clearsEnable; + end + 8'h54 : begin + io_apb_PRDATA[15 : 0] = system_timer_timerB_io_limit_driver; + end + 8'h58 : begin + io_apb_PRDATA[15 : 0] = timerB_io_value; + end + 8'h10 : begin + io_apb_PRDATA[1 : 0] = interruptCtrl_1_io_pendings; + end + 8'h14 : begin + io_apb_PRDATA[1 : 0] = system_timer_interruptCtrl_1_io_masks_driver; + end + default : begin + end + endcase + end + + assign busCtrl_askWrite = ((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PWRITE); + assign busCtrl_askRead = ((io_apb_PSEL[0] && io_apb_PENABLE) && (! io_apb_PWRITE)); + assign busCtrl_doWrite = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && io_apb_PWRITE); + assign busCtrl_doRead = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && (! io_apb_PWRITE)); + assign io_apb_PSLVERROR = ((busCtrl_doWrite && busCtrl_writeErrorFlag) || (busCtrl_doRead && busCtrl_readErrorFlag)); + always @(*) begin + _zz_io_clear = 1'b0; + case(io_apb_PADDR) + 8'h0 : begin + if(busCtrl_doWrite) begin + _zz_io_clear = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + timerABridge_busClearing = 1'b0; + if(when_Timer_l40) begin + timerABridge_busClearing = 1'b1; + end + if(when_Timer_l44) begin + timerABridge_busClearing = 1'b1; + end + end + + always @(*) begin + when_Timer_l40 = 1'b0; + case(io_apb_PADDR) + 8'h44 : begin + if(busCtrl_doWrite) begin + when_Timer_l40 = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + when_Timer_l44 = 1'b0; + case(io_apb_PADDR) + 8'h48 : begin + if(busCtrl_doWrite) begin + when_Timer_l44 = 1'b1; + end + end + default : begin + end + endcase + end + + assign timerA_io_clear = ((|(timerABridge_clearsEnable & timerA_io_full)) || timerABridge_busClearing); + assign timerA_io_tick = (|(timerABridge_ticksEnable & {prescaler_1_io_overflow,1'b1})); + always @(*) begin + timerBBridge_busClearing = 1'b0; + if(when_Timer_l40_1) begin + timerBBridge_busClearing = 1'b1; + end + if(when_Timer_l44_1) begin + timerBBridge_busClearing = 1'b1; + end + end + + always @(*) begin + when_Timer_l40_1 = 1'b0; + case(io_apb_PADDR) + 8'h54 : begin + if(busCtrl_doWrite) begin + when_Timer_l40_1 = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + when_Timer_l44_1 = 1'b0; + case(io_apb_PADDR) + 8'h58 : begin + if(busCtrl_doWrite) begin + when_Timer_l44_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign timerB_io_clear = ((|(timerBBridge_clearsEnable & timerB_io_full)) || timerBBridge_busClearing); + assign timerB_io_tick = (|(timerBBridge_ticksEnable & {prescaler_1_io_overflow,1'b1})); + always @(*) begin + interruptCtrl_1_io_clears = 2'b00; + case(io_apb_PADDR) + 8'h10 : begin + if(busCtrl_doWrite) begin + interruptCtrl_1_io_clears = io_apb_PWDATA[1 : 0]; + end + end + default : begin + end + endcase + end + + always @(*) begin + interruptCtrl_1_io_inputs[0] = timerA_io_full; + interruptCtrl_1_io_inputs[1] = timerB_io_full; + end + + assign io_interrupt = (|interruptCtrl_1_io_pendings); + always @(posedge io_mainClk or posedge resetCtrl_systemReset) begin + if(resetCtrl_systemReset) begin + timerABridge_ticksEnable <= 2'b00; + timerABridge_clearsEnable <= 1'b0; + timerBBridge_ticksEnable <= 2'b00; + timerBBridge_clearsEnable <= 1'b0; + system_timer_interruptCtrl_1_io_masks_driver <= 2'b00; + end else begin + case(io_apb_PADDR) + 8'h40 : begin + if(busCtrl_doWrite) begin + timerABridge_ticksEnable <= io_apb_PWDATA[1 : 0]; + timerABridge_clearsEnable <= io_apb_PWDATA[16 : 16]; + end + end + 8'h50 : begin + if(busCtrl_doWrite) begin + timerBBridge_ticksEnable <= io_apb_PWDATA[1 : 0]; + timerBBridge_clearsEnable <= io_apb_PWDATA[16 : 16]; + end + end + 8'h14 : begin + if(busCtrl_doWrite) begin + system_timer_interruptCtrl_1_io_masks_driver <= io_apb_PWDATA[1 : 0]; + end + end + default : begin + end + endcase + end + end + + always @(posedge io_mainClk) begin + case(io_apb_PADDR) + 8'h0 : begin + if(busCtrl_doWrite) begin + _zz_io_limit <= io_apb_PWDATA[15 : 0]; + end + end + 8'h44 : begin + if(busCtrl_doWrite) begin + system_timer_timerA_io_limit_driver <= io_apb_PWDATA[15 : 0]; + end + end + 8'h54 : begin + if(busCtrl_doWrite) begin + system_timer_timerB_io_limit_driver <= io_apb_PWDATA[15 : 0]; + end + end + default : begin + end + endcase + end + + +endmodule + +module Apb3UartCtrl ( + input wire [4:0] io_apb_PADDR, + input wire [0:0] io_apb_PSEL, + input wire io_apb_PENABLE, + output wire io_apb_PREADY, + input wire io_apb_PWRITE, + input wire [31:0] io_apb_PWDATA, + output reg [31:0] io_apb_PRDATA, + output wire io_uart_txd, + input wire io_uart_rxd, + output wire io_interrupt, + input wire io_mainClk, + input wire resetCtrl_systemReset +); + localparam UartStopType_ONE = 1'd0; + localparam UartStopType_TWO = 1'd1; + localparam UartParityType_NONE = 2'd0; + localparam UartParityType_EVEN = 2'd1; + localparam UartParityType_ODD = 2'd2; + + reg system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready; + wire uartCtrl_1_io_write_ready; + wire uartCtrl_1_io_read_valid; + wire [7:0] uartCtrl_1_io_read_payload; + wire uartCtrl_1_io_uart_txd; + wire uartCtrl_1_io_readError; + wire uartCtrl_1_io_readBreak; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload; + wire [4:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy; + wire [4:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_availability; + wire system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy_io_push_ready; + wire system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid; + wire [7:0] system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload; + wire [4:0] system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy_io_occupancy; + wire [4:0] system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy_io_availability; + wire [0:0] _zz_bridge_misc_readError; + wire [0:0] _zz_bridge_misc_readOverflowError; + wire [0:0] _zz_bridge_misc_breakDetected; + wire [0:0] _zz_bridge_misc_doBreak; + wire [0:0] _zz_bridge_misc_doBreak_1; + wire [4:0] _zz_io_apb_PRDATA; + wire busCtrl_readErrorFlag; + wire busCtrl_writeErrorFlag; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire busCtrl_doWrite; + wire busCtrl_doRead; + wire bridge_busCtrlWrapped_readErrorFlag; + wire bridge_busCtrlWrapped_writeErrorFlag; + wire [2:0] bridge_uartConfigReg_frame_dataLength; + wire [0:0] bridge_uartConfigReg_frame_stop; + wire [1:0] bridge_uartConfigReg_frame_parity; + reg [19:0] bridge_uartConfigReg_clockDivider; + reg _zz_bridge_write_streamUnbuffered_valid; + wire bridge_write_streamUnbuffered_valid; + wire bridge_write_streamUnbuffered_ready; + wire [7:0] bridge_write_streamUnbuffered_payload; + reg bridge_read_streamBreaked_valid; + reg bridge_read_streamBreaked_ready; + wire [7:0] bridge_read_streamBreaked_payload; + reg bridge_interruptCtrl_writeIntEnable; + reg bridge_interruptCtrl_readIntEnable; + wire bridge_interruptCtrl_readInt; + wire bridge_interruptCtrl_writeInt; + wire bridge_interruptCtrl_interrupt; + reg bridge_misc_readError; + reg when_BusSlaveFactory_l341; + wire when_BusSlaveFactory_l347; + reg bridge_misc_readOverflowError; + reg when_BusSlaveFactory_l341_1; + wire when_BusSlaveFactory_l347_1; + wire system_uartCtrl_uartCtrl_1_io_read_isStall; + reg bridge_misc_breakDetected; + reg system_uartCtrl_uartCtrl_1_io_readBreak_regNext; + wire when_UartCtrl_l155; + reg when_BusSlaveFactory_l341_2; + wire when_BusSlaveFactory_l347_2; + reg bridge_misc_doBreak; + reg when_BusSlaveFactory_l377; + wire when_BusSlaveFactory_l379; + reg when_BusSlaveFactory_l341_3; + wire when_BusSlaveFactory_l347_3; + `ifndef SYNTHESIS + reg [23:0] bridge_uartConfigReg_frame_stop_string; + reg [31:0] bridge_uartConfigReg_frame_parity_string; + `endif + + function [19:0] zz_bridge_uartConfigReg_clockDivider(input dummy); + begin + zz_bridge_uartConfigReg_clockDivider = 20'h0; + zz_bridge_uartConfigReg_clockDivider = 20'h00013; + end + endfunction + wire [19:0] _zz_1; + + assign _zz_bridge_misc_readError = 1'b0; + assign _zz_bridge_misc_readOverflowError = 1'b0; + assign _zz_bridge_misc_breakDetected = 1'b0; + assign _zz_bridge_misc_doBreak = 1'b1; + assign _zz_bridge_misc_doBreak_1 = 1'b0; + assign _zz_io_apb_PRDATA = (5'h10 - bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy); + UartCtrl uartCtrl_1 ( + .io_config_frame_dataLength (bridge_uartConfigReg_frame_dataLength[2:0] ), //i + .io_config_frame_stop (bridge_uartConfigReg_frame_stop ), //i + .io_config_frame_parity (bridge_uartConfigReg_frame_parity[1:0] ), //i + .io_config_clockDivider (bridge_uartConfigReg_clockDivider[19:0] ), //i + .io_write_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //i + .io_write_ready (uartCtrl_1_io_write_ready ), //o + .io_write_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0]), //i + .io_read_valid (uartCtrl_1_io_read_valid ), //o + .io_read_ready (system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy_io_push_ready ), //i + .io_read_payload (uartCtrl_1_io_read_payload[7:0] ), //o + .io_uart_txd (uartCtrl_1_io_uart_txd ), //o + .io_uart_rxd (io_uart_rxd ), //i + .io_readError (uartCtrl_1_io_readError ), //o + .io_writeBreak (bridge_misc_doBreak ), //i + .io_readBreak (uartCtrl_1_io_readBreak ), //o + .io_mainClk (io_mainClk ), //i + .resetCtrl_systemReset (resetCtrl_systemReset ) //i + ); + StreamFifo bridge_write_streamUnbuffered_queueWithOccupancy ( + .io_push_valid (bridge_write_streamUnbuffered_valid ), //i + .io_push_ready (bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (bridge_write_streamUnbuffered_payload[7:0] ), //i + .io_pop_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (uartCtrl_1_io_write_ready ), //i + .io_pop_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy[4:0] ), //o + .io_availability (bridge_write_streamUnbuffered_queueWithOccupancy_io_availability[4:0]), //o + .io_mainClk (io_mainClk ), //i + .resetCtrl_systemReset (resetCtrl_systemReset ) //i + ); + StreamFifo system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy ( + .io_push_valid (uartCtrl_1_io_read_valid ), //i + .io_push_ready (system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (uartCtrl_1_io_read_payload[7:0] ), //i + .io_pop_valid (system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready ), //i + .io_pop_payload (system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy_io_occupancy[4:0] ), //o + .io_availability (system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy_io_availability[4:0]), //o + .io_mainClk (io_mainClk ), //i + .resetCtrl_systemReset (resetCtrl_systemReset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(bridge_uartConfigReg_frame_stop) + UartStopType_ONE : bridge_uartConfigReg_frame_stop_string = "ONE"; + UartStopType_TWO : bridge_uartConfigReg_frame_stop_string = "TWO"; + default : bridge_uartConfigReg_frame_stop_string = "???"; + endcase + end + always @(*) begin + case(bridge_uartConfigReg_frame_parity) + UartParityType_NONE : bridge_uartConfigReg_frame_parity_string = "NONE"; + UartParityType_EVEN : bridge_uartConfigReg_frame_parity_string = "EVEN"; + UartParityType_ODD : bridge_uartConfigReg_frame_parity_string = "ODD "; + default : bridge_uartConfigReg_frame_parity_string = "????"; + endcase + end + `endif + + assign io_uart_txd = uartCtrl_1_io_uart_txd; + assign busCtrl_readErrorFlag = 1'b0; + assign busCtrl_writeErrorFlag = 1'b0; + assign io_apb_PREADY = 1'b1; + always @(*) begin + io_apb_PRDATA = 32'h0; + case(io_apb_PADDR) + 5'h0 : begin + io_apb_PRDATA[16 : 16] = (bridge_read_streamBreaked_valid ^ 1'b0); + io_apb_PRDATA[7 : 0] = bridge_read_streamBreaked_payload; + end + 5'h04 : begin + io_apb_PRDATA[20 : 16] = _zz_io_apb_PRDATA; + io_apb_PRDATA[15 : 15] = bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + io_apb_PRDATA[28 : 24] = system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy_io_occupancy; + io_apb_PRDATA[0 : 0] = bridge_interruptCtrl_writeIntEnable; + io_apb_PRDATA[1 : 1] = bridge_interruptCtrl_readIntEnable; + io_apb_PRDATA[8 : 8] = bridge_interruptCtrl_writeInt; + io_apb_PRDATA[9 : 9] = bridge_interruptCtrl_readInt; + end + 5'h10 : begin + io_apb_PRDATA[0 : 0] = bridge_misc_readError; + io_apb_PRDATA[1 : 1] = bridge_misc_readOverflowError; + io_apb_PRDATA[8 : 8] = uartCtrl_1_io_readBreak; + io_apb_PRDATA[9 : 9] = bridge_misc_breakDetected; + end + default : begin + end + endcase + end + + assign busCtrl_askWrite = ((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PWRITE); + assign busCtrl_askRead = ((io_apb_PSEL[0] && io_apb_PENABLE) && (! io_apb_PWRITE)); + assign busCtrl_doWrite = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && io_apb_PWRITE); + assign busCtrl_doRead = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && (! io_apb_PWRITE)); + assign bridge_busCtrlWrapped_readErrorFlag = 1'b0; + assign bridge_busCtrlWrapped_writeErrorFlag = 1'b0; + assign _zz_1 = zz_bridge_uartConfigReg_clockDivider(1'b0); + always @(*) bridge_uartConfigReg_clockDivider = _zz_1; + assign bridge_uartConfigReg_frame_dataLength = 3'b111; + assign bridge_uartConfigReg_frame_parity = UartParityType_NONE; + assign bridge_uartConfigReg_frame_stop = UartStopType_ONE; + always @(*) begin + _zz_bridge_write_streamUnbuffered_valid = 1'b0; + case(io_apb_PADDR) + 5'h0 : begin + if(busCtrl_doWrite) begin + _zz_bridge_write_streamUnbuffered_valid = 1'b1; + end + end + default : begin + end + endcase + end + + assign bridge_write_streamUnbuffered_valid = _zz_bridge_write_streamUnbuffered_valid; + assign bridge_write_streamUnbuffered_payload = io_apb_PWDATA[7 : 0]; + assign bridge_write_streamUnbuffered_ready = bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + always @(*) begin + bridge_read_streamBreaked_valid = system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid; + if(uartCtrl_1_io_readBreak) begin + bridge_read_streamBreaked_valid = 1'b0; + end + end + + always @(*) begin + system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready = bridge_read_streamBreaked_ready; + if(uartCtrl_1_io_readBreak) begin + system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready = 1'b1; + end + end + + assign bridge_read_streamBreaked_payload = system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload; + always @(*) begin + bridge_read_streamBreaked_ready = 1'b0; + case(io_apb_PADDR) + 5'h0 : begin + if(busCtrl_doRead) begin + bridge_read_streamBreaked_ready = 1'b1; + end + end + default : begin + end + endcase + end + + assign bridge_interruptCtrl_readInt = (bridge_interruptCtrl_readIntEnable && bridge_read_streamBreaked_valid); + assign bridge_interruptCtrl_writeInt = (bridge_interruptCtrl_writeIntEnable && (! bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid)); + assign bridge_interruptCtrl_interrupt = (bridge_interruptCtrl_readInt || bridge_interruptCtrl_writeInt); + always @(*) begin + when_BusSlaveFactory_l341 = 1'b0; + case(io_apb_PADDR) + 5'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347 = io_apb_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l341_1 = 1'b0; + case(io_apb_PADDR) + 5'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_1 = io_apb_PWDATA[1]; + assign system_uartCtrl_uartCtrl_1_io_read_isStall = (uartCtrl_1_io_read_valid && (! system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy_io_push_ready)); + assign when_UartCtrl_l155 = (uartCtrl_1_io_readBreak && (! system_uartCtrl_uartCtrl_1_io_readBreak_regNext)); + always @(*) begin + when_BusSlaveFactory_l341_2 = 1'b0; + case(io_apb_PADDR) + 5'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_2 = io_apb_PWDATA[9]; + always @(*) begin + when_BusSlaveFactory_l377 = 1'b0; + case(io_apb_PADDR) + 5'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l377 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379 = io_apb_PWDATA[10]; + always @(*) begin + when_BusSlaveFactory_l341_3 = 1'b0; + case(io_apb_PADDR) + 5'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_3 = io_apb_PWDATA[11]; + assign io_interrupt = bridge_interruptCtrl_interrupt; + always @(posedge io_mainClk or posedge resetCtrl_systemReset) begin + if(resetCtrl_systemReset) begin + bridge_interruptCtrl_writeIntEnable <= 1'b0; + bridge_interruptCtrl_readIntEnable <= 1'b0; + bridge_misc_readError <= 1'b0; + bridge_misc_readOverflowError <= 1'b0; + bridge_misc_breakDetected <= 1'b0; + bridge_misc_doBreak <= 1'b0; + end else begin + if(when_BusSlaveFactory_l341) begin + if(when_BusSlaveFactory_l347) begin + bridge_misc_readError <= _zz_bridge_misc_readError[0]; + end + end + if(uartCtrl_1_io_readError) begin + bridge_misc_readError <= 1'b1; + end + if(when_BusSlaveFactory_l341_1) begin + if(when_BusSlaveFactory_l347_1) begin + bridge_misc_readOverflowError <= _zz_bridge_misc_readOverflowError[0]; + end + end + if(system_uartCtrl_uartCtrl_1_io_read_isStall) begin + bridge_misc_readOverflowError <= 1'b1; + end + if(when_UartCtrl_l155) begin + bridge_misc_breakDetected <= 1'b1; + end + if(when_BusSlaveFactory_l341_2) begin + if(when_BusSlaveFactory_l347_2) begin + bridge_misc_breakDetected <= _zz_bridge_misc_breakDetected[0]; + end + end + if(when_BusSlaveFactory_l377) begin + if(when_BusSlaveFactory_l379) begin + bridge_misc_doBreak <= _zz_bridge_misc_doBreak[0]; + end + end + if(when_BusSlaveFactory_l341_3) begin + if(when_BusSlaveFactory_l347_3) begin + bridge_misc_doBreak <= _zz_bridge_misc_doBreak_1[0]; + end + end + case(io_apb_PADDR) + 5'h04 : begin + if(busCtrl_doWrite) begin + bridge_interruptCtrl_writeIntEnable <= io_apb_PWDATA[0]; + bridge_interruptCtrl_readIntEnable <= io_apb_PWDATA[1]; + end + end + default : begin + end + endcase + end + end + + always @(posedge io_mainClk) begin + system_uartCtrl_uartCtrl_1_io_readBreak_regNext <= uartCtrl_1_io_readBreak; + end + + +endmodule + +module Apb3Gpio ( + input wire [3:0] io_apb_PADDR, + input wire [0:0] io_apb_PSEL, + input wire io_apb_PENABLE, + output wire io_apb_PREADY, + input wire io_apb_PWRITE, + input wire [31:0] io_apb_PWDATA, + output reg [31:0] io_apb_PRDATA, + output wire io_apb_PSLVERROR, + input wire [31:0] io_gpio_read, + output wire [31:0] io_gpio_write, + output wire [31:0] io_gpio_writeEnable, + output wire [31:0] io_value, + input wire io_mainClk, + input wire resetCtrl_systemReset +); + + wire [31:0] io_gpio_read_buffercc_io_dataOut; + wire ctrl_readErrorFlag; + wire ctrl_writeErrorFlag; + wire ctrl_askWrite; + wire ctrl_askRead; + wire ctrl_doWrite; + wire ctrl_doRead; + reg [31:0] io_gpio_write_driver; + reg [31:0] io_gpio_writeEnable_driver; + + (* keep_hierarchy = "TRUE" *) BufferCC_1 io_gpio_read_buffercc ( + .io_dataIn (io_gpio_read[31:0] ), //i + .io_dataOut (io_gpio_read_buffercc_io_dataOut[31:0]), //o + .io_mainClk (io_mainClk ), //i + .resetCtrl_systemReset (resetCtrl_systemReset ) //i + ); + assign io_value = io_gpio_read_buffercc_io_dataOut; + assign ctrl_readErrorFlag = 1'b0; + assign ctrl_writeErrorFlag = 1'b0; + assign io_apb_PREADY = 1'b1; + always @(*) begin + io_apb_PRDATA = 32'h0; + case(io_apb_PADDR) + 4'b0000 : begin + io_apb_PRDATA[31 : 0] = io_value; + end + 4'b0100 : begin + io_apb_PRDATA[31 : 0] = io_gpio_write_driver; + end + 4'b1000 : begin + io_apb_PRDATA[31 : 0] = io_gpio_writeEnable_driver; + end + default : begin + end + endcase + end + + assign ctrl_askWrite = ((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PWRITE); + assign ctrl_askRead = ((io_apb_PSEL[0] && io_apb_PENABLE) && (! io_apb_PWRITE)); + assign ctrl_doWrite = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && io_apb_PWRITE); + assign ctrl_doRead = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && (! io_apb_PWRITE)); + assign io_apb_PSLVERROR = ((ctrl_doWrite && ctrl_writeErrorFlag) || (ctrl_doRead && ctrl_readErrorFlag)); + assign io_gpio_write = io_gpio_write_driver; + assign io_gpio_writeEnable = io_gpio_writeEnable_driver; + always @(posedge io_mainClk or posedge resetCtrl_systemReset) begin + if(resetCtrl_systemReset) begin + io_gpio_writeEnable_driver <= 32'h0; + end else begin + case(io_apb_PADDR) + 4'b1000 : begin + if(ctrl_doWrite) begin + io_gpio_writeEnable_driver <= io_apb_PWDATA[31 : 0]; + end + end + default : begin + end + endcase + end + end + + always @(posedge io_mainClk) begin + case(io_apb_PADDR) + 4'b0100 : begin + if(ctrl_doWrite) begin + io_gpio_write_driver <= io_apb_PWDATA[31 : 0]; + end + end + default : begin + end + endcase + end + + +endmodule + +module PipelinedMemoryBusToApbBridge ( + input wire io_pipelinedMemoryBus_cmd_valid, + output wire io_pipelinedMemoryBus_cmd_ready, + input wire io_pipelinedMemoryBus_cmd_payload_write, + input wire [31:0] io_pipelinedMemoryBus_cmd_payload_address, + input wire [31:0] io_pipelinedMemoryBus_cmd_payload_data, + input wire [3:0] io_pipelinedMemoryBus_cmd_payload_mask, + output wire io_pipelinedMemoryBus_rsp_valid, + output wire [31:0] io_pipelinedMemoryBus_rsp_payload_data, + output wire [19:0] io_apb_PADDR, + output wire [0:0] io_apb_PSEL, + output wire io_apb_PENABLE, + input wire io_apb_PREADY, + output wire io_apb_PWRITE, + output wire [31:0] io_apb_PWDATA, + input wire [31:0] io_apb_PRDATA, + input wire io_apb_PSLVERROR, + input wire io_mainClk, + input wire resetCtrl_systemReset +); + + wire pipelinedMemoryBusStage_cmd_valid; + reg pipelinedMemoryBusStage_cmd_ready; + wire pipelinedMemoryBusStage_cmd_payload_write; + wire [31:0] pipelinedMemoryBusStage_cmd_payload_address; + wire [31:0] pipelinedMemoryBusStage_cmd_payload_data; + wire [3:0] pipelinedMemoryBusStage_cmd_payload_mask; + reg pipelinedMemoryBusStage_rsp_valid; + wire [31:0] pipelinedMemoryBusStage_rsp_payload_data; + wire io_pipelinedMemoryBus_cmd_halfPipe_valid; + wire io_pipelinedMemoryBus_cmd_halfPipe_ready; + wire io_pipelinedMemoryBus_cmd_halfPipe_payload_write; + wire [31:0] io_pipelinedMemoryBus_cmd_halfPipe_payload_address; + wire [31:0] io_pipelinedMemoryBus_cmd_halfPipe_payload_data; + wire [3:0] io_pipelinedMemoryBus_cmd_halfPipe_payload_mask; + reg io_pipelinedMemoryBus_cmd_rValid; + wire io_pipelinedMemoryBus_cmd_halfPipe_fire; + reg io_pipelinedMemoryBus_cmd_rData_write; + reg [31:0] io_pipelinedMemoryBus_cmd_rData_address; + reg [31:0] io_pipelinedMemoryBus_cmd_rData_data; + reg [3:0] io_pipelinedMemoryBus_cmd_rData_mask; + reg pipelinedMemoryBusStage_rsp_regNext_valid; + reg [31:0] pipelinedMemoryBusStage_rsp_regNext_payload_data; + reg state; + wire when_PipelinedMemoryBus_l369; + + assign io_pipelinedMemoryBus_cmd_halfPipe_fire = (io_pipelinedMemoryBus_cmd_halfPipe_valid && io_pipelinedMemoryBus_cmd_halfPipe_ready); + assign io_pipelinedMemoryBus_cmd_ready = (! io_pipelinedMemoryBus_cmd_rValid); + assign io_pipelinedMemoryBus_cmd_halfPipe_valid = io_pipelinedMemoryBus_cmd_rValid; + assign io_pipelinedMemoryBus_cmd_halfPipe_payload_write = io_pipelinedMemoryBus_cmd_rData_write; + assign io_pipelinedMemoryBus_cmd_halfPipe_payload_address = io_pipelinedMemoryBus_cmd_rData_address; + assign io_pipelinedMemoryBus_cmd_halfPipe_payload_data = io_pipelinedMemoryBus_cmd_rData_data; + assign io_pipelinedMemoryBus_cmd_halfPipe_payload_mask = io_pipelinedMemoryBus_cmd_rData_mask; + assign pipelinedMemoryBusStage_cmd_valid = io_pipelinedMemoryBus_cmd_halfPipe_valid; + assign io_pipelinedMemoryBus_cmd_halfPipe_ready = pipelinedMemoryBusStage_cmd_ready; + assign pipelinedMemoryBusStage_cmd_payload_write = io_pipelinedMemoryBus_cmd_halfPipe_payload_write; + assign pipelinedMemoryBusStage_cmd_payload_address = io_pipelinedMemoryBus_cmd_halfPipe_payload_address; + assign pipelinedMemoryBusStage_cmd_payload_data = io_pipelinedMemoryBus_cmd_halfPipe_payload_data; + assign pipelinedMemoryBusStage_cmd_payload_mask = io_pipelinedMemoryBus_cmd_halfPipe_payload_mask; + assign io_pipelinedMemoryBus_rsp_valid = pipelinedMemoryBusStage_rsp_regNext_valid; + assign io_pipelinedMemoryBus_rsp_payload_data = pipelinedMemoryBusStage_rsp_regNext_payload_data; + always @(*) begin + pipelinedMemoryBusStage_cmd_ready = 1'b0; + if(!when_PipelinedMemoryBus_l369) begin + if(io_apb_PREADY) begin + pipelinedMemoryBusStage_cmd_ready = 1'b1; + end + end + end + + assign io_apb_PSEL[0] = pipelinedMemoryBusStage_cmd_valid; + assign io_apb_PENABLE = state; + assign io_apb_PWRITE = pipelinedMemoryBusStage_cmd_payload_write; + assign io_apb_PADDR = pipelinedMemoryBusStage_cmd_payload_address[19:0]; + assign io_apb_PWDATA = pipelinedMemoryBusStage_cmd_payload_data; + always @(*) begin + pipelinedMemoryBusStage_rsp_valid = 1'b0; + if(!when_PipelinedMemoryBus_l369) begin + if(io_apb_PREADY) begin + pipelinedMemoryBusStage_rsp_valid = (! pipelinedMemoryBusStage_cmd_payload_write); + end + end + end + + assign pipelinedMemoryBusStage_rsp_payload_data = io_apb_PRDATA; + assign when_PipelinedMemoryBus_l369 = (! state); + always @(posedge io_mainClk or posedge resetCtrl_systemReset) begin + if(resetCtrl_systemReset) begin + io_pipelinedMemoryBus_cmd_rValid <= 1'b0; + pipelinedMemoryBusStage_rsp_regNext_valid <= 1'b0; + state <= 1'b0; + end else begin + if(io_pipelinedMemoryBus_cmd_valid) begin + io_pipelinedMemoryBus_cmd_rValid <= 1'b1; + end + if(io_pipelinedMemoryBus_cmd_halfPipe_fire) begin + io_pipelinedMemoryBus_cmd_rValid <= 1'b0; + end + pipelinedMemoryBusStage_rsp_regNext_valid <= pipelinedMemoryBusStage_rsp_valid; + if(when_PipelinedMemoryBus_l369) begin + state <= pipelinedMemoryBusStage_cmd_valid; + end else begin + if(io_apb_PREADY) begin + state <= 1'b0; + end + end + end + end + + always @(posedge io_mainClk) begin + if(io_pipelinedMemoryBus_cmd_ready) begin + io_pipelinedMemoryBus_cmd_rData_write <= io_pipelinedMemoryBus_cmd_payload_write; + io_pipelinedMemoryBus_cmd_rData_address <= io_pipelinedMemoryBus_cmd_payload_address; + io_pipelinedMemoryBus_cmd_rData_data <= io_pipelinedMemoryBus_cmd_payload_data; + io_pipelinedMemoryBus_cmd_rData_mask <= io_pipelinedMemoryBus_cmd_payload_mask; + end + pipelinedMemoryBusStage_rsp_regNext_payload_data <= pipelinedMemoryBusStage_rsp_payload_data; + end + + +endmodule + +module MuraxPipelinedMemoryBusRam ( + input wire io_bus_cmd_valid, + output wire io_bus_cmd_ready, + input wire io_bus_cmd_payload_write, + input wire [31:0] io_bus_cmd_payload_address, + input wire [31:0] io_bus_cmd_payload_data, + input wire [3:0] io_bus_cmd_payload_mask, + output wire io_bus_rsp_valid, + output wire [31:0] io_bus_rsp_payload_data, + input wire io_mainClk, + input wire resetCtrl_systemReset +); + + reg [31:0] ram_spinal_port0; + wire [9:0] _zz_ram_port; + wire [9:0] _zz_io_bus_rsp_payload_data_2; + wire io_bus_cmd_fire; + reg _zz_io_bus_rsp_valid; + wire [29:0] _zz_io_bus_rsp_payload_data; + wire [31:0] _zz_io_bus_rsp_payload_data_1; + reg [7:0] ram_symbol0 [0:1023]; + reg [7:0] ram_symbol1 [0:1023]; + reg [7:0] ram_symbol2 [0:1023]; + reg [7:0] ram_symbol3 [0:1023]; + reg [7:0] _zz_ramsymbol_read; + reg [7:0] _zz_ramsymbol_read_1; + reg [7:0] _zz_ramsymbol_read_2; + reg [7:0] _zz_ramsymbol_read_3; + + assign _zz_io_bus_rsp_payload_data_2 = _zz_io_bus_rsp_payload_data[9:0]; + initial begin + $readmemb("Murax.v_toplevel_system_ram_ram_symbol0.bin",ram_symbol0); + $readmemb("Murax.v_toplevel_system_ram_ram_symbol1.bin",ram_symbol1); + $readmemb("Murax.v_toplevel_system_ram_ram_symbol2.bin",ram_symbol2); + $readmemb("Murax.v_toplevel_system_ram_ram_symbol3.bin",ram_symbol3); + end + always @(*) begin + ram_spinal_port0 = {_zz_ramsymbol_read_3, _zz_ramsymbol_read_2, _zz_ramsymbol_read_1, _zz_ramsymbol_read}; + end + always @(posedge io_mainClk) begin + if(io_bus_cmd_valid) begin + _zz_ramsymbol_read <= ram_symbol0[_zz_io_bus_rsp_payload_data_2]; + _zz_ramsymbol_read_1 <= ram_symbol1[_zz_io_bus_rsp_payload_data_2]; + _zz_ramsymbol_read_2 <= ram_symbol2[_zz_io_bus_rsp_payload_data_2]; + _zz_ramsymbol_read_3 <= ram_symbol3[_zz_io_bus_rsp_payload_data_2]; + end + end + + always @(posedge io_mainClk) begin + if(io_bus_cmd_payload_mask[0] && io_bus_cmd_valid && io_bus_cmd_payload_write ) begin + ram_symbol0[_zz_io_bus_rsp_payload_data_2] <= _zz_io_bus_rsp_payload_data_1[7 : 0]; + end + if(io_bus_cmd_payload_mask[1] && io_bus_cmd_valid && io_bus_cmd_payload_write ) begin + ram_symbol1[_zz_io_bus_rsp_payload_data_2] <= _zz_io_bus_rsp_payload_data_1[15 : 8]; + end + if(io_bus_cmd_payload_mask[2] && io_bus_cmd_valid && io_bus_cmd_payload_write ) begin + ram_symbol2[_zz_io_bus_rsp_payload_data_2] <= _zz_io_bus_rsp_payload_data_1[23 : 16]; + end + if(io_bus_cmd_payload_mask[3] && io_bus_cmd_valid && io_bus_cmd_payload_write ) begin + ram_symbol3[_zz_io_bus_rsp_payload_data_2] <= _zz_io_bus_rsp_payload_data_1[31 : 24]; + end + end + + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid; + assign _zz_io_bus_rsp_payload_data = (io_bus_cmd_payload_address >>> 2'd2); + assign _zz_io_bus_rsp_payload_data_1 = io_bus_cmd_payload_data; + assign io_bus_rsp_payload_data = ram_spinal_port0; + assign io_bus_cmd_ready = 1'b1; + always @(posedge io_mainClk or posedge resetCtrl_systemReset) begin + if(resetCtrl_systemReset) begin + _zz_io_bus_rsp_valid <= 1'b0; + end else begin + _zz_io_bus_rsp_valid <= (io_bus_cmd_fire && (! io_bus_cmd_payload_write)); + end + end + + +endmodule + +module SystemDebugger ( + input wire io_remote_cmd_valid, + output wire io_remote_cmd_ready, + input wire io_remote_cmd_payload_last, + input wire [0:0] io_remote_cmd_payload_fragment, + output wire io_remote_rsp_valid, + input wire io_remote_rsp_ready, + output wire io_remote_rsp_payload_error, + output wire [31:0] io_remote_rsp_payload_data, + output wire io_mem_cmd_valid, + input wire io_mem_cmd_ready, + output wire [31:0] io_mem_cmd_payload_address, + output wire [31:0] io_mem_cmd_payload_data, + output wire io_mem_cmd_payload_wr, + output wire [1:0] io_mem_cmd_payload_size, + input wire io_mem_rsp_valid, + input wire [31:0] io_mem_rsp_payload, + input wire io_mainClk, + input wire resetCtrl_mainClkReset +); + + reg [66:0] dispatcher_dataShifter; + reg dispatcher_dataLoaded; + reg [7:0] dispatcher_headerShifter; + wire [7:0] dispatcher_header; + reg dispatcher_headerLoaded; + reg [2:0] dispatcher_counter; + wire when_Fragment_l356; + wire when_Fragment_l359; + wire [66:0] _zz_io_mem_cmd_payload_address; + wire io_mem_cmd_isStall; + wire when_Fragment_l382; + + assign dispatcher_header = dispatcher_headerShifter[7 : 0]; + assign when_Fragment_l356 = (dispatcher_headerLoaded == 1'b0); + assign when_Fragment_l359 = (dispatcher_counter == 3'b111); + assign io_remote_cmd_ready = (! dispatcher_dataLoaded); + assign _zz_io_mem_cmd_payload_address = dispatcher_dataShifter[66 : 0]; + assign io_mem_cmd_payload_address = _zz_io_mem_cmd_payload_address[31 : 0]; + assign io_mem_cmd_payload_data = _zz_io_mem_cmd_payload_address[63 : 32]; + assign io_mem_cmd_payload_wr = _zz_io_mem_cmd_payload_address[64]; + assign io_mem_cmd_payload_size = _zz_io_mem_cmd_payload_address[66 : 65]; + assign io_mem_cmd_valid = (dispatcher_dataLoaded && (dispatcher_header == 8'h0)); + assign io_mem_cmd_isStall = (io_mem_cmd_valid && (! io_mem_cmd_ready)); + assign when_Fragment_l382 = ((dispatcher_headerLoaded && dispatcher_dataLoaded) && (! io_mem_cmd_isStall)); + assign io_remote_rsp_valid = io_mem_rsp_valid; + assign io_remote_rsp_payload_error = 1'b0; + assign io_remote_rsp_payload_data = io_mem_rsp_payload; + always @(posedge io_mainClk or posedge resetCtrl_mainClkReset) begin + if(resetCtrl_mainClkReset) begin + dispatcher_dataLoaded <= 1'b0; + dispatcher_headerLoaded <= 1'b0; + dispatcher_counter <= 3'b000; + end else begin + if(io_remote_cmd_valid) begin + if(when_Fragment_l356) begin + dispatcher_counter <= (dispatcher_counter + 3'b001); + if(when_Fragment_l359) begin + dispatcher_headerLoaded <= 1'b1; + end + end + if(io_remote_cmd_payload_last) begin + dispatcher_headerLoaded <= 1'b1; + dispatcher_dataLoaded <= 1'b1; + dispatcher_counter <= 3'b000; + end + end + if(when_Fragment_l382) begin + dispatcher_headerLoaded <= 1'b0; + dispatcher_dataLoaded <= 1'b0; + end + end + end + + always @(posedge io_mainClk) begin + if(io_remote_cmd_valid) begin + if(when_Fragment_l356) begin + dispatcher_headerShifter <= ({io_remote_cmd_payload_fragment,dispatcher_headerShifter} >>> 1'd1); + end else begin + dispatcher_dataShifter <= ({io_remote_cmd_payload_fragment,dispatcher_dataShifter} >>> 1'd1); + end + end + end + + +endmodule + +module JtagBridge ( + input wire io_jtag_tms, + input wire io_jtag_tdi, + output wire io_jtag_tdo, + input wire io_jtag_tck, + output wire io_remote_cmd_valid, + input wire io_remote_cmd_ready, + output wire io_remote_cmd_payload_last, + output wire [0:0] io_remote_cmd_payload_fragment, + input wire io_remote_rsp_valid, + output wire io_remote_rsp_ready, + input wire io_remote_rsp_payload_error, + input wire [31:0] io_remote_rsp_payload_data, + input wire io_mainClk, + input wire resetCtrl_mainClkReset +); + localparam JtagState_RESET = 4'd0; + localparam JtagState_IDLE = 4'd1; + localparam JtagState_IR_SELECT = 4'd2; + localparam JtagState_IR_CAPTURE = 4'd3; + localparam JtagState_IR_SHIFT = 4'd4; + localparam JtagState_IR_EXIT1 = 4'd5; + localparam JtagState_IR_PAUSE = 4'd6; + localparam JtagState_IR_EXIT2 = 4'd7; + localparam JtagState_IR_UPDATE = 4'd8; + localparam JtagState_DR_SELECT = 4'd9; + localparam JtagState_DR_CAPTURE = 4'd10; + localparam JtagState_DR_SHIFT = 4'd11; + localparam JtagState_DR_EXIT1 = 4'd12; + localparam JtagState_DR_PAUSE = 4'd13; + localparam JtagState_DR_EXIT2 = 4'd14; + localparam JtagState_DR_UPDATE = 4'd15; + + wire flowCCUnsafeByToggle_1_io_output_valid; + wire flowCCUnsafeByToggle_1_io_output_payload_last; + wire [0:0] flowCCUnsafeByToggle_1_io_output_payload_fragment; + wire [3:0] _zz_jtag_tap_isBypass; + wire [1:0] _zz_jtag_tap_instructionShift; + wire system_cmd_valid; + wire system_cmd_payload_last; + wire [0:0] system_cmd_payload_fragment; + wire system_cmd_toStream_valid; + wire system_cmd_toStream_ready; + wire system_cmd_toStream_payload_last; + wire [0:0] system_cmd_toStream_payload_fragment; + (* async_reg = "true" *) reg system_rsp_valid; + (* async_reg = "true" *) reg system_rsp_payload_error; + (* async_reg = "true" *) reg [31:0] system_rsp_payload_data; + wire io_remote_rsp_fire; + reg [3:0] jtag_tap_fsm_stateNext; + reg [3:0] jtag_tap_fsm_state; + wire [3:0] _zz_jtag_tap_fsm_stateNext; + wire [3:0] _zz_jtag_tap_fsm_stateNext_1; + wire [3:0] _zz_jtag_tap_fsm_stateNext_2; + wire [3:0] _zz_jtag_tap_fsm_stateNext_3; + wire [3:0] _zz_jtag_tap_fsm_stateNext_4; + wire [3:0] _zz_jtag_tap_fsm_stateNext_5; + wire [3:0] _zz_jtag_tap_fsm_stateNext_6; + wire [3:0] _zz_jtag_tap_fsm_stateNext_7; + wire [3:0] _zz_jtag_tap_fsm_stateNext_8; + wire [3:0] _zz_jtag_tap_fsm_stateNext_9; + wire [3:0] _zz_jtag_tap_fsm_stateNext_10; + wire [3:0] _zz_jtag_tap_fsm_stateNext_11; + wire [3:0] _zz_jtag_tap_fsm_stateNext_12; + wire [3:0] _zz_jtag_tap_fsm_stateNext_13; + wire [3:0] _zz_jtag_tap_fsm_stateNext_14; + wire [3:0] _zz_jtag_tap_fsm_stateNext_15; + reg [3:0] jtag_tap_instruction; + reg [3:0] jtag_tap_instructionShift; + reg jtag_tap_bypass; + reg jtag_tap_tdoUnbufferd; + reg jtag_tap_tdoDr; + wire jtag_tap_tdoIr; + wire jtag_tap_isBypass; + reg jtag_tap_tdoUnbufferd_regNext; + wire jtag_idcodeArea_ctrl_tdi; + wire jtag_idcodeArea_ctrl_enable; + wire jtag_idcodeArea_ctrl_capture; + wire jtag_idcodeArea_ctrl_shift; + wire jtag_idcodeArea_ctrl_update; + wire jtag_idcodeArea_ctrl_reset; + wire jtag_idcodeArea_ctrl_tdo; + reg [31:0] jtag_idcodeArea_shifter; + wire when_JtagTap_l121; + wire jtag_writeArea_ctrl_tdi; + wire jtag_writeArea_ctrl_enable; + wire jtag_writeArea_ctrl_capture; + wire jtag_writeArea_ctrl_shift; + wire jtag_writeArea_ctrl_update; + wire jtag_writeArea_ctrl_reset; + wire jtag_writeArea_ctrl_tdo; + wire jtag_writeArea_source_valid; + wire jtag_writeArea_source_payload_last; + wire [0:0] jtag_writeArea_source_payload_fragment; + reg jtag_writeArea_valid; + reg jtag_writeArea_data; + wire jtag_readArea_ctrl_tdi; + wire jtag_readArea_ctrl_enable; + wire jtag_readArea_ctrl_capture; + wire jtag_readArea_ctrl_shift; + wire jtag_readArea_ctrl_update; + wire jtag_readArea_ctrl_reset; + wire jtag_readArea_ctrl_tdo; + reg [33:0] jtag_readArea_full_shifter; + `ifndef SYNTHESIS + reg [79:0] jtag_tap_fsm_stateNext_string; + reg [79:0] jtag_tap_fsm_state_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_1_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_2_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_3_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_4_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_5_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_6_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_7_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_8_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_9_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_10_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_11_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_12_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_13_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_14_string; + reg [79:0] _zz_jtag_tap_fsm_stateNext_15_string; + `endif + + + assign _zz_jtag_tap_isBypass = jtag_tap_instruction; + assign _zz_jtag_tap_instructionShift = 2'b01; + FlowCCUnsafeByToggle flowCCUnsafeByToggle_1 ( + .io_input_valid (jtag_writeArea_source_valid ), //i + .io_input_payload_last (jtag_writeArea_source_payload_last ), //i + .io_input_payload_fragment (jtag_writeArea_source_payload_fragment ), //i + .io_output_valid (flowCCUnsafeByToggle_1_io_output_valid ), //o + .io_output_payload_last (flowCCUnsafeByToggle_1_io_output_payload_last ), //o + .io_output_payload_fragment (flowCCUnsafeByToggle_1_io_output_payload_fragment), //o + .io_jtag_tck (io_jtag_tck ), //i + .io_mainClk (io_mainClk ), //i + .resetCtrl_mainClkReset (resetCtrl_mainClkReset ) //i + ); + initial begin + `ifndef SYNTHESIS + jtag_tap_fsm_state = {$urandom}; + `endif + end + + `ifndef SYNTHESIS + always @(*) begin + case(jtag_tap_fsm_stateNext) + JtagState_RESET : jtag_tap_fsm_stateNext_string = "RESET "; + JtagState_IDLE : jtag_tap_fsm_stateNext_string = "IDLE "; + JtagState_IR_SELECT : jtag_tap_fsm_stateNext_string = "IR_SELECT "; + JtagState_IR_CAPTURE : jtag_tap_fsm_stateNext_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : jtag_tap_fsm_stateNext_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : jtag_tap_fsm_stateNext_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : jtag_tap_fsm_stateNext_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : jtag_tap_fsm_stateNext_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : jtag_tap_fsm_stateNext_string = "IR_UPDATE "; + JtagState_DR_SELECT : jtag_tap_fsm_stateNext_string = "DR_SELECT "; + JtagState_DR_CAPTURE : jtag_tap_fsm_stateNext_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : jtag_tap_fsm_stateNext_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : jtag_tap_fsm_stateNext_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : jtag_tap_fsm_stateNext_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : jtag_tap_fsm_stateNext_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : jtag_tap_fsm_stateNext_string = "DR_UPDATE "; + default : jtag_tap_fsm_stateNext_string = "??????????"; + endcase + end + always @(*) begin + case(jtag_tap_fsm_state) + JtagState_RESET : jtag_tap_fsm_state_string = "RESET "; + JtagState_IDLE : jtag_tap_fsm_state_string = "IDLE "; + JtagState_IR_SELECT : jtag_tap_fsm_state_string = "IR_SELECT "; + JtagState_IR_CAPTURE : jtag_tap_fsm_state_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : jtag_tap_fsm_state_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : jtag_tap_fsm_state_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : jtag_tap_fsm_state_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : jtag_tap_fsm_state_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : jtag_tap_fsm_state_string = "IR_UPDATE "; + JtagState_DR_SELECT : jtag_tap_fsm_state_string = "DR_SELECT "; + JtagState_DR_CAPTURE : jtag_tap_fsm_state_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : jtag_tap_fsm_state_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : jtag_tap_fsm_state_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : jtag_tap_fsm_state_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : jtag_tap_fsm_state_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : jtag_tap_fsm_state_string = "DR_UPDATE "; + default : jtag_tap_fsm_state_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_1) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_1_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_1_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_1_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_1_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_1_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_1_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_1_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_1_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_1_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_1_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_1_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_1_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_1_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_1_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_1_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_1_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_1_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_2) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_2_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_2_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_2_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_2_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_2_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_2_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_2_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_2_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_2_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_2_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_2_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_2_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_2_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_2_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_2_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_2_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_2_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_3) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_3_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_3_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_3_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_3_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_3_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_3_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_3_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_3_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_3_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_3_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_3_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_3_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_3_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_3_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_3_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_3_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_3_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_4) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_4_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_4_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_4_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_4_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_4_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_4_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_4_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_4_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_4_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_4_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_4_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_4_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_4_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_4_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_4_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_4_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_4_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_5) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_5_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_5_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_5_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_5_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_5_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_5_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_5_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_5_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_5_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_5_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_5_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_5_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_5_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_5_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_5_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_5_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_5_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_6) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_6_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_6_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_6_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_6_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_6_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_6_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_6_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_6_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_6_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_6_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_6_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_6_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_6_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_6_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_6_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_6_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_6_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_7) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_7_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_7_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_7_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_7_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_7_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_7_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_7_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_7_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_7_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_7_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_7_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_7_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_7_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_7_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_7_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_7_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_7_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_8) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_8_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_8_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_8_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_8_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_8_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_8_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_8_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_8_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_8_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_8_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_8_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_8_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_8_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_8_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_8_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_8_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_8_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_9) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_9_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_9_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_9_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_9_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_9_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_9_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_9_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_9_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_9_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_9_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_9_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_9_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_9_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_9_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_9_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_9_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_9_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_10) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_10_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_10_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_10_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_10_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_10_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_10_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_10_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_10_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_10_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_10_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_10_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_10_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_10_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_10_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_10_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_10_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_10_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_11) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_11_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_11_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_11_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_11_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_11_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_11_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_11_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_11_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_11_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_11_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_11_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_11_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_11_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_11_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_11_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_11_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_11_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_12) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_12_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_12_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_12_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_12_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_12_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_12_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_12_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_12_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_12_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_12_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_12_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_12_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_12_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_12_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_12_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_12_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_12_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_13) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_13_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_13_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_13_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_13_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_13_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_13_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_13_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_13_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_13_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_13_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_13_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_13_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_13_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_13_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_13_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_13_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_13_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_14) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_14_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_14_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_14_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_14_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_14_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_14_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_14_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_14_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_14_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_14_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_14_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_14_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_14_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_14_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_14_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_14_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_14_string = "??????????"; + endcase + end + always @(*) begin + case(_zz_jtag_tap_fsm_stateNext_15) + JtagState_RESET : _zz_jtag_tap_fsm_stateNext_15_string = "RESET "; + JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_15_string = "IDLE "; + JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_15_string = "IR_SELECT "; + JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_15_string = "IR_CAPTURE"; + JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_15_string = "IR_SHIFT "; + JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_15_string = "IR_EXIT1 "; + JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_15_string = "IR_PAUSE "; + JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_15_string = "IR_EXIT2 "; + JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_15_string = "IR_UPDATE "; + JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_15_string = "DR_SELECT "; + JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_15_string = "DR_CAPTURE"; + JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_15_string = "DR_SHIFT "; + JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_15_string = "DR_EXIT1 "; + JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_15_string = "DR_PAUSE "; + JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_15_string = "DR_EXIT2 "; + JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_15_string = "DR_UPDATE "; + default : _zz_jtag_tap_fsm_stateNext_15_string = "??????????"; + endcase + end + `endif + + assign system_cmd_toStream_valid = system_cmd_valid; + assign system_cmd_toStream_payload_last = system_cmd_payload_last; + assign system_cmd_toStream_payload_fragment = system_cmd_payload_fragment; + assign io_remote_cmd_valid = system_cmd_toStream_valid; + assign system_cmd_toStream_ready = io_remote_cmd_ready; + assign io_remote_cmd_payload_last = system_cmd_toStream_payload_last; + assign io_remote_cmd_payload_fragment = system_cmd_toStream_payload_fragment; + assign io_remote_rsp_fire = (io_remote_rsp_valid && io_remote_rsp_ready); + assign io_remote_rsp_ready = 1'b1; + assign _zz_jtag_tap_fsm_stateNext = (io_jtag_tms ? JtagState_RESET : JtagState_IDLE); + always @(*) begin + case(jtag_tap_fsm_state) + JtagState_RESET : begin + jtag_tap_fsm_stateNext = _zz_jtag_tap_fsm_stateNext; + end + JtagState_IDLE : begin + jtag_tap_fsm_stateNext = _zz_jtag_tap_fsm_stateNext_1; + end + JtagState_IR_SELECT : begin + jtag_tap_fsm_stateNext = _zz_jtag_tap_fsm_stateNext_2; + end + JtagState_IR_CAPTURE : begin + jtag_tap_fsm_stateNext = _zz_jtag_tap_fsm_stateNext_3; + end + JtagState_IR_SHIFT : begin + jtag_tap_fsm_stateNext = _zz_jtag_tap_fsm_stateNext_4; + end + JtagState_IR_EXIT1 : begin + jtag_tap_fsm_stateNext = _zz_jtag_tap_fsm_stateNext_5; + end + JtagState_IR_PAUSE : begin + jtag_tap_fsm_stateNext = _zz_jtag_tap_fsm_stateNext_6; + end + JtagState_IR_EXIT2 : begin + jtag_tap_fsm_stateNext = _zz_jtag_tap_fsm_stateNext_7; + end + JtagState_IR_UPDATE : begin + jtag_tap_fsm_stateNext = _zz_jtag_tap_fsm_stateNext_8; + end + JtagState_DR_SELECT : begin + jtag_tap_fsm_stateNext = _zz_jtag_tap_fsm_stateNext_9; + end + JtagState_DR_CAPTURE : begin + jtag_tap_fsm_stateNext = _zz_jtag_tap_fsm_stateNext_10; + end + JtagState_DR_SHIFT : begin + jtag_tap_fsm_stateNext = _zz_jtag_tap_fsm_stateNext_11; + end + JtagState_DR_EXIT1 : begin + jtag_tap_fsm_stateNext = _zz_jtag_tap_fsm_stateNext_12; + end + JtagState_DR_PAUSE : begin + jtag_tap_fsm_stateNext = _zz_jtag_tap_fsm_stateNext_13; + end + JtagState_DR_EXIT2 : begin + jtag_tap_fsm_stateNext = _zz_jtag_tap_fsm_stateNext_14; + end + JtagState_DR_UPDATE : begin + jtag_tap_fsm_stateNext = _zz_jtag_tap_fsm_stateNext_15; + end + default : begin + end + endcase + end + + assign _zz_jtag_tap_fsm_stateNext_1 = (io_jtag_tms ? JtagState_DR_SELECT : JtagState_IDLE); + assign _zz_jtag_tap_fsm_stateNext_2 = (io_jtag_tms ? JtagState_RESET : JtagState_IR_CAPTURE); + assign _zz_jtag_tap_fsm_stateNext_3 = (io_jtag_tms ? JtagState_IR_EXIT1 : JtagState_IR_SHIFT); + assign _zz_jtag_tap_fsm_stateNext_4 = (io_jtag_tms ? JtagState_IR_EXIT1 : JtagState_IR_SHIFT); + assign _zz_jtag_tap_fsm_stateNext_5 = (io_jtag_tms ? JtagState_IR_UPDATE : JtagState_IR_PAUSE); + assign _zz_jtag_tap_fsm_stateNext_6 = (io_jtag_tms ? JtagState_IR_EXIT2 : JtagState_IR_PAUSE); + assign _zz_jtag_tap_fsm_stateNext_7 = (io_jtag_tms ? JtagState_IR_UPDATE : JtagState_IR_SHIFT); + assign _zz_jtag_tap_fsm_stateNext_8 = (io_jtag_tms ? JtagState_DR_SELECT : JtagState_IDLE); + assign _zz_jtag_tap_fsm_stateNext_9 = (io_jtag_tms ? JtagState_IR_SELECT : JtagState_DR_CAPTURE); + assign _zz_jtag_tap_fsm_stateNext_10 = (io_jtag_tms ? JtagState_DR_EXIT1 : JtagState_DR_SHIFT); + assign _zz_jtag_tap_fsm_stateNext_11 = (io_jtag_tms ? JtagState_DR_EXIT1 : JtagState_DR_SHIFT); + assign _zz_jtag_tap_fsm_stateNext_12 = (io_jtag_tms ? JtagState_DR_UPDATE : JtagState_DR_PAUSE); + assign _zz_jtag_tap_fsm_stateNext_13 = (io_jtag_tms ? JtagState_DR_EXIT2 : JtagState_DR_PAUSE); + assign _zz_jtag_tap_fsm_stateNext_14 = (io_jtag_tms ? JtagState_DR_UPDATE : JtagState_DR_SHIFT); + assign _zz_jtag_tap_fsm_stateNext_15 = (io_jtag_tms ? JtagState_DR_SELECT : JtagState_IDLE); + always @(*) begin + jtag_tap_tdoUnbufferd = jtag_tap_bypass; + case(jtag_tap_fsm_state) + JtagState_IR_SHIFT : begin + jtag_tap_tdoUnbufferd = jtag_tap_tdoIr; + end + JtagState_DR_SHIFT : begin + if(jtag_tap_isBypass) begin + jtag_tap_tdoUnbufferd = jtag_tap_bypass; + end else begin + jtag_tap_tdoUnbufferd = jtag_tap_tdoDr; + end + end + default : begin + end + endcase + end + + always @(*) begin + jtag_tap_tdoDr = 1'b0; + if(jtag_idcodeArea_ctrl_enable) begin + jtag_tap_tdoDr = jtag_idcodeArea_ctrl_tdo; + end + if(jtag_writeArea_ctrl_enable) begin + jtag_tap_tdoDr = jtag_writeArea_ctrl_tdo; + end + if(jtag_readArea_ctrl_enable) begin + jtag_tap_tdoDr = jtag_readArea_ctrl_tdo; + end + end + + assign jtag_tap_tdoIr = jtag_tap_instructionShift[0]; + assign jtag_tap_isBypass = ($signed(_zz_jtag_tap_isBypass) == $signed(4'b1111)); + assign io_jtag_tdo = jtag_tap_tdoUnbufferd_regNext; + assign jtag_idcodeArea_ctrl_tdo = jtag_idcodeArea_shifter[0]; + assign jtag_idcodeArea_ctrl_tdi = io_jtag_tdi; + assign jtag_idcodeArea_ctrl_enable = (jtag_tap_instruction == 4'b0001); + assign jtag_idcodeArea_ctrl_capture = (jtag_tap_fsm_state == JtagState_DR_CAPTURE); + assign jtag_idcodeArea_ctrl_shift = (jtag_tap_fsm_state == JtagState_DR_SHIFT); + assign jtag_idcodeArea_ctrl_update = (jtag_tap_fsm_state == JtagState_DR_UPDATE); + assign jtag_idcodeArea_ctrl_reset = (jtag_tap_fsm_state == JtagState_RESET); + assign when_JtagTap_l121 = (jtag_tap_fsm_state == JtagState_RESET); + assign jtag_writeArea_source_valid = jtag_writeArea_valid; + assign jtag_writeArea_source_payload_last = (! (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift)); + assign jtag_writeArea_source_payload_fragment[0] = jtag_writeArea_data; + assign system_cmd_valid = flowCCUnsafeByToggle_1_io_output_valid; + assign system_cmd_payload_last = flowCCUnsafeByToggle_1_io_output_payload_last; + assign system_cmd_payload_fragment = flowCCUnsafeByToggle_1_io_output_payload_fragment; + assign jtag_writeArea_ctrl_tdo = 1'b0; + assign jtag_writeArea_ctrl_tdi = io_jtag_tdi; + assign jtag_writeArea_ctrl_enable = (jtag_tap_instruction == 4'b0010); + assign jtag_writeArea_ctrl_capture = (jtag_tap_fsm_state == JtagState_DR_CAPTURE); + assign jtag_writeArea_ctrl_shift = (jtag_tap_fsm_state == JtagState_DR_SHIFT); + assign jtag_writeArea_ctrl_update = (jtag_tap_fsm_state == JtagState_DR_UPDATE); + assign jtag_writeArea_ctrl_reset = (jtag_tap_fsm_state == JtagState_RESET); + assign jtag_readArea_ctrl_tdo = jtag_readArea_full_shifter[0]; + assign jtag_readArea_ctrl_tdi = io_jtag_tdi; + assign jtag_readArea_ctrl_enable = (jtag_tap_instruction == 4'b0011); + assign jtag_readArea_ctrl_capture = (jtag_tap_fsm_state == JtagState_DR_CAPTURE); + assign jtag_readArea_ctrl_shift = (jtag_tap_fsm_state == JtagState_DR_SHIFT); + assign jtag_readArea_ctrl_update = (jtag_tap_fsm_state == JtagState_DR_UPDATE); + assign jtag_readArea_ctrl_reset = (jtag_tap_fsm_state == JtagState_RESET); + always @(posedge io_mainClk) begin + if(io_remote_cmd_valid) begin + system_rsp_valid <= 1'b0; + end + if(io_remote_rsp_fire) begin + system_rsp_valid <= 1'b1; + system_rsp_payload_error <= io_remote_rsp_payload_error; + system_rsp_payload_data <= io_remote_rsp_payload_data; + end + end + + always @(posedge io_jtag_tck) begin + jtag_tap_fsm_state <= jtag_tap_fsm_stateNext; + jtag_tap_bypass <= io_jtag_tdi; + case(jtag_tap_fsm_state) + JtagState_IR_CAPTURE : begin + jtag_tap_instructionShift <= {2'd0, _zz_jtag_tap_instructionShift}; + end + JtagState_IR_SHIFT : begin + jtag_tap_instructionShift <= ({io_jtag_tdi,jtag_tap_instructionShift} >>> 1'd1); + end + JtagState_IR_UPDATE : begin + jtag_tap_instruction <= jtag_tap_instructionShift; + end + JtagState_DR_SHIFT : begin + jtag_tap_instructionShift <= ({io_jtag_tdi,jtag_tap_instructionShift} >>> 1'd1); + end + default : begin + end + endcase + if(jtag_idcodeArea_ctrl_enable) begin + if(jtag_idcodeArea_ctrl_shift) begin + jtag_idcodeArea_shifter <= ({jtag_idcodeArea_ctrl_tdi,jtag_idcodeArea_shifter} >>> 1'd1); + end + end + if(jtag_idcodeArea_ctrl_capture) begin + jtag_idcodeArea_shifter <= 32'h10001fff; + end + if(when_JtagTap_l121) begin + jtag_tap_instruction <= 4'b0001; + end + jtag_writeArea_valid <= (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift); + jtag_writeArea_data <= jtag_writeArea_ctrl_tdi; + if(jtag_readArea_ctrl_enable) begin + if(jtag_readArea_ctrl_capture) begin + jtag_readArea_full_shifter <= {{system_rsp_payload_data,system_rsp_payload_error},system_rsp_valid}; + end + if(jtag_readArea_ctrl_shift) begin + jtag_readArea_full_shifter <= ({jtag_readArea_ctrl_tdi,jtag_readArea_full_shifter} >>> 1'd1); + end + end + end + + always @(negedge io_jtag_tck) begin + jtag_tap_tdoUnbufferd_regNext <= jtag_tap_tdoUnbufferd; + end + + +endmodule + +module VexRiscv ( + output wire iBus_cmd_valid, + input wire iBus_cmd_ready, + output wire [31:0] iBus_cmd_payload_pc, + input wire iBus_rsp_valid, + input wire iBus_rsp_payload_error, + input wire [31:0] iBus_rsp_payload_inst, + input wire timerInterrupt, + input wire externalInterrupt, + input wire softwareInterrupt, + input wire debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input wire debug_bus_cmd_payload_wr, + input wire [7:0] debug_bus_cmd_payload_address, + input wire [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output wire debug_resetOut, + output wire dBus_cmd_valid, + input wire dBus_cmd_ready, + output wire dBus_cmd_payload_wr, + output wire [3:0] dBus_cmd_payload_mask, + output wire [31:0] dBus_cmd_payload_address, + output wire [31:0] dBus_cmd_payload_data, + output wire [1:0] dBus_cmd_payload_size, + input wire dBus_rsp_ready, + input wire dBus_rsp_error, + input wire [31:0] dBus_rsp_data, + input wire io_mainClk, + input wire resetCtrl_systemReset, + input wire resetCtrl_mainClkReset +); + localparam BranchCtrlEnum_INC = 2'd0; + localparam BranchCtrlEnum_B = 2'd1; + localparam BranchCtrlEnum_JAL = 2'd2; + localparam BranchCtrlEnum_JALR = 2'd3; + localparam ShiftCtrlEnum_DISABLE_1 = 2'd0; + localparam ShiftCtrlEnum_SLL_1 = 2'd1; + localparam ShiftCtrlEnum_SRL_1 = 2'd2; + localparam ShiftCtrlEnum_SRA_1 = 2'd3; + localparam AluBitwiseCtrlEnum_XOR_1 = 2'd0; + localparam AluBitwiseCtrlEnum_OR_1 = 2'd1; + localparam AluBitwiseCtrlEnum_AND_1 = 2'd2; + localparam AluCtrlEnum_ADD_SUB = 2'd0; + localparam AluCtrlEnum_SLT_SLTU = 2'd1; + localparam AluCtrlEnum_BITWISE = 2'd2; + localparam EnvCtrlEnum_NONE = 1'd0; + localparam EnvCtrlEnum_XRET = 1'd1; + localparam Src2CtrlEnum_RS = 2'd0; + localparam Src2CtrlEnum_IMI = 2'd1; + localparam Src2CtrlEnum_IMS = 2'd2; + localparam Src2CtrlEnum_PC = 2'd3; + localparam Src1CtrlEnum_RS = 2'd0; + localparam Src1CtrlEnum_IMU = 2'd1; + localparam Src1CtrlEnum_PC_INCREMENT = 2'd2; + localparam Src1CtrlEnum_URS1 = 2'd3; + + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready; + reg [31:0] RegFilePlugin_regFile_spinal_port0; + reg [31:0] RegFilePlugin_regFile_spinal_port1; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; + wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_availability; + wire [1:0] _zz_IBusSimplePlugin_jump_pcLoad_payload_1; + wire [1:0] _zz_IBusSimplePlugin_jump_pcLoad_payload_2; + wire [31:0] _zz_IBusSimplePlugin_fetchPc_pc; + wire [2:0] _zz_IBusSimplePlugin_fetchPc_pc_1; + wire [2:0] _zz_IBusSimplePlugin_pending_next; + wire [2:0] _zz_IBusSimplePlugin_pending_next_1; + wire [0:0] _zz_IBusSimplePlugin_pending_next_2; + wire [2:0] _zz_IBusSimplePlugin_pending_next_3; + wire [0:0] _zz_IBusSimplePlugin_pending_next_4; + wire [2:0] _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter; + wire [0:0] _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED; + wire _zz__zz_decode_SRC_LESS_UNSIGNED_1; + wire _zz__zz_decode_SRC_LESS_UNSIGNED_2; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_3; + wire _zz__zz_decode_SRC_LESS_UNSIGNED_4; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_5; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_6; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_7; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_8; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_9; + wire _zz__zz_decode_SRC_LESS_UNSIGNED_10; + wire _zz__zz_decode_SRC_LESS_UNSIGNED_11; + wire [19:0] _zz__zz_decode_SRC_LESS_UNSIGNED_12; + wire _zz__zz_decode_SRC_LESS_UNSIGNED_13; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_14; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_15; + wire _zz__zz_decode_SRC_LESS_UNSIGNED_16; + wire _zz__zz_decode_SRC_LESS_UNSIGNED_17; + wire _zz__zz_decode_SRC_LESS_UNSIGNED_18; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_19; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_20; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_21; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_22; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_23; + wire [15:0] _zz__zz_decode_SRC_LESS_UNSIGNED_24; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_25; + wire _zz__zz_decode_SRC_LESS_UNSIGNED_26; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_27; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_28; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_29; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_30; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_31; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_32; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_33; + wire [12:0] _zz__zz_decode_SRC_LESS_UNSIGNED_34; + wire [1:0] _zz__zz_decode_SRC_LESS_UNSIGNED_35; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_36; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_37; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_38; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_39; + wire _zz__zz_decode_SRC_LESS_UNSIGNED_40; + wire _zz__zz_decode_SRC_LESS_UNSIGNED_41; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_42; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_43; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_44; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_45; + wire _zz__zz_decode_SRC_LESS_UNSIGNED_46; + wire [9:0] _zz__zz_decode_SRC_LESS_UNSIGNED_47; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_48; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_49; + wire _zz__zz_decode_SRC_LESS_UNSIGNED_50; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_51; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_52; + wire [4:0] _zz__zz_decode_SRC_LESS_UNSIGNED_53; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_54; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_55; + wire _zz__zz_decode_SRC_LESS_UNSIGNED_56; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_57; + wire [1:0] _zz__zz_decode_SRC_LESS_UNSIGNED_58; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_59; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_60; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_61; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_62; + wire [6:0] _zz__zz_decode_SRC_LESS_UNSIGNED_63; + wire [1:0] _zz__zz_decode_SRC_LESS_UNSIGNED_64; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_65; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_66; + wire _zz__zz_decode_SRC_LESS_UNSIGNED_67; + wire _zz__zz_decode_SRC_LESS_UNSIGNED_68; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_69; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_70; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_71; + wire [2:0] _zz__zz_decode_SRC_LESS_UNSIGNED_72; + wire _zz__zz_decode_SRC_LESS_UNSIGNED_73; + wire [3:0] _zz__zz_decode_SRC_LESS_UNSIGNED_74; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_75; + wire [31:0] _zz__zz_decode_SRC_LESS_UNSIGNED_76; + wire _zz__zz_decode_SRC_LESS_UNSIGNED_77; + wire _zz__zz_decode_SRC_LESS_UNSIGNED_78; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_79; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_80; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_81; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_82; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_83; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_84; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_85; + wire [0:0] _zz__zz_decode_SRC_LESS_UNSIGNED_86; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_decode_SRC1; + wire [4:0] _zz__zz_decode_SRC1_1; + wire [11:0] _zz__zz_decode_SRC2_2; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1; + wire [32:0] _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1_1; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire [31:0] memory_MEMORY_READ_DATA; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_DO_EBREAK; + wire [31:0] decode_SRC2; + wire [31:0] decode_SRC1; + wire decode_SRC2_FORCE_ZERO; + wire [31:0] decode_RS2; + wire [31:0] decode_RS1; + wire [1:0] decode_BRANCH_CTRL; + wire [1:0] _zz_decode_BRANCH_CTRL; + wire [1:0] _zz_decode_to_execute_BRANCH_CTRL; + wire [1:0] _zz_decode_to_execute_BRANCH_CTRL_1; + wire [1:0] decode_SHIFT_CTRL; + wire [1:0] _zz_decode_SHIFT_CTRL; + wire [1:0] _zz_decode_to_execute_SHIFT_CTRL; + wire [1:0] _zz_decode_to_execute_SHIFT_CTRL_1; + wire [1:0] decode_ALU_BITWISE_CTRL; + wire [1:0] _zz_decode_ALU_BITWISE_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + wire decode_SRC_LESS_UNSIGNED; + wire [1:0] decode_ALU_CTRL; + wire [1:0] _zz_decode_ALU_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_CTRL_1; + wire [0:0] _zz_memory_to_writeBack_ENV_CTRL; + wire [0:0] _zz_memory_to_writeBack_ENV_CTRL_1; + wire [0:0] _zz_execute_to_memory_ENV_CTRL; + wire [0:0] _zz_execute_to_memory_ENV_CTRL_1; + wire [0:0] decode_ENV_CTRL; + wire [0:0] _zz_decode_ENV_CTRL; + wire [0:0] _zz_decode_to_execute_ENV_CTRL; + wire [0:0] _zz_decode_to_execute_ENV_CTRL_1; + wire decode_IS_CSR; + wire decode_MEMORY_STORE; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire decode_MEMORY_ENABLE; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire [31:0] execute_RS1; + wire [1:0] execute_BRANCH_CTRL; + wire [1:0] _zz_execute_BRANCH_CTRL; + wire decode_RS2_USE; + wire decode_RS1_USE; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire [1:0] execute_SHIFT_CTRL; + wire [1:0] _zz_execute_SHIFT_CTRL; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_decode_to_execute_PC; + wire [31:0] _zz_decode_to_execute_RS2; + wire [1:0] decode_SRC2_CTRL; + wire [1:0] _zz_decode_SRC2_CTRL; + wire [31:0] _zz_decode_to_execute_RS1; + wire [1:0] decode_SRC1_CTRL; + wire [1:0] _zz_decode_SRC1_CTRL; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire [1:0] execute_ALU_CTRL; + wire [1:0] _zz_execute_ALU_CTRL; + wire [31:0] execute_SRC2; + wire [1:0] execute_ALU_BITWISE_CTRL; + wire [1:0] _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire [1:0] _zz_decode_BRANCH_CTRL_1; + wire [1:0] _zz_decode_SHIFT_CTRL_1; + wire [1:0] _zz_decode_ALU_BITWISE_CTRL_1; + wire [1:0] _zz_decode_ALU_CTRL_1; + wire [0:0] _zz_decode_ENV_CTRL_1; + wire [1:0] _zz_decode_SRC2_CTRL_1; + wire [1:0] _zz_decode_SRC1_CTRL_1; + reg [31:0] _zz_execute_to_memory_REGFILE_WRITE_DATA; + wire [31:0] execute_SRC1; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire [0:0] memory_ENV_CTRL; + wire [0:0] _zz_memory_ENV_CTRL; + wire [0:0] execute_ENV_CTRL; + wire [0:0] _zz_execute_ENV_CTRL; + wire [0:0] writeBack_ENV_CTRL; + wire [0:0] _zz_writeBack_ENV_CTRL; + reg [31:0] _zz_lastStageRegFileWrite_payload_data; + wire writeBack_MEMORY_ENABLE; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_MEMORY_READ_DATA; + wire memory_MEMORY_STORE; + wire memory_MEMORY_ENABLE; + wire [31:0] execute_SRC_ADD; + wire [31:0] execute_RS2; + wire [31:0] execute_INSTRUCTION; + wire execute_MEMORY_STORE; + wire execute_MEMORY_ENABLE; + wire execute_ALIGNEMENT_FAULT; + reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; + wire [31:0] decode_PC; + wire [31:0] decode_INSTRUCTION; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + wire decode_arbitration_flushNext; + reg decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + wire writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + wire writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusSimplePlugin_fetcherHalt; + wire IBusSimplePlugin_forceNoDecodeCond; + reg IBusSimplePlugin_incomingInstruction; + wire IBusSimplePlugin_pcValids_0; + wire IBusSimplePlugin_pcValids_1; + wire IBusSimplePlugin_pcValids_2; + wire IBusSimplePlugin_pcValids_3; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + reg CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; + wire CsrPlugin_csrMapping_doForceFailCsr; + wire CsrPlugin_inWfi /* verilator public */ ; + reg CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg CsrPlugin_allowEbreakException; + wire CsrPlugin_xretAwayFromMachine; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + reg BranchPlugin_inDebugNoFetchFlag; + reg DebugPlugin_injectionPort_valid; + reg DebugPlugin_injectionPort_ready; + wire [31:0] DebugPlugin_injectionPort_payload; + wire IBusSimplePlugin_externalFlush; + wire IBusSimplePlugin_jump_pcLoad_valid; + wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; + wire [1:0] _zz_IBusSimplePlugin_jump_pcLoad_payload; + wire IBusSimplePlugin_fetchPc_output_valid; + wire IBusSimplePlugin_fetchPc_output_ready; + wire [31:0] IBusSimplePlugin_fetchPc_output_payload; + reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusSimplePlugin_fetchPc_correction; + reg IBusSimplePlugin_fetchPc_correctionReg; + wire IBusSimplePlugin_fetchPc_output_fire; + wire IBusSimplePlugin_fetchPc_corrected; + reg IBusSimplePlugin_fetchPc_pcRegPropagate; + reg IBusSimplePlugin_fetchPc_booted; + reg IBusSimplePlugin_fetchPc_inc; + wire when_Fetcher_l133; + wire when_Fetcher_l133_1; + reg [31:0] IBusSimplePlugin_fetchPc_pc; + reg IBusSimplePlugin_fetchPc_flushed; + wire when_Fetcher_l160; + wire IBusSimplePlugin_iBusRsp_redoFetch; + wire IBusSimplePlugin_iBusRsp_stages_0_input_valid; + wire IBusSimplePlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_0_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload; + wire IBusSimplePlugin_iBusRsp_stages_0_halt; + wire IBusSimplePlugin_iBusRsp_stages_1_input_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_1_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload; + reg IBusSimplePlugin_iBusRsp_stages_1_halt; + wire IBusSimplePlugin_iBusRsp_stages_2_input_valid; + wire IBusSimplePlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_2_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_2_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_2_output_payload; + wire IBusSimplePlugin_iBusRsp_stages_2_halt; + wire _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusSimplePlugin_iBusRsp_stages_2_input_ready; + wire IBusSimplePlugin_iBusRsp_flush; + wire _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusSimplePlugin_iBusRsp_stages_1_input_valid; + reg _zz_IBusSimplePlugin_iBusRsp_stages_1_input_valid_1; + wire IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg IBusSimplePlugin_iBusRsp_readyForError; + wire IBusSimplePlugin_iBusRsp_output_valid; + wire IBusSimplePlugin_iBusRsp_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_pc; + wire IBusSimplePlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + wire IBusSimplePlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l242; + wire IBusSimplePlugin_injector_decodeInput_valid; + wire IBusSimplePlugin_injector_decodeInput_ready; + wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc; + wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error; + wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + wire IBusSimplePlugin_injector_decodeInput_payload_isRvc; + reg _zz_IBusSimplePlugin_injector_decodeInput_valid; + reg [31:0] _zz_IBusSimplePlugin_injector_decodeInput_payload_pc; + reg _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error; + reg [31:0] _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + reg _zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc; + wire when_Fetcher_l322; + reg IBusSimplePlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l331; + reg IBusSimplePlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l331_1; + reg IBusSimplePlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l331_2; + reg IBusSimplePlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l331_3; + reg IBusSimplePlugin_injector_nextPcCalc_valids_4; + wire when_Fetcher_l331_4; + reg IBusSimplePlugin_injector_nextPcCalc_valids_5; + wire when_Fetcher_l331_5; + reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode; + wire IBusSimplePlugin_cmd_valid; + wire IBusSimplePlugin_cmd_ready; + wire [31:0] IBusSimplePlugin_cmd_payload_pc; + wire IBusSimplePlugin_pending_inc; + wire IBusSimplePlugin_pending_dec; + reg [2:0] IBusSimplePlugin_pending_value; + wire [2:0] IBusSimplePlugin_pending_next; + wire IBusSimplePlugin_cmdFork_canEmit; + wire when_IBusSimplePlugin_l306; + wire IBusSimplePlugin_cmd_fire; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_valid; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_ready; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; + reg [2:0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter; + wire iBus_rsp_toStream_valid; + wire iBus_rsp_toStream_ready; + wire iBus_rsp_toStream_payload_error; + wire [31:0] iBus_rsp_toStream_payload_inst; + wire IBusSimplePlugin_rspJoin_rspBuffer_flush; + wire system_cpu_IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc; + reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; + wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + wire when_IBusSimplePlugin_l378; + wire IBusSimplePlugin_rspJoin_join_valid; + wire IBusSimplePlugin_rspJoin_join_ready; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc; + wire IBusSimplePlugin_rspJoin_join_payload_rsp_error; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + wire IBusSimplePlugin_rspJoin_join_payload_isRvc; + wire IBusSimplePlugin_rspJoin_exceptionDetected; + wire IBusSimplePlugin_rspJoin_join_fire; + wire _zz_IBusSimplePlugin_iBusRsp_output_valid; + wire _zz_dBus_cmd_valid; + reg execute_DBusSimplePlugin_skipCmd; + reg [31:0] _zz_dBus_cmd_payload_data; + wire when_DBusSimplePlugin_l435; + reg [3:0] _zz_execute_DBusSimplePlugin_formalMask; + wire [3:0] execute_DBusSimplePlugin_formalMask; + wire when_DBusSimplePlugin_l490; + reg [31:0] writeBack_DBusSimplePlugin_rspShifted; + wire [1:0] switch_Misc_l241; + wire _zz_writeBack_DBusSimplePlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_1; + wire _zz_writeBack_DBusSimplePlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_3; + reg [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire when_DBusSimplePlugin_l566; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + wire [1:0] CsrPlugin_mtvec_mode; + wire [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle; + reg [63:0] CsrPlugin_minstret; + wire _zz_when_CsrPlugin_l1302; + wire _zz_when_CsrPlugin_l1302_1; + wire _zz_when_CsrPlugin_l1302_2; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l1296; + wire when_CsrPlugin_l1302; + wire when_CsrPlugin_l1302_1; + wire when_CsrPlugin_l1302_2; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l1335; + wire when_CsrPlugin_l1335_1; + wire when_CsrPlugin_l1335_2; + wire when_CsrPlugin_l1340; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + wire [1:0] CsrPlugin_targetPrivilege; + wire [3:0] CsrPlugin_trapCause; + wire CsrPlugin_trapCauseEbreakDebug; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + wire CsrPlugin_trapEnterDebug; + wire when_CsrPlugin_l1390; + wire when_CsrPlugin_l1398; + wire when_CsrPlugin_l1456; + wire [1:0] switch_CsrPlugin_l1460; + reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1527; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire when_CsrPlugin_l1547; + wire when_CsrPlugin_l1548; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + wire switch_Misc_l241_1; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1587; + wire when_CsrPlugin_l1591; + wire [11:0] execute_CsrPlugin_csrAddress; + wire [25:0] _zz_decode_SRC_LESS_UNSIGNED; + wire _zz_decode_SRC_LESS_UNSIGNED_1; + wire _zz_decode_SRC_LESS_UNSIGNED_2; + wire _zz_decode_SRC_LESS_UNSIGNED_3; + wire _zz_decode_SRC_LESS_UNSIGNED_4; + wire _zz_decode_SRC_LESS_UNSIGNED_5; + wire _zz_decode_SRC_LESS_UNSIGNED_6; + wire [1:0] _zz_decode_SRC1_CTRL_2; + wire [1:0] _zz_decode_SRC2_CTRL_2; + wire [0:0] _zz_decode_ENV_CTRL_2; + wire [1:0] _zz_decode_ALU_CTRL_2; + wire [1:0] _zz_decode_ALU_BITWISE_CTRL_2; + wire [1:0] _zz_decode_SHIFT_CTRL_2; + wire [1:0] _zz_decode_BRANCH_CTRL_2; + wire when_RegFilePlugin_l63; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_5; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_decode_SRC1; + wire _zz_decode_SRC2; + reg [19:0] _zz_decode_SRC2_1; + wire _zz_decode_SRC2_2; + reg [19:0] _zz_decode_SRC2_3; + reg [31:0] _zz_decode_SRC2_4; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + reg execute_LightShifterPlugin_isActive; + wire execute_LightShifterPlugin_isShift; + reg [4:0] execute_LightShifterPlugin_amplitudeReg; + wire [4:0] execute_LightShifterPlugin_amplitude; + wire [31:0] execute_LightShifterPlugin_shiftInput; + wire execute_LightShifterPlugin_done; + wire when_ShiftPlugins_l169; + reg [31:0] _zz_execute_to_memory_REGFILE_WRITE_DATA_1; + wire when_ShiftPlugins_l175; + wire when_ShiftPlugins_l184; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l59; + wire when_HazardSimplePlugin_l62; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l59_1; + wire when_HazardSimplePlugin_l62_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l59_2; + wire when_HazardSimplePlugin_l62_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; + wire execute_BranchPlugin_eq; + wire [2:0] switch_Misc_l241_2; + reg _zz_execute_BRANCH_DO; + reg _zz_execute_BRANCH_DO_1; + wire [31:0] execute_BranchPlugin_branch_src1; + wire _zz_execute_BranchPlugin_branch_src2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; + reg [31:0] _zz_execute_BranchPlugin_branch_src2_6; + wire [31:0] execute_BranchPlugin_branch_src2; + wire [31:0] execute_BranchPlugin_branchAdder; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + wire when_DebugPlugin_l238; + reg DebugPlugin_haltedByBreak; + reg DebugPlugin_debugUsed /* verilator public */ ; + reg DebugPlugin_disableEbreak; + wire DebugPlugin_allowEBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_when_DebugPlugin_l257; + wire when_DebugPlugin_l257; + wire [5:0] switch_DebugPlugin_l280; + wire when_DebugPlugin_l284; + wire when_DebugPlugin_l284_1; + wire when_DebugPlugin_l285; + wire when_DebugPlugin_l285_1; + wire when_DebugPlugin_l286; + wire when_DebugPlugin_l287; + wire when_DebugPlugin_l288; + wire when_DebugPlugin_l288_1; + wire when_DebugPlugin_l308; + wire when_DebugPlugin_l311; + wire when_DebugPlugin_l324; + reg DebugPlugin_resetIt_regNext; + wire when_DebugPlugin_l344; + wire when_Pipeline_l124; + reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; + reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; + reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; + reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; + reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; + reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; + reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_10; + reg decode_to_execute_CSR_READ_OPCODE; + wire when_Pipeline_l124_11; + reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_12; + reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_13; + reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_14; + reg memory_to_writeBack_MEMORY_ENABLE; + wire when_Pipeline_l124_15; + reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_16; + reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_17; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_19; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_20; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_21; + reg decode_to_execute_MEMORY_STORE; + wire when_Pipeline_l124_22; + reg execute_to_memory_MEMORY_STORE; + wire when_Pipeline_l124_23; + reg decode_to_execute_IS_CSR; + wire when_Pipeline_l124_24; + reg [0:0] decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_25; + reg [0:0] execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_26; + reg [0:0] memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_27; + reg [1:0] decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_28; + reg decode_to_execute_SRC_LESS_UNSIGNED; + wire when_Pipeline_l124_29; + reg [1:0] decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_30; + reg [1:0] decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_31; + reg [1:0] decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_32; + reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_33; + reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_34; + reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_35; + reg [31:0] decode_to_execute_SRC1; + wire when_Pipeline_l124_36; + reg [31:0] decode_to_execute_SRC2; + wire when_Pipeline_l124_37; + reg decode_to_execute_DO_EBREAK; + wire when_Pipeline_l124_38; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_39; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_40; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_41; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_42; + reg execute_to_memory_BRANCH_DO; + wire when_Pipeline_l124_43; + reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l124_44; + reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + reg [2:0] IBusSimplePlugin_injector_port_state; + wire when_Fetcher_l391; + wire when_Fetcher_l411; + wire when_CsrPlugin_l1669; + reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1669_1; + reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1669_2; + reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1669_3; + reg execute_CsrPlugin_csr_834; + wire [1:0] switch_CsrPlugin_l1031; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + wire when_CsrPlugin_l1702; + wire [11:0] _zz_when_CsrPlugin_l1709; + wire when_CsrPlugin_l1709; + reg when_CsrPlugin_l1719; + wire when_CsrPlugin_l1717; + wire when_CsrPlugin_l1725; + `ifndef SYNTHESIS + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; + reg [31:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [31:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [31:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [31:0] _zz_execute_to_memory_ENV_CTRL_1_string; + reg [31:0] decode_ENV_CTRL_string; + reg [31:0] _zz_decode_ENV_CTRL_string; + reg [31:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [31:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_execute_ALU_CTRL_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [31:0] _zz_decode_ENV_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; + reg [31:0] memory_ENV_CTRL_string; + reg [31:0] _zz_memory_ENV_CTRL_string; + reg [31:0] execute_ENV_CTRL_string; + reg [31:0] _zz_execute_ENV_CTRL_string; + reg [31:0] writeBack_ENV_CTRL_string; + reg [31:0] _zz_writeBack_ENV_CTRL_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [31:0] _zz_decode_ENV_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [31:0] decode_to_execute_ENV_CTRL_string; + reg [31:0] execute_to_memory_ENV_CTRL_string; + reg [31:0] memory_to_writeBack_ENV_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + `endif + + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_IBusSimplePlugin_jump_pcLoad_payload_1 = (_zz_IBusSimplePlugin_jump_pcLoad_payload & (~ _zz_IBusSimplePlugin_jump_pcLoad_payload_2)); + assign _zz_IBusSimplePlugin_jump_pcLoad_payload_2 = (_zz_IBusSimplePlugin_jump_pcLoad_payload - 2'b01); + assign _zz_IBusSimplePlugin_fetchPc_pc_1 = {IBusSimplePlugin_fetchPc_inc,2'b00}; + assign _zz_IBusSimplePlugin_fetchPc_pc = {29'd0, _zz_IBusSimplePlugin_fetchPc_pc_1}; + assign _zz_IBusSimplePlugin_pending_next = (IBusSimplePlugin_pending_value + _zz_IBusSimplePlugin_pending_next_1); + assign _zz_IBusSimplePlugin_pending_next_2 = IBusSimplePlugin_pending_inc; + assign _zz_IBusSimplePlugin_pending_next_1 = {2'd0, _zz_IBusSimplePlugin_pending_next_2}; + assign _zz_IBusSimplePlugin_pending_next_4 = IBusSimplePlugin_pending_dec; + assign _zz_IBusSimplePlugin_pending_next_3 = {2'd0, _zz_IBusSimplePlugin_pending_next_4}; + assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); + assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter = {2'd0, _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1}; + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_decode_SRC1 = 3'b100; + assign _zz__zz_decode_SRC1_1 = decode_INSTRUCTION[19 : 15]; + assign _zz__zz_decode_SRC2_2 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? 32'h00000001 : 32'h0); + assign _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1 = (_zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1_1 >>> 1'd1); + assign _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1_1 = {((execute_SHIFT_CTRL == ShiftCtrlEnum_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz__zz_execute_BranchPlugin_branch_src2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz__zz_decode_SRC_LESS_UNSIGNED = 32'h10003050; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_1 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_2 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_3 = ((decode_INSTRUCTION & 32'h00007054) == 32'h00005010); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_4 = (|{(_zz__zz_decode_SRC_LESS_UNSIGNED_5 == _zz__zz_decode_SRC_LESS_UNSIGNED_6),(_zz__zz_decode_SRC_LESS_UNSIGNED_7 == _zz__zz_decode_SRC_LESS_UNSIGNED_8)}); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_9 = (|{_zz__zz_decode_SRC_LESS_UNSIGNED_10,_zz__zz_decode_SRC_LESS_UNSIGNED_11}); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_12 = {(|_zz__zz_decode_SRC_LESS_UNSIGNED_13),{(|_zz__zz_decode_SRC_LESS_UNSIGNED_14),{_zz__zz_decode_SRC_LESS_UNSIGNED_16,{_zz__zz_decode_SRC_LESS_UNSIGNED_19,_zz__zz_decode_SRC_LESS_UNSIGNED_24}}}}; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_5 = (decode_INSTRUCTION & 32'h40003054); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_6 = 32'h40001010; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_7 = (decode_INSTRUCTION & 32'h00007054); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_8 = 32'h00001010; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_10 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_11 = ((decode_INSTRUCTION & 32'h00003054) == 32'h00001010); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_13 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_14 = ((decode_INSTRUCTION & _zz__zz_decode_SRC_LESS_UNSIGNED_15) == 32'h00002000); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_16 = (|{_zz__zz_decode_SRC_LESS_UNSIGNED_17,_zz__zz_decode_SRC_LESS_UNSIGNED_18}); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_19 = (|{_zz__zz_decode_SRC_LESS_UNSIGNED_20,_zz__zz_decode_SRC_LESS_UNSIGNED_22}); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_24 = {(|_zz__zz_decode_SRC_LESS_UNSIGNED_25),{_zz__zz_decode_SRC_LESS_UNSIGNED_26,{_zz__zz_decode_SRC_LESS_UNSIGNED_29,_zz__zz_decode_SRC_LESS_UNSIGNED_34}}}; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_15 = 32'h00003000; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_17 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_18 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_20 = ((decode_INSTRUCTION & _zz__zz_decode_SRC_LESS_UNSIGNED_21) == 32'h00006000); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_22 = ((decode_INSTRUCTION & _zz__zz_decode_SRC_LESS_UNSIGNED_23) == 32'h00004000); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_25 = _zz_decode_SRC_LESS_UNSIGNED_2; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_26 = (|(_zz__zz_decode_SRC_LESS_UNSIGNED_27 == _zz__zz_decode_SRC_LESS_UNSIGNED_28)); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_29 = (|{_zz__zz_decode_SRC_LESS_UNSIGNED_30,_zz__zz_decode_SRC_LESS_UNSIGNED_32}); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_34 = {(|_zz__zz_decode_SRC_LESS_UNSIGNED_35),{_zz__zz_decode_SRC_LESS_UNSIGNED_40,{_zz__zz_decode_SRC_LESS_UNSIGNED_45,_zz__zz_decode_SRC_LESS_UNSIGNED_47}}}; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_21 = 32'h00006004; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_23 = 32'h00005004; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_27 = (decode_INSTRUCTION & 32'h00103050); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_28 = 32'h00000050; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_30 = ((decode_INSTRUCTION & _zz__zz_decode_SRC_LESS_UNSIGNED_31) == 32'h00001050); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_32 = ((decode_INSTRUCTION & _zz__zz_decode_SRC_LESS_UNSIGNED_33) == 32'h00002050); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_35 = {(_zz__zz_decode_SRC_LESS_UNSIGNED_36 == _zz__zz_decode_SRC_LESS_UNSIGNED_37),(_zz__zz_decode_SRC_LESS_UNSIGNED_38 == _zz__zz_decode_SRC_LESS_UNSIGNED_39)}; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_40 = (|{_zz__zz_decode_SRC_LESS_UNSIGNED_41,{_zz__zz_decode_SRC_LESS_UNSIGNED_42,_zz__zz_decode_SRC_LESS_UNSIGNED_43}}); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_45 = (|_zz__zz_decode_SRC_LESS_UNSIGNED_46); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_47 = {(|_zz__zz_decode_SRC_LESS_UNSIGNED_48),{_zz__zz_decode_SRC_LESS_UNSIGNED_50,{_zz__zz_decode_SRC_LESS_UNSIGNED_51,_zz__zz_decode_SRC_LESS_UNSIGNED_63}}}; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_31 = 32'h00001050; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_33 = 32'h00002050; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_36 = (decode_INSTRUCTION & 32'h00000034); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_37 = 32'h00000020; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_38 = (decode_INSTRUCTION & 32'h00000064); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_39 = 32'h00000020; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_41 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_42 = _zz_decode_SRC_LESS_UNSIGNED_3; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_43 = ((decode_INSTRUCTION & _zz__zz_decode_SRC_LESS_UNSIGNED_44) == 32'h00000040); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_46 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_48 = ((decode_INSTRUCTION & _zz__zz_decode_SRC_LESS_UNSIGNED_49) == 32'h00000010); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_50 = (|_zz_decode_SRC_LESS_UNSIGNED_5); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_51 = (|{_zz__zz_decode_SRC_LESS_UNSIGNED_52,_zz__zz_decode_SRC_LESS_UNSIGNED_53}); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_63 = {(|_zz__zz_decode_SRC_LESS_UNSIGNED_64),{_zz__zz_decode_SRC_LESS_UNSIGNED_67,{_zz__zz_decode_SRC_LESS_UNSIGNED_69,_zz__zz_decode_SRC_LESS_UNSIGNED_74}}}; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_44 = 32'h00103040; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_49 = 32'h00000010; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_52 = _zz_decode_SRC_LESS_UNSIGNED_6; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_53 = {(_zz__zz_decode_SRC_LESS_UNSIGNED_54 == _zz__zz_decode_SRC_LESS_UNSIGNED_55),{_zz__zz_decode_SRC_LESS_UNSIGNED_56,{_zz__zz_decode_SRC_LESS_UNSIGNED_57,_zz__zz_decode_SRC_LESS_UNSIGNED_58}}}; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_64 = {_zz_decode_SRC_LESS_UNSIGNED_4,(_zz__zz_decode_SRC_LESS_UNSIGNED_65 == _zz__zz_decode_SRC_LESS_UNSIGNED_66)}; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_67 = (|{_zz_decode_SRC_LESS_UNSIGNED_4,_zz__zz_decode_SRC_LESS_UNSIGNED_68}); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_69 = (|{_zz__zz_decode_SRC_LESS_UNSIGNED_70,_zz__zz_decode_SRC_LESS_UNSIGNED_72}); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_74 = {(|_zz__zz_decode_SRC_LESS_UNSIGNED_75),{_zz__zz_decode_SRC_LESS_UNSIGNED_77,{_zz__zz_decode_SRC_LESS_UNSIGNED_81,_zz__zz_decode_SRC_LESS_UNSIGNED_84}}}; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_54 = (decode_INSTRUCTION & 32'h00001010); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_55 = 32'h00001010; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_56 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002010); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_57 = _zz_decode_SRC_LESS_UNSIGNED_5; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_58 = {(_zz__zz_decode_SRC_LESS_UNSIGNED_59 == _zz__zz_decode_SRC_LESS_UNSIGNED_60),(_zz__zz_decode_SRC_LESS_UNSIGNED_61 == _zz__zz_decode_SRC_LESS_UNSIGNED_62)}; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_65 = (decode_INSTRUCTION & 32'h00000070); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_66 = 32'h00000020; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_68 = ((decode_INSTRUCTION & 32'h00000020) == 32'h0); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_70 = ((decode_INSTRUCTION & _zz__zz_decode_SRC_LESS_UNSIGNED_71) == 32'h0); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_72 = {_zz_decode_SRC_LESS_UNSIGNED_3,{_zz_decode_SRC_LESS_UNSIGNED_2,_zz__zz_decode_SRC_LESS_UNSIGNED_73}}; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_75 = ((decode_INSTRUCTION & _zz__zz_decode_SRC_LESS_UNSIGNED_76) == 32'h0); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_77 = (|{_zz__zz_decode_SRC_LESS_UNSIGNED_78,{_zz__zz_decode_SRC_LESS_UNSIGNED_79,_zz__zz_decode_SRC_LESS_UNSIGNED_80}}); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_81 = (|{_zz__zz_decode_SRC_LESS_UNSIGNED_82,_zz__zz_decode_SRC_LESS_UNSIGNED_83}); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_84 = (|{_zz__zz_decode_SRC_LESS_UNSIGNED_85,_zz__zz_decode_SRC_LESS_UNSIGNED_86}); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_59 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_60 = 32'h00000004; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_61 = (decode_INSTRUCTION & 32'h00000028); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_62 = 32'h0; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_71 = 32'h00000044; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_73 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_76 = 32'h00000058; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_78 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_79 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_80 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_82 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_83 = _zz_decode_SRC_LESS_UNSIGNED_1; + assign _zz__zz_decode_SRC_LESS_UNSIGNED_85 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz__zz_decode_SRC_LESS_UNSIGNED_86 = _zz_decode_SRC_LESS_UNSIGNED_1; + always @(posedge io_mainClk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + RegFilePlugin_regFile_spinal_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge io_mainClk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + RegFilePlugin_regFile_spinal_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge io_mainClk) begin + if(_zz_1) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( + .io_push_valid (iBus_rsp_toStream_valid ), //i + .io_push_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready ), //o + .io_push_payload_error (iBus_rsp_toStream_payload_error ), //i + .io_push_payload_inst (iBus_rsp_toStream_payload_inst[31:0] ), //i + .io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o + .io_pop_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready ), //i + .io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o + .io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst[31:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o + .io_availability (IBusSimplePlugin_rspJoin_rspBuffer_c_io_availability ), //o + .io_mainClk (io_mainClk ), //i + .resetCtrl_systemReset (resetCtrl_systemReset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(decode_BRANCH_CTRL) + BranchCtrlEnum_INC : decode_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : decode_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : decode_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_BRANCH_CTRL) + BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_BRANCH_CTRL) + BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_BRANCH_CTRL_1) + BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_SHIFT_CTRL_1) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + AluCtrlEnum_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_CTRL) + AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_CTRL) + AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_CTRL_1) + AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; + endcase + end + always @(*) begin + case(_zz_memory_to_writeBack_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE"; + EnvCtrlEnum_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_memory_to_writeBack_ENV_CTRL_1) + EnvCtrlEnum_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE"; + EnvCtrlEnum_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE"; + EnvCtrlEnum_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET"; + default : _zz_execute_to_memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_ENV_CTRL_1) + EnvCtrlEnum_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE"; + EnvCtrlEnum_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + EnvCtrlEnum_NONE : decode_ENV_CTRL_string = "NONE"; + EnvCtrlEnum_XRET : decode_ENV_CTRL_string = "XRET"; + default : decode_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_string = "NONE"; + EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_string = "XRET"; + default : _zz_decode_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE"; + EnvCtrlEnum_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET"; + default : _zz_decode_to_execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ENV_CTRL_1) + EnvCtrlEnum_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE"; + EnvCtrlEnum_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + BranchCtrlEnum_INC : execute_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : execute_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : execute_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_execute_BRANCH_CTRL) + BranchCtrlEnum_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : _zz_execute_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_execute_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + Src2CtrlEnum_RS : decode_SRC2_CTRL_string = "RS "; + Src2CtrlEnum_IMI : decode_SRC2_CTRL_string = "IMI"; + Src2CtrlEnum_IMS : decode_SRC2_CTRL_string = "IMS"; + Src2CtrlEnum_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_SRC2_CTRL) + Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_string = "RS "; + Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + Src1CtrlEnum_RS : decode_SRC1_CTRL_string = "RS "; + Src1CtrlEnum_IMU : decode_SRC1_CTRL_string = "IMU "; + Src1CtrlEnum_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + Src1CtrlEnum_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC1_CTRL) + Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_string = "RS "; + Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + AluCtrlEnum_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_execute_ALU_CTRL) + AluCtrlEnum_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_BRANCH_CTRL_1) + BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_SHIFT_CTRL_1) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_BITWISE_CTRL_1) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_CTRL_1) + AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_ENV_CTRL_1) + EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_1_string = "NONE"; + EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_1_string = "XRET"; + default : _zz_decode_ENV_CTRL_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC2_CTRL_1) + Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_SRC1_CTRL_1) + Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + EnvCtrlEnum_NONE : memory_ENV_CTRL_string = "NONE"; + EnvCtrlEnum_XRET : memory_ENV_CTRL_string = "XRET"; + default : memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_memory_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_memory_ENV_CTRL_string = "NONE"; + EnvCtrlEnum_XRET : _zz_memory_ENV_CTRL_string = "XRET"; + default : _zz_memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + EnvCtrlEnum_NONE : execute_ENV_CTRL_string = "NONE"; + EnvCtrlEnum_XRET : execute_ENV_CTRL_string = "XRET"; + default : execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_execute_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_execute_ENV_CTRL_string = "NONE"; + EnvCtrlEnum_XRET : _zz_execute_ENV_CTRL_string = "XRET"; + default : _zz_execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + EnvCtrlEnum_NONE : writeBack_ENV_CTRL_string = "NONE"; + EnvCtrlEnum_XRET : writeBack_ENV_CTRL_string = "XRET"; + default : writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_writeBack_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_writeBack_ENV_CTRL_string = "NONE"; + EnvCtrlEnum_XRET : _zz_writeBack_ENV_CTRL_string = "XRET"; + default : _zz_writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC1_CTRL_2) + Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC2_CTRL_2) + Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_ENV_CTRL_2) + EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_2_string = "NONE"; + EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_2_string = "XRET"; + default : _zz_decode_ENV_CTRL_2_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_CTRL_2) + AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_BITWISE_CTRL_2) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_SHIFT_CTRL_2) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_BRANCH_CTRL_2) + BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + EnvCtrlEnum_NONE : decode_to_execute_ENV_CTRL_string = "NONE"; + EnvCtrlEnum_XRET : decode_to_execute_ENV_CTRL_string = "XRET"; + default : decode_to_execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + EnvCtrlEnum_NONE : execute_to_memory_ENV_CTRL_string = "NONE"; + EnvCtrlEnum_XRET : execute_to_memory_ENV_CTRL_string = "XRET"; + default : execute_to_memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + EnvCtrlEnum_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE"; + EnvCtrlEnum_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET"; + default : memory_to_writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + AluCtrlEnum_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + BranchCtrlEnum_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : decode_to_execute_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + `endif + + assign memory_MEMORY_READ_DATA = dBus_rsp_data; + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = _zz_execute_BRANCH_DO_1; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; + assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); + assign decode_SRC2 = _zz_decode_SRC2_4; + assign decode_SRC1 = _zz_decode_SRC1; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_RS2 = decode_RegFilePlugin_rs2Data; + assign decode_RS1 = decode_RegFilePlugin_rs1Data; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_SRC_LESS_UNSIGNED[17]; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_SRC_LESS_UNSIGNED[13]; + assign decode_MEMORY_STORE = _zz_decode_SRC_LESS_UNSIGNED[10]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_SRC_LESS_UNSIGNED[9]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_SRC_LESS_UNSIGNED[8]; + assign decode_MEMORY_ENABLE = _zz_decode_SRC_LESS_UNSIGNED[3]; + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_decode_SRC_LESS_UNSIGNED[25]; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PC = decode_to_execute_PC; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_SRC_LESS_UNSIGNED[12]; + assign decode_RS1_USE = _zz_decode_SRC_LESS_UNSIGNED[4]; + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_decode_to_execute_PC = decode_PC; + assign _zz_decode_to_execute_RS2 = decode_RS2; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_RS1 = decode_RS1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_SRC_LESS_UNSIGNED[2]; + assign decode_SRC_ADD_ZERO = _zz_decode_SRC_LESS_UNSIGNED[20]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = decode_to_execute_SRC2; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_output_payload_rsp_inst); + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_SRC_LESS_UNSIGNED[7]; + if(when_RegFilePlugin_l63) begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + always @(*) begin + _zz_execute_to_memory_REGFILE_WRITE_DATA = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1587) begin + _zz_execute_to_memory_REGFILE_WRITE_DATA = CsrPlugin_csrMapping_readDataSignal; + end + if(when_ShiftPlugins_l169) begin + _zz_execute_to_memory_REGFILE_WRITE_DATA = _zz_execute_to_memory_REGFILE_WRITE_DATA_1; + end + end + + assign execute_SRC1 = decode_to_execute_SRC1; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; + always @(*) begin + _zz_lastStageRegFileWrite_payload_data = writeBack_REGFILE_WRITE_DATA; + if(when_DBusSimplePlugin_l566) begin + _zz_lastStageRegFileWrite_payload_data = writeBack_DBusSimplePlugin_rspFormated; + end + end + + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; + assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_ALIGNEMENT_FAULT = 1'b0; + always @(*) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; + end + end + + assign decode_PC = IBusSimplePlugin_injector_decodeInput_payload_pc; + assign decode_INSTRUCTION = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @(*) begin + decode_arbitration_haltItself = 1'b0; + case(IBusSimplePlugin_injector_port_state) + 3'b010 : begin + decode_arbitration_haltItself = 1'b1; + end + default : begin + end + endcase + end + + always @(*) begin + decode_arbitration_haltByOther = 1'b0; + if(CsrPlugin_pipelineLiberator_active) begin + decode_arbitration_haltByOther = 1'b1; + end + if(when_CsrPlugin_l1527) begin + decode_arbitration_haltByOther = 1'b1; + end + if(when_HazardSimplePlugin_l113) begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @(*) begin + decode_arbitration_removeIt = 1'b0; + if(decode_arbitration_isFlushed) begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + assign decode_arbitration_flushNext = 1'b0; + always @(*) begin + execute_arbitration_haltItself = 1'b0; + if(when_DBusSimplePlugin_l435) begin + execute_arbitration_haltItself = 1'b1; + end + if(when_CsrPlugin_l1591) begin + if(execute_CsrPlugin_blockedBySideEffects) begin + execute_arbitration_haltItself = 1'b1; + end + end + if(when_ShiftPlugins_l169) begin + if(when_ShiftPlugins_l184) begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + always @(*) begin + execute_arbitration_haltByOther = 1'b0; + if(when_DebugPlugin_l308) begin + execute_arbitration_haltByOther = 1'b1; + end + end + + always @(*) begin + execute_arbitration_removeIt = 1'b0; + if(execute_arbitration_isFlushed) begin + execute_arbitration_removeIt = 1'b1; + end + end + + always @(*) begin + execute_arbitration_flushIt = 1'b0; + if(when_DebugPlugin_l308) begin + if(when_DebugPlugin_l311) begin + execute_arbitration_flushIt = 1'b1; + end + end + end + + always @(*) begin + execute_arbitration_flushNext = 1'b0; + if(when_DebugPlugin_l308) begin + if(when_DebugPlugin_l311) begin + execute_arbitration_flushNext = 1'b1; + end + end + end + + always @(*) begin + memory_arbitration_haltItself = 1'b0; + if(when_DBusSimplePlugin_l490) begin + memory_arbitration_haltItself = 1'b1; + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @(*) begin + memory_arbitration_removeIt = 1'b0; + if(memory_arbitration_isFlushed) begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @(*) begin + memory_arbitration_flushNext = 1'b0; + if(BranchPlugin_jumpInterface_valid) begin + memory_arbitration_flushNext = 1'b1; + end + end + + assign writeBack_arbitration_haltItself = 1'b0; + assign writeBack_arbitration_haltByOther = 1'b0; + always @(*) begin + writeBack_arbitration_removeIt = 1'b0; + if(writeBack_arbitration_isFlushed) begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + assign writeBack_arbitration_flushIt = 1'b0; + always @(*) begin + writeBack_arbitration_flushNext = 1'b0; + if(when_CsrPlugin_l1390) begin + writeBack_arbitration_flushNext = 1'b1; + end + if(when_CsrPlugin_l1456) begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @(*) begin + IBusSimplePlugin_fetcherHalt = 1'b0; + if(when_CsrPlugin_l1390) begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + if(when_CsrPlugin_l1456) begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + if(when_DebugPlugin_l308) begin + if(when_DebugPlugin_l311) begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + end + if(DebugPlugin_haltIt) begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + if(when_DebugPlugin_l324) begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + end + + assign IBusSimplePlugin_forceNoDecodeCond = 1'b0; + always @(*) begin + IBusSimplePlugin_incomingInstruction = 1'b0; + if(when_Fetcher_l242) begin + IBusSimplePlugin_incomingInstruction = 1'b1; + end + if(IBusSimplePlugin_injector_decodeInput_valid) begin + IBusSimplePlugin_incomingInstruction = 1'b1; + end + end + + always @(*) begin + CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + if(when_CsrPlugin_l1702) begin + CsrPlugin_csrMapping_allowCsrSignal = 1'b1; + end + if(when_CsrPlugin_l1709) begin + CsrPlugin_csrMapping_allowCsrSignal = 1'b1; + end + end + + assign CsrPlugin_csrMapping_doForceFailCsr = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + assign CsrPlugin_inWfi = 1'b0; + always @(*) begin + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt) begin + CsrPlugin_thirdPartyWake = 1'b1; + end + end + + always @(*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(when_CsrPlugin_l1390) begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(when_CsrPlugin_l1456) begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1390) begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(when_CsrPlugin_l1456) begin + case(switch_CsrPlugin_l1460) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + always @(*) begin + CsrPlugin_forceMachineWire = 1'b0; + if(DebugPlugin_godmode) begin + CsrPlugin_forceMachineWire = 1'b1; + end + end + + always @(*) begin + CsrPlugin_allowInterrupts = 1'b1; + if(when_DebugPlugin_l344) begin + CsrPlugin_allowInterrupts = 1'b0; + end + end + + always @(*) begin + CsrPlugin_allowException = 1'b1; + if(DebugPlugin_godmode) begin + CsrPlugin_allowException = 1'b0; + end + end + + always @(*) begin + CsrPlugin_allowEbreakException = 1'b1; + if(DebugPlugin_allowEBreak) begin + CsrPlugin_allowEbreakException = 1'b0; + end + end + + assign CsrPlugin_xretAwayFromMachine = 1'b0; + always @(*) begin + BranchPlugin_inDebugNoFetchFlag = 1'b0; + if(DebugPlugin_godmode) begin + BranchPlugin_inDebugNoFetchFlag = 1'b1; + end + end + + assign IBusSimplePlugin_externalFlush = (|{writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}}); + assign IBusSimplePlugin_jump_pcLoad_valid = (|{BranchPlugin_jumpInterface_valid,CsrPlugin_jumpInterface_valid}); + assign _zz_IBusSimplePlugin_jump_pcLoad_payload = {BranchPlugin_jumpInterface_valid,CsrPlugin_jumpInterface_valid}; + assign IBusSimplePlugin_jump_pcLoad_payload = (_zz_IBusSimplePlugin_jump_pcLoad_payload_1[0] ? CsrPlugin_jumpInterface_payload : BranchPlugin_jumpInterface_payload); + always @(*) begin + IBusSimplePlugin_fetchPc_correction = 1'b0; + if(IBusSimplePlugin_jump_pcLoad_valid) begin + IBusSimplePlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusSimplePlugin_fetchPc_output_fire = (IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready); + assign IBusSimplePlugin_fetchPc_corrected = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_correctionReg); + always @(*) begin + IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusSimplePlugin_iBusRsp_stages_1_input_ready) begin + IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + assign when_Fetcher_l133 = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_pcRegPropagate); + assign when_Fetcher_l133_1 = ((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready); + always @(*) begin + IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_IBusSimplePlugin_fetchPc_pc); + if(IBusSimplePlugin_jump_pcLoad_valid) begin + IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload; + end + IBusSimplePlugin_fetchPc_pc[0] = 1'b0; + IBusSimplePlugin_fetchPc_pc[1] = 1'b0; + end + + always @(*) begin + IBusSimplePlugin_fetchPc_flushed = 1'b0; + if(IBusSimplePlugin_jump_pcLoad_valid) begin + IBusSimplePlugin_fetchPc_flushed = 1'b1; + end + end + + assign when_Fetcher_l160 = (IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetchPc_correction) || IBusSimplePlugin_fetchPc_pcRegPropagate)); + assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted); + assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc; + assign IBusSimplePlugin_iBusRsp_redoFetch = 1'b0; + assign IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; + assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready; + assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload; + assign IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; + assign _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready = (! IBusSimplePlugin_iBusRsp_stages_0_halt); + assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready); + assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready); + assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload; + always @(*) begin + IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0; + if(when_IBusSimplePlugin_l306) begin + IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready = (! IBusSimplePlugin_iBusRsp_stages_1_halt); + assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready); + assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready); + assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; + assign IBusSimplePlugin_iBusRsp_stages_2_halt = 1'b0; + assign _zz_IBusSimplePlugin_iBusRsp_stages_2_input_ready = (! IBusSimplePlugin_iBusRsp_stages_2_halt); + assign IBusSimplePlugin_iBusRsp_stages_2_input_ready = (IBusSimplePlugin_iBusRsp_stages_2_output_ready && _zz_IBusSimplePlugin_iBusRsp_stages_2_input_ready); + assign IBusSimplePlugin_iBusRsp_stages_2_output_valid = (IBusSimplePlugin_iBusRsp_stages_2_input_valid && _zz_IBusSimplePlugin_iBusRsp_stages_2_input_ready); + assign IBusSimplePlugin_iBusRsp_stages_2_output_payload = IBusSimplePlugin_iBusRsp_stages_2_input_payload; + assign IBusSimplePlugin_iBusRsp_flush = (IBusSimplePlugin_externalFlush || IBusSimplePlugin_iBusRsp_redoFetch); + assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusSimplePlugin_iBusRsp_stages_1_input_valid)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_IBusSimplePlugin_iBusRsp_stages_1_input_valid_1; + assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_IBusSimplePlugin_iBusRsp_stages_1_input_valid; + assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg; + assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusSimplePlugin_iBusRsp_stages_2_input_valid = IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusSimplePlugin_iBusRsp_stages_2_input_ready; + assign IBusSimplePlugin_iBusRsp_stages_2_input_payload = IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b1; + if(IBusSimplePlugin_injector_decodeInput_valid) begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b0; + end + if(when_Fetcher_l322) begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign when_Fetcher_l242 = (IBusSimplePlugin_iBusRsp_stages_1_input_valid || IBusSimplePlugin_iBusRsp_stages_2_input_valid); + assign IBusSimplePlugin_iBusRsp_output_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready); + assign IBusSimplePlugin_injector_decodeInput_valid = _zz_IBusSimplePlugin_injector_decodeInput_valid; + assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_IBusSimplePlugin_injector_decodeInput_payload_pc; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc; + assign when_Fetcher_l322 = (! IBusSimplePlugin_pcValids_0); + assign when_Fetcher_l331 = (! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l331_1 = (! (! IBusSimplePlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l331_2 = (! (! IBusSimplePlugin_injector_decodeInput_ready)); + assign when_Fetcher_l331_3 = (! execute_arbitration_isStuck); + assign when_Fetcher_l331_4 = (! memory_arbitration_isStuck); + assign when_Fetcher_l331_5 = (! writeBack_arbitration_isStuck); + assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_2; + assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_3; + assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_4; + assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_5; + assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); + always @(*) begin + decode_arbitration_isValid = IBusSimplePlugin_injector_decodeInput_valid; + case(IBusSimplePlugin_injector_port_state) + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + default : begin + end + endcase + if(IBusSimplePlugin_forceNoDecodeCond) begin + decode_arbitration_isValid = 1'b0; + end + end + + assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; + assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; + assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; + assign IBusSimplePlugin_pending_next = (_zz_IBusSimplePlugin_pending_next - _zz_IBusSimplePlugin_pending_next_3); + assign IBusSimplePlugin_cmdFork_canEmit = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && (IBusSimplePlugin_pending_value != 3'b111)); + assign when_IBusSimplePlugin_l306 = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && ((! IBusSimplePlugin_cmdFork_canEmit) || (! IBusSimplePlugin_cmd_ready))); + assign IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_cmdFork_canEmit); + assign IBusSimplePlugin_cmd_fire = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); + assign IBusSimplePlugin_pending_inc = IBusSimplePlugin_cmd_fire; + assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_iBusRsp_stages_1_input_payload[31 : 2],2'b00}; + assign iBus_rsp_toStream_valid = iBus_rsp_valid; + assign iBus_rsp_toStream_payload_error = iBus_rsp_payload_error; + assign iBus_rsp_toStream_payload_inst = iBus_rsp_payload_inst; + assign iBus_rsp_toStream_ready = IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; + assign IBusSimplePlugin_rspJoin_rspBuffer_flush = ((IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000) || IBusSimplePlugin_iBusRsp_flush); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_valid = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter == 3'b000)); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + assign IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); + assign system_cpu_IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready); + assign IBusSimplePlugin_pending_dec = system_cpu_IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire; + assign IBusSimplePlugin_rspJoin_fetchRsp_isRvc = 1'b0; + assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_2_output_payload; + always @(*) begin + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; + if(when_IBusSimplePlugin_l378) begin + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0; + end + end + + assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; + assign when_IBusSimplePlugin_l378 = (! IBusSimplePlugin_rspJoin_rspBuffer_output_valid); + assign IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; + assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_2_output_valid && IBusSimplePlugin_rspJoin_rspBuffer_output_valid); + assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc; + assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; + assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; + assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + assign IBusSimplePlugin_rspJoin_join_fire = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); + assign IBusSimplePlugin_iBusRsp_stages_2_output_ready = (IBusSimplePlugin_iBusRsp_stages_2_output_valid ? IBusSimplePlugin_rspJoin_join_fire : IBusSimplePlugin_rspJoin_join_ready); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_ready = IBusSimplePlugin_rspJoin_join_fire; + assign _zz_IBusSimplePlugin_iBusRsp_output_valid = (! IBusSimplePlugin_rspJoin_exceptionDetected); + assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_output_ready && _zz_IBusSimplePlugin_iBusRsp_output_valid); + assign IBusSimplePlugin_iBusRsp_output_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_IBusSimplePlugin_iBusRsp_output_valid); + assign IBusSimplePlugin_iBusRsp_output_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; + assign IBusSimplePlugin_iBusRsp_output_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; + assign IBusSimplePlugin_iBusRsp_output_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; + assign _zz_dBus_cmd_valid = 1'b0; + always @(*) begin + execute_DBusSimplePlugin_skipCmd = 1'b0; + if(execute_ALIGNEMENT_FAULT) begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + end + + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_dBus_cmd_valid)); + assign dBus_cmd_payload_wr = execute_MEMORY_STORE; + assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_dBus_cmd_payload_data = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_dBus_cmd_payload_data = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_dBus_cmd_payload_data = execute_RS2[31 : 0]; + end + endcase + end + + assign dBus_cmd_payload_data = _zz_dBus_cmd_payload_data; + assign when_DBusSimplePlugin_l435 = ((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_dBus_cmd_valid)); + always @(*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_execute_DBusSimplePlugin_formalMask = 4'b0001; + end + 2'b01 : begin + _zz_execute_DBusSimplePlugin_formalMask = 4'b0011; + end + default : begin + _zz_execute_DBusSimplePlugin_formalMask = 4'b1111; + end + endcase + end + + assign execute_DBusSimplePlugin_formalMask = (_zz_execute_DBusSimplePlugin_formalMask <<< dBus_cmd_payload_address[1 : 0]); + assign dBus_cmd_payload_mask = execute_DBusSimplePlugin_formalMask; + assign dBus_cmd_payload_address = execute_SRC_ADD; + assign when_DBusSimplePlugin_l490 = (((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)); + always @(*) begin + writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; + end + 2'b10 : begin + writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; + end + 2'b11 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; + end + default : begin + end + endcase + end + + assign switch_Misc_l241 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusSimplePlugin_rspFormated = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusSimplePlugin_rspFormated_1[31] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[30] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[29] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[28] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[27] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[26] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[25] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[24] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[23] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[22] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[21] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[20] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[19] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[18] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[17] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[16] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[15] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[14] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[13] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[12] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[11] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[10] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[9] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[8] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_writeBack_DBusSimplePlugin_rspFormated_2 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusSimplePlugin_rspFormated_3[31] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[30] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[29] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[28] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[27] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[26] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[25] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[24] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[23] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[22] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[21] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[20] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[19] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[18] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[17] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[16] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @(*) begin + case(switch_Misc_l241) + 2'b00 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_writeBack_DBusSimplePlugin_rspFormated_1; + end + 2'b01 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_writeBack_DBusSimplePlugin_rspFormated_3; + end + default : begin + writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; + end + endcase + end + + assign when_DBusSimplePlugin_l566 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + always @(*) begin + CsrPlugin_privilege = 2'b11; + if(CsrPlugin_forceMachineWire) begin + CsrPlugin_privilege = 2'b11; + end + end + + assign CsrPlugin_misa_base = 2'b01; + assign CsrPlugin_misa_extensions = 26'h0000042; + assign CsrPlugin_mtvec_mode = 2'b00; + assign CsrPlugin_mtvec_base = 30'h20000008; + assign _zz_when_CsrPlugin_l1302 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l1302_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l1302_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign when_CsrPlugin_l1296 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l1302 = ((_zz_when_CsrPlugin_l1302 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l1302_1 = ((_zz_when_CsrPlugin_l1302_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l1302_2 = ((_zz_when_CsrPlugin_l1302_2 && 1'b1) && (! 1'b0)); + assign CsrPlugin_exception = 1'b0; + assign CsrPlugin_lastStageWasWfi = 1'b0; + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + assign when_CsrPlugin_l1335 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1335_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l1335_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l1340 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(CsrPlugin_hadException) begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + assign CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + assign CsrPlugin_trapCause = CsrPlugin_interrupt_code; + assign CsrPlugin_trapCauseEbreakDebug = 1'b0; + always @(*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign CsrPlugin_trapEnterDebug = 1'b0; + assign when_CsrPlugin_l1390 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1398 = (! CsrPlugin_trapEnterDebug); + assign when_CsrPlugin_l1456 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == EnvCtrlEnum_XRET)); + assign switch_CsrPlugin_l1460 = writeBack_INSTRUCTION[29 : 28]; + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1527 = (|{(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == EnvCtrlEnum_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == EnvCtrlEnum_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_XRET))}}); + assign execute_CsrPlugin_blockedBySideEffects = ((|{writeBack_arbitration_isValid,memory_arbitration_isValid}) || 1'b0); + always @(*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_768) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1719) begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(when_CsrPlugin_l1725) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @(*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if(when_CsrPlugin_l1547) begin + if(when_CsrPlugin_l1548) begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + assign when_CsrPlugin_l1547 = (execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_XRET)); + assign when_CsrPlugin_l1548 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + always @(*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(when_CsrPlugin_l1719) begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @(*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(when_CsrPlugin_l1719) begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l241_1 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l241_1) + 1'b0 : begin + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; + end + default : begin + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1587 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1591 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign _zz_decode_SRC_LESS_UNSIGNED_1 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_SRC_LESS_UNSIGNED_2 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_decode_SRC_LESS_UNSIGNED_3 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0); + assign _zz_decode_SRC_LESS_UNSIGNED_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_SRC_LESS_UNSIGNED_5 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); + assign _zz_decode_SRC_LESS_UNSIGNED_6 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_SRC_LESS_UNSIGNED = {(|((decode_INSTRUCTION & _zz__zz_decode_SRC_LESS_UNSIGNED) == 32'h00000050)),{(|{_zz_decode_SRC_LESS_UNSIGNED_6,_zz__zz_decode_SRC_LESS_UNSIGNED_1}),{(|_zz__zz_decode_SRC_LESS_UNSIGNED_2),{(|_zz__zz_decode_SRC_LESS_UNSIGNED_3),{_zz__zz_decode_SRC_LESS_UNSIGNED_4,{_zz__zz_decode_SRC_LESS_UNSIGNED_9,_zz__zz_decode_SRC_LESS_UNSIGNED_12}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_SRC_LESS_UNSIGNED[1 : 0]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_SRC_LESS_UNSIGNED[6 : 5]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_SRC_LESS_UNSIGNED[14 : 14]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_SRC_LESS_UNSIGNED[16 : 15]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_SRC_LESS_UNSIGNED[19 : 18]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_SRC_LESS_UNSIGNED[22 : 21]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_SRC_LESS_UNSIGNED[24 : 23]; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL_2; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = RegFilePlugin_regFile_spinal_port0; + assign decode_RegFilePlugin_rs2Data = RegFilePlugin_regFile_spinal_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_5) begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_5) begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_lastStageRegFileWrite_payload_data; + if(_zz_5) begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + AluBitwiseCtrlEnum_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @(*) begin + case(execute_ALU_CTRL) + AluCtrlEnum_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; + end + AluCtrlEnum_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; + end + default : begin + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; + end + endcase + end + + always @(*) begin + case(decode_SRC1_CTRL) + Src1CtrlEnum_RS : begin + _zz_decode_SRC1 = _zz_decode_to_execute_RS1; + end + Src1CtrlEnum_PC_INCREMENT : begin + _zz_decode_SRC1 = {29'd0, _zz__zz_decode_SRC1}; + end + Src1CtrlEnum_IMU : begin + _zz_decode_SRC1 = {decode_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_decode_SRC1 = {27'd0, _zz__zz_decode_SRC1_1}; + end + endcase + end + + assign _zz_decode_SRC2 = decode_INSTRUCTION[31]; + always @(*) begin + _zz_decode_SRC2_1[19] = _zz_decode_SRC2; + _zz_decode_SRC2_1[18] = _zz_decode_SRC2; + _zz_decode_SRC2_1[17] = _zz_decode_SRC2; + _zz_decode_SRC2_1[16] = _zz_decode_SRC2; + _zz_decode_SRC2_1[15] = _zz_decode_SRC2; + _zz_decode_SRC2_1[14] = _zz_decode_SRC2; + _zz_decode_SRC2_1[13] = _zz_decode_SRC2; + _zz_decode_SRC2_1[12] = _zz_decode_SRC2; + _zz_decode_SRC2_1[11] = _zz_decode_SRC2; + _zz_decode_SRC2_1[10] = _zz_decode_SRC2; + _zz_decode_SRC2_1[9] = _zz_decode_SRC2; + _zz_decode_SRC2_1[8] = _zz_decode_SRC2; + _zz_decode_SRC2_1[7] = _zz_decode_SRC2; + _zz_decode_SRC2_1[6] = _zz_decode_SRC2; + _zz_decode_SRC2_1[5] = _zz_decode_SRC2; + _zz_decode_SRC2_1[4] = _zz_decode_SRC2; + _zz_decode_SRC2_1[3] = _zz_decode_SRC2; + _zz_decode_SRC2_1[2] = _zz_decode_SRC2; + _zz_decode_SRC2_1[1] = _zz_decode_SRC2; + _zz_decode_SRC2_1[0] = _zz_decode_SRC2; + end + + assign _zz_decode_SRC2_2 = _zz__zz_decode_SRC2_2[11]; + always @(*) begin + _zz_decode_SRC2_3[19] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[18] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[17] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[16] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[15] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[14] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[13] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[12] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[11] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[10] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[9] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[8] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[7] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[6] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[5] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[4] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[3] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[2] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[1] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[0] = _zz_decode_SRC2_2; + end + + always @(*) begin + case(decode_SRC2_CTRL) + Src2CtrlEnum_RS : begin + _zz_decode_SRC2_4 = _zz_decode_to_execute_RS2; + end + Src2CtrlEnum_IMI : begin + _zz_decode_SRC2_4 = {_zz_decode_SRC2_1,decode_INSTRUCTION[31 : 20]}; + end + Src2CtrlEnum_IMS : begin + _zz_decode_SRC2_4 = {_zz_decode_SRC2_3,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_decode_SRC2_4 = _zz_decode_to_execute_PC; + end + endcase + end + + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != ShiftCtrlEnum_DISABLE_1); + assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); + assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); + assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == 4'b0000); + assign when_ShiftPlugins_l169 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + always @(*) begin + case(execute_SHIFT_CTRL) + ShiftCtrlEnum_SLL_1 : begin + _zz_execute_to_memory_REGFILE_WRITE_DATA_1 = (execute_LightShifterPlugin_shiftInput <<< 1); + end + default : begin + _zz_execute_to_memory_REGFILE_WRITE_DATA_1 = _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1; + end + endcase + end + + assign when_ShiftPlugins_l175 = (! execute_arbitration_isStuckByOthers); + assign when_ShiftPlugins_l184 = (! execute_LightShifterPlugin_done); + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l59) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l59_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l59_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; + end + end + + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l62) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l62_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l62_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_lastStageRegFileWrite_payload_data; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l59 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l62 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b1 || (! 1'b1)); + assign when_HazardSimplePlugin_l59_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l62_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l59_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l62_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign switch_Misc_l241_2 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + case(switch_Misc_l241_2) + 3'b000 : begin + _zz_execute_BRANCH_DO = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_DO = (! execute_BranchPlugin_eq); + end + 3'b101 : begin + _zz_execute_BRANCH_DO = (! execute_SRC_LESS); + end + 3'b111 : begin + _zz_execute_BRANCH_DO = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_DO = execute_SRC_LESS; + end + endcase + end + + always @(*) begin + case(execute_BRANCH_CTRL) + BranchCtrlEnum_INC : begin + _zz_execute_BRANCH_DO_1 = 1'b0; + end + BranchCtrlEnum_JAL : begin + _zz_execute_BRANCH_DO_1 = 1'b1; + end + BranchCtrlEnum_JALR : begin + _zz_execute_BRANCH_DO_1 = 1'b1; + end + default : begin + _zz_execute_BRANCH_DO_1 = _zz_execute_BRANCH_DO; + end + endcase + end + + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == BranchCtrlEnum_JALR) ? execute_RS1 : execute_PC); + assign _zz_execute_BranchPlugin_branch_src2 = _zz__zz_execute_BranchPlugin_branch_src2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + assign _zz_execute_BranchPlugin_branch_src2_2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[19] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[18] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[17] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[16] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[15] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[14] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[13] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[12] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[11] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; + end + + always @(*) begin + case(execute_BRANCH_CTRL) + BranchCtrlEnum_JAL : begin + _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_1,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + end + BranchCtrlEnum_JALR : begin + _zz_execute_BranchPlugin_branch_src2_6 = {_zz_execute_BranchPlugin_branch_src2_3,execute_INSTRUCTION[31 : 20]}; + end + default : begin + _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + end + endcase + end + + assign execute_BranchPlugin_branch_src2 = _zz_execute_BranchPlugin_branch_src2_6; + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign when_DebugPlugin_l238 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); + assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); + always @(*) begin + debug_bus_cmd_ready = 1'b1; + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l280) + 6'h01 : begin + if(debug_bus_cmd_payload_wr) begin + debug_bus_cmd_ready = DebugPlugin_injectionPort_ready; + end + end + default : begin + end + endcase + end + end + + always @(*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if(when_DebugPlugin_l257) begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + assign when_DebugPlugin_l257 = (! _zz_when_DebugPlugin_l257); + always @(*) begin + DebugPlugin_injectionPort_valid = 1'b0; + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l280) + 6'h01 : begin + if(debug_bus_cmd_payload_wr) begin + DebugPlugin_injectionPort_valid = 1'b1; + end + end + default : begin + end + endcase + end + end + + assign DebugPlugin_injectionPort_payload = debug_bus_cmd_payload_data; + assign switch_DebugPlugin_l280 = debug_bus_cmd_payload_address[7 : 2]; + assign when_DebugPlugin_l284 = debug_bus_cmd_payload_data[16]; + assign when_DebugPlugin_l284_1 = debug_bus_cmd_payload_data[24]; + assign when_DebugPlugin_l285 = debug_bus_cmd_payload_data[17]; + assign when_DebugPlugin_l285_1 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l286 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l287 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l288 = debug_bus_cmd_payload_data[18]; + assign when_DebugPlugin_l288_1 = debug_bus_cmd_payload_data[26]; + assign when_DebugPlugin_l308 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign when_DebugPlugin_l311 = ((|{writeBack_arbitration_isValid,memory_arbitration_isValid}) == 1'b0); + assign when_DebugPlugin_l324 = (DebugPlugin_stepIt && IBusSimplePlugin_incomingInstruction); + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign when_DebugPlugin_l344 = (DebugPlugin_haltIt || DebugPlugin_stepIt); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck); + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_16 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_17 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_24 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_25 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_26 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_30 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_34 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_35 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_37 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_38 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_39 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_40 = ((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)); + assign when_Pipeline_l124_41 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_44 = (! writeBack_arbitration_isStuck); + assign decode_arbitration_isFlushed = ((|{writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}}) || (|{writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}})); + assign execute_arbitration_isFlushed = ((|{writeBack_arbitration_flushNext,memory_arbitration_flushNext}) || (|{writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}})); + assign memory_arbitration_isFlushed = ((|writeBack_arbitration_flushNext) || (|{writeBack_arbitration_flushIt,memory_arbitration_flushIt})); + assign writeBack_arbitration_isFlushed = (1'b0 || (|writeBack_arbitration_flushIt)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + always @(*) begin + DebugPlugin_injectionPort_ready = 1'b0; + case(IBusSimplePlugin_injector_port_state) + 3'b100 : begin + DebugPlugin_injectionPort_ready = 1'b1; + end + default : begin + end + endcase + end + + assign when_Fetcher_l391 = (! decode_arbitration_isStuck); + assign when_Fetcher_l411 = (IBusSimplePlugin_injector_port_state != 3'b000); + assign when_CsrPlugin_l1669 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1669_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1669_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1669_3 = (! execute_arbitration_isStuck); + assign switch_CsrPlugin_l1031 = CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_CsrPlugin_csrMapping_readDataInit[12 : 11] = CsrPlugin_mstatus_MPP; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_1 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_1[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_1[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_1[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_2[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_2[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_2[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_3[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_3[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + assign CsrPlugin_csrMapping_readDataInit = ((_zz_CsrPlugin_csrMapping_readDataInit | _zz_CsrPlugin_csrMapping_readDataInit_1) | (_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3)); + assign when_CsrPlugin_l1702 = ((execute_arbitration_isValid && execute_IS_CSR) && (({execute_CsrPlugin_csrAddress[11 : 2],2'b00} == 12'h3a0) || ({execute_CsrPlugin_csrAddress[11 : 4],4'b0000} == 12'h3b0))); + assign _zz_when_CsrPlugin_l1709 = (execute_CsrPlugin_csrAddress & 12'hf60); + assign when_CsrPlugin_l1709 = (((execute_arbitration_isValid && execute_IS_CSR) && (5'h03 <= execute_CsrPlugin_csrAddress[4 : 0])) && (((_zz_when_CsrPlugin_l1709 == 12'hb00) || (((_zz_when_CsrPlugin_l1709 == 12'hc00) && (! execute_CsrPlugin_writeInstruction)) && (CsrPlugin_privilege == 2'b11))) || ((execute_CsrPlugin_csrAddress & 12'hfe0) == 12'h320))); + always @(*) begin + when_CsrPlugin_l1719 = CsrPlugin_csrMapping_doForceFailCsr; + if(when_CsrPlugin_l1717) begin + when_CsrPlugin_l1719 = 1'b1; + end + end + + assign when_CsrPlugin_l1717 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1725 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + always @(posedge io_mainClk or posedge resetCtrl_systemReset) begin + if(resetCtrl_systemReset) begin + IBusSimplePlugin_fetchPc_pcReg <= 32'h80000000; + IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; + IBusSimplePlugin_fetchPc_booted <= 1'b0; + IBusSimplePlugin_fetchPc_inc <= 1'b0; + _zz_IBusSimplePlugin_iBusRsp_stages_1_input_valid_1 <= 1'b0; + _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; + _zz_IBusSimplePlugin_injector_decodeInput_valid <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_5 <= 1'b0; + IBusSimplePlugin_pending_value <= 3'b000; + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= 3'b000; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_mcycle <= 64'h0; + CsrPlugin_minstret <= 64'h0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + _zz_5 <= 1'b1; + execute_LightShifterPlugin_isActive <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + IBusSimplePlugin_injector_port_state <= 3'b000; + end else begin + if(IBusSimplePlugin_fetchPc_correction) begin + IBusSimplePlugin_fetchPc_correctionReg <= 1'b1; + end + if(IBusSimplePlugin_fetchPc_output_fire) begin + IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; + end + IBusSimplePlugin_fetchPc_booted <= 1'b1; + if(when_Fetcher_l133) begin + IBusSimplePlugin_fetchPc_inc <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_output_fire) begin + IBusSimplePlugin_fetchPc_inc <= 1'b1; + end + if(when_Fetcher_l133_1) begin + IBusSimplePlugin_fetchPc_inc <= 1'b0; + end + if(when_Fetcher_l160) begin + IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc; + end + if(IBusSimplePlugin_iBusRsp_flush) begin + _zz_IBusSimplePlugin_iBusRsp_stages_1_input_valid_1 <= 1'b0; + end + if(_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusSimplePlugin_iBusRsp_stages_1_input_valid_1 <= (IBusSimplePlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusSimplePlugin_iBusRsp_flush) begin + _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; + end + if(IBusSimplePlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusSimplePlugin_iBusRsp_stages_1_output_valid && (! IBusSimplePlugin_iBusRsp_flush)); + end + if(decode_arbitration_removeIt) begin + _zz_IBusSimplePlugin_injector_decodeInput_valid <= 1'b0; + end + if(IBusSimplePlugin_iBusRsp_output_ready) begin + _zz_IBusSimplePlugin_injector_decodeInput_valid <= (IBusSimplePlugin_iBusRsp_output_valid && (! IBusSimplePlugin_externalFlush)); + end + if(IBusSimplePlugin_fetchPc_flushed) begin + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if(when_Fetcher_l331) begin + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusSimplePlugin_fetchPc_flushed) begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(when_Fetcher_l331_1) begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0; + end + if(IBusSimplePlugin_fetchPc_flushed) begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed) begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(when_Fetcher_l331_2) begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1; + end + if(IBusSimplePlugin_fetchPc_flushed) begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed) begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(when_Fetcher_l331_3) begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2; + end + if(IBusSimplePlugin_fetchPc_flushed) begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed) begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(when_Fetcher_l331_4) begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= IBusSimplePlugin_injector_nextPcCalc_valids_3; + end + if(IBusSimplePlugin_fetchPc_flushed) begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed) begin + IBusSimplePlugin_injector_nextPcCalc_valids_5 <= 1'b0; + end + if(when_Fetcher_l331_5) begin + IBusSimplePlugin_injector_nextPcCalc_valids_5 <= IBusSimplePlugin_injector_nextPcCalc_valids_4; + end + if(IBusSimplePlugin_fetchPc_flushed) begin + IBusSimplePlugin_injector_nextPcCalc_valids_5 <= 1'b0; + end + IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next; + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter); + if(IBusSimplePlugin_iBusRsp_flush) begin + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= IBusSimplePlugin_pending_next; + end + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring) begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + CsrPlugin_interrupt_valid <= 1'b0; + if(when_CsrPlugin_l1296) begin + if(when_CsrPlugin_l1302) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(when_CsrPlugin_l1302_1) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(when_CsrPlugin_l1302_2) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l1335) begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if(when_CsrPlugin_l1335_1) begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if(when_CsrPlugin_l1335_2) begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(when_CsrPlugin_l1340) begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump) begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(when_CsrPlugin_l1390) begin + if(when_CsrPlugin_l1398) begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + end + if(when_CsrPlugin_l1456) begin + case(switch_CsrPlugin_l1460) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= ((|{_zz_when_CsrPlugin_l1302_2,{_zz_when_CsrPlugin_l1302_1,_zz_when_CsrPlugin_l1302}}) || CsrPlugin_thirdPartyWake); + _zz_5 <= 1'b0; + if(when_ShiftPlugins_l169) begin + if(when_ShiftPlugins_l175) begin + execute_LightShifterPlugin_isActive <= 1'b1; + if(execute_LightShifterPlugin_done) begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + end + end + if(execute_arbitration_removeIt) begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_Pipeline_l151) begin + execute_arbitration_isValid <= 1'b0; + end + if(when_Pipeline_l154) begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(when_Pipeline_l151_1) begin + memory_arbitration_isValid <= 1'b0; + end + if(when_Pipeline_l154_1) begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(when_Pipeline_l151_2) begin + writeBack_arbitration_isValid <= 1'b0; + end + if(when_Pipeline_l154_2) begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(IBusSimplePlugin_injector_port_state) + 3'b000 : begin + if(DebugPlugin_injectionPort_valid) begin + IBusSimplePlugin_injector_port_state <= 3'b001; + end + end + 3'b001 : begin + IBusSimplePlugin_injector_port_state <= 3'b010; + end + 3'b010 : begin + IBusSimplePlugin_injector_port_state <= 3'b011; + end + 3'b011 : begin + if(when_Fetcher_l391) begin + IBusSimplePlugin_injector_port_state <= 3'b100; + end + end + 3'b100 : begin + IBusSimplePlugin_injector_port_state <= 3'b000; + end + default : begin + end + endcase + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; + case(switch_CsrPlugin_l1031) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b11; + end + default : begin + end + endcase + end + end + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; + end + end + end + end + + always @(posedge io_mainClk) begin + if(IBusSimplePlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusSimplePlugin_iBusRsp_stages_1_output_payload; + end + if(IBusSimplePlugin_iBusRsp_output_ready) begin + _zz_IBusSimplePlugin_injector_decodeInput_payload_pc <= IBusSimplePlugin_iBusRsp_output_payload_pc; + _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error <= IBusSimplePlugin_iBusRsp_output_payload_rsp_error; + _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + _zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc <= IBusSimplePlugin_iBusRsp_output_payload_isRvc; + end + if(IBusSimplePlugin_injector_decodeInput_ready) begin + IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + if(when_CsrPlugin_l1296) begin + if(when_CsrPlugin_l1302) begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(when_CsrPlugin_l1302_1) begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(when_CsrPlugin_l1302_2) begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(when_CsrPlugin_l1390) begin + if(when_CsrPlugin_l1398) begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= decode_PC; + end + default : begin + end + endcase + end + end + if(when_ShiftPlugins_l169) begin + if(when_ShiftPlugins_l175) begin + execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); + end + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + if(when_Pipeline_l124) begin + decode_to_execute_PC <= _zz_decode_to_execute_PC; + end + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= execute_PC; + end + if(when_Pipeline_l124_2) begin + memory_to_writeBack_PC <= memory_PC; + end + if(when_Pipeline_l124_3) begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if(when_Pipeline_l124_4) begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if(when_Pipeline_l124_5) begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; + end + if(when_Pipeline_l124_7) begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if(when_Pipeline_l124_8) begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; + end + if(when_Pipeline_l124_9) begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if(when_Pipeline_l124_10) begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if(when_Pipeline_l124_11) begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if(when_Pipeline_l124_12) begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if(when_Pipeline_l124_13) begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if(when_Pipeline_l124_14) begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if(when_Pipeline_l124_15) begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if(when_Pipeline_l124_16) begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if(when_Pipeline_l124_17) begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if(when_Pipeline_l124_18) begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if(when_Pipeline_l124_19) begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if(when_Pipeline_l124_20) begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if(when_Pipeline_l124_21) begin + decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + end + if(when_Pipeline_l124_22) begin + execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; + end + if(when_Pipeline_l124_23) begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if(when_Pipeline_l124_24) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; + end + if(when_Pipeline_l124_25) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; + end + if(when_Pipeline_l124_26) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; + end + if(when_Pipeline_l124_27) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; + end + if(when_Pipeline_l124_28) begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if(when_Pipeline_l124_29) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; + end + if(when_Pipeline_l124_30) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; + end + if(when_Pipeline_l124_31) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; + end + if(when_Pipeline_l124_32) begin + decode_to_execute_RS1 <= _zz_decode_to_execute_RS1; + end + if(when_Pipeline_l124_33) begin + decode_to_execute_RS2 <= _zz_decode_to_execute_RS2; + end + if(when_Pipeline_l124_34) begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if(when_Pipeline_l124_35) begin + decode_to_execute_SRC1 <= decode_SRC1; + end + if(when_Pipeline_l124_36) begin + decode_to_execute_SRC2 <= decode_SRC2; + end + if(when_Pipeline_l124_37) begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if(when_Pipeline_l124_38) begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if(when_Pipeline_l124_39) begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if(when_Pipeline_l124_40) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_execute_to_memory_REGFILE_WRITE_DATA; + end + if(when_Pipeline_l124_41) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= memory_REGFILE_WRITE_DATA; + end + if(when_Pipeline_l124_42) begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if(when_Pipeline_l124_43) begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if(when_Pipeline_l124_44) begin + memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + end + if(when_Fetcher_l411) begin + _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst <= DebugPlugin_injectionPort_payload; + end + if(when_CsrPlugin_l1669) begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if(when_CsrPlugin_l1669_1) begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if(when_CsrPlugin_l1669_2) begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if(when_CsrPlugin_l1669_3) begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; + end + end + end + + always @(posedge io_mainClk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready) begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= ((|{writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}}) || IBusSimplePlugin_incomingInstruction); + if(writeBack_arbitration_isValid) begin + DebugPlugin_busReadDataReg <= _zz_lastStageRegFileWrite_payload_data; + end + _zz_when_DebugPlugin_l257 <= debug_bus_cmd_payload_address[2]; + if(when_DebugPlugin_l308) begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @(posedge io_mainClk or posedge resetCtrl_mainClkReset) begin + if(resetCtrl_mainClkReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_debugUsed <= 1'b0; + DebugPlugin_disableEbreak <= 1'b0; + end else begin + if(when_DebugPlugin_l238) begin + DebugPlugin_godmode <= 1'b1; + end + if(debug_bus_cmd_valid) begin + DebugPlugin_debugUsed <= 1'b1; + end + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l280) + 6'h0 : begin + if(debug_bus_cmd_payload_wr) begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(when_DebugPlugin_l284) begin + DebugPlugin_resetIt <= 1'b1; + end + if(when_DebugPlugin_l284_1) begin + DebugPlugin_resetIt <= 1'b0; + end + if(when_DebugPlugin_l285) begin + DebugPlugin_haltIt <= 1'b1; + end + if(when_DebugPlugin_l285_1) begin + DebugPlugin_haltIt <= 1'b0; + end + if(when_DebugPlugin_l286) begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(when_DebugPlugin_l287) begin + DebugPlugin_godmode <= 1'b0; + end + if(when_DebugPlugin_l288) begin + DebugPlugin_disableEbreak <= 1'b1; + end + if(when_DebugPlugin_l288_1) begin + DebugPlugin_disableEbreak <= 1'b0; + end + end + end + default : begin + end + endcase + end + if(when_DebugPlugin_l308) begin + if(when_DebugPlugin_l311) begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(when_DebugPlugin_l324) begin + if(decode_arbitration_isValid) begin + DebugPlugin_haltIt <= 1'b1; + end + end + end + end + + +endmodule + +module MuraxMasterArbiter ( + input wire io_iBus_cmd_valid, + output reg io_iBus_cmd_ready, + input wire [31:0] io_iBus_cmd_payload_pc, + output wire io_iBus_rsp_valid, + output wire io_iBus_rsp_payload_error, + output wire [31:0] io_iBus_rsp_payload_inst, + input wire io_dBus_cmd_valid, + output reg io_dBus_cmd_ready, + input wire io_dBus_cmd_payload_wr, + input wire [3:0] io_dBus_cmd_payload_mask, + input wire [31:0] io_dBus_cmd_payload_address, + input wire [31:0] io_dBus_cmd_payload_data, + input wire [1:0] io_dBus_cmd_payload_size, + output wire io_dBus_rsp_ready, + output wire io_dBus_rsp_error, + output wire [31:0] io_dBus_rsp_data, + output reg io_masterBus_cmd_valid, + input wire io_masterBus_cmd_ready, + output wire io_masterBus_cmd_payload_write, + output wire [31:0] io_masterBus_cmd_payload_address, + output wire [31:0] io_masterBus_cmd_payload_data, + output wire [3:0] io_masterBus_cmd_payload_mask, + input wire io_masterBus_rsp_valid, + input wire [31:0] io_masterBus_rsp_payload_data, + input wire io_mainClk, + input wire resetCtrl_systemReset +); + + reg [3:0] _zz_io_masterBus_cmd_payload_mask; + reg rspPending; + reg rspTarget; + wire io_masterBus_cmd_fire; + wire when_MuraxUtiles_l31; + wire when_MuraxUtiles_l36; + + always @(*) begin + io_masterBus_cmd_valid = (io_iBus_cmd_valid || io_dBus_cmd_valid); + if(when_MuraxUtiles_l36) begin + io_masterBus_cmd_valid = 1'b0; + end + end + + assign io_masterBus_cmd_payload_write = (io_dBus_cmd_valid && io_dBus_cmd_payload_wr); + assign io_masterBus_cmd_payload_address = (io_dBus_cmd_valid ? io_dBus_cmd_payload_address : io_iBus_cmd_payload_pc); + assign io_masterBus_cmd_payload_data = io_dBus_cmd_payload_data; + always @(*) begin + case(io_dBus_cmd_payload_size) + 2'b00 : begin + _zz_io_masterBus_cmd_payload_mask = 4'b0001; + end + 2'b01 : begin + _zz_io_masterBus_cmd_payload_mask = 4'b0011; + end + default : begin + _zz_io_masterBus_cmd_payload_mask = 4'b1111; + end + endcase + end + + assign io_masterBus_cmd_payload_mask = (_zz_io_masterBus_cmd_payload_mask <<< io_dBus_cmd_payload_address[1 : 0]); + always @(*) begin + io_iBus_cmd_ready = (io_masterBus_cmd_ready && (! io_dBus_cmd_valid)); + if(when_MuraxUtiles_l36) begin + io_iBus_cmd_ready = 1'b0; + end + end + + always @(*) begin + io_dBus_cmd_ready = io_masterBus_cmd_ready; + if(when_MuraxUtiles_l36) begin + io_dBus_cmd_ready = 1'b0; + end + end + + assign io_masterBus_cmd_fire = (io_masterBus_cmd_valid && io_masterBus_cmd_ready); + assign when_MuraxUtiles_l31 = (io_masterBus_cmd_fire && (! io_masterBus_cmd_payload_write)); + assign when_MuraxUtiles_l36 = (rspPending && (! io_masterBus_rsp_valid)); + assign io_iBus_rsp_valid = (io_masterBus_rsp_valid && (! rspTarget)); + assign io_iBus_rsp_payload_inst = io_masterBus_rsp_payload_data; + assign io_iBus_rsp_payload_error = 1'b0; + assign io_dBus_rsp_ready = (io_masterBus_rsp_valid && rspTarget); + assign io_dBus_rsp_data = io_masterBus_rsp_payload_data; + assign io_dBus_rsp_error = 1'b0; + always @(posedge io_mainClk or posedge resetCtrl_systemReset) begin + if(resetCtrl_systemReset) begin + rspPending <= 1'b0; + rspTarget <= 1'b0; + end else begin + if(io_masterBus_rsp_valid) begin + rspPending <= 1'b0; + end + if(when_MuraxUtiles_l31) begin + rspTarget <= io_dBus_cmd_valid; + rspPending <= 1'b1; + end + end + end + + +endmodule + +module BufferCC ( + input wire io_dataIn, + output wire io_dataOut, + input wire io_mainClk +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge io_mainClk) begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + + +endmodule + +module InterruptCtrl ( + input wire [1:0] io_inputs, + input wire [1:0] io_clears, + input wire [1:0] io_masks, + output wire [1:0] io_pendings, + input wire io_mainClk, + input wire resetCtrl_systemReset +); + + reg [1:0] pendings; + + assign io_pendings = (pendings & io_masks); + always @(posedge io_mainClk or posedge resetCtrl_systemReset) begin + if(resetCtrl_systemReset) begin + pendings <= 2'b00; + end else begin + pendings <= ((pendings & (~ io_clears)) | io_inputs); + end + end + + +endmodule + +//Timer_1 replaced by Timer + +module Timer ( + input wire io_tick, + input wire io_clear, + input wire [15:0] io_limit, + output wire io_full, + output wire [15:0] io_value, + input wire io_mainClk, + input wire resetCtrl_systemReset +); + + wire [15:0] _zz_counter; + wire [0:0] _zz_counter_1; + reg [15:0] counter; + wire limitHit; + reg inhibitFull; + + assign _zz_counter_1 = (! limitHit); + assign _zz_counter = {15'd0, _zz_counter_1}; + assign limitHit = (counter == io_limit); + assign io_full = ((limitHit && io_tick) && (! inhibitFull)); + assign io_value = counter; + always @(posedge io_mainClk or posedge resetCtrl_systemReset) begin + if(resetCtrl_systemReset) begin + inhibitFull <= 1'b0; + end else begin + if(io_tick) begin + inhibitFull <= limitHit; + end + if(io_clear) begin + inhibitFull <= 1'b0; + end + end + end + + always @(posedge io_mainClk) begin + if(io_tick) begin + counter <= (counter + _zz_counter); + end + if(io_clear) begin + counter <= 16'h0; + end + end + + +endmodule + +module Prescaler ( + input wire io_clear, + input wire [15:0] io_limit, + output wire io_overflow, + input wire io_mainClk, + input wire resetCtrl_systemReset +); + + reg [15:0] counter; + wire when_Prescaler_l17; + + assign when_Prescaler_l17 = (io_clear || io_overflow); + assign io_overflow = (counter == io_limit); + always @(posedge io_mainClk) begin + counter <= (counter + 16'h0001); + if(when_Prescaler_l17) begin + counter <= 16'h0; + end + end + + +endmodule + +//StreamFifo_1 replaced by StreamFifo + +module StreamFifo ( + input wire io_push_valid, + output wire io_push_ready, + input wire [7:0] io_push_payload, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [7:0] io_pop_payload, + input wire io_flush, + output wire [4:0] io_occupancy, + output wire [4:0] io_availability, + input wire io_mainClk, + input wire resetCtrl_systemReset +); + + reg [7:0] logic_ram_spinal_port1; + reg _zz_1; + wire logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [4:0] logic_ptr_push; + reg [4:0] logic_ptr_pop; + wire [4:0] logic_ptr_occupancy; + wire [4:0] logic_ptr_popOnIo; + wire when_Stream_l1248; + reg logic_ptr_wentUp; + wire io_push_fire; + wire logic_push_onRam_write_valid; + wire [3:0] logic_push_onRam_write_payload_address; + wire [7:0] logic_push_onRam_write_payload_data; + wire logic_pop_addressGen_valid; + reg logic_pop_addressGen_ready; + wire [3:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire logic_pop_sync_readArbitation_valid; + wire logic_pop_sync_readArbitation_ready; + wire [3:0] logic_pop_sync_readArbitation_payload; + reg logic_pop_addressGen_rValid; + reg [3:0] logic_pop_addressGen_rData; + wire when_Stream_l375; + wire logic_pop_sync_readPort_cmd_valid; + wire [3:0] logic_pop_sync_readPort_cmd_payload; + wire [7:0] logic_pop_sync_readPort_rsp; + wire logic_pop_sync_readArbitation_translated_valid; + wire logic_pop_sync_readArbitation_translated_ready; + wire [7:0] logic_pop_sync_readArbitation_translated_payload; + wire logic_pop_sync_readArbitation_fire; + reg [4:0] logic_pop_sync_popReg; + reg [7:0] logic_ram [0:15]; + + always @(posedge io_mainClk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data; + end + end + + always @(posedge io_mainClk) begin + if(logic_pop_sync_readPort_cmd_valid) begin + logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 5'h10) == 5'h0); + assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop); + assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo); + assign io_push_ready = (! logic_ptr_full); + assign io_push_fire = (io_push_valid && io_push_ready); + assign logic_ptr_doPush = io_push_fire; + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push[3:0]; + assign logic_push_onRam_write_payload_data = io_push_payload; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop[3:0]; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + always @(*) begin + logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; + if(when_Stream_l375) begin + logic_pop_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); + assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; + assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; + assign logic_pop_sync_readPort_rsp = logic_ram_spinal_port1; + assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; + assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; + assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; + assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; + assign logic_pop_sync_readArbitation_translated_payload = logic_pop_sync_readPort_rsp; + assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; + assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload = logic_pop_sync_readArbitation_translated_payload; + assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); + assign logic_ptr_popOnIo = logic_pop_sync_popReg; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (5'h10 - logic_ptr_occupancy); + always @(posedge io_mainClk or posedge resetCtrl_systemReset) begin + if(resetCtrl_systemReset) begin + logic_ptr_push <= 5'h0; + logic_ptr_pop <= 5'h0; + logic_ptr_wentUp <= 1'b0; + logic_pop_addressGen_rValid <= 1'b0; + logic_pop_sync_popReg <= 5'h0; + end else begin + if(when_Stream_l1248) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 5'h01); + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 5'h01); + end + if(io_flush) begin + logic_ptr_push <= 5'h0; + logic_ptr_pop <= 5'h0; + end + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; + end + if(io_flush) begin + logic_pop_addressGen_rValid <= 1'b0; + end + if(logic_pop_sync_readArbitation_fire) begin + logic_pop_sync_popReg <= logic_ptr_pop; + end + if(io_flush) begin + logic_pop_sync_popReg <= 5'h0; + end + end + end + + always @(posedge io_mainClk) begin + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rData <= logic_pop_addressGen_payload; + end + end + + +endmodule + +module UartCtrl ( + input wire [2:0] io_config_frame_dataLength, + input wire [0:0] io_config_frame_stop, + input wire [1:0] io_config_frame_parity, + input wire [19:0] io_config_clockDivider, + input wire io_write_valid, + output reg io_write_ready, + input wire [7:0] io_write_payload, + output wire io_read_valid, + input wire io_read_ready, + output wire [7:0] io_read_payload, + output wire io_uart_txd, + input wire io_uart_rxd, + output wire io_readError, + input wire io_writeBreak, + output wire io_readBreak, + input wire io_mainClk, + input wire resetCtrl_systemReset +); + localparam UartStopType_ONE = 1'd0; + localparam UartStopType_TWO = 1'd1; + localparam UartParityType_NONE = 2'd0; + localparam UartParityType_EVEN = 2'd1; + localparam UartParityType_ODD = 2'd2; + + wire tx_io_write_ready; + wire tx_io_txd; + wire rx_io_read_valid; + wire [7:0] rx_io_read_payload; + wire rx_io_rts; + wire rx_io_error; + wire rx_io_break; + reg [19:0] clockDivider_counter; + wire clockDivider_tick; + reg clockDivider_tickReg; + reg io_write_thrown_valid; + wire io_write_thrown_ready; + wire [7:0] io_write_thrown_payload; + `ifndef SYNTHESIS + reg [23:0] io_config_frame_stop_string; + reg [31:0] io_config_frame_parity_string; + `endif + + + UartCtrlTx tx ( + .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i + .io_configFrame_stop (io_config_frame_stop ), //i + .io_configFrame_parity (io_config_frame_parity[1:0] ), //i + .io_samplingTick (clockDivider_tickReg ), //i + .io_write_valid (io_write_thrown_valid ), //i + .io_write_ready (tx_io_write_ready ), //o + .io_write_payload (io_write_thrown_payload[7:0] ), //i + .io_cts (1'b0 ), //i + .io_txd (tx_io_txd ), //o + .io_break (io_writeBreak ), //i + .io_mainClk (io_mainClk ), //i + .resetCtrl_systemReset (resetCtrl_systemReset ) //i + ); + UartCtrlRx rx ( + .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i + .io_configFrame_stop (io_config_frame_stop ), //i + .io_configFrame_parity (io_config_frame_parity[1:0] ), //i + .io_samplingTick (clockDivider_tickReg ), //i + .io_read_valid (rx_io_read_valid ), //o + .io_read_ready (io_read_ready ), //i + .io_read_payload (rx_io_read_payload[7:0] ), //o + .io_rxd (io_uart_rxd ), //i + .io_rts (rx_io_rts ), //o + .io_error (rx_io_error ), //o + .io_break (rx_io_break ), //o + .io_mainClk (io_mainClk ), //i + .resetCtrl_systemReset (resetCtrl_systemReset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_config_frame_stop) + UartStopType_ONE : io_config_frame_stop_string = "ONE"; + UartStopType_TWO : io_config_frame_stop_string = "TWO"; + default : io_config_frame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_config_frame_parity) + UartParityType_NONE : io_config_frame_parity_string = "NONE"; + UartParityType_EVEN : io_config_frame_parity_string = "EVEN"; + UartParityType_ODD : io_config_frame_parity_string = "ODD "; + default : io_config_frame_parity_string = "????"; + endcase + end + `endif + + assign clockDivider_tick = (clockDivider_counter == 20'h0); + always @(*) begin + io_write_thrown_valid = io_write_valid; + if(rx_io_break) begin + io_write_thrown_valid = 1'b0; + end + end + + always @(*) begin + io_write_ready = io_write_thrown_ready; + if(rx_io_break) begin + io_write_ready = 1'b1; + end + end + + assign io_write_thrown_payload = io_write_payload; + assign io_write_thrown_ready = tx_io_write_ready; + assign io_read_valid = rx_io_read_valid; + assign io_read_payload = rx_io_read_payload; + assign io_uart_txd = tx_io_txd; + assign io_readError = rx_io_error; + assign io_readBreak = rx_io_break; + always @(posedge io_mainClk or posedge resetCtrl_systemReset) begin + if(resetCtrl_systemReset) begin + clockDivider_counter <= 20'h0; + clockDivider_tickReg <= 1'b0; + end else begin + clockDivider_tickReg <= clockDivider_tick; + clockDivider_counter <= (clockDivider_counter - 20'h00001); + if(clockDivider_tick) begin + clockDivider_counter <= io_config_clockDivider; + end + end + end + + +endmodule + +module BufferCC_1 ( + input wire [31:0] io_dataIn, + output wire [31:0] io_dataOut, + input wire io_mainClk, + input wire resetCtrl_systemReset +); + + (* async_reg = "true" *) reg [31:0] buffers_0; + (* async_reg = "true" *) reg [31:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge io_mainClk) begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + + +endmodule + +module FlowCCUnsafeByToggle ( + input wire io_input_valid, + input wire io_input_payload_last, + input wire [0:0] io_input_payload_fragment, + output wire io_output_valid, + output wire io_output_payload_last, + output wire [0:0] io_output_payload_fragment, + input wire io_jtag_tck, + input wire io_mainClk, + input wire resetCtrl_mainClkReset +); + + wire inputArea_target_buffercc_io_dataOut; + reg inputArea_target; + reg inputArea_data_last; + reg [0:0] inputArea_data_fragment; + wire outputArea_target; + reg outputArea_hit; + wire outputArea_flow_valid; + wire outputArea_flow_payload_last; + wire [0:0] outputArea_flow_payload_fragment; + reg outputArea_flow_m2sPipe_valid; + (* async_reg = "true" *) reg outputArea_flow_m2sPipe_payload_last; + (* async_reg = "true" *) reg [0:0] outputArea_flow_m2sPipe_payload_fragment; + + (* keep_hierarchy = "TRUE" *) BufferCC_2 inputArea_target_buffercc ( + .io_dataIn (inputArea_target ), //i + .io_dataOut (inputArea_target_buffercc_io_dataOut), //o + .io_mainClk (io_mainClk ), //i + .resetCtrl_mainClkReset (resetCtrl_mainClkReset ) //i + ); + initial begin + `ifndef SYNTHESIS + inputArea_target = $urandom; + outputArea_hit = $urandom; + `endif + end + + assign outputArea_target = inputArea_target_buffercc_io_dataOut; + assign outputArea_flow_valid = (outputArea_target != outputArea_hit); + assign outputArea_flow_payload_last = inputArea_data_last; + assign outputArea_flow_payload_fragment = inputArea_data_fragment; + assign io_output_valid = outputArea_flow_m2sPipe_valid; + assign io_output_payload_last = outputArea_flow_m2sPipe_payload_last; + assign io_output_payload_fragment = outputArea_flow_m2sPipe_payload_fragment; + always @(posedge io_jtag_tck) begin + if(io_input_valid) begin + inputArea_target <= (! inputArea_target); + inputArea_data_last <= io_input_payload_last; + inputArea_data_fragment <= io_input_payload_fragment; + end + end + + always @(posedge io_mainClk) begin + outputArea_hit <= outputArea_target; + if(outputArea_flow_valid) begin + outputArea_flow_m2sPipe_payload_last <= outputArea_flow_payload_last; + outputArea_flow_m2sPipe_payload_fragment <= outputArea_flow_payload_fragment; + end + end + + always @(posedge io_mainClk or posedge resetCtrl_mainClkReset) begin + if(resetCtrl_mainClkReset) begin + outputArea_flow_m2sPipe_valid <= 1'b0; + end else begin + outputArea_flow_m2sPipe_valid <= outputArea_flow_valid; + end + end + + +endmodule + +module StreamFifoLowLatency ( + input wire io_push_valid, + output wire io_push_ready, + input wire io_push_payload_error, + input wire [31:0] io_push_payload_inst, + output wire io_pop_valid, + input wire io_pop_ready, + output wire io_pop_payload_error, + output wire [31:0] io_pop_payload_inst, + input wire io_flush, + output wire [0:0] io_occupancy, + output wire [0:0] io_availability, + input wire io_mainClk, + input wire resetCtrl_systemReset +); + + wire fifo_io_push_ready; + wire fifo_io_pop_valid; + wire fifo_io_pop_payload_error; + wire [31:0] fifo_io_pop_payload_inst; + wire [0:0] fifo_io_occupancy; + wire [0:0] fifo_io_availability; + + StreamFifo_2 fifo ( + .io_push_valid (io_push_valid ), //i + .io_push_ready (fifo_io_push_ready ), //o + .io_push_payload_error (io_push_payload_error ), //i + .io_push_payload_inst (io_push_payload_inst[31:0] ), //i + .io_pop_valid (fifo_io_pop_valid ), //o + .io_pop_ready (io_pop_ready ), //i + .io_pop_payload_error (fifo_io_pop_payload_error ), //o + .io_pop_payload_inst (fifo_io_pop_payload_inst[31:0]), //o + .io_flush (io_flush ), //i + .io_occupancy (fifo_io_occupancy ), //o + .io_availability (fifo_io_availability ), //o + .io_mainClk (io_mainClk ), //i + .resetCtrl_systemReset (resetCtrl_systemReset ) //i + ); + assign io_push_ready = fifo_io_push_ready; + assign io_pop_valid = fifo_io_pop_valid; + assign io_pop_payload_error = fifo_io_pop_payload_error; + assign io_pop_payload_inst = fifo_io_pop_payload_inst; + assign io_occupancy = fifo_io_occupancy; + assign io_availability = fifo_io_availability; + +endmodule + +module UartCtrlRx ( + input wire [2:0] io_configFrame_dataLength, + input wire [0:0] io_configFrame_stop, + input wire [1:0] io_configFrame_parity, + input wire io_samplingTick, + output wire io_read_valid, + input wire io_read_ready, + output wire [7:0] io_read_payload, + input wire io_rxd, + output wire io_rts, + output reg io_error, + output wire io_break, + input wire io_mainClk, + input wire resetCtrl_systemReset +); + localparam UartStopType_ONE = 1'd0; + localparam UartStopType_TWO = 1'd1; + localparam UartParityType_NONE = 2'd0; + localparam UartParityType_EVEN = 2'd1; + localparam UartParityType_ODD = 2'd2; + localparam UartCtrlRxState_IDLE = 3'd0; + localparam UartCtrlRxState_START = 3'd1; + localparam UartCtrlRxState_DATA = 3'd2; + localparam UartCtrlRxState_PARITY = 3'd3; + localparam UartCtrlRxState_STOP = 3'd4; + + wire io_rxd_buffercc_io_dataOut; + wire [2:0] _zz_when_UartCtrlRx_l139; + wire [0:0] _zz_when_UartCtrlRx_l139_1; + reg _zz_io_rts; + wire sampler_synchroniser; + wire sampler_samples_0; + reg sampler_samples_1; + reg sampler_samples_2; + reg sampler_value; + reg sampler_tick; + reg [2:0] bitTimer_counter; + reg bitTimer_tick; + wire when_UartCtrlRx_l43; + reg [2:0] bitCounter_value; + reg [6:0] break_counter; + wire break_valid; + wire when_UartCtrlRx_l69; + reg [2:0] stateMachine_state; + reg stateMachine_parity; + reg [7:0] stateMachine_shifter; + reg stateMachine_validReg; + wire when_UartCtrlRx_l93; + wire when_UartCtrlRx_l103; + wire when_UartCtrlRx_l111; + wire when_UartCtrlRx_l113; + wire when_UartCtrlRx_l125; + wire when_UartCtrlRx_l136; + wire when_UartCtrlRx_l139; + `ifndef SYNTHESIS + reg [23:0] io_configFrame_stop_string; + reg [31:0] io_configFrame_parity_string; + reg [47:0] stateMachine_state_string; + `endif + + + assign _zz_when_UartCtrlRx_l139_1 = ((io_configFrame_stop == UartStopType_ONE) ? 1'b0 : 1'b1); + assign _zz_when_UartCtrlRx_l139 = {2'd0, _zz_when_UartCtrlRx_l139_1}; + (* keep_hierarchy = "TRUE" *) BufferCC_3 io_rxd_buffercc ( + .io_dataIn (io_rxd ), //i + .io_dataOut (io_rxd_buffercc_io_dataOut), //o + .io_mainClk (io_mainClk ), //i + .resetCtrl_systemReset (resetCtrl_systemReset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_configFrame_stop) + UartStopType_ONE : io_configFrame_stop_string = "ONE"; + UartStopType_TWO : io_configFrame_stop_string = "TWO"; + default : io_configFrame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_configFrame_parity) + UartParityType_NONE : io_configFrame_parity_string = "NONE"; + UartParityType_EVEN : io_configFrame_parity_string = "EVEN"; + UartParityType_ODD : io_configFrame_parity_string = "ODD "; + default : io_configFrame_parity_string = "????"; + endcase + end + always @(*) begin + case(stateMachine_state) + UartCtrlRxState_IDLE : stateMachine_state_string = "IDLE "; + UartCtrlRxState_START : stateMachine_state_string = "START "; + UartCtrlRxState_DATA : stateMachine_state_string = "DATA "; + UartCtrlRxState_PARITY : stateMachine_state_string = "PARITY"; + UartCtrlRxState_STOP : stateMachine_state_string = "STOP "; + default : stateMachine_state_string = "??????"; + endcase + end + `endif + + always @(*) begin + io_error = 1'b0; + case(stateMachine_state) + UartCtrlRxState_IDLE : begin + end + UartCtrlRxState_START : begin + end + UartCtrlRxState_DATA : begin + end + UartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + if(!when_UartCtrlRx_l125) begin + io_error = 1'b1; + end + end + end + default : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l136) begin + io_error = 1'b1; + end + end + end + endcase + end + + assign io_rts = _zz_io_rts; + assign sampler_synchroniser = io_rxd_buffercc_io_dataOut; + assign sampler_samples_0 = sampler_synchroniser; + always @(*) begin + bitTimer_tick = 1'b0; + if(sampler_tick) begin + if(when_UartCtrlRx_l43) begin + bitTimer_tick = 1'b1; + end + end + end + + assign when_UartCtrlRx_l43 = (bitTimer_counter == 3'b000); + assign break_valid = (break_counter == 7'h41); + assign when_UartCtrlRx_l69 = (io_samplingTick && (! break_valid)); + assign io_break = break_valid; + assign io_read_valid = stateMachine_validReg; + assign when_UartCtrlRx_l93 = ((sampler_tick && (! sampler_value)) && (! break_valid)); + assign when_UartCtrlRx_l103 = (sampler_value == 1'b1); + assign when_UartCtrlRx_l111 = (bitCounter_value == io_configFrame_dataLength); + assign when_UartCtrlRx_l113 = (io_configFrame_parity == UartParityType_NONE); + assign when_UartCtrlRx_l125 = (stateMachine_parity == sampler_value); + assign when_UartCtrlRx_l136 = (! sampler_value); + assign when_UartCtrlRx_l139 = (bitCounter_value == _zz_when_UartCtrlRx_l139); + assign io_read_payload = stateMachine_shifter; + always @(posedge io_mainClk or posedge resetCtrl_systemReset) begin + if(resetCtrl_systemReset) begin + _zz_io_rts <= 1'b0; + sampler_samples_1 <= 1'b1; + sampler_samples_2 <= 1'b1; + sampler_value <= 1'b1; + sampler_tick <= 1'b0; + break_counter <= 7'h0; + stateMachine_state <= UartCtrlRxState_IDLE; + stateMachine_validReg <= 1'b0; + end else begin + _zz_io_rts <= (! io_read_ready); + if(io_samplingTick) begin + sampler_samples_1 <= sampler_samples_0; + end + if(io_samplingTick) begin + sampler_samples_2 <= sampler_samples_1; + end + sampler_value <= (((1'b0 || ((1'b1 && sampler_samples_0) && sampler_samples_1)) || ((1'b1 && sampler_samples_0) && sampler_samples_2)) || ((1'b1 && sampler_samples_1) && sampler_samples_2)); + sampler_tick <= io_samplingTick; + if(sampler_value) begin + break_counter <= 7'h0; + end else begin + if(when_UartCtrlRx_l69) begin + break_counter <= (break_counter + 7'h01); + end + end + stateMachine_validReg <= 1'b0; + case(stateMachine_state) + UartCtrlRxState_IDLE : begin + if(when_UartCtrlRx_l93) begin + stateMachine_state <= UartCtrlRxState_START; + end + end + UartCtrlRxState_START : begin + if(bitTimer_tick) begin + stateMachine_state <= UartCtrlRxState_DATA; + if(when_UartCtrlRx_l103) begin + stateMachine_state <= UartCtrlRxState_IDLE; + end + end + end + UartCtrlRxState_DATA : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l111) begin + if(when_UartCtrlRx_l113) begin + stateMachine_state <= UartCtrlRxState_STOP; + stateMachine_validReg <= 1'b1; + end else begin + stateMachine_state <= UartCtrlRxState_PARITY; + end + end + end + end + UartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l125) begin + stateMachine_state <= UartCtrlRxState_STOP; + stateMachine_validReg <= 1'b1; + end else begin + stateMachine_state <= UartCtrlRxState_IDLE; + end + end + end + default : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l136) begin + stateMachine_state <= UartCtrlRxState_IDLE; + end else begin + if(when_UartCtrlRx_l139) begin + stateMachine_state <= UartCtrlRxState_IDLE; + end + end + end + end + endcase + end + end + + always @(posedge io_mainClk) begin + if(sampler_tick) begin + bitTimer_counter <= (bitTimer_counter - 3'b001); + if(when_UartCtrlRx_l43) begin + bitTimer_counter <= 3'b100; + end + end + if(bitTimer_tick) begin + bitCounter_value <= (bitCounter_value + 3'b001); + end + if(bitTimer_tick) begin + stateMachine_parity <= (stateMachine_parity ^ sampler_value); + end + case(stateMachine_state) + UartCtrlRxState_IDLE : begin + if(when_UartCtrlRx_l93) begin + bitTimer_counter <= 3'b001; + end + end + UartCtrlRxState_START : begin + if(bitTimer_tick) begin + bitCounter_value <= 3'b000; + stateMachine_parity <= (io_configFrame_parity == UartParityType_ODD); + end + end + UartCtrlRxState_DATA : begin + if(bitTimer_tick) begin + stateMachine_shifter[bitCounter_value] <= sampler_value; + if(when_UartCtrlRx_l111) begin + bitCounter_value <= 3'b000; + end + end + end + UartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + bitCounter_value <= 3'b000; + end + end + default : begin + end + endcase + end + + +endmodule + +module UartCtrlTx ( + input wire [2:0] io_configFrame_dataLength, + input wire [0:0] io_configFrame_stop, + input wire [1:0] io_configFrame_parity, + input wire io_samplingTick, + input wire io_write_valid, + output reg io_write_ready, + input wire [7:0] io_write_payload, + input wire io_cts, + output wire io_txd, + input wire io_break, + input wire io_mainClk, + input wire resetCtrl_systemReset +); + localparam UartStopType_ONE = 1'd0; + localparam UartStopType_TWO = 1'd1; + localparam UartParityType_NONE = 2'd0; + localparam UartParityType_EVEN = 2'd1; + localparam UartParityType_ODD = 2'd2; + localparam UartCtrlTxState_IDLE = 3'd0; + localparam UartCtrlTxState_START = 3'd1; + localparam UartCtrlTxState_DATA = 3'd2; + localparam UartCtrlTxState_PARITY = 3'd3; + localparam UartCtrlTxState_STOP = 3'd4; + + wire [2:0] _zz_clockDivider_counter_valueNext; + wire [0:0] _zz_clockDivider_counter_valueNext_1; + wire [2:0] _zz_when_UartCtrlTx_l93; + wire [0:0] _zz_when_UartCtrlTx_l93_1; + reg clockDivider_counter_willIncrement; + wire clockDivider_counter_willClear; + reg [2:0] clockDivider_counter_valueNext; + reg [2:0] clockDivider_counter_value; + wire clockDivider_counter_willOverflowIfInc; + wire clockDivider_counter_willOverflow; + reg [2:0] tickCounter_value; + reg [2:0] stateMachine_state; + reg stateMachine_parity; + reg stateMachine_txd; + wire when_UartCtrlTx_l58; + wire when_UartCtrlTx_l73; + wire when_UartCtrlTx_l76; + wire when_UartCtrlTx_l93; + wire [2:0] _zz_stateMachine_state; + reg _zz_io_txd; + `ifndef SYNTHESIS + reg [23:0] io_configFrame_stop_string; + reg [31:0] io_configFrame_parity_string; + reg [47:0] stateMachine_state_string; + reg [47:0] _zz_stateMachine_state_string; + `endif + + + assign _zz_clockDivider_counter_valueNext_1 = clockDivider_counter_willIncrement; + assign _zz_clockDivider_counter_valueNext = {2'd0, _zz_clockDivider_counter_valueNext_1}; + assign _zz_when_UartCtrlTx_l93_1 = ((io_configFrame_stop == UartStopType_ONE) ? 1'b0 : 1'b1); + assign _zz_when_UartCtrlTx_l93 = {2'd0, _zz_when_UartCtrlTx_l93_1}; + `ifndef SYNTHESIS + always @(*) begin + case(io_configFrame_stop) + UartStopType_ONE : io_configFrame_stop_string = "ONE"; + UartStopType_TWO : io_configFrame_stop_string = "TWO"; + default : io_configFrame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_configFrame_parity) + UartParityType_NONE : io_configFrame_parity_string = "NONE"; + UartParityType_EVEN : io_configFrame_parity_string = "EVEN"; + UartParityType_ODD : io_configFrame_parity_string = "ODD "; + default : io_configFrame_parity_string = "????"; + endcase + end + always @(*) begin + case(stateMachine_state) + UartCtrlTxState_IDLE : stateMachine_state_string = "IDLE "; + UartCtrlTxState_START : stateMachine_state_string = "START "; + UartCtrlTxState_DATA : stateMachine_state_string = "DATA "; + UartCtrlTxState_PARITY : stateMachine_state_string = "PARITY"; + UartCtrlTxState_STOP : stateMachine_state_string = "STOP "; + default : stateMachine_state_string = "??????"; + endcase + end + always @(*) begin + case(_zz_stateMachine_state) + UartCtrlTxState_IDLE : _zz_stateMachine_state_string = "IDLE "; + UartCtrlTxState_START : _zz_stateMachine_state_string = "START "; + UartCtrlTxState_DATA : _zz_stateMachine_state_string = "DATA "; + UartCtrlTxState_PARITY : _zz_stateMachine_state_string = "PARITY"; + UartCtrlTxState_STOP : _zz_stateMachine_state_string = "STOP "; + default : _zz_stateMachine_state_string = "??????"; + endcase + end + `endif + + always @(*) begin + clockDivider_counter_willIncrement = 1'b0; + if(io_samplingTick) begin + clockDivider_counter_willIncrement = 1'b1; + end + end + + assign clockDivider_counter_willClear = 1'b0; + assign clockDivider_counter_willOverflowIfInc = (clockDivider_counter_value == 3'b100); + assign clockDivider_counter_willOverflow = (clockDivider_counter_willOverflowIfInc && clockDivider_counter_willIncrement); + always @(*) begin + if(clockDivider_counter_willOverflow) begin + clockDivider_counter_valueNext = 3'b000; + end else begin + clockDivider_counter_valueNext = (clockDivider_counter_value + _zz_clockDivider_counter_valueNext); + end + if(clockDivider_counter_willClear) begin + clockDivider_counter_valueNext = 3'b000; + end + end + + always @(*) begin + stateMachine_txd = 1'b1; + case(stateMachine_state) + UartCtrlTxState_IDLE : begin + end + UartCtrlTxState_START : begin + stateMachine_txd = 1'b0; + end + UartCtrlTxState_DATA : begin + stateMachine_txd = io_write_payload[tickCounter_value]; + end + UartCtrlTxState_PARITY : begin + stateMachine_txd = stateMachine_parity; + end + default : begin + end + endcase + end + + always @(*) begin + io_write_ready = io_break; + case(stateMachine_state) + UartCtrlTxState_IDLE : begin + end + UartCtrlTxState_START : begin + end + UartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + io_write_ready = 1'b1; + end + end + end + UartCtrlTxState_PARITY : begin + end + default : begin + end + endcase + end + + assign when_UartCtrlTx_l58 = ((io_write_valid && (! io_cts)) && clockDivider_counter_willOverflow); + assign when_UartCtrlTx_l73 = (tickCounter_value == io_configFrame_dataLength); + assign when_UartCtrlTx_l76 = (io_configFrame_parity == UartParityType_NONE); + assign when_UartCtrlTx_l93 = (tickCounter_value == _zz_when_UartCtrlTx_l93); + assign _zz_stateMachine_state = (io_write_valid ? UartCtrlTxState_START : UartCtrlTxState_IDLE); + assign io_txd = _zz_io_txd; + always @(posedge io_mainClk or posedge resetCtrl_systemReset) begin + if(resetCtrl_systemReset) begin + clockDivider_counter_value <= 3'b000; + stateMachine_state <= UartCtrlTxState_IDLE; + _zz_io_txd <= 1'b1; + end else begin + clockDivider_counter_value <= clockDivider_counter_valueNext; + case(stateMachine_state) + UartCtrlTxState_IDLE : begin + if(when_UartCtrlTx_l58) begin + stateMachine_state <= UartCtrlTxState_START; + end + end + UartCtrlTxState_START : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_state <= UartCtrlTxState_DATA; + end + end + UartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + if(when_UartCtrlTx_l76) begin + stateMachine_state <= UartCtrlTxState_STOP; + end else begin + stateMachine_state <= UartCtrlTxState_PARITY; + end + end + end + end + UartCtrlTxState_PARITY : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_state <= UartCtrlTxState_STOP; + end + end + default : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l93) begin + stateMachine_state <= _zz_stateMachine_state; + end + end + end + endcase + _zz_io_txd <= (stateMachine_txd && (! io_break)); + end + end + + always @(posedge io_mainClk) begin + if(clockDivider_counter_willOverflow) begin + tickCounter_value <= (tickCounter_value + 3'b001); + end + if(clockDivider_counter_willOverflow) begin + stateMachine_parity <= (stateMachine_parity ^ stateMachine_txd); + end + case(stateMachine_state) + UartCtrlTxState_IDLE : begin + end + UartCtrlTxState_START : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_parity <= (io_configFrame_parity == UartParityType_ODD); + tickCounter_value <= 3'b000; + end + end + UartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + tickCounter_value <= 3'b000; + end + end + end + UartCtrlTxState_PARITY : begin + if(clockDivider_counter_willOverflow) begin + tickCounter_value <= 3'b000; + end + end + default : begin + end + endcase + end + + +endmodule + +module BufferCC_2 ( + input wire io_dataIn, + output wire io_dataOut, + input wire io_mainClk, + input wire resetCtrl_mainClkReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + initial begin + `ifndef SYNTHESIS + buffers_0 = $urandom; + buffers_1 = $urandom; + `endif + end + + assign io_dataOut = buffers_1; + always @(posedge io_mainClk) begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + + +endmodule + +module StreamFifo_2 ( + input wire io_push_valid, + output reg io_push_ready, + input wire io_push_payload_error, + input wire [31:0] io_push_payload_inst, + output reg io_pop_valid, + input wire io_pop_ready, + output reg io_pop_payload_error, + output reg [31:0] io_pop_payload_inst, + input wire io_flush, + output wire [0:0] io_occupancy, + output wire [0:0] io_availability, + input wire io_mainClk, + input wire resetCtrl_systemReset +); + + reg oneStage_doFlush; + wire oneStage_buffer_valid; + wire oneStage_buffer_ready; + wire oneStage_buffer_payload_error; + wire [31:0] oneStage_buffer_payload_inst; + reg io_push_rValid; + reg io_push_rData_error; + reg [31:0] io_push_rData_inst; + wire when_Stream_l375; + wire when_Stream_l1230; + + always @(*) begin + oneStage_doFlush = io_flush; + if(when_Stream_l1230) begin + if(io_pop_ready) begin + oneStage_doFlush = 1'b1; + end + end + end + + always @(*) begin + io_push_ready = oneStage_buffer_ready; + if(when_Stream_l375) begin + io_push_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! oneStage_buffer_valid); + assign oneStage_buffer_valid = io_push_rValid; + assign oneStage_buffer_payload_error = io_push_rData_error; + assign oneStage_buffer_payload_inst = io_push_rData_inst; + always @(*) begin + io_pop_valid = oneStage_buffer_valid; + if(when_Stream_l1230) begin + io_pop_valid = io_push_valid; + end + end + + assign oneStage_buffer_ready = io_pop_ready; + always @(*) begin + io_pop_payload_error = oneStage_buffer_payload_error; + if(when_Stream_l1230) begin + io_pop_payload_error = io_push_payload_error; + end + end + + always @(*) begin + io_pop_payload_inst = oneStage_buffer_payload_inst; + if(when_Stream_l1230) begin + io_pop_payload_inst = io_push_payload_inst; + end + end + + assign io_occupancy = oneStage_buffer_valid; + assign io_availability = (! oneStage_buffer_valid); + assign when_Stream_l1230 = (! oneStage_buffer_valid); + always @(posedge io_mainClk or posedge resetCtrl_systemReset) begin + if(resetCtrl_systemReset) begin + io_push_rValid <= 1'b0; + end else begin + if(io_push_ready) begin + io_push_rValid <= io_push_valid; + end + if(oneStage_doFlush) begin + io_push_rValid <= 1'b0; + end + end + end + + always @(posedge io_mainClk) begin + if(io_push_ready) begin + io_push_rData_error <= io_push_payload_error; + io_push_rData_inst <= io_push_payload_inst; + end + end + + +endmodule + +module BufferCC_3 ( + input wire io_dataIn, + output wire io_dataOut, + input wire io_mainClk, + input wire resetCtrl_systemReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge io_mainClk or posedge resetCtrl_systemReset) begin + if(resetCtrl_systemReset) begin + buffers_0 <= 1'b0; + buffers_1 <= 1'b0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule diff --git a/VexRiscv/murax/Murax.v_toplevel_system_ram_ram_symbol0.bin b/VexRiscv/murax/Murax.v_toplevel_system_ram_ram_symbol0.bin new file mode 100644 index 0000000..c190c3d --- /dev/null +++ b/VexRiscv/murax/Murax.v_toplevel_system_ram_ram_symbol0.bin @@ -0,0 +1,1024 @@ +01101111 +00010011 +00010011 +00010011 +00010011 +00010011 +00010011 +00010011 +00100011 +00100011 +00100011 +00100011 +00100011 +00100011 +00100011 +00100011 +00100011 +00100011 +00100011 +00100011 +00100011 +00100011 +00100011 +00100011 +00010011 +11101111 +10000011 +10000011 +00000011 +10000011 +00000011 +10000011 +00000011 +10000011 +00000011 +10000011 +00000011 +10000011 +00000011 +10000011 +00000011 +10000011 +00010011 +01110011 +10010111 +10010011 +00010011 +00010111 +00010011 +10010111 +10010011 +01100011 +00100011 +00010011 +01101111 +00010111 +00010011 +00010011 +10010111 +10010011 +01100011 +10000011 +00010011 +00100011 +11100111 +00000011 +01101111 +00010011 +00110111 +00010011 +01110011 +00110111 +00010011 +01110011 +11101111 +01101111 +00010011 +00100011 +00010011 +00100011 +10000011 +00100011 +10000011 +00100011 +00010011 +00000011 +00010011 +01100111 +00010011 +00100011 +00010011 +00100011 +00010011 +00000011 +00010011 +01100111 +00010011 +00100011 +00010011 +00100011 +10000011 +00100011 +10000011 +00010011 +00100011 +00010011 +00000011 +00010011 +01100111 +00010011 +00100011 +00010011 +00100011 +10000011 +10000011 +10010011 +10010011 +00010011 +00000011 +00010011 +01100111 +00010011 +00100011 +00010011 +00100011 +10000011 +10000011 +10010011 +00010011 +00000011 +00010011 +01100111 +00010011 +00100011 +00100011 +00010011 +00100011 +00100011 +00010011 +00000011 +11101111 +10010011 +11100011 +10000011 +00000011 +00100011 +00010011 +10000011 +00000011 +00010011 +01100111 +00010011 +00100011 +00010011 +00100011 +00100011 +10000011 +00000011 +10000011 +00100011 +10000011 +10000011 +00010011 +10000011 +10000011 +10010011 +00110011 +10000011 +10000011 +10010011 +00110011 +10000011 +00100011 +00010011 +00000011 +00010011 +01100111 +00010011 +00100011 +00100011 +00010011 +10010011 +00100011 +10010011 +00100011 +10010011 +00100011 +00100011 +10110111 +00010011 +11101111 +00110111 +11101111 +10110111 +00010011 +11101111 +10110111 +00110111 +00010011 +00100011 +10110111 +10010011 +00010011 +00100011 +10110111 +10010011 +00110111 +00010011 +00100011 +10110111 +10010011 +00010011 +00100011 +10110111 +10010011 +00010011 +00100011 +10110111 +00010011 +00100011 +10110111 +00100011 +10110111 +00010011 +00100011 +10110111 +00010011 +00100011 +10000011 +00000011 +10110011 +00100011 +00000011 +10000011 +10110011 +00000011 +10110011 +00100011 +00100011 +01101111 +10000011 +10010011 +00100011 +00000011 +10110111 +10010011 +11100011 +10110111 +10000011 +10010011 +10110111 +10000011 +10010011 +00010011 +10110111 +00110011 +00100011 +01101111 +00010011 +00100011 +00010011 +10110111 +10010011 +10000011 +10010011 +01100011 +10110111 +00000011 +10110111 +00010011 +00100011 +10110111 +10010011 +00010011 +00100011 +01101111 +10110111 +00000011 +10110111 +00010011 +00100011 +10110111 +10000011 +10010011 +11100011 +00010011 +00000011 +00010011 +01100111 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/VexRiscv/murax/Murax.v_toplevel_system_ram_ram_symbol1.bin b/VexRiscv/murax/Murax.v_toplevel_system_ram_ram_symbol1.bin new file mode 100644 index 0000000..3c6cc0e --- /dev/null +++ b/VexRiscv/murax/Murax.v_toplevel_system_ram_ram_symbol1.bin @@ -0,0 +1,1024 @@ +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00101110 +00101100 +00101010 +00101000 +00100110 +00100100 +00100010 +00100000 +00101110 +00101100 +00101010 +00101000 +00100110 +00100100 +00100010 +00100000 +00000001 +00000000 +00100000 +00100010 +00100011 +00100011 +00100101 +00100101 +00100110 +00100110 +00100111 +00100111 +00101000 +00101000 +00101110 +00101110 +00101111 +00101111 +00000001 +00000000 +00010001 +10000001 +10000001 +00000101 +00000101 +00000101 +10000101 +00001000 +00100000 +00000101 +11110000 +00000101 +00000101 +00000001 +00000101 +10000101 +00001110 +00100110 +00000101 +00100000 +10000000 +00100101 +11110000 +00000001 +00010101 +00000101 +00010000 +00100101 +00000101 +00010000 +00000000 +00000000 +00000001 +00101110 +00000100 +00100110 +00100111 +10100000 +00100111 +10100100 +00000000 +00100100 +00000001 +10000000 +00000001 +00101110 +00000100 +00100110 +00000000 +00100100 +00000001 +10000000 +00000001 +00101110 +00000100 +00100110 +00100111 +10100010 +00100111 +00000111 +10100000 +00000000 +00100100 +00000001 +10000000 +00000001 +00101110 +00000100 +00100110 +00100111 +10100111 +11010111 +11110111 +10000101 +00100100 +00000001 +10000000 +00000001 +00101110 +00000100 +00100110 +00100111 +10100111 +11010111 +10000101 +00100100 +00000001 +10000000 +00000001 +00101110 +00101100 +00000100 +00100110 +00100100 +00000000 +00100101 +11110000 +00000111 +10001010 +00100111 +00100111 +10100000 +00000000 +00100000 +00100100 +00000001 +10000000 +00000001 +00101110 +00000100 +00100110 +00100100 +00100111 +10100111 +00100111 +10100100 +00100111 +10100111 +10000111 +00100111 +10100111 +10010111 +01100111 +00100111 +10100111 +10010111 +01100111 +00100111 +10100110 +00000000 +00100100 +00000001 +10000000 +00000001 +00100110 +00100100 +00000100 +00000111 +00100010 +00000111 +00100000 +00000111 +00101110 +00100110 +00000111 +10000101 +11110000 +00000101 +11110000 +00000111 +10000101 +11110000 +00000111 +00110111 +00000111 +10100000 +00000111 +10000111 +00000111 +10100010 +00000111 +10000111 +00000111 +00000111 +10100000 +00000111 +10000111 +00000111 +10100000 +00000111 +10000111 +00000111 +10100010 +00000111 +00000111 +10100100 +00000111 +10100010 +00000111 +00000111 +10100010 +00000111 +00000111 +10100000 +00100111 +00100111 +00000111 +00100110 +00100111 +00100111 +00000111 +00100111 +00000111 +00100110 +00100100 +00000000 +00100111 +10000111 +00100100 +00100111 +11000111 +10000111 +11110100 +00000111 +10100111 +11110110 +00000111 +10100111 +10000111 +11110111 +00000111 +11100111 +10100010 +11110000 +00000001 +00100110 +00000100 +00000111 +10000111 +10100111 +11110111 +10000000 +00000111 +10100111 +00000111 +01000111 +10100010 +00000111 +10000111 +00000111 +10100000 +00000000 +00000111 +10100111 +00000111 +01110111 +10100000 +00000111 +10100111 +11110111 +10010000 +00000000 +00100100 +00000001 +10000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/VexRiscv/murax/Murax.v_toplevel_system_ram_ram_symbol2.bin b/VexRiscv/murax/Murax.v_toplevel_system_ram_ram_symbol2.bin new file mode 100644 index 0000000..db76177 --- /dev/null +++ b/VexRiscv/murax/Murax.v_toplevel_system_ram_ram_symbol2.bin @@ -0,0 +1,1024 @@ +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00010001 +01010001 +01100001 +01110001 +10100001 +10110001 +11000001 +11010001 +11100001 +11110001 +00000001 +00010001 +11000001 +11010001 +11100001 +11110001 +00000001 +01000000 +11000001 +10000001 +01000001 +00000001 +11000001 +10000001 +01000001 +00000001 +11000001 +10000001 +01000001 +00000001 +11000001 +10000001 +01000001 +00000001 +00000001 +00100000 +00000000 +10000001 +10000001 +00000000 +11000101 +00000000 +01000101 +10110101 +00000101 +01000101 +01011111 +00000000 +10000101 +11000001 +00000000 +11000101 +10110101 +00000101 +01000101 +10100001 +00000110 +00000001 +00011111 +01000001 +00000000 +00000101 +01000101 +00000000 +10000101 +00000101 +11000000 +00000000 +00000001 +10000001 +00000001 +10100100 +11000100 +00000111 +11000100 +00000111 +00000000 +11000001 +00000001 +00000000 +00000001 +10000001 +00000001 +10100100 +00000000 +11000001 +00000001 +00000000 +00000001 +10000001 +00000001 +10100100 +11000100 +00000111 +11000100 +11110000 +11100111 +00000000 +11000001 +00000001 +00000000 +00000001 +10000001 +00000001 +10100100 +11000100 +01000111 +00000111 +11110111 +00000111 +11000001 +00000001 +00000000 +00000001 +10000001 +00000001 +10100100 +11000100 +01000111 +10000111 +00000111 +11000001 +00000001 +00000000 +00000001 +00010001 +10000001 +00000001 +10100100 +10110100 +00000000 +11000100 +01011111 +00000101 +00000111 +11000100 +10000100 +11100111 +00000000 +11000001 +10000001 +00000001 +00000000 +00000001 +10000001 +00000001 +10100100 +10110100 +10000100 +11000111 +11000100 +11100111 +10000100 +00000111 +11110111 +10000100 +01000111 +10000111 +11110111 +10000100 +10000111 +00000111 +11110111 +11000100 +11100111 +00000000 +11000001 +00000001 +00000000 +00000001 +00010001 +10000001 +00000001 +00010000 +11110100 +00100000 +11110100 +00110000 +11110100 +00000100 +00000010 +00000111 +10011111 +00000010 +00011111 +00000010 +00000111 +01011111 +00000010 +00000000 +11110111 +11100111 +00000010 +00000111 +01110000 +11100111 +00000010 +00000111 +00000001 +00100111 +11100111 +00000010 +00000111 +11110000 +11100111 +00000010 +00000111 +00010000 +11100111 +00000000 +11110000 +11100111 +00000000 +00000111 +00000001 +00100000 +11100111 +00000001 +00010000 +11100111 +01000100 +11000100 +11110111 +11110100 +00000100 +11000100 +11110111 +11000100 +11110111 +11110100 +00000100 +00000000 +10000100 +00010111 +11110100 +10000100 +00000000 +11110111 +11100111 +00000000 +01000111 +00000111 +00000000 +01000111 +00010111 +11110111 +00000000 +11100110 +11100111 +11011111 +00000001 +10000001 +00000001 +00000010 +00000111 +00000111 +00010111 +00000111 +00000000 +01000111 +00000000 +00000111 +11100111 +00000010 +00000111 +00010000 +11100111 +10000000 +00000001 +00000111 +00000001 +11110111 +11100111 +00000001 +01000111 +00000111 +00000111 +00000000 +11000001 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/VexRiscv/murax/Murax.v_toplevel_system_ram_ram_symbol3.bin b/VexRiscv/murax/Murax.v_toplevel_system_ram_ram_symbol3.bin new file mode 100644 index 0000000..bd6c120 --- /dev/null +++ b/VexRiscv/murax/Murax.v_toplevel_system_ram_ram_symbol3.bin @@ -0,0 +1,1024 @@ +00001011 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111110 +11111110 +11111110 +11111110 +11111110 +11111110 +11111110 +11111110 +11111100 +11111100 +11111101 +11111101 +11111101 +11111101 +11111101 +11111101 +11111100 +00111010 +00000011 +00000011 +00000011 +00000011 +00000010 +00000010 +00000010 +00000010 +00000001 +00000001 +00000001 +00000001 +00000000 +00000000 +00000000 +00000000 +00000100 +00110000 +00000000 +10111101 +10100000 +00000000 +00111100 +00000000 +00111100 +00000000 +00000000 +00000000 +11111111 +00000000 +00111010 +11111111 +00000000 +00111001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111110 +00000000 +00000000 +10001000 +00110000 +00000000 +10000000 +00110000 +00011001 +00000000 +11111110 +00000000 +00000010 +11111110 +11111110 +00000000 +11111110 +00000000 +00000000 +00000001 +00000010 +00000000 +11111110 +00000000 +00000010 +11111110 +00000000 +00000001 +00000010 +00000000 +11111110 +00000000 +00000010 +11111110 +11111110 +00000000 +11111110 +11111111 +00000000 +00000000 +00000001 +00000010 +00000000 +11111110 +00000000 +00000010 +11111110 +11111110 +00000000 +00000001 +00001111 +00000000 +00000001 +00000010 +00000000 +11111110 +00000000 +00000010 +11111110 +11111110 +00000000 +00000001 +00000000 +00000001 +00000010 +00000000 +11111110 +00000000 +00000000 +00000010 +11111110 +11111110 +00000000 +11111110 +11111000 +00000000 +11111110 +11111110 +11111110 +00000000 +00000000 +00000001 +00000001 +00000010 +00000000 +11111110 +00000000 +00000010 +11111110 +11111110 +11111110 +00000000 +11111110 +00000000 +11111110 +00000000 +11111111 +11111110 +00000000 +00000000 +00000000 +11111110 +00000000 +00000001 +00000000 +11111110 +00000000 +00000000 +00000001 +00000010 +00000000 +11111101 +00000010 +00000010 +00000011 +00000000 +11111110 +00000000 +11111110 +00000000 +11111100 +11111110 +11110000 +00000001 +11101000 +11110000 +11100110 +11110000 +00000100 +11100010 +11110000 +00000000 +11101101 +00000000 +11110000 +00000100 +00111110 +00000000 +11110000 +00000100 +00000000 +00000000 +00000000 +11110000 +00000001 +00000000 +00000000 +11110000 +00000001 +00000000 +00000000 +11110000 +00001111 +00000000 +11110000 +00000000 +11110000 +00000000 +00000000 +11110000 +00000100 +00000000 +11111110 +11111110 +00000000 +11111110 +11111110 +11111101 +00000000 +11111110 +00000000 +11111110 +11111110 +00000001 +11111110 +00000000 +11111110 +11111110 +00000000 +00110100 +11111110 +11110000 +00000000 +11111100 +11110000 +00000000 +00000000 +00000011 +11110000 +00000000 +00000000 +11111000 +11111111 +00000000 +00000001 +11110000 +00000001 +00000000 +00000000 +00000100 +11110000 +00000000 +11110000 +00001000 +00000000 +11110000 +00000001 +00000000 +00000000 +00000001 +11110000 +00000000 +11110000 +00001111 +00000000 +11110000 +00000000 +00100000 +11111110 +00000000 +00000000 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/VexRiscv/murax/main.cpp b/VexRiscv/murax/main.cpp new file mode 100644 index 0000000..735875f --- /dev/null +++ b/VexRiscv/murax/main.cpp @@ -0,0 +1,64 @@ +#include "VMurax.h" +#include "VMurax_Murax.h" +#include "verilated.h" +#include "verilated_vcd_c.h" + +#include "../common/framework.h" +#include "../common/jtag.h" +#include "../common/uart.h" + +class MuraxWorkspace : public Workspace{ +public: + MuraxWorkspace() : Workspace("Murax"){ + ClockDomain *mainClk = new ClockDomain(&top->io_mainClk,NULL,83333,300000); + AsyncReset *asyncReset = new AsyncReset(&top->io_asyncReset,50000); + UartRx *uartRx = new UartRx(&top->io_uart_txd,1.0e12/115200); + UartTx *uartTx = new UartTx(&top->io_uart_rxd,1.0e12/115200); + + timeProcesses.push_back(mainClk); + timeProcesses.push_back(asyncReset); + timeProcesses.push_back(uartRx); + timeProcesses.push_back(uartTx); + + Jtag *jtag = new Jtag(&top->io_jtag_tms,&top->io_jtag_tdi,&top->io_jtag_tdo,&top->io_jtag_tck,83333*4); + timeProcesses.push_back(jtag); + + #ifdef TRACE + //speedFactor = 10e-3; + //cout << "Simulation caped to " << speedFactor << " of real time"<< endl; + #endif + } +}; + + +struct timespec timer_start(){ + struct timespec start_time; + clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &start_time); + return start_time; +} + +long timer_end(struct timespec start_time){ + struct timespec end_time; + clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &end_time); + uint64_t diffInNanos = end_time.tv_sec*1e9 + end_time.tv_nsec - start_time.tv_sec*1e9 - start_time.tv_nsec; + return diffInNanos; +} + + + +int main(int argc, char **argv, char **env) { + + Verilated::randReset(2); + Verilated::commandArgs(argc, argv); + + printf("BOOT\n"); + timespec startedAt = timer_start(); + + MuraxWorkspace().run(1e9); + + uint64_t duration = timer_end(startedAt); + cout << endl << "****************************************************************" << endl; + + + exit(0); +} diff --git a/VexRiscv/murax/makefile b/VexRiscv/murax/makefile new file mode 100644 index 0000000..004d126 --- /dev/null +++ b/VexRiscv/murax/makefile @@ -0,0 +1,39 @@ +DEBUG?=no +TRACE?=no +PRINT_PERF?=no +TRACE_START=0 +ADDCFLAGS += -CFLAGS -pthread -LDFLAGS -pthread + + +ifeq ($(TRACE),yes) + VERILATOR_ARGS += --trace + ADDCFLAGS += -CFLAGS -DTRACE --trace-fst +endif +ifeq ($(DEBUG),yes) + ADDCFLAGS += -CFLAGS "-g3 -O0" +endif +ifneq ($(DEBUG),yes) + ADDCFLAGS += -CFLAGS "-O3" +endif +ifeq ($(PRINT_PERF),yes) + ADDCFLAGS += -CFLAGS -DPRINT_PERF +endif + +ADDCFLAGS += -CFLAGS -DTRACE_START=${TRACE_START} + + + +all: clean compile + +run: compile + ./obj_dir/VMurax + +verilate: ./Murax.v + verilator -cc ./Murax.v ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH -Wno-UNOPTFLAT --x-assign unique --exe main.cpp + +compile: verilate + make -j -C obj_dir/ -f VMurax.mk VMurax + +clean: + rm -rf obj_dir + diff --git a/VexRiscv/murax/murax.gtkw b/VexRiscv/murax/murax.gtkw new file mode 100644 index 0000000..5fa869b --- /dev/null +++ b/VexRiscv/murax/murax.gtkw @@ -0,0 +1,51 @@ +[*] +[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI +[*] Mon Jul 31 17:03:11 2017 +[*] +[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/murax/Murax.vcd" +[dumpfile_mtime] "Mon Jul 31 17:03:01 2017" +[dumpfile_size] 1539276802 +[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/murax/murax.gtkw" +[timestart] 300964770000 +[size] 1776 953 +[pos] -1 -353 +*-23.000000 300989600000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] TOP. +[treeopen] TOP.Murax. +[treeopen] TOP.Murax.system_uartCtrl. +[treeopen] TOP.Murax.system_uartCtrl.uartCtrl_1. +[sst_width] 454 +[signals_width] 327 +[sst_expanded] 1 +[sst_vpaned_height] 279 +@28 +TOP.Murax.system_uartCtrl.io_uart_rxd +TOP.Murax.system_uartCtrl.io_uart_txd +TOP.Murax.system_uartCtrl.io_interrupt +TOP.Murax.system_cpu.CsrPlugin_mstatus_MIE +@22 +TOP.Murax.system_uartCtrl.streamFifo_2.io_push_payload[7:0] +@28 +TOP.Murax.system_uartCtrl.streamFifo_2.io_push_valid +TOP.Murax.system_uartCtrl.streamFifo_2.io_pop_valid +TOP.Murax.system_uartCtrl.streamFifo_2.io_pop_ready +@22 +TOP.Murax.system_uartCtrl.streamFifo_2.io_pop_payload[7:0] +TOP.Murax.system_uartCtrl.uartCtrl_1.rx.io_read_payload[7:0] +@28 +TOP.Murax.system_uartCtrl.uartCtrl_1.rx.io_read_valid +TOP.Murax.system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2:0] +@22 +TOP.Murax.system_uartCtrl.uartCtrl_1.rx.stateMachine_shifter[7:0] +@28 +TOP.Murax.system_uartCtrl.uartCtrl_1.rx.bitTimer_tick +TOP.Murax.system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[2:0] +@29 +TOP.Murax.system_uartCtrl.uartCtrl_1.rx.io_rxd +@28 +TOP.Murax.system_uartCtrl.uartCtrl_1.rx.sampler_value +TOP.Murax.system_uartCtrl.uartCtrl_1.rx.sampler_tick +TOP.Murax.system_uartCtrl.uartCtrl_1.rx.sampler_samples_1 +TOP.Murax.system_uartCtrl.uartCtrl_1.rx.sampler_samples_2 +[pattern_trace] 1 +[pattern_trace] 0