From e1aec7d193aa31f61269cd23de737b5750c156f6 Mon Sep 17 00:00:00 2001 From: Daniel Mlynek Date: Thu, 27 Feb 2020 09:40:53 +0100 Subject: [PATCH 1/2] Riviera simulator added to Readme --- README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index d4c83d2..b791c97 100644 --- a/README.md +++ b/README.md @@ -142,9 +142,9 @@ make -f $RV_ROOT/tools/Makefile [] [debug=1] [snapshot=] [t where: - - can be 'verilator' (by default) 'irun' - Cadence xrun, 'vcs' - Synopsys VCS, 'vlog' Mentor Questa - if not provided, 'make' cleans work directory, builds verilator executable and runs a test. -debug=1 - allows VCD generation for verilator and VCS and SHM waves for irun option. + - can be 'verilator' (by default) 'irun' - Cadence xrun, 'vcs' - Synopsys VCS, 'vlog' Mentor Questa, + 'riviera' - Aldec Riviera-PRO if not provided, 'make' cleans work directory, builds verilator executable and runs a test. +debug=1 - allows VCD generation for verilator, VCS and Riviera-PRO and SHM waves for irun option. - predefined CPU configurations 'default' ( by default), 'default_ahb', 'default_pd', 'high_perf' TEST - allows to run a C (.c) or assembly (.s) test, hello_world is run by default TEST_DIR - alternative to test source directory testbench/asm From 040d2807c91ef70ee20f0337c9491888bc6edc21 Mon Sep 17 00:00:00 2001 From: Daniel Mlynek Date: Thu, 27 Feb 2020 09:59:42 +0100 Subject: [PATCH 2/2] Fix Riviera -l switch --- tools/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/Makefile b/tools/Makefile index cc3300b..fe54d55 100755 --- a/tools/Makefile +++ b/tools/Makefile @@ -113,7 +113,7 @@ irun-build: ${TBFILES} ${BUILD_DIR}/defines.h riviera-build: ${TBFILES} ${BUILD_DIR}/defines.h vlib work vlog -work work \ - -l riviera_compile.log -err VCP2694 W1 \ + -err VCP2694 W1 \ +incdir+${RV_ROOT}/design/lib \ +incdir+${RV_ROOT}/design/include \ +incdir+${BUILD_DIR} +libext+.v $(defines) \ @@ -173,4 +173,4 @@ help: @echo Make sure the environment variable RV_ROOT is set. @echo Possible targets: verilator vcs irun vlog riviera help clean all verilator-build irun-build vcs-build riviera-build program.hex -.PHONY: help clean verilator vcs irun vlog riviera \ No newline at end of file +.PHONY: help clean verilator vcs irun vlog riviera