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Delete unuse file and configs.

This commit is contained in:
colin 2022-05-23 13:53:58 +00:00
parent a9bfa80cc1
commit 2f8715aeb6
31 changed files with 25 additions and 3655 deletions
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44
Flow/configs/README.md
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@ -1,44 +0,0 @@
# SweRV RISC-V EL2 core from Western Digital
## Configuration
### Contents
Name | Description
---------------------- | ------------------------------
swerv.config | Configuration script for SweRV-EL2
swerv_config_gen.py | Python wrapper to run swerv.config, used by SweRVolf
This script will generate a consistent set of `defines/#defines/parameters` needed for the design and testbench.
A perl hash (*perl_configs.pl*) and a JSON format for SweRV-iss are also generated.
This set of include files :
./snapshots/<target>
├── common_defines.vh # `defines for testbench
├── defines.h # #defines for C/assembly headers
├── el2_param.vh # Actual Design parameters
├── el2_pdef.vh # Parameter structure definition
├── pd_defines.vh # `defines for physical design
├── perl_configs.pl # Perl %configs hash for scripting
├── pic_map_auto.h # PIC memory map based on configure size
├── whisper.json # JSON file for swerv-iss
└── link.ld # Default linker file for tests
While the defines may be modified by hand, it is recommended that this script be used to generate a consistent set.
### Targets
There are 4 predefined target configurations: `default`, `default_ahb`, `typical_pd` and `high_perf` that can be selected via the `-target=name` option to swerv.config.
Target | Description
---------------------- | ------------------------------
default | Default configuration. AXI4 bus interface.
default_ahb | Default configuration, AHB-Lite bus interface
typical_pd | No ICCM, AXI4 bus interface
high_perf | Large BTB/BHT, AXI4 interface
`swerv.config` may be edited to add additional target configurations, or new configurations may be created via the command line `-set` or `-unset` options.
**Run `$RV_ROOT/configs/swerv.config -h` for options and settable parameters.**

2609
Flow/configs/swerv.config
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File diff suppressed because it is too large Load Diff

41
Flow/configs/swerv_config_gen.py
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@ -1,41 +0,0 @@
#!/usr/bin/env python3
from fusesoc.capi2.generator import Generator
import os
import subprocess
import sys
class SwervConfigGenerator(Generator):
def run(self):
script_root = os.path.abspath(os.path.join(os.path.dirname(sys.argv[0]), '..'))
files = [
{"common_defines.vh" : {
"copyto" : "config/common_defines.vh",
"file_type" : "systemVerilogSource"}},
{"el2_pdef.vh" : {
"copyto" : "config/el2_pdef.vh",
"file_type" : "systemVerilogSource"}},
{"el2_param.vh" : {
"is_include_file" : True,
"file_type" : "systemVerilogSource"}},
{"pic_map_auto.h" : {
"is_include_file" : True,
"file_type" : "systemVerilogSource"}}]
env = os.environ.copy()
env['RV_ROOT'] = script_root
env['BUILD_PATH'] = os.getcwd()
args = ['configs/swerv.config'] + self.config.get('args', [])
rc = subprocess.call(args, cwd=script_root, env=env, stdout=subprocess.DEVNULL)
if rc:
exit(1)
filenames = []
for f in files:
for k in f:
filenames.append(k)
self.add_files(files)
g = SwervConfigGenerator()
g.run()
g.write()

1
Flow/demo/Makefile
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@ -36,7 +36,6 @@ swerv_define :
##################### Verilog Builds #####################################
verilator-build: swerv_define
echo '`undef RV_ASSERT_ON' >> ${BUILD_DIR}/common_defines.vh
verilator --cc -CFLAGS ${CFLAGS} \
$(BUILD_DIR)/common_defines.vh \
$(BUILD_DIR)/el2_pdef.vh \

8
Flow/design/dbg/el2_dbg.sv
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@ -747,12 +747,4 @@ import el2_pkg::*;
({64{sb_axi_size == 3'h2}} & ((sb_axi_rdata[63:0] >> 32*sb_axi_addr[2]) & 64'hffff_ffff)) |
({64{sb_axi_size == 3'h3}} & sb_axi_rdata[63:0]);
`ifdef RV_ASSERT_ON
// assertion.
// when the resume_ack is asserted then the dec_tlu_dbg_halted should be 0
dm_check_resume_and_halted: assert property (@(posedge clk) disable iff(~rst_l) (~dec_tlu_resume_ack | ~dec_tlu_dbg_halted));
assert_b2b_haltreq: assert property (@(posedge clk) disable iff (~(rst_l)) (##1 dbg_halt_req |=> ~dbg_halt_req)); // One cycle delay to fix weird issue around reset
assert_halt_resume_onehot: assert #0 ($onehot0({dbg_halt_req, dbg_resume_req}));
`endif
endmodule

15
Flow/design/dec/el2_dec_decode_ctl.sv
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@ -629,16 +629,6 @@ end // else: !if(pt.BTB_ENABLE==1)
assign nonblock_load_rd[4:0] = (x_d.i0load) ? x_d.i0rd[4:0] : 5'b0; // rd data
// checks
`ifdef RV_ASSERT_ON
assert_dec_data_valid_data_error_onehot: assert #0 ($onehot0({lsu_nonblock_load_data_valid,lsu_nonblock_load_data_error}));
assert_dec_cam_inv_reset_onehot: assert #0 ($onehot0(cam_inv_reset_val[NBLOAD_SIZE_MSB:0]));
assert_dec_cam_data_reset_onehot: assert #0 ($onehot0(cam_data_reset_val[NBLOAD_SIZE_MSB:0]));
`endif
// case of multiple loads to same dest ie. x1 ... you have to invalidate the older one
for (genvar i=0; i<NBLOAD_SIZE; i++) begin : cam_array
@ -689,11 +679,6 @@ end : cam_array
assign load_data_tag[NBLOAD_TAG_MSB:0] = lsu_nonblock_load_data_tag[NBLOAD_TAG_MSB:0];
`ifdef RV_ASSERT_ON
assert_dec_cam_nonblock_load_write_onehot: assert #0 ($onehot0(nonblock_load_write[NBLOAD_SIZE_MSB:0]));
`endif
assign nonblock_load_cancel = ((r_d_in.i0rd[4:0] == dec_nonblock_load_waddr[4:0]) & i0_wen_r); // cancel if any younger inst (including another nonblock) committing this cycle

13
Flow/design/dec/el2_dec_gpr_ctl.sv
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@ -79,17 +79,4 @@ import el2_pkg::*;
end
end // always_comb begin
`ifdef RV_ASSERT_ON
logic write_collision_unused;
assign write_collision_unused = ( (w0v[31:1] == w1v[31:1]) & wen0 & wen1 ) |
( (w0v[31:1] == w2v[31:1]) & wen0 & wen2 ) |
( (w1v[31:1] == w2v[31:1]) & wen1 & wen2 );
// asserting that no 2 ports will write to the same gpr simultaneously
assert_multiple_wen_to_same_gpr: assert #0 (~( write_collision_unused ) );
`endif
endmodule

4
Flow/design/dec/el2_dec_tlu_ctl.sv
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@ -835,10 +835,6 @@ localparam MTDATA1_LD = 0;
assign debug_mode_status = internal_dbg_halt_mode_f;
assign o_debug_mode_status = debug_mode_status;
`ifdef RV_ASSERT_ON
assert_commit_while_halted: assert #0 (~(tlu_i0_commit_cmt & o_cpu_halt_status)) else $display("ERROR: Commiting while cpu_halt_status asserted!");
assert_flush_while_fastint: assert #0 (~((take_ext_int_start_d1 | take_ext_int_start_d2) & dec_tlu_flush_lower_r)) else $display("ERROR: TLU Flushing inside fast interrupt procedure!");
`endif
// high priority interrupts can wakeup from external halt, so can unmasked timer interrupts
assign i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | ((nmi_int_detected | timer_int_ready | soft_int_ready | int_timer0_int_hold_f | int_timer1_int_hold_f | (mhwakeup & mhwakeup_ready)) & o_cpu_halt_status & ~i_cpu_halt_req_d1);

146
Flow/design/el2_dma_ctrl.sv
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@ -415,11 +415,7 @@ module el2_dma_ctrl #(
rvoclkhdr dma_buffer_c1cgc ( .en(dma_buffer_c1_clken), .l1clk(dma_buffer_c1_clk), .* );
rvoclkhdr dma_free_cgc (.en(dma_free_clken), .l1clk(dma_free_clk), .*);
`ifdef RV_FPGA_OPTIMIZE
assign dma_bus_clk = 1'b0;
`else
rvclkhdr dma_bus_cgc (.en(dma_bus_clk_en), .l1clk(dma_bus_clk), .*);
`endif
// Write channel buffer
assign wrbuf_en = dma_axi_awvalid & dma_axi_awready;
@ -492,146 +488,4 @@ module el2_dma_ctrl #(
assign dma_active = wrbuf_vld | rdbuf_vld | (|fifo_valid[DEPTH-1:0]);
`ifdef RV_ASSERT_ON
for (genvar i=0; i<DEPTH; i++) begin
assert_fifo_done_and_novalid: assert #0 (~fifo_done[i] | fifo_valid[i]);
end
// Assertion to check awvalid stays stable during entire bus clock
property dma_axi_awvalid_stable;
@(posedge clk) disable iff(~rst_l) (dma_axi_awvalid != $past(dma_axi_awvalid)) |-> $past(dma_bus_clk_en);
endproperty
assert_dma_axi_awvalid_stable: assert property (dma_axi_awvalid_stable) else
$display("DMA AXI awvalid changed in middle of bus clock");
// Assertion to check awid stays stable during entire bus clock
property dma_axi_awid_stable;
@(posedge clk) disable iff(~rst_l) (dma_axi_awvalid & (dma_axi_awid[pt.DMA_BUS_TAG-1:0] != $past(dma_axi_awid[pt.DMA_BUS_TAG-1:0]))) |-> $past(dma_bus_clk_en);
endproperty
assert_dma_axi_awid_stable: assert property (dma_axi_awid_stable) else
$display("DMA AXI awid changed in middle of bus clock");
// Assertion to check awaddr stays stable during entire bus clock
property dma_axi_awaddr_stable;
@(posedge clk) disable iff(~rst_l) (dma_axi_awvalid & (dma_axi_awaddr[31:0] != $past(dma_axi_awaddr[31:0]))) |-> $past(dma_bus_clk_en);
endproperty
assert_dma_axi_awaddr_stable: assert property (dma_axi_awaddr_stable) else
$display("DMA AXI awaddr changed in middle of bus clock");
// Assertion to check awsize stays stable during entire bus clock
property dma_axi_awsize_stable;
@(posedge clk) disable iff(~rst_l) (dma_axi_awvalid & (dma_axi_awsize[2:0] != $past(dma_axi_awsize[2:0]))) |-> $past(dma_bus_clk_en);
endproperty
assert_dma_axi_awsize_stable: assert property (dma_axi_awsize_stable) else
$display("DMA AXI awsize changed in middle of bus clock");
// Assertion to check wstrb stays stable during entire bus clock
property dma_axi_wstrb_stable;
@(posedge clk) disable iff(~rst_l) (dma_axi_wvalid & (dma_axi_wstrb[7:0] != $past(dma_axi_wstrb[7:0]))) |-> $past(dma_bus_clk_en);
endproperty
assert_dma_axi_wstrb_stable: assert property (dma_axi_wstrb_stable) else
$display("DMA AXI wstrb changed in middle of bus clock");
// Assertion to check wdata stays stable during entire bus clock
property dma_axi_wdata_stable;
@(posedge clk) disable iff(~rst_l) (dma_axi_wvalid & (dma_axi_wdata[63:0] != $past(dma_axi_wdata[63:0]))) |-> $past(dma_bus_clk_en);
endproperty
assert_dma_axi_wdata_stable: assert property (dma_axi_wdata_stable) else
$display("DMA AXI wdata changed in middle of bus clock");
// Assertion to check awvalid stays stable during entire bus clock
property dma_axi_arvalid_stable;
@(posedge clk) disable iff(~rst_l) (dma_axi_arvalid != $past(dma_axi_arvalid)) |-> $past(dma_bus_clk_en);
endproperty
assert_dma_axi_arvalid_stable: assert property (dma_axi_arvalid_stable) else
$display("DMA AXI awvalid changed in middle of bus clock");
// Assertion to check awid stays stable during entire bus clock
property dma_axi_arid_stable;
@(posedge clk) disable iff(~rst_l) (dma_axi_arvalid & (dma_axi_arid[pt.DMA_BUS_TAG-1:0] != $past(dma_axi_arid[pt.DMA_BUS_TAG-1:0]))) |-> $past(dma_bus_clk_en);
endproperty
assert_dma_axi_arid_stable: assert property (dma_axi_arid_stable) else
$display("DMA AXI awid changed in middle of bus clock");
// Assertion to check awaddr stays stable during entire bus clock
property dma_axi_araddr_stable;
@(posedge clk) disable iff(~rst_l) (dma_axi_arvalid & (dma_axi_araddr[31:0] != $past(dma_axi_araddr[31:0]))) |-> $past(dma_bus_clk_en);
endproperty
assert_dma_axi_araddr_stable: assert property (dma_axi_araddr_stable) else
$display("DMA AXI awaddr changed in middle of bus clock");
// Assertion to check awsize stays stable during entire bus clock
property dma_axi_arsize_stable;
@(posedge clk) disable iff(~rst_l) (dma_axi_awvalid & (dma_axi_arsize[2:0] != $past(dma_axi_arsize[2:0]))) |-> $past(dma_bus_clk_en);
endproperty
assert_dma_axi_arsize_stable: assert property (dma_axi_arsize_stable) else
$display("DMA AXI awsize changed in middle of bus clock");
// Assertion to check bvalid stays stable during entire bus clock
property dma_axi_bvalid_stable;
@(posedge clk) disable iff(~rst_l) (dma_axi_bvalid != $past(dma_axi_bvalid)) |-> $past(dma_bus_clk_en);
endproperty
assert_dma_axi_bvalid_stable: assert property (dma_axi_bvalid_stable) else
$display("DMA AXI bvalid changed in middle of bus clock");
// Assertion to check bvalid stays stable if bready is low
property dma_axi_bvalid_stable_till_bready;
@(posedge clk) disable iff(~rst_l) (~dma_axi_bvalid && $past(dma_axi_bvalid)) |-> $past(dma_axi_bready);
endproperty
assert_dma_axi_bvalid_stable_till_bready: assert property (dma_axi_bvalid_stable_till_bready) else
$display("DMA AXI bvalid deasserted without bready");
// Assertion to check bresp stays stable during entire bus clock
property dma_axi_bresp_stable;
@(posedge clk) disable iff(~rst_l) (dma_axi_bvalid & (dma_axi_bresp[1:0] != $past(dma_axi_bresp[1:0]))) |-> $past(dma_bus_clk_en);
endproperty
assert_dma_axi_bresp_stable: assert property (dma_axi_bresp_stable) else
$display("DMA AXI bresp changed in middle of bus clock");
// Assertion to check bid stays stable during entire bus clock
property dma_axi_bid_stable;
@(posedge clk) disable iff(~rst_l) (dma_axi_bvalid & (dma_axi_bid[pt.DMA_BUS_TAG-1:0] != $past(dma_axi_bid[pt.DMA_BUS_TAG-1:0]))) |-> $past(dma_bus_clk_en);
endproperty
assert_dma_axi_bid_stable: assert property (dma_axi_bid_stable) else
$display("DMA AXI bid changed in middle of bus clock");
// Assertion to check rvalid stays stable during entire bus clock
property dma_axi_rvalid_stable;
@(posedge clk) disable iff(~rst_l) (dma_axi_rvalid != $past(dma_axi_rvalid)) |-> $past(dma_bus_clk_en);
endproperty
assert_dma_axi_rvalid_stable: assert property (dma_axi_rvalid_stable) else
$display("DMA AXI bvalid changed in middle of bus clock");
// Assertion to check rvalid stays stable if bready is low
property dma_axi_rvalid_stable_till_ready;
@(posedge clk) disable iff(~rst_l) (~dma_axi_rvalid && $past(dma_axi_rvalid)) |-> $past(dma_axi_rready);
endproperty
assert_dma_axi_rvalid_stable_till_ready: assert property (dma_axi_rvalid_stable_till_ready) else
$display("DMA AXI bvalid changed in middle of bus clock");
// Assertion to check rresp stays stable during entire bus clock
property dma_axi_rresp_stable;
@(posedge clk) disable iff(~rst_l) (dma_axi_rvalid & (dma_axi_rresp[1:0] != $past(dma_axi_rresp[1:0]))) |-> $past(dma_bus_clk_en);
endproperty
assert_dma_axi_rresp_stable: assert property (dma_axi_rresp_stable) else
$display("DMA AXI bresp changed in middle of bus clock");
// Assertion to check rid stays stable during entire bus clock
property dma_axi_rid_stable;
@(posedge clk) disable iff(~rst_l) (dma_axi_rvalid & (dma_axi_rid[pt.DMA_BUS_TAG-1:0] != $past(dma_axi_rid[pt.DMA_BUS_TAG-1:0]))) |-> $past(dma_bus_clk_en);
endproperty
assert_dma_axi_rid_stable: assert property (dma_axi_rid_stable) else
$display("DMA AXI bid changed in middle of bus clock");
// Assertion to check rdata stays stable during entire bus clock
property dma_axi_rdata_stable;
@(posedge clk) disable iff(~rst_l) (dma_axi_rvalid & (dma_axi_rdata[63:0] != $past(dma_axi_rdata[63:0]))) |-> $past(dma_bus_clk_en);
endproperty
assert_dma_axi_rdata_stable: assert property (dma_axi_rdata_stable) else
$display("DMA AXI bid changed in middle of bus clock");
`endif
endmodule // el2_dma_ctrl

4
Flow/design/el2_pic_ctrl.sv
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@ -226,11 +226,7 @@ wire grp_clk, grp_clken;
assign grp_clken = |intenable_clk_enable[(p==INT_ENABLE_GRPS?pt.PIC_TOTAL_INT_PLUS1-1:p*4+3) : p*4] | io_clk_override;
`ifndef RV_FPGA_OPTIMIZE
rvclkhdr intenable_c1_cgc( .en(grp_clken), .l1clk(grp_clk), .* );
`else
assign gw_clk[p] = 1'b0 ;
`endif
for(genvar i= (p==0 ? 1: 0); i< (p==INT_ENABLE_GRPS ? pt.PIC_TOTAL_INT_PLUS1-p*4 :4); i++) begin : GW
el2_configurable_gw gw_inst(

22
Flow/design/el2_swerv.sv
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@ -850,10 +850,6 @@ import el2_pkg::*;
.*
);
`ifdef RV_ASSERT_ON
assert_fetch_indbghalt: assert #0 (~(ifu.ifc_fetch_req_f & dec.tlu.dbg_tlu_halted_f & ~dec.tlu.dcsr_single_step_running)) else $display("ERROR: Fetching in dBG halt!");
`endif
// ----------------- DEBUG END -----------------------------
assign core_rst_l = rst_l & (dbg_core_rst_l | scan_mode);
@ -1264,25 +1260,7 @@ import el2_pkg::*;
if (pt.BUILD_AHB_LITE == 1) begin
`ifdef RV_ASSERT_ON
property ahb_trxn_aligned;
@(posedge clk) disable iff(~rst_l) (lsu_htrans[1:0] != 2'b0) |-> ((lsu_hsize[2:0] == 3'h0) |
((lsu_hsize[2:0] == 3'h1) & (lsu_haddr[0] == 1'b0)) |
((lsu_hsize[2:0] == 3'h2) & (lsu_haddr[1:0] == 2'b0)) |
((lsu_hsize[2:0] == 3'h3) & (lsu_haddr[2:0] == 3'b0)));
endproperty
assert_ahb_trxn_aligned: assert property (ahb_trxn_aligned) else
$display("Assertion ahb_trxn_aligned failed: lsu_htrans=2'h%h, lsu_hsize=3'h%h, lsu_haddr=32'h%h",lsu_htrans[1:0], lsu_hsize[2:0], lsu_haddr[31:0]);
property dma_trxn_aligned;
@(posedge clk) disable iff(~rst_l) (dma_htrans[1:0] != 2'b0) |-> ((dma_hsize[2:0] == 3'h0) |
((dma_hsize[2:0] == 3'h1) & (dma_haddr[0] == 1'b0)) |
((dma_hsize[2:0] == 3'h2) & (dma_haddr[1:0] == 2'b0)) |
((dma_hsize[2:0] == 3'h3) & (dma_haddr[2:0] == 3'b0)));
endproperty
`endif
end // if (pt.BUILD_AHB_LITE == 1)

8
Flow/design/el2_swerv_wrapper.sv
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@ -719,12 +719,4 @@ import el2_pkg::*;
.dmi_hard_reset ()
);
`ifdef RV_ASSERT_ON
// to avoid internal assertions failure at time 0
initial begin
$assertoff(0, swerv);
@ (negedge clk) $asserton(0, swerv);
end
`endif
endmodule

43
Flow/design/flist
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@ -1,43 +0,0 @@
$RV_ROOT/design/el2_swerv_wrapper.sv
$RV_ROOT/design/el2_mem.sv
$RV_ROOT/design/el2_pic_ctrl.sv
$RV_ROOT/design/el2_swerv.sv
$RV_ROOT/design/el2_dma_ctrl.sv
$RV_ROOT/design/ifu/el2_ifu_aln_ctl.sv
$RV_ROOT/design/ifu/el2_ifu_compress_ctl.sv
$RV_ROOT/design/ifu/el2_ifu_ifc_ctl.sv
$RV_ROOT/design/ifu/el2_ifu_bp_ctl.sv
$RV_ROOT/design/ifu/el2_ifu_ic_mem.sv
$RV_ROOT/design/ifu/el2_ifu_mem_ctl.sv
$RV_ROOT/design/ifu/el2_ifu_iccm_mem.sv
$RV_ROOT/design/ifu/el2_ifu.sv
$RV_ROOT/design/dec/el2_dec_decode_ctl.sv
$RV_ROOT/design/dec/el2_dec_gpr_ctl.sv
$RV_ROOT/design/dec/el2_dec_ib_ctl.sv
$RV_ROOT/design/dec/el2_dec_tlu_ctl.sv
$RV_ROOT/design/dec/el2_dec_trigger.sv
$RV_ROOT/design/dec/el2_dec.sv
$RV_ROOT/design/exu/el2_exu_alu_ctl.sv
$RV_ROOT/design/exu/el2_exu_mul_ctl.sv
$RV_ROOT/design/exu/el2_exu_div_ctl.sv
$RV_ROOT/design/exu/el2_exu.sv
$RV_ROOT/design/lsu/el2_lsu.sv
$RV_ROOT/design/lsu/el2_lsu_clkdomain.sv
$RV_ROOT/design/lsu/el2_lsu_addrcheck.sv
$RV_ROOT/design/lsu/el2_lsu_lsc_ctl.sv
$RV_ROOT/design/lsu/el2_lsu_stbuf.sv
$RV_ROOT/design/lsu/el2_lsu_bus_buffer.sv
$RV_ROOT/design/lsu/el2_lsu_bus_intf.sv
$RV_ROOT/design/lsu/el2_lsu_ecc.sv
$RV_ROOT/design/lsu/el2_lsu_dccm_mem.sv
$RV_ROOT/design/lsu/el2_lsu_dccm_ctl.sv
$RV_ROOT/design/lsu/el2_lsu_trigger.sv
$RV_ROOT/design/dbg/el2_dbg.sv
$RV_ROOT/design/dmi/dmi_wrapper.v
$RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v
$RV_ROOT/design/dmi/rvjtag_tap.v
$RV_ROOT/design/lib/el2_lib.sv
-v $RV_ROOT/design/lib/beh_lib.sv
-v $RV_ROOT/design/lib/mem_lib.sv
$RV_ROOT/design/lib/ahb_to_axi4.sv
$RV_ROOT/design/lib/axi4_to_ahb.sv

63
Flow/design/flist.formal
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@ -1,63 +0,0 @@
#-*-dotf-*-
$RV_ROOT/design/include/el2_def.sv
+incdir+$RV_ROOT/design/lib
+incdir+$RV_ROOT/design/include
+incdir+$RV_ROOT/design/dmi
//|+incdir+$SYNOPSYS_SYN_ROOT/dw/sim_ver
//|-y $SYNOPSYS_SYN_ROOT/dw/sim_ver
//|
//|$SYNOPSYS_SYN_ROOT/dw/sim_ver/DW01_addsub.v
//|$SYNOPSYS_SYN_ROOT/dw/sim_ver/DW_lzd.v
//|$SYNOPSYS_SYN_ROOT/dw/sim_ver/DW_minmax.v
//|$SYNOPSYS_SYN_ROOT/dw/sim_ver/DW02_mult.v
+incdir+/wdc/apps/mentor/questa/formal/2019.2/share/MODIFIED/dw
+incdir+/wdc/apps/mentor/questa/formal/2019.2/share/MODIFIED/dw/dw_datapath
/wdc/apps/mentor/questa/formal/2019.2/share/MODIFIED/dw/dw.remodel.v
$RV_ROOT/design/el2_swerv_wrapper.sv
$RV_ROOT/design/el2_mem.sv
$RV_ROOT/design/el2_pic_ctrl.sv
$RV_ROOT/design/el2_swerv.sv
$RV_ROOT/design/el2_dma_ctrl.sv
$RV_ROOT/design/ifu/el2_ifu_aln_ctl.sv
$RV_ROOT/design/ifu/el2_ifu_compress_ctl.sv
$RV_ROOT/design/ifu/el2_ifu_ifc_ctl.sv
$RV_ROOT/design/ifu/el2_ifu_bp_ctl.sv
$RV_ROOT/design/ifu/el2_ifu_ic_mem.sv
$RV_ROOT/design/ifu/el2_ifu_mem_ctl.sv
$RV_ROOT/design/ifu/el2_ifu_iccm_mem.sv
$RV_ROOT/design/ifu/el2_ifu.sv
$RV_ROOT/design/dec/el2_dec_decode_ctl.sv
$RV_ROOT/design/dec/el2_dec_gpr_ctl.sv
$RV_ROOT/design/dec/el2_dec_ib_ctl.sv
$RV_ROOT/design/dec/el2_dec_tlu_ctl.sv
$RV_ROOT/design/dec/el2_dec_trigger.sv
$RV_ROOT/design/dec/el2_dec.sv
$RV_ROOT/design/exu/el2_exu_alu_ctl.sv
$RV_ROOT/design/exu/el2_exu_mul_ctl.sv
$RV_ROOT/design/exu/el2_exu_div_ctl.sv
$RV_ROOT/design/exu/el2_exu.sv
$RV_ROOT/design/lsu/el2_lsu.sv
$RV_ROOT/design/lsu/el2_lsu_clkdomain.sv
$RV_ROOT/design/lsu/el2_lsu_addrcheck.sv
$RV_ROOT/design/lsu/el2_lsu_lsc_ctl.sv
$RV_ROOT/design/lsu/el2_lsu_stbuf.sv
$RV_ROOT/design/lsu/el2_lsu_bus_buffer.sv
$RV_ROOT/design/lsu/el2_lsu_bus_intf.sv
$RV_ROOT/design/lsu/el2_lsu_ecc.sv
$RV_ROOT/design/lsu/el2_lsu_dccm_mem.sv
$RV_ROOT/design/lsu/el2_lsu_dccm_ctl.sv
$RV_ROOT/design/lsu/el2_lsu_trigger.sv
$RV_ROOT/design/dbg/el2_dbg.sv
$RV_ROOT/design/dmi/dmi_wrapper.v
$RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v
$RV_ROOT/design/dmi/rvjtag_tap.v
$RV_ROOT/design/lib/el2_lib.sv
$RV_ROOT/design/lib/beh_lib.sv
$RV_ROOT/design/lib/mem_lib.sv
$RV_ROOT/design/lib/ahb_to_axi4.sv
$RV_ROOT/design/lib/axi4_to_ahb.sv

61
Flow/design/flist.questa
View File

@ -1,61 +0,0 @@
#-*-dotf-*-
# $RV_ROOT/workspace/work/snapshots/default/common_defines.vh
# $RV_ROOT/configs/snapshots/default/common_defines.vh
$RV_ROOT/workspace/work/snapshots/default/common_defines.vh
$RV_ROOT/design/include/el2_def.sv
# +incdir+$RV_ROOT/workspace/work/snapshots/default
# +incdir+$RV_ROOT/configs/snapshots/default
+incdir+$RV_ROOT/workspace/work/snapshots/default
+incdir+$RV_ROOT/design/lib
+incdir+$RV_ROOT/design/include
+incdir+$RV_ROOT/design/dmi
+incdir+$SYNOPSYS_SYN_ROOT/dw/sim_ver
-y $SYNOPSYS_SYN_ROOT/dw/sim_ver
$RV_ROOT/design/el2_swerv_wrapper.sv
$RV_ROOT/design/el2_mem.sv
$RV_ROOT/design/el2_pic_ctrl.sv
$RV_ROOT/design/el2_swerv.sv
$RV_ROOT/design/el2_dma_ctrl.sv
$RV_ROOT/design/ifu/el2_ifu_aln_ctl.sv
$RV_ROOT/design/ifu/el2_ifu_compress_ctl.sv
$RV_ROOT/design/ifu/el2_ifu_ifc_ctl.sv
$RV_ROOT/design/ifu/el2_ifu_bp_ctl.sv
$RV_ROOT/design/ifu/el2_ifu_ic_mem.sv
$RV_ROOT/design/ifu/el2_ifu_mem_ctl.sv
$RV_ROOT/design/ifu/el2_ifu_iccm_mem.sv
$RV_ROOT/design/ifu/el2_ifu.sv
$RV_ROOT/design/dec/el2_dec_decode_ctl.sv
$RV_ROOT/design/dec/el2_dec_gpr_ctl.sv
$RV_ROOT/design/dec/el2_dec_ib_ctl.sv
$RV_ROOT/design/dec/el2_dec_tlu_ctl.sv
$RV_ROOT/design/dec/el2_dec_trigger.sv
$RV_ROOT/design/dec/el2_dec.sv
$RV_ROOT/design/exu/el2_exu_alu_ctl.sv
$RV_ROOT/design/exu/el2_exu_mul_ctl.sv
$RV_ROOT/design/exu/el2_exu_div_ctl.sv
$RV_ROOT/design/exu/el2_exu.sv
$RV_ROOT/design/lsu/el2_lsu.sv
$RV_ROOT/design/lsu/el2_lsu_clkdomain.sv
$RV_ROOT/design/lsu/el2_lsu_addrcheck.sv
$RV_ROOT/design/lsu/el2_lsu_lsc_ctl.sv
$RV_ROOT/design/lsu/el2_lsu_stbuf.sv
$RV_ROOT/design/lsu/el2_lsu_bus_buffer.sv
$RV_ROOT/design/lsu/el2_lsu_bus_intf.sv
$RV_ROOT/design/lsu/el2_lsu_ecc.sv
$RV_ROOT/design/lsu/el2_lsu_dccm_mem.sv
$RV_ROOT/design/lsu/el2_lsu_dccm_ctl.sv
$RV_ROOT/design/lsu/el2_lsu_trigger.sv
$RV_ROOT/design/dbg/el2_dbg.sv
$RV_ROOT/design/dmi/dmi_wrapper.v
$RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v
$RV_ROOT/design/dmi/rvjtag_tap.v
$RV_ROOT/design/lib/el2_lib.sv
$RV_ROOT/design/lib/beh_lib.sv
$RV_ROOT/design/lib/mem_lib.sv
$RV_ROOT/design/lib/ahb_to_axi4.sv
$RV_ROOT/design/lib/axi4_to_ahb.sv

4
Flow/design/ifu/el2_ifu.sv
View File

@ -326,8 +326,8 @@ import el2_pkg::*;
assign exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = exu_mp_index[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ; // BTB/BHT address
logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] btb_rd_addr_f;
`define DEC `CPU_TOP.dec
`define EXU `CPU_TOP.exu
`define DEC top.rvtop.swerv.dec
`define EXU top.rvtop.swerv.exu
el2_btb_addr_hash f2hash(.pc(ifc_fetch_addr_f[pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO]), .hash(btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]));
logic [31:0] mppc_ns, mppc;
logic exu_flush_final_d1;

10
Flow/design/ifu/el2_ifu_bp_ctl.sv
View File

@ -778,11 +778,6 @@ end // if (!pt.BTB_FULLYA)
end
end // always_comb begin
//`ifdef RV_ASSERT_ON
// btbhitonehot0: assert #0 ($onehot0(btb_offset_0));
// btbhitonehot1: assert #0 ($onehot0(btb_offset_1));
//`endif
assign vwayhit_f[1:0] = {hit1, hit0} & {eoc_mask, 1'b1};
// way bit is reused as the predicted bit
@ -840,9 +835,8 @@ end // block: fa
for (genvar k=0 ; k < (pt.BHT_ARRAY_DEPTH)/NUM_BHT_LOOP ; k++) begin : BHT_CLK_GROUP
assign bht_bank_clken[i][k] = (bht_wr_en0[i] & ((bht_wr_addr0[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) |
(bht_wr_en2[i] & ((bht_wr_addr2[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH));
`ifndef RV_FPGA_OPTIMIZE
rvclkhdr bht_bank_grp_cgc ( .en(bht_bank_clken[i][k]), .l1clk(bht_bank_clk[i][k]), .* ); // ifndef RV_FPGA_OPTIMIZE
`endif
rvclkhdr bht_bank_grp_cgc ( .en(bht_bank_clken[i][k]), .l1clk(bht_bank_clk[i][k]), .* );
for (j=0 ; j<NUM_BHT_LOOP ; j++) begin : BHT_FLOPS
wire[1:0] wdata;

35
Flow/design/ifu/el2_ifu_mem_ctl.sv
View File

@ -444,14 +444,9 @@ import el2_pkg::*;
assign fetch_bf_f_c1_clken = ifc_fetch_req_bf_raw | ifc_fetch_req_f | miss_pending | exu_flush_final | scnd_miss_req;
assign debug_c1_clken = ic_debug_rd_en | ic_debug_wr_en ;
// C1 - 1 clock pulse for data
`ifdef RV_FPGA_OPTIMIZE
assign fetch_bf_f_c1_clk = 1'b0;
assign debug_c1_clk = 1'b0;
`else
rvclkhdr fetch_bf_f_c1_cgc ( .en(fetch_bf_f_c1_clken), .l1clk(fetch_bf_f_c1_clk), .* );
rvclkhdr debug_c1_cgc ( .en(debug_c1_clken), .l1clk(debug_c1_clk), .* );
`endif
// ------ end clock gating section ------------------------
@ -1031,15 +1026,9 @@ logic perr_sb_write_status ;
assign bus_ifu_bus_clk_en = ifu_bus_clk_en ;
`ifdef RV_FPGA_OPTIMIZE
assign busclk = 1'b0;
assign busclk_force = 1'b0;
`else
rvclkhdr bus_clk_f(.en(bus_ifu_bus_clk_en), .l1clk(busclk), .*);
rvclkhdr bus_clk(.en(bus_ifu_bus_clk_en | dec_tlu_force_halt), .l1clk(busclk_force), .*);
`endif
assign scnd_miss_req = scnd_miss_req_q & ~exu_flush_final;
@ -1158,13 +1147,8 @@ logic perr_sb_write_status ;
({pt.ICACHE_BEAT_BITS{bus_inc_cmd_beat_cnt}} & (bus_cmd_beat_count[pt.ICACHE_BEAT_BITS-1:0] + {{pt.ICACHE_BEAT_BITS-1{1'b0}}, 1'b1})) |
({pt.ICACHE_BEAT_BITS{bus_hold_cmd_beat_cnt}} & bus_cmd_beat_count[pt.ICACHE_BEAT_BITS-1:0]) ;
`ifdef RV_FPGA_OPTIMIZE
assign busclk_reset = 1'b0;
`else
rvclkhdr bus_clk_reset(.en(bus_ifu_bus_clk_en | ic_act_miss_f | dec_tlu_force_halt), .l1clk(busclk_reset), .*);
`endif
rvdffs_fpga #(pt.ICACHE_BEAT_BITS) bus_cmd_beat_ff (.*, .clk(busclk_reset), .clken (bus_ifu_bus_clk_en | ic_act_miss_f | dec_tlu_force_halt), .rawclk(clk), .en (bus_cmd_beat_en), .din ({bus_new_cmd_beat_count[pt.ICACHE_BEAT_BITS-1:0]}),
.dout({bus_cmd_beat_count[pt.ICACHE_BEAT_BITS-1:0]}));
@ -1416,11 +1400,8 @@ if (pt.ICACHE_ENABLE == 1 ) begin: icache_enabled
for (genvar i=0 ; i<pt.ICACHE_TAG_DEPTH/8 ; i++) begin : CLK_GRP_WAY_STATUS
assign way_status_clken[i] = (ifu_status_wr_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO+3] == i );
`ifdef RV_FPGA_OPTIMIZE
assign way_status_clk[i] = 1'b0;
`else
rvclkhdr way_status_cgc ( .en(way_status_clken[i]), .l1clk(way_status_clk[i]), .* );
`endif
rvclkhdr way_status_cgc ( .en(way_status_clken[i]), .l1clk(way_status_clk[i]), .* );
for (genvar j=0 ; j<8 ; j++) begin : WAY_STATUS
@ -1475,12 +1456,8 @@ if (pt.ICACHE_ENABLE == 1 ) begin: icache_enabled
((perr_ic_index_ff [pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO+5] == i ) & perr_err_inv_way[j]) | reset_all_tags);
end
`ifdef RV_FPGA_OPTIMIZE
assign tag_valid_clk[i][j] = 1'b0;
`else
rvclkhdr way_status_cgc ( .en(tag_valid_clken[i][j]), .l1clk(tag_valid_clk[i][j]), .* );
`endif
rvclkhdr way_status_cgc ( .en(tag_valid_clken[i][j]), .l1clk(tag_valid_clk[i][j]), .* );
for (genvar k=0 ; k<32 ; k++) begin : TAG_VALID

15
Flow/design/lib/ahb_to_axi4.sv
View File

@ -267,23 +267,8 @@ import el2_pkg::*;
assign ahb_addr_clk_en = bus_clk_en & (ahb_hready & ahb_htrans[1]);
assign buf_rdata_clk_en = bus_clk_en & buf_rdata_en;
`ifdef RV_FPGA_OPTIMIZE
assign bus_clk = 1'b0;
assign ahb_addr_clk = 1'b0;
assign buf_rdata_clk = 1'b0;
`else
rvclkhdr bus_cgc (.en(bus_clk_en), .l1clk(bus_clk), .*);
rvclkhdr ahb_addr_cgc (.en(ahb_addr_clk_en), .l1clk(ahb_addr_clk), .*);
rvclkhdr buf_rdata_cgc (.en(buf_rdata_clk_en), .l1clk(buf_rdata_clk), .*);
`endif
`ifdef RV_ASSERT_ON
property ahb_error_protocol;
@(posedge bus_clk) (ahb_hready & ahb_hresp) |-> (~$past(ahb_hready) & $past(ahb_hresp));
endproperty
assert_ahb_error_protocol: assert property (ahb_error_protocol) else
$display("Bus Error with hReady isn't preceded with Bus Error without hready");
`endif
endmodule // ahb_to_axi4

23
Flow/design/lib/axi4_to_ahb.sv
View File

@ -447,31 +447,8 @@ import el2_pkg::*;
assign buf_clken = bus_clk_en & (buf_wr_en | slvbuf_wr_en | clk_override);
assign ahbm_data_clken = bus_clk_en & ((buf_state != IDLE) | clk_override);
`ifdef RV_FPGA_OPTIMIZE
assign bus_clk = 1'b0;
assign buf_clk = 1'b0;
assign ahbm_data_clk = 1'b0;
`else
rvclkhdr bus_cgc (.en(bus_clk_en), .l1clk(bus_clk), .*);
rvclkhdr buf_cgc (.en(buf_clken), .l1clk(buf_clk), .*);
rvclkhdr ahbm_data_cgc (.en(ahbm_data_clken), .l1clk(ahbm_data_clk), .*);
`endif
`ifdef RV_ASSERT_ON
property ahb_trxn_aligned;
@(posedge bus_clk) ahb_htrans[1] |-> ((ahb_hsize[2:0] == 3'h0) |
((ahb_hsize[2:0] == 3'h1) & (ahb_haddr[0] == 1'b0)) |
((ahb_hsize[2:0] == 3'h2) & (ahb_haddr[1:0] == 2'b0)) |
((ahb_hsize[2:0] == 3'h3) & (ahb_haddr[2:0] == 3'b0)));
endproperty
assert_ahb_trxn_aligned: assert property (ahb_trxn_aligned) else
$display("Assertion ahb_trxn_aligned failed: ahb_htrans=2'h%h, ahb_hsize=3'h%h, ahb_haddr=32'h%h",ahb_htrans[1:0], ahb_hsize[2:0], ahb_haddr[31:0]);
property ahb_error_protocol;
@(posedge bus_clk) (ahb_hready & ahb_hresp) |-> (~$past(ahb_hready) & $past(ahb_hresp));
endproperty
assert_ahb_error_protocol: assert property (ahb_error_protocol) else
$display("Bus Error with hReady isn't preceded with Bus Error without hready");
`endif
endmodule // axi4_to_ahb

153
Flow/design/lib/beh_lib.sv
View File

@ -101,11 +101,7 @@ if (SHORT == 1) begin
assign dout = din;
end
else begin
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dffs (.clk(rawclk), .en(clken), .*);
`else
rvdff #(WIDTH) dff (.*);
`endif
end
endmodule
@ -126,11 +122,7 @@ if (SHORT == 1) begin : genblock
assign dout = din;
end
else begin : genblock
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dffs (.clk(rawclk), .en(clken & en), .*);
`else
rvdffs #(WIDTH) dffs (.*);
`endif
end
endmodule
@ -154,11 +146,7 @@ if (SHORT == 1) begin
assign dout = din;
end
else begin
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dffs (.clk(rawclk), .din(din[WIDTH-1:0] & {WIDTH{~clear}}),.en((en | clear) & clken), .*);
`else
rvdffsc #(WIDTH) dffsc (.*);
`endif
end
endmodule
@ -181,23 +169,8 @@ if (SHORT == 1) begin : genblock
end
end
else begin : genblock
`ifndef RV_PHYSICAL
if (WIDTH >= 8 || OVERRIDE==1) begin: genblock
`endif
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dff ( .* );
`else
rvclkhdr clkhdr ( .* );
rvdff #(WIDTH) dff (.*, .clk(l1clk));
`endif
`ifndef RV_PHYSICAL
end
else
$error("%m: rvdffe must be WIDTH >= 8");
`endif
end // else: !if(SHORT == 1)
endmodule // rvdffe
@ -213,25 +186,9 @@ module rvdffpcie #( parameter WIDTH=31 )
output logic [WIDTH-1:0] dout
);
rvdfflie #(.WIDTH(WIDTH), .LEFT(19)) dff (.*);
`ifndef RV_PHYSICAL
if (WIDTH == 31) begin: genblock
`endif
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dff ( .* );
`else
rvdfflie #(.WIDTH(WIDTH), .LEFT(19)) dff (.*);
`endif
`ifndef RV_PHYSICAL
end
else
$error("%m: rvdffpcie width must be 31");
`endif
endmodule
// format: { LEFT, EXTRA }
@ -248,41 +205,14 @@ module rvdfflie #( parameter WIDTH=16, LEFT=8 )
localparam EXTRA = WIDTH-LEFT;
localparam LMSB = WIDTH-1;
localparam LLSB = LMSB-LEFT+1;
localparam XMSB = LLSB-1;
localparam XLSB = LLSB-EXTRA;
rvdffiee #(LEFT) dff_left (.*, .din(din[LMSB:LLSB]), .dout(dout[LMSB:LLSB]));
rvdffe #(EXTRA) dff_extra (.*, .din(din[XMSB:XLSB]), .dout(dout[XMSB:XLSB]));
`ifndef RV_PHYSICAL
if (WIDTH >= 16 && LEFT >= 8 && EXTRA >= 8) begin: genblock
`endif
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dff ( .* );
`else
rvdffiee #(LEFT) dff_left (.*, .din(din[LMSB:LLSB]), .dout(dout[LMSB:LLSB]));
rvdffe #(EXTRA) dff_extra (.*, .din(din[XMSB:XLSB]), .dout(dout[XMSB:XLSB]));
`endif
`ifndef RV_PHYSICAL
end
else
$error("%m: rvdfflie musb be WIDTH >= 16 && LEFT >= 8 && EXTRA >= 8");
`endif
endmodule
@ -309,26 +239,9 @@ module rvdffppe #( parameter WIDTH=32 )
localparam RMSB = LLSB-1;
localparam RLSB = LLSB-RIGHT;
rvdffe #(LEFT) dff_left (.*, .din(din[LMSB:LLSB]), .dout(dout[LMSB:LLSB]));
rvdffe #(RIGHT) dff_right (.*, .din(din[RMSB:RLSB]), .dout(dout[RMSB:RLSB]), .en(en & din[LLSB])); // qualify with pret
`ifndef RV_PHYSICAL
if (WIDTH>=32 && LEFT>=8 && RIGHT>=8) begin: genblock
`endif
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dff ( .* );
`else
rvdffe #(LEFT) dff_left (.*, .din(din[LMSB:LLSB]), .dout(dout[LMSB:LLSB]));
rvdffe #(RIGHT) dff_right (.*, .din(din[RMSB:RLSB]), .dout(dout[RMSB:RLSB]), .en(en & din[LLSB])); // qualify with pret
`endif
`ifndef RV_PHYSICAL
end
else
$error("%m: must be WIDTH>=32 && LEFT>=8 && RIGHT>=8");
`endif
endmodule
@ -347,32 +260,10 @@ module rvdffie #( parameter WIDTH=1, OVERRIDE=0 )
logic l1clk;
logic en;
assign en = |(din ^ dout);
`ifndef RV_PHYSICAL
if (WIDTH >= 8 || OVERRIDE==1) begin: genblock
`endif
assign en = |(din ^ dout);
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dff ( .* );
`else
rvclkhdr clkhdr ( .* );
rvdff #(WIDTH) dff (.*, .clk(l1clk));
`endif
`ifndef RV_PHYSICAL
end
else
$error("%m: rvdffie must be WIDTH >= 8");
`endif
rvclkhdr clkhdr ( .* );
rvdff #(WIDTH) dff (.*, .clk(l1clk));
endmodule
@ -391,23 +282,10 @@ module rvdffiee #( parameter WIDTH=1, OVERRIDE=0 )
logic l1clk;
logic final_en;
`ifndef RV_PHYSICAL
if (WIDTH >= 8 || OVERRIDE==1) begin: genblock
`endif
assign final_en = (|(din ^ dout)) & en;
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dff ( .*, .en(final_en) );
`else
rvdffe #(WIDTH) dff (.*, .en(final_en));
`endif
`ifndef RV_PHYSICAL
end
else
$error("%m: rvdffie width must be >= 8");
`endif
rvdffe #(WIDTH) dff (.*, .en(final_en));
endmodule
@ -749,7 +627,7 @@ module rvecc_decode_64 (
endmodule // rvecc_decode_64
module `TEC_RV_ICG
module clockhdr
(
input logic SE, EN, CK,
output Q
@ -774,7 +652,6 @@ module `TEC_RV_ICG
endmodule
`ifndef RV_FPGA_OPTIMIZE
module rvclkhdr
(
input logic en,
@ -786,10 +663,9 @@ module rvclkhdr
logic SE;
assign SE = 0;
`TEC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
clockhdr clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
endmodule // rvclkhdr
`endif
module rvoclkhdr
(
@ -802,12 +678,7 @@ module rvoclkhdr
logic SE;
assign SE = 0;
`ifdef RV_FPGA_OPTIMIZE
assign l1clk = clk;
`else
`TEC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
`endif
clockhdr clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
endmodule

40
Flow/design/lsu/el2_lsu.sv
View File

@ -381,44 +381,4 @@ import el2_pkg::*;
rvdff #(3) dma_mem_tag_mff (.*, .din(dma_mem_tag_d[2:0]), .dout(dma_mem_tag_m[2:0]), .clk(lsu_c1_m_clk));
rvdff #(2) lsu_raw_fwd_r_ff (.*, .din({lsu_raw_fwd_hi_m, lsu_raw_fwd_lo_m}), .dout({lsu_raw_fwd_hi_r, lsu_raw_fwd_lo_r}), .clk(lsu_c2_r_clk));
`ifdef RV_ASSERT_ON
logic [1:0] store_data_bypass_sel;
assign store_data_bypass_sel[1:0] = {lsu_p.store_data_bypass_d, lsu_p.store_data_bypass_m};
property exception_no_lsu_flush;
@(posedge clk) disable iff(~rst_l) lsu_lsc_ctl.lsu_error_pkt_m.exc_valid |-> ##[1:2] (flush_r );
endproperty
assert_exception_no_lsu_flush: assert property (exception_no_lsu_flush) else
$display("No flush within 2 cycles of exception");
// offset should be zero for fast interrupt
property offset_0_fastint;
@(posedge clk) disable iff(~rst_l) (lsu_p.valid & lsu_p.fast_int) |-> (dec_lsu_offset_d[11:0] == 12'b0);
endproperty
assert_offset_0_fastint: assert property (offset_0_fastint) else
$display("dec_tlu_offset_d not zero for fast interrupt redirect");
// DMA req should assert dccm rden/wren
property dmareq_dccm_wren_or_rden;
@(posedge clk) disable iff(~rst_l) dma_dccm_req |-> (dccm_rden | dccm_wren | addr_in_pic_d);
endproperty
assert_dmareq_dccm_wren_or_rden: assert property(dmareq_dccm_wren_or_rden) else
$display("dccm rden or wren not asserted during DMA request");
// fastint_stall should cause load/store stall next cycle
property fastint_stall_imply_loadstore_stall;
@(posedge clk) disable iff(~rst_l) (lsu_fastint_stall_any & (lsu_commit_r | lsu_pkt_r.dma)) |-> ##1 ((lsu_load_stall_any | lsu_store_stall_any) | ~ld_single_ecc_error_r_ff);
endproperty
assert_fastint_stall_imply_loadstore_stall: assert property (fastint_stall_imply_loadstore_stall) else
$display("fastint_stall should be followed by lsu_load/store_stall_any");
// Single ECC error implies rfnpc flush
property single_ecc_error_rfnpc_flush;
@(posedge clk) disable iff(~rst_l) (lsu_error_pkt_r.single_ecc_error & lsu_pkt_r.load) |=> ~lsu_commit_r;
endproperty
assert_single_ecc_error_rfnpc_flush: assert property (single_ecc_error_rfnpc_flush) else
$display("LSU commit next cycle after single ecc error");
`endif
endmodule // el2_lsu

16
Flow/design/lsu/el2_lsu_bus_buffer.sv
View File

@ -917,20 +917,4 @@ import el2_pkg::*;
rvdff #(.WIDTH(1)) lsu_busreq_rff (.din(lsu_busreq_m & ~flush_r & ~ld_full_hit_m), .dout(lsu_busreq_r), .clk(lsu_c2_r_clk), .*);
rvdff #(.WIDTH(1)) lsu_nonblock_load_valid_rff (.din(lsu_nonblock_load_valid_m), .dout(lsu_nonblock_load_valid_r), .clk(lsu_c2_r_clk), .*);
`ifdef RV_ASSERT_ON
for (genvar i=0; i<4; i++) begin: GenByte
assert_ld_byte_hitvecfn_lo_onehot: assert #0 ($onehot0(ld_byte_hitvecfn_lo[i][DEPTH-1:0]));
assert_ld_byte_hitvecfn_hi_onehot: assert #0 ($onehot0(ld_byte_hitvecfn_hi[i][DEPTH-1:0]));
end
for (genvar i=0; i<DEPTH; i++) begin: GenAssertAge
assert_bufempty_agevec: assert #0 (~(lsu_bus_buffer_empty_any & |(buf_age[i])));
end
assert_CmdPtr0Dec_onehot: assert #0 ($onehot0(CmdPtr0Dec[DEPTH-1:0] & ~{DEPTH{dec_tlu_force_halt}}));
assert_CmdPtr1Dec_onehot: assert #0 ($onehot0(CmdPtr1Dec[DEPTH-1:0] & ~{DEPTH{dec_tlu_force_halt}}));
`endif
endmodule // el2_lsu_bus_buffer

95
Flow/design/lsu/el2_lsu_bus_intf.sv
View File

@ -267,99 +267,4 @@ import el2_pkg::*;
rvdff #(4) lsu_byten_rff (.*, .din(ldst_byteen_m[3:0]), .dout(ldst_byteen_r[3:0]), .clk(lsu_c1_r_clk));
`ifdef RV_ASSERT_ON
// Assertion to check AXI write address is aligned to size
property lsu_axi_awaddr_aligned;
@(posedge lsu_busm_clk) disable iff(~rst_l) lsu_axi_awvalid |-> ((lsu_axi_awsize[2:0] == 3'h0) |
((lsu_axi_awsize[2:0] == 3'h1) & (lsu_axi_awaddr[0] == 1'b0)) |
((lsu_axi_awsize[2:0] == 3'h2) & (lsu_axi_awaddr[1:0] == 2'b0)) |
((lsu_axi_awsize[2:0] == 3'h3) & (lsu_axi_awaddr[2:0] == 3'b0)));
endproperty
assert_lsu_axi_awaddr_aligned: assert property (lsu_axi_awaddr_aligned) else
$display("Assertion lsu_axi_awaddr_aligned failed: lsu_axi_awvalid=1'b%b, lsu_axi_awsize=3'h%h, lsu_axi_awaddr=32'h%h",lsu_axi_awvalid, lsu_axi_awsize[2:0], lsu_axi_awaddr[31:0]);
// Assertion to check awvalid stays stable during entire bus clock
// Assertion to check AXI read address is aligned to size
property lsu_axi_araddr_aligned;
@(posedge lsu_busm_clk) disable iff(~rst_l) lsu_axi_arvalid |-> ((lsu_axi_arsize[2:0] == 3'h0) |
((lsu_axi_arsize[2:0] == 3'h1) & (lsu_axi_araddr[0] == 1'b0)) |
((lsu_axi_arsize[2:0] == 3'h2) & (lsu_axi_araddr[1:0] == 2'b0)) |
((lsu_axi_arsize[2:0] == 3'h3) & (lsu_axi_araddr[2:0] == 3'b0)));
endproperty
assert_lsu_axi_araddr_aligned: assert property (lsu_axi_araddr_aligned) else
$display("Assertion lsu_axi_araddr_aligned failed: lsu_axi_awvalid=1'b%b, lsu_axi_awsize=3'h%h, lsu_axi_araddr=32'h%h",lsu_axi_awvalid, lsu_axi_awsize[2:0], lsu_axi_araddr[31:0]);
// Assertion to check awvalid stays stable during entire bus clock
property lsu_axi_awvalid_stable;
@(posedge clk) disable iff(~rst_l) (lsu_axi_awvalid != $past(lsu_axi_awvalid)) |-> ($past(lsu_bus_clk_en) | dec_tlu_force_halt);
endproperty
assert_lsu_axi_awvalid_stable: assert property (lsu_axi_awvalid_stable) else
$display("LSU AXI awvalid changed in middle of bus clock");
// Assertion to check awid stays stable during entire bus clock
property lsu_axi_awid_stable;
@(posedge clk) disable iff(~rst_l) (lsu_axi_awvalid & (lsu_axi_awid[pt.LSU_BUS_TAG-1:0] != $past(lsu_axi_awid[pt.LSU_BUS_TAG-1:0]))) |-> $past(lsu_bus_clk_en);
endproperty
assert_lsu_axi_awid_stable: assert property (lsu_axi_awid_stable) else
$display("LSU AXI awid changed in middle of bus clock");
// Assertion to check awaddr stays stable during entire bus clock
property lsu_axi_awaddr_stable;
@(posedge clk) disable iff(~rst_l) (lsu_axi_awvalid & (lsu_axi_awaddr[31:0] != $past(lsu_axi_awaddr[31:0]))) |-> $past(lsu_bus_clk_en);
endproperty
assert_lsu_axi_awaddr_stable: assert property (lsu_axi_awaddr_stable) else
$display("LSU AXI awaddr changed in middle of bus clock");
// Assertion to check awsize stays stable during entire bus clock
property lsu_axi_awsize_stable;
@(posedge clk) disable iff(~rst_l) (lsu_axi_awvalid & (lsu_axi_awsize[2:0] != $past(lsu_axi_awsize[2:0]))) |-> $past(lsu_bus_clk_en);
endproperty
assert_lsu_axi_awsize_stable: assert property (lsu_axi_awsize_stable) else
$display("LSU AXI awsize changed in middle of bus clock");
// Assertion to check wstrb stays stable during entire bus clock
property lsu_axi_wstrb_stable;
@(posedge clk) disable iff(~rst_l) (lsu_axi_wvalid & (lsu_axi_wstrb[7:0] != $past(lsu_axi_wstrb[7:0]))) |-> $past(lsu_bus_clk_en);
endproperty
assert_lsu_axi_wstrb_stable: assert property (lsu_axi_wstrb_stable) else
$display("LSU AXI wstrb changed in middle of bus clock");
// Assertion to check wdata stays stable during entire bus clock
property lsu_axi_wdata_stable;
@(posedge clk) disable iff(~rst_l) (lsu_axi_wvalid & (lsu_axi_wdata[63:0] != $past(lsu_axi_wdata[63:0]))) |-> $past(lsu_bus_clk_en);
endproperty
assert_lsu_axi_wdata_stable: assert property (lsu_axi_wdata_stable) else
$display("LSU AXI wdata changed in middle of bus clock");
// Assertion to check awvalid stays stable during entire bus clock
property lsu_axi_arvalid_stable;
@(posedge clk) disable iff(~rst_l) (lsu_axi_arvalid != $past(lsu_axi_arvalid)) |-> ($past(lsu_bus_clk_en) | dec_tlu_force_halt);
endproperty
assert_lsu_axi_arvalid_stable: assert property (lsu_axi_arvalid_stable) else
$display("LSU AXI awvalid changed in middle of bus clock");
// Assertion to check awid stays stable during entire bus clock
property lsu_axi_arid_stable;
@(posedge clk) disable iff(~rst_l) (lsu_axi_arvalid & (lsu_axi_arid[pt.LSU_BUS_TAG-1:0] != $past(lsu_axi_arid[pt.LSU_BUS_TAG-1:0]))) |-> $past(lsu_bus_clk_en);
endproperty
assert_lsu_axi_arid_stable: assert property (lsu_axi_arid_stable) else
$display("LSU AXI awid changed in middle of bus clock");
// Assertion to check awaddr stays stable during entire bus clock
property lsu_axi_araddr_stable;
@(posedge clk) disable iff(~rst_l) (lsu_axi_arvalid & (lsu_axi_araddr[31:0] != $past(lsu_axi_araddr[31:0]))) |-> $past(lsu_bus_clk_en);
endproperty
assert_lsu_axi_araddr_stable: assert property (lsu_axi_araddr_stable) else
$display("LSU AXI awaddr changed in middle of bus clock");
// Assertion to check awsize stays stable during entire bus clock
property lsu_axi_arsize_stable;
@(posedge clk) disable iff(~rst_l) (lsu_axi_awvalid & (lsu_axi_arsize[2:0] != $past(lsu_axi_arsize[2:0]))) |-> $past(lsu_bus_clk_en);
endproperty
assert_lsu_axi_arsize_stable: assert property (lsu_axi_arsize_stable) else
$display("LSU AXI awsize changed in middle of bus clock");
`endif
endmodule // el2_lsu_bus_intf

5
Flow/design/lsu/el2_lsu_clkdomain.sv
View File

@ -131,13 +131,8 @@ import el2_pkg::*;
assign lsu_busm_clken = (~lsu_bus_buffer_empty_any | lsu_busreq_r | clk_override) & lsu_bus_clk_en;
`ifdef RV_FPGA_OPTIMIZE
assign lsu_busm_clk = 1'b0;
assign lsu_bus_obuf_c1_clk = 1'b0;
`else
rvclkhdr lsu_bus_obuf_c1_cgc ( .en(lsu_bus_obuf_c1_clken), .l1clk(lsu_bus_obuf_c1_clk), .* );
rvclkhdr lsu_busm_cgc (.en(lsu_busm_clken), .l1clk(lsu_busm_clk), .*);
`endif
rvoclkhdr lsu_free_cgc (.en(lsu_free_c2_clken), .l1clk(lsu_free_c2_clk), .*);

12
Flow/design/lsu/el2_lsu_dccm_ctl.sv
View File

@ -410,16 +410,4 @@ import el2_pkg::*;
assign ld_sec_addr_lo_r_ff[pt.DCCM_BITS-1:0] = '0;
end
`ifdef RV_ASSERT_ON
// Load single ECC error correction implies commit/dma
property ld_single_ecc_error_commit;
@(posedge clk) disable iff(~rst_l) (ld_single_ecc_error_r_ff & dccm_wren) |-> ($past(lsu_commit_r | lsu_pkt_r.dma));
endproperty
assert_ld_single_ecc_error_commit: assert property (ld_single_ecc_error_commit) else
$display("No commit or DMA but ECC correction happened");
`endif
endmodule

11
Flow/design/lsu/el2_lsu_stbuf.sv
View File

@ -336,16 +336,5 @@ import el2_pkg::*;
rvdffs #(.WIDTH(DEPTH_LOG2)) WrPtrff (.din(NxtWrPtr[DEPTH_LOG2-1:0]), .dout(WrPtr[DEPTH_LOG2-1:0]), .en(WrPtrEn), .clk(lsu_stbuf_c1_clk), .*);
rvdffs #(.WIDTH(DEPTH_LOG2)) RdPtrff (.din(NxtRdPtr[DEPTH_LOG2-1:0]), .dout(RdPtr[DEPTH_LOG2-1:0]), .en(RdPtrEn), .clk(lsu_stbuf_c1_clk), .*);
`ifdef RV_ASSERT_ON
assert_stbuf_overflow: assert #0 (stbuf_specvld_any[2:0] <= DEPTH);
property stbuf_wren_store_dccm;
@(posedge clk) disable iff(~rst_l) (|stbuf_wr_en[DEPTH-1:0]) |-> (lsu_pkt_r.valid & lsu_pkt_r.store & addr_in_dccm_r);
endproperty
assert_stbuf_wren_store_dccm: assert property (stbuf_wren_store_dccm) else
$display("Illegal store buffer write");
`endif
endmodule

2
Flow/soc/soc_sim.sv
View File

@ -229,7 +229,7 @@ module soc_sim (
`define DRAM(bank) \
rvsoc.rvtop.mem.Gen_dccm_enable.dccm.mem_bank[bank].dccm_bank.ram_core
`define ICCM_PATH `RV_TOP.mem.iccm
`define ICCM_PATH top.rvtop.mem.iccm
`define IRAM0(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_lo0.ram_core
`define IRAM1(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_lo1.ram_core
`define IRAM2(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_hi0.ram_core

39
Flow/soc/swerv.config
View File

@ -33,7 +33,7 @@ my @argv_orig = @ARGV;
my $defines_case = "U";
# Include these macros in verilog (pattern matched)
my @verilog_vars = qw (xlen config_key reset_vec tec_rv_icg numiregs nmi_vec target protection.* testbench.* dccm.* retstack core.* iccm.* btb.* bht.* icache.* pic.* regwidth memmap bus.*);
my @verilog_vars = qw (xlen reset_vec tec_rv_icg numiregs nmi_vec target protection.* testbench.* dccm.* retstack core.* iccm.* btb.* bht.* icache.* pic.* regwidth memmap bus.*);
# Include these macros in assembly (pattern matched)
my @asm_vars = qw (xlen reset_vec nmi_vec target dccm.* iccm.* pic.* memmap testbench.* protection.* core.*);
@ -48,7 +48,7 @@ my @dvars = qw(retstack btb bht core dccm iccm icache pic protection memmap bus)
# Prefix all macros with
my $prefix = "RV_";
# No prefix if keyword has
my $no_prefix = 'RV|TOP|tec_rv_icg|regwidth|clock_period|^datawidth|verilator|SDVT_AHB';
my $no_prefix = 'RV|tec_rv_icg|regwidth|clock_period|^datawidth|verilator|SDVT_AHB';
my $vlog_use__wh = 1;
@ -195,8 +195,6 @@ Parameters that can be set by the end user:
Bit manipulation extension ZBr enabled/legal
-set=bitmanip_zbs = {0,1}
Bit manipulation extension ZBs enabled/legal
-fpga_optimize = { 0, 1 }
if 1, minimize clock-gating to facilitate FPGA builds
-text_in_iccm = {0, 1}
Don't add ICCM preload code in generated link.ld
@ -305,8 +303,6 @@ $dma_buf_depth=5;
my $div_bit=4; # number of bits to process each cycle for div
my $div_new=1; # old or new div algorithm
my $fpga_optimize = 1;
# Default bitmanip options
my $bitmanip_zba = 1;
my $bitmanip_zbb = 1;
@ -353,7 +349,6 @@ GetOptions(
"icache_size=s" => \$icache_size,
"set=s@" => \@sets,
"unset=s@" => \@unsets,
"fpga_optimize=s" => \$fpga_optimize,
"text_in_iccm" => \$text_in_iccm,
) || die("$helpusage");
@ -412,7 +407,6 @@ elsif ($target eq "lsu2dma_axi") {
}
elsif ($target eq "typical_pd") {
print "$self: Using target \"typical_pd\"\n";
$fpga_optimize = 0;
$ret_stack_size=2;
$btb_size=32;
$bht_size=128;
@ -840,12 +834,9 @@ our %config = (#{{{
"regwidth" => "32", # Testbench, Do Not Override
"reset_vec" => "0x80000000", # Testbench, Overridable
"nmi_vec" => "0x11110000", # Testbench, Overridable
"physical" => "1",
"num_mmode_perf_regs" => "4", # Whisper only
"max_mmode_perf_event" => "516", # Whisper only: performance counters event ids will be clamped to this
"target" => $target, # Flow Infrastructure
"config_key" => "derived",
"tec_rv_icg" => "clockhdr",
"retstack" => {
"ret_stack_size" => "$ret_stack_size", # Design Parm, Overridable
@ -904,7 +895,6 @@ our %config = (#{{{
"bitmanip_zbs" => $bitmanip_zbs, # Design Parm, Overridable
"fast_interrupt_redirect" => "$fast_interrupt_redirect", # Design Parm, Overridable
"lsu2dma" => $lsu2dma, # used by design/TB for LSU to DMA bridge
"fpga_optimize" => $fpga_optimize # Design Parm, Overridable
},
"dccm" => {
@ -924,7 +914,6 @@ our %config = (#{{{
"dccm_index_bits" => 'derived',
"dccm_ecc_width" => 'derived',
"lsu_sb_bits" => 'derived',
"dccm_data_cell" => 'derived',
"dccm_rows" => 'derived',
"dccm_reserved" => 'derived', # Testbench use only : reserve dccm space for SW/stack - no random r/w
},
@ -939,7 +928,6 @@ our %config = (#{{{
"iccm_bank_bits" => 'derived',
"iccm_index_bits" => 'derived',
"iccm_rows" => 'derived',
"iccm_data_cell" => 'derived',
"iccm_sadr" => 'derived',
"iccm_eadr" => 'derived',
"iccm_reserved" => 'derived', # Testbench use only : reserve iccm space for SW/handlers - no random r/w
@ -962,8 +950,6 @@ our %config = (#{{{
"icache_tag_num_bypass_width" => 'derived',
"icache_bank_hi" => 'derived',
"icache_bank_lo" => 'derived',
"icache_data_cell" => 'derived',
"icache_tag_cell" => 'derived',
"icache_tag_depth" => 'derived',
"icache_data_depth" => 'derived',
"icache_num_lines" => 'derived',
@ -1020,14 +1006,10 @@ our %config = (#{{{
"pic_meigwclr_count" => 'derived',
},
"testbench" => { # Testbench only
"TOP" => "tb_top",
"RV_TOP" => "`TOP.rvtop",
"CPU_TOP" => "`RV_TOP.swerv",
"clock_period" => "100",
"build_ahb_lite" => "$ahb",
"build_axi4" => "$axi",
"build_axi_native" => "1",
"assert_on" => "",
"ext_datawidth" => "64",
"ext_addrwidth" => "32",
"sterr_rollback" => "0",
@ -1565,8 +1547,6 @@ $config{dccm}{dccm_index_bits} = $config{dccm}{dccm_bits} - $config{dccm}{dccm_b
$config{dccm}{dccm_ecc_width} = log2($config{dccm}{dccm_data_width}) + 2;
$config{dccm}{lsu_sb_bits} = $config{dccm}{dccm_bits};
$config{dccm}{dccm_rows} = ($config{dccm}{dccm_size}==48 ) ? (2**($config{dccm}{dccm_index_bits}-1) + 2**$config{dccm}{dccm_index_bits})/2 : 2**$config{dccm}{dccm_index_bits};
$config{dccm}{dccm_data_cell} = "ram_$config{dccm}{dccm_rows}x39";
$config{icache}{icache_num_lines} = $config{icache}{icache_size}*1024/$config{icache}{icache_ln_sz};
$config{icache}{icache_num_lines_way} = $config{icache}{icache_num_lines}/$config{icache}{icache_num_ways};
@ -1591,14 +1571,10 @@ $config{icache}{icache_beat_addr_hi} = ($config{icache}{icache_ln_sz}==64) ? 5
if (($config{icache}{icache_ecc})) {
$config{icache}{icache_fdata_width} = $config{icache}{icache_data_width} + 7;
$config{icache}{icache_data_cell} = "ram_$config{icache}{icache_data_depth}x$config{icache}{icache_fdata_width}";
$config{icache}{icache_tag_cell} = ($config{icache}{icache_tag_depth} == 32) ? "ram_$config{icache}{icache_tag_depth}x26" : "ram_$config{icache}{icache_tag_depth}x25";
}
else {
$config{icache}{icache_fdata_width} = $config{icache}{icache_data_width} + 4;
$config{icache}{icache_data_cell} = "ram_$config{icache}{icache_data_depth}x$config{icache}{icache_fdata_width}";
$config{icache}{icache_tag_cell} = "ram_$config{icache}{icache_tag_depth}x21";
}
$config{pic}{pic_total_int_plus1} = $config{pic}{pic_total_int} + 1;
# Defines with explicit values in the macro name
@ -1626,7 +1602,6 @@ $config{iccm}{iccm_bits} = 10 + log2($config{iccm}{iccm_size});
$config{iccm}{iccm_bank_bits} = log2($config{iccm}{iccm_num_banks}); //-1;
$config{iccm}{iccm_index_bits} = $config{iccm}{iccm_bits} - $config{iccm}{iccm_bank_bits} - 2; # always 4 bytes
$config{iccm}{iccm_rows} = 2**$config{iccm}{iccm_index_bits};
$config{iccm}{iccm_data_cell} = "ram_$config{iccm}{iccm_rows}x39";
$config{iccm}{iccm_bank_hi} = 2+$config{iccm}{iccm_bank_bits}-1;
$config{iccm}{iccm_bank_index_lo} = 1+$config{iccm}{iccm_bank_hi};
@ -1884,13 +1859,8 @@ if (defined($config{"testbench"}{"build_axi_native"}) && ($config{"testbench"}{"
}
# parm processing before any values are deleted from the hash
delete $config{core}{fpga_optimize} if ($config{core}{fpga_optimize} == 0);
print "$self: Writing $tdfile\n";
print "$self: Writing $paramfile\n";
open (FILE1, ">$tdfile") || die "Cannot open $tdfile for writing $!\n";
@ -1901,7 +1871,6 @@ dump_parms(\%verilog_parms);
close FILE1;
close FILE2;
$config{config_key}="32'hdeadbeef";
# end parms
@ -1979,14 +1948,10 @@ print_header("//");
gen_define("","#", \%config, "", \@asm_vars, \@asm_overridable);
close FILE;
# add `define PHYSICAL 1
# remove `undef RV_ICCM_ENABLE
my $pddata='
`include "common_defines.vh"
`undef RV_ASSERT_ON
`undef TEC_RV_ICG
`define RV_PHYSICAL 1
';

41
Flow/soc/swerv_config_gen.py
View File

@ -1,41 +0,0 @@
#!/usr/bin/env python3
from fusesoc.capi2.generator import Generator
import os
import subprocess
import sys
class SwervConfigGenerator(Generator):
def run(self):
script_root = os.path.abspath(os.path.join(os.path.dirname(sys.argv[0]), '..'))
files = [
{"common_defines.vh" : {
"copyto" : "config/common_defines.vh",
"file_type" : "systemVerilogSource"}},
{"el2_pdef.vh" : {
"copyto" : "config/el2_pdef.vh",
"file_type" : "systemVerilogSource"}},
{"el2_param.vh" : {
"is_include_file" : True,
"file_type" : "systemVerilogSource"}},
{"pic_map_auto.h" : {
"is_include_file" : True,
"file_type" : "systemVerilogSource"}}]
env = os.environ.copy()
env['RV_ROOT'] = script_root
env['BUILD_PATH'] = os.getcwd()
args = ['configs/swerv.config'] + self.config.get('args', [])
rc = subprocess.call(args, cwd=script_root, env=env, stdout=subprocess.DEVNULL)
if rc:
exit(1)
filenames = []
for f in files:
for k in f:
filenames.append(k)
self.add_files(files)
g = SwervConfigGenerator()
g.run()
g.write()

97
Flow/swerv_el2.core
View File

@ -1,97 +0,0 @@
CAPI=2:
name : chipsalliance.org:cores:SweRV_EL2:1.3
filesets:
rtl:
files:
- design/include/el2_def.sv
- design/lib/el2_lib.sv
- design/lib/beh_lib.sv
- design/el2_mem.sv
- design/el2_pic_ctrl.sv
- design/el2_dma_ctrl.sv
- design/ifu/el2_ifu_aln_ctl.sv
- design/ifu/el2_ifu_compress_ctl.sv
- design/ifu/el2_ifu_ifc_ctl.sv
- design/ifu/el2_ifu_bp_ctl.sv
- design/ifu/el2_ifu_ic_mem.sv
- design/ifu/el2_ifu_mem_ctl.sv
- design/ifu/el2_ifu_iccm_mem.sv
- design/ifu/el2_ifu.sv
- design/dec/el2_dec_decode_ctl.sv
- design/dec/el2_dec_gpr_ctl.sv
- design/dec/el2_dec_ib_ctl.sv
- design/dec/el2_dec_tlu_ctl.sv
- design/dec/el2_dec_trigger.sv
- design/dec/el2_dec.sv
- design/exu/el2_exu_alu_ctl.sv
- design/exu/el2_exu_mul_ctl.sv
- design/exu/el2_exu_div_ctl.sv
- design/exu/el2_exu.sv
- design/lsu/el2_lsu.sv
- design/lsu/el2_lsu_bus_buffer.sv
- design/lsu/el2_lsu_clkdomain.sv
- design/lsu/el2_lsu_addrcheck.sv
- design/lsu/el2_lsu_lsc_ctl.sv
- design/lsu/el2_lsu_stbuf.sv
- design/lsu/el2_lsu_bus_intf.sv
- design/lsu/el2_lsu_ecc.sv
- design/lsu/el2_lsu_dccm_mem.sv
- design/lsu/el2_lsu_dccm_ctl.sv
- design/lsu/el2_lsu_trigger.sv
- design/dbg/el2_dbg.sv
- design/dmi/dmi_wrapper.v
- design/dmi/dmi_jtag_to_core_sync.v
- design/dmi/rvjtag_tap.v
- design/lib/mem_lib.sv
- design/el2_swerv.sv
- design/el2_swerv_wrapper.sv
file_type : systemVerilogSource
vivado_tcl: {files: [tools/vivado.tcl : {file_type : tclSource}]}
targets:
default:
filesets :
- rtl
- "tool_vivado ? (vivado_tcl)"
lint:
default_tool: verilator
filesets : [rtl]
generate : [swerv_default_config]
tools:
verilator :
mode : lint-only
toplevel : el2_swerv_wrapper
synth:
default_tool : vivado
filesets : [rtl, vivado_tcl]
generate : [swerv_default_config]
parameters : [RV_FPGA_OPTIMIZE]
tools:
vivado:
part : xc7a100tcsg324-1
pnr : none
toplevel : el2_swerv_wrapper
generate:
swerv_default_config:
generator: swerv_el2_config
position : first
parameters:
args : [-unset=assert_on]
generators:
swerv_el2_config:
interpreter: python3
command: configs/swerv_config_gen.py
description : Create a SweRV EL2 configuration. Note! Only supports the default config
parameters:
RV_FPGA_OPTIMIZE:
datatype : bool
default : true
description : Minimize clock gating to map better to FPGAs
paramtype : vlogdefine