Updated release notes.
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@ -9,7 +9,8 @@ is added to the SweRV core.
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1. Bug fixes:
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* Hart incorrectly cleared dmcontrol.dmactive on reset (reported by
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Codasip).
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Codasip). Note that a separate system power-on-reset signal `dbg_rst_l`
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was added to differentiate power-on-reset vs core reset.
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* Hart never asserted the dmstatus.allrunning signal on reset which
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caused a timeout in OpenOCD (reported by Codasip).
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* Debug module failed to auto-increment register on system-bus access
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