Add fpga demo in Cores.

Cores-SweRV/demo/Readme.md

@@ -23,6 +23,10 @@ make
 sudo make install
 ```
 
+## may be install sv2v
+
+`https://github.com/zachjs/sv2v`
+
 ## install ninja
 
 `sudo apt-get install -y ninja-build`

Cores-SweRV/demo/fpga/.gitignore

@@ -0,0 +1 @@
+gen/

Cores-SweRV/demo/fpga/Makefile

@@ -0,0 +1,81 @@
+export RV_ROOT = ${PWD}/../..
+GCC_PREFIX = /opt/riscv/bin/riscv32-unknown-elf
+GDB_PREFIX = /opt/riscv/bin/riscv32-unknown-elf-gdb
+
+
+TEST_CFLAGS = -g -O3 -funroll-all-loops
+ABI = -mabi=ilp32 -march=rv32imc
+
+DEMODIR = ${PWD}
+BUILD_DIR = ${DEMODIR}/build
+RV_SOC = ${RV_ROOT}/soc
+
+TEST = jtag
+
+ifdef debug
+ DEBUG_PLUS = +dumpon
+ VERILATOR_DEBUG = --trace
+endif
+
+LINK = $(DEMODIR)/link.ld
+
+# CFLAGS for verilator generated Makefiles. Without -std=c++11 it complains for `auto` variables
+CFLAGS += "-std=c++11"
+# Optimization for better performance; alternative is nothing for slower runtime (faster compiles)
+# -O2 for faster runtime (slower compiles), or -O for balance.
+VERILATOR_MAKE_FLAGS = OPT_FAST="-Os"
+
+# Targets
+all: clean verilator
+
+clean:
+	rm -rf build obj_dir
+
+swerv_define :
+	BUILD_PATH=${BUILD_DIR} PERLLIB=${RV_SOC} ${RV_SOC}/swerv.config -target=default_ahb -set iccm_enable
+
+##################### Verilog Builds #####################################
+
+verilator-build: swerv_define
+	echo '`undef ASSERT_ON' >> ${BUILD_DIR}/common_defines.vh
+	verilator --cc -CFLAGS ${CFLAGS} \
+	              $(BUILD_DIR)/common_defines.vh \
+	              -I${BUILD_DIR} \
+	              -Wno-UNOPTFLAT \
+	              -F ${RV_SOC}/soc_top.mk \
+	              -F ${RV_SOC}/soc_sim.mk \
+	              $(RV_SOC)/soc_sim.sv \
+	              --top-module soc_sim -exe test_soc_sim.cpp --autoflush $(VERILATOR_DEBUG)
+	cp ${DEMODIR}/test_soc_sim.cpp obj_dir
+	$(MAKE) -j -C obj_dir/ -f Vsoc_sim.mk $(VERILATOR_MAKE_FLAGS)
+
+##################### Simulation Runs #####################################
+
+verilator: program.hex verilator-build
+	cd build && ../obj_dir/Vsoc_sim ${DEBUG_PLUS}
+
+##################### Test hex Build #####################################
+
+program.hex: $(TEST).o $(LINK)
+	@echo Building $(TEST)
+	$(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(BUILD_DIR)/$(TEST).map -lgcc -T$(LINK) -o $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/$(TEST).o -nostartfiles  $(TEST_LIBS)
+	$(GCC_PREFIX)-objcopy -O verilog $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/program.hex
+	$(GCC_PREFIX)-objdump -S  $(BUILD_DIR)/$(TEST).bin > $(BUILD_DIR)/$(TEST).dis
+	@echo Completed building $(TEST)
+
+%.o : %.s swerv_define
+	$(GCC_PREFIX)-cpp -g -I${BUILD_DIR}  $<  > $(BUILD_DIR)/$*.cpp.s
+	$(GCC_PREFIX)-as -g $(ABI) $(BUILD_DIR)/$*.cpp.s -o $(BUILD_DIR)/$@
+
+##################### openocd #####################################
+
+openocd:
+	openocd -f swerv.cfg
+
+gdb:
+	$(GDB_PREFIX) -x gdbinit ./build/jtag.bin
+
+help:
+	@echo Possible targets: verilator help clean all verilator-build program.hex
+
+.PHONY: help clean verilator

Cores-SweRV/demo/fpga/Makefile.bk

@@ -0,0 +1,81 @@
+export RV_ROOT = ${PWD}/../..
+GCC_PREFIX = /opt/riscv/bin/riscv32-unknown-elf
+GDB_PREFIX = /opt/riscv/bin/riscv32-unknown-elf-gdb
+
+
+TEST_CFLAGS = -g -O3 -funroll-all-loops
+ABI = -mabi=ilp32 -march=rv32imc
+
+DEMODIR = ${PWD}
+BUILD_DIR = ${DEMODIR}/build
+RV_SOC = ${RV_ROOT}/soc
+
+TEST = jtag
+
+ifdef debug
+ DEBUG_PLUS = +dumpon
+ VERILATOR_DEBUG = --trace
+endif
+
+LINK = $(DEMODIR)/link.ld
+
+# CFLAGS for verilator generated Makefiles. Without -std=c++11 it complains for `auto` variables
+CFLAGS += "-std=c++11"
+# Optimization for better performance; alternative is nothing for slower runtime (faster compiles)
+# -O2 for faster runtime (slower compiles), or -O for balance.
+VERILATOR_MAKE_FLAGS = OPT_FAST="-Os"
+
+# Targets
+all: clean verilator
+
+clean:
+	rm -rf build obj_dir
+
+swerv_define :
+	BUILD_PATH=${BUILD_DIR} PERLLIB=${RV_SOC} ${RV_SOC}/swerv.config -target=default_ahb -set iccm_enable
+
+##################### Verilog Builds #####################################
+
+verilator-build: swerv_define
+	echo '`undef ASSERT_ON' >> ${BUILD_DIR}/common_defines.vh
+	verilator --cc -CFLAGS ${CFLAGS} \
+	              $(BUILD_DIR)/common_defines.vh \
+	              -I${BUILD_DIR} \
+	              -Wno-UNOPTFLAT \
+	              -F ${RV_SOC}/soc_top.mk \
+	              -F ${RV_SOC}/soc_sim.mk \
+	              $(RV_SOC)/soc_sim.sv \
+	              --top-module soc_sim -exe test_soc_sim.cpp --autoflush $(VERILATOR_DEBUG)
+	cp ${DEMODIR}/test_soc_sim.cpp obj_dir
+	$(MAKE) -j -C obj_dir/ -f Vsoc_sim.mk $(VERILATOR_MAKE_FLAGS)
+
+##################### Simulation Runs #####################################
+
+verilator: program.hex verilator-build
+	cd build && ../obj_dir/Vsoc_sim ${DEBUG_PLUS}
+
+##################### Test hex Build #####################################
+
+program.hex: $(TEST).o $(LINK)
+	@echo Building $(TEST)
+	$(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(BUILD_DIR)/$(TEST).map -lgcc -T$(LINK) -o $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/$(TEST).o -nostartfiles  $(TEST_LIBS)
+	$(GCC_PREFIX)-objcopy -O verilog $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/program.hex
+	$(GCC_PREFIX)-objdump -S  $(BUILD_DIR)/$(TEST).bin > $(BUILD_DIR)/$(TEST).dis
+	@echo Completed building $(TEST)
+
+%.o : %.s swerv_define
+	$(GCC_PREFIX)-cpp -g -I${BUILD_DIR}  $<  > $(BUILD_DIR)/$*.cpp.s
+	$(GCC_PREFIX)-as -g $(ABI) $(BUILD_DIR)/$*.cpp.s -o $(BUILD_DIR)/$@
+
+##################### openocd #####################################
+
+openocd:
+	openocd -f swerv.cfg
+
+gdb:
+	$(GDB_PREFIX) -x gdbinit ./build/jtag.bin
+
+help:
+	@echo Possible targets: verilator help clean all verilator-build program.hex
+
+.PHONY: help clean verilator

Cores-SweRV/demo/fpga/Readmd.md

@@ -0,0 +1,18 @@
+# jtag simulation
+
+
+## start openocd
+
+`openocd -d -f swerv.cfg`
+
+## start gdb
+
+`/opt/riscv/bin/riscv32-unknown-elf-gdb -ex "target extended-remote :3333"`
+
+## quick start
+
+At demo/jtag/  
+
+1. `make all`  
+2. `make openocd` 
+3. `make gdb`

Cores-SweRV/demo/fpga/gdbinit

@@ -0,0 +1,2 @@
+target remote :3333
+set remotetimeout 2000

Cores-SweRV/demo/fpga/jtag.s

@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2019 Western Digital Corporation or its affiliates.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+// Assembly code for Hello World
+// Not using only ALU ops for creating the string
+
+
+#include "defines.h"
+
+#define STDOUT 0xd0580000
+
+
+// Code to execute
+.section .text
+.global _start
+_start:
+
+    // Clear minstret
+    csrw minstret, zero
+    csrw minstreth, zero
+
+    // Set up MTVEC - not expecting to use it though
+    li x1, RV_ICCM_SADR
+    csrw mtvec, x1
+
+
+    // Enable Caches in MRAC
+    li x1, 0x5f555555
+    csrw 0x7c0, x1
+
+    // Load string from hw_data
+    // and write to stdout address
+
+    li x3, STDOUT
+    la x4, hw_data
+
+loop:
+   lb x5, 0(x4)
+   sb x5, 0(x3)
+   addi x4, x4, 1
+   bnez x5, loop
+
+   li x3, STDOUT
+   la x4, hw_data
+
+loop2:
+   lb x5, 0(x4)
+   sb x5, 0(x3)
+   addi x4, x4, 1
+   bnez x5, loop2
+
+loop3:
+   beq x0, x0, loop3
+
+// Write 0xff to STDOUT for TB to terminate test.
+_finish:
+    li x3, STDOUT
+    addi x5, x0, 0xff
+    sb x5, 0(x3)
+    beq x0, x0, _finish
+.rept 100
+    nop
+.endr
+
+.global hw_data
+.data
+hw_data:
+.ascii "----------------------------------\n"
+.ascii "Hello World Colin.liang EH1@WDC !!\n"
+.ascii "----------------------------------\n"
+.byte 0

Cores-SweRV/demo/fpga/link.ld

@@ -0,0 +1,16 @@
+
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+SECTIONS
+{
+  . = 0;
+  .text_init   : { *(.text_init*) }
+  .text   : { *(.text*) }
+  _end = .;
+  . = 0x4000;
+  .data  :  ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x2000; }
+  .bss : { *(.bss) }
+  . = 0xd0580000;
+  .data.io   : { *(.data.io) }
+}

Cores-SweRV/demo/fpga/program.hex

@@ -0,0 +1,28 @@
+@00000000
+73 10 20 B0 73 10 20 B8 B7 00 00 EE 73 90 50 30 
+B7 50 55 5F 93 80 50 55 73 90 00 7C B7 01 58 D0 
+17 42 00 00 13 02 02 FE 83 02 02 00 23 80 51 00 
+05 02 E3 9B 02 FE B7 01 58 D0 17 42 00 00 13 02 
+62 FC 83 02 02 00 23 80 51 00 05 02 E3 9B 02 FE 
+63 00 00 00 B7 01 58 D0 93 02 F0 0F 23 80 51 00 
+E3 0A 00 FE 01 00 01 00 01 00 01 00 01 00 01 00 
+01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 
+01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 
+01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 
+01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 
+01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 
+01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 
+01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 
+01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 
+01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 
+01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 
+01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 
+01 00 01 00 01 00 01 00 01 00 01 00 
+@00004000
+2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 
+2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 
+2D 2D 0A 48 65 6C 6C 6F 20 57 6F 72 6C 64 20 43 
+6F 6C 69 6E 2E 6C 69 61 6E 67 20 45 48 31 40 57 
+44 43 20 21 21 0A 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 
+2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 
+2D 2D 2D 2D 2D 2D 2D 2D 0A 00 

Cores-SweRV/demo/fpga/soc.lpf

@@ -0,0 +1,32 @@
+LOCATE COMP "clk" SITE "P3";
+IOBUF PORT "clk" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "clk" 25 MHZ;
+
+LOCATE COMP "dbg_rst" SITE "N2";
+IOBUF PORT "dbg_rst" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "dbg_rst" 25 MHZ;
+
+LOCATE COMP "rst" SITE "N3";
+IOBUF PORT "rst" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "rst" 25 MHZ;
+
+LOCATE COMP "jtag_tck" SITE "T2";
+IOBUF PORT "jtag_tck" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "jtag_tck" 25 MHZ;
+
+LOCATE COMP "jtag_tms" SITE "T3";
+IOBUF PORT "jtag_tms" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "jtag_tms" 25 MHZ;
+
+LOCATE COMP "jtag_tdi" SITE "N4";
+IOBUF PORT "jtag_tdi" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "jtag_tdi" 25 MHZ;
+
+LOCATE COMP "jtag_trst_n" SITE "M3";
+IOBUF PORT "jtag_trst_n" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "jtag_trst_n" 25 MHZ;
+
+
+
+LOCATE COMP "jtag_tdo" SITE "M4";
+IOBUF PORT "jtag_tdo" IO_TYPE=LVCMOS33;

Cores-SweRV/demo/fpga/swerv.cfg

@@ -0,0 +1,34 @@
+# "JTAG adapter" for simulation, exposed to OpenOCD through a TCP socket 
+# speaking the remote_bitbang protocol. The adapter is implemented as 
+# SystemVerilog DPI module.
+
+adapter driver remote_bitbang
+remote_bitbang host localhost
+remote_bitbang port 44853
+
+# Target configuration for the riscv chip
+
+set  _CHIPNAME riscv
+set _TARGETNAME $_CHIPNAME.cpu
+
+jtag newtap $_CHIPNAME tap -irlen 5 -expected-id 0x01
+set _TARGETNAME $_CHIPNAME.tap
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME 
+
+# Configure work area in on-chip SRAM
+# $_TARGETNAME configure -work-area-phys 0x1000e000 -work-area-size 1000 -work-area-backup 0
+
+riscv expose_csrs 1988
+
+# Be verbose about GDB errors
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+# Increase timeouts in simulation
+riscv set_command_timeout_sec 1200
+
+# Conclude OpenOCD configuration
+init
+
+# Halt the target
+halt

Cores-SweRV/demo/fpga/synth.sh

@@ -0,0 +1,77 @@
+#!/bin/bash
+
+# if [ $# -ne 1 -o ! -d "$1" ]; then
+# 	echo "Usage: $0 <design>" >&2
+# 	exit 1
+# fi
+
+set -ex
+
+PWD=$(pwd)
+SOC=$PWD/../../soc
+design=${1%/}
+
+YOSYS_COARSE=true
+YOSYS_GLOBRST=false
+YOSYS_SPLITNETS=false
+TOP="soc_top"
+RTL=$(cat ../../soc/soc_top.mk)
+
+rtl_files=""
+for src in $RTL; do
+	rtl_files="$rtl_files $SOC/$src"
+done
+
+mkdir -p gen
+rm -rf gen/*
+mkdir gen/design
+
+BUILD_PATH=gen/ PERLLIB=${SOC} ${SOC}/swerv.config -target=default -set iccm_enable
+
+filelist=""
+for file in $rtl_files; do
+	filelist="$filelist $file"
+done
+sv2v -Igen -I/home/colin/develop/AbstractAccelerator/Cores-SweRV/design/include \
+  gen/common_defines.vh $filelist > gen/soc_top.v
+
+{
+	# echo "read_verilog -sv -Igen/ gen/common_defines.vh"
+  # for file in $rtl_files; do
+	# 	echo "read_verilog -sv -I../../design/include $file"
+	# done
+	echo "read_verilog gen/soc_top.v"
+
+	if test -n "$TOP"; then
+		echo "hierarchy -check -top $TOP"
+	else
+		echo "hierarchy -check"
+	fi
+	if $YOSYS_GLOBRST; then
+		# insertation of global reset (e.g. for FPGA cores)
+		echo "add -global_input globrst 1"
+		echo "proc -global_arst globrst"
+	fi
+	echo "synth -run coarse; opt -fine"
+	# echo "tee -o gen/brams.log memory_bram -rules scripts/brams.txt;;"
+	if ! $YOSYS_COARSE; then
+		echo "memory_map; techmap; opt; abc -dff; clean"
+	fi
+	if $YOSYS_SPLITNETS; then
+		# icarus verilog has a performance problems when there are
+		# dependencies between the bits of a long vector
+		echo "splitnets; clean"
+	fi
+	if $YOSYS_COARSE; then
+		echo "write_verilog -noexpr -noattr gen/synth.v"
+	else
+		echo "select -assert-none t:\$[!_]"
+		echo "write_verilog -noattr gen/synth.v"
+	fi
+	echo "synth_ecp5 -top $TOP -json gen/soc.json"
+	# echo "synth_xilinx -top $TOP"
+} > gen/synth.ys
+
+yosys -v2 -l gen/synth.log gen/synth.ys
+
+nextpnr-ecp5 --25k --package CABGA381 --speed 6 --textcfg soc.cfg --lpf soc.lpf --freq 1  --json gen/soc.json

Cores-SweRV/demo/fpga/test_soc_sim.cpp

@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2019 Western Digital Corporation or its affiliates.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+#include <stdlib.h>
+#include <iostream>
+#include <utility>
+#include <string>
+#include "Vsoc_sim.h"
+#include "verilated.h"
+#include "verilated_vcd_c.h"
+
+
+vluint64_t main_time = 0;
+
+double sc_time_stamp () {
+ return main_time;
+}
+
+
+int main(int argc, char** argv) {
+  std::cout << "\nVerilatorTB: Start of sim\n" << std::endl;
+
+  Verilated::commandArgs(argc, argv);
+
+  Vsoc_sim* soc = new Vsoc_sim;
+
+  // init trace dump
+  VerilatedVcdC* tfp = NULL;
+
+#if VM_TRACE
+  Verilated::traceEverOn(true);
+  tfp = new VerilatedVcdC;
+  soc->trace (tfp, 24);
+  tfp->open ("sim.vcd");
+#endif
+  // Simulate
+  while(!Verilated::gotFinish()){
+#if VM_TRACE
+      tfp->dump (main_time);
+#endif
+      main_time += 5;
+      soc->core_clk = !soc->core_clk;
+      soc->eval();
+  }
+
+#if VM_TRACE
+  tfp->close();
+#endif
+
+  std::cout << "\nVerilatorTB: End of sim" << std::endl;
+  exit(EXIT_SUCCESS);
+
+}

Cores-SweRV/design/lib/beh_lib.sv

@@ -200,7 +200,7 @@ module rvoclkhdr
 
 endmodule
 
-module rvdffe #( parameter WIDTH=1, parameter OVERRIDE=0 )
+module rvdffe #( parameter WIDTH=8, parameter OVERRIDE=0 )
    (
      input  logic [WIDTH-1:0] din,
      input  logic           en,

Cores-SweRV/soc/ahb_sif.sv

@@ -55,7 +55,8 @@ module axi_slv #(
 
   parameter MEM_DEPTH = 15;  // memory size = 0x8000 = 32k
 
-  bit [7:0] mem[bit [MEM_DEPTH-1:0]];
+  bit [7:0] mem[(1<<MEM_DEPTH)-1:0];
+
   bit [63:0] memdata;
 
   wire [MEM_DEPTH-1:0] saraddr = araddr[MEM_DEPTH-1:0];

Cores-SweRV/soc/swerv.config

@@ -860,7 +860,7 @@ our %config = (#{{{
         "clock_period"      => "100",
         "build_ahb_lite"    => "$ahb_lite",       # one and only one bus build arg will ever be defined
         "build_axi4"        => "1",
-        "assert_on"         => "",
+        # "assert_on"         => "",
         "datawidth"         => "64",                        # deprecate this !! FIXME
         "ext_datawidth"     => "64",
         "ext_addrwidth"     => "32",