diff --git a/fpga/blink/.gitignore b/fpga/blink/.gitignore
index b39d90a..9715b96 100644
--- a/fpga/blink/.gitignore
+++ b/fpga/blink/.gitignore
@@ -1,5 +1,5 @@
 *.svf 
 *.bit 
-blink.cfg 
+*.config 
 *.ys 
 *.json
diff --git a/fpga/ram/.gitignore b/fpga/ram/.gitignore
new file mode 100644
index 0000000..9715b96
--- /dev/null
+++ b/fpga/ram/.gitignore
@@ -0,0 +1,5 @@
+*.svf 
+*.bit 
+*.config 
+*.ys 
+*.json
diff --git a/fpga/ram/Makefile b/fpga/ram/Makefile
new file mode 100644
index 0000000..75d4875
--- /dev/null
+++ b/fpga/ram/Makefile
@@ -0,0 +1,25 @@
+TARGET=ram
+
+OBJS+=ram.v
+
+all: ${TARGET}.bit
+
+$(TARGET).json: $(OBJS)
+	yosys -p "read_verilog $(OBJS); synth_ecp5 -top ${TARGET} -json $@"
+
+$(TARGET).config: $(TARGET).json
+	nextpnr-ecp5 --25k --package CABGA381 --speed 6 --json $< --textcfg $@ --lpf $(TARGET).lpf --freq 65
+
+$(TARGET).bit: $(TARGET).config
+	ecppack --svf ${TARGET}.svf $< $@
+
+${TARGET}.svf : ${TARGET}.bit
+
+prog: ${TARGET}.svf
+	# openFPGALoader -c digilent_hs2 $(TARGET).bit
+	./dapprog ${TARGET}.svf 
+
+clean:
+	rm -f *.svf *.bit *.config *.ys *.json
+
+.PHONY: prog clean
diff --git a/fpga/ram/cmsisdap.cfg b/fpga/ram/cmsisdap.cfg
new file mode 100644
index 0000000..44fb6a4
--- /dev/null
+++ b/fpga/ram/cmsisdap.cfg
@@ -0,0 +1,28 @@
+#
+# Buspirate with OpenOCD support
+#
+# http://dangerousprototypes.com/bus-pirate-manual/
+#
+# http://www.fabienm.eu/flf/15-ecp5-board-kit/
+# https://github.com/Martoni/blp/tree/master/platforms/colorlight
+# https://github.com/HarmonInstruments/JTAG_SWD
+
+interface cmsis-dap
+transport select jtag
+
+adapter_khz 10000
+
+#jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043
+
+#LFE5U-25F 0x41111043
+#LFE5U-45F 0x41112043
+jtag newtap ecp5 tap -irlen 8
+
+#init
+#scan_chain
+#
+#svf -tap ecp5.tap -quiet -progress blink.svf
+#exit
+
+# this depends on the cable, you are safe with this option
+#reset_config srst_only
\ No newline at end of file
diff --git a/fpga/ram/dapprog b/fpga/ram/dapprog
new file mode 100755
index 0000000..6565002
--- /dev/null
+++ b/fpga/ram/dapprog
@@ -0,0 +1,54 @@
+#!/bin/bash
+
+if [ ${#1} -eq 0 ]; then
+    echo "usage: dapprog xxx.bit or xxx.svf"
+    exit 0
+fi
+
+CURRENT_DIR=$(cd $(dirname $0); pwd)
+CONFIG=${CURRENT_DIR}/cmsisdap.cfg
+
+if [ "$1" == "--probe" ] || [ "$1" == "-p" ]; then
+    #probe add -d4 for detail log
+    sudo openocd -f ${CONFIG} -c \
+    "   init;
+        scan_chain;
+        exit;
+    "
+    exit $?
+
+else
+    # program 
+    IMAGE_FILE=$1
+    
+    EXT="${IMAGE_FILE##*.}"
+    echo EXT: $EXT
+    
+    #flash write_image erase xxx.hex;
+    #flash write_image erase xxx.bin 0x08000000;
+    
+    if [ "${EXT}" == "svf" ]; then
+        TARGET="$IMAGE_FILE"
+    elif [ "${EXT}" == "bit" ]; then
+        NAME="${IMAGE_FILE%%.bit}"
+        #/home/pi/oss/ulx3s/tools/ujprog/ujprog -j SRAM  ${IMAGE_FILE} > ${NAME}_sram.svf
+        ${CURRENT_DIR}/ujprog.bit2svf -j FLASH ${IMAGE_FILE} > ${NAME}_flash.svf
+        TARGET="${NAME}_flash.svf"
+    else
+        echo "illegal suffix [$EXT]"
+        exit 1
+    fi
+    
+    echo "TARGET: ${TARGET}"
+    
+    sudo openocd -f ${CONFIG} -c \
+    "   init;
+        scan_chain;
+        svf -tap ecp5.tap -quiet -progress ${TARGET};
+        exit;
+    "
+    
+    exit $?
+
+fi
+
diff --git a/fpga/ram/ram.lpf b/fpga/ram/ram.lpf
new file mode 100644
index 0000000..4354bd3
--- /dev/null
+++ b/fpga/ram/ram.lpf
@@ -0,0 +1,8 @@
+LOCATE COMP "clk_i" SITE "P3";
+IOBUF PORT "clk_i" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "clk_i" 25 MHZ;
+
+LOCATE COMP "led_o" SITE "U16";
+
+IOBUF PORT "led_o" IO_TYPE=LVCMOS33;
+
diff --git a/fpga/ram/ram.v b/fpga/ram/ram.v
new file mode 100644
index 0000000..e8edeaa
--- /dev/null
+++ b/fpga/ram/ram.v
@@ -0,0 +1,49 @@
+module ram_single(dataout, addr, datain, we, clk);
+   output[7:0] dataout;
+   input [7:0] datain;
+   input [10:0] addr;
+   input we, clk;
+   reg [7:0] mem [2048:0];
+    always @(posedge clk) begin
+        if (we)
+            mem[addr] <= datain;
+        dataout <= mem[addr];
+   end
+endmodule
+
+module ram (
+    input      clk_i,
+    output reg led_o
+);
+localparam MAX = 2_500_000_0;
+localparam WIDTH = $clog2(MAX);
+
+
+wire[7:0] dataout;
+reg[7:0] datain;
+reg[10:0] addr;
+reg we;
+
+ram_single mem(.dataout(dataout), .addr(addr), .datain(datain), .we(we), .clk(clk_i));
+
+
+wire clk_s;
+assign clk_s = clk_i;
+
+reg  [WIDTH-1:0] cpt_s;
+wire [WIDTH-1:0] cpt_next_s = cpt_s + 1'b1;
+wire             end_s = cpt_s == MAX-1;
+
+wire nextAddr = addr + 1'b1;
+wire dataAdd = dataout + 1'b1;
+ 
+always @(posedge clk_s) begin
+	cpt_s <= cpt_next_s;
+    addr <= nextAddr;
+    datain <= dataAdd;
+
+    led_o <= dataout[0];
+    // if (end_s)
+    //     led_o <= ~led_o;
+end
+endmodule