From 3c50837a75dc7f0e03c2df5e6ece4d5fb9c157cc Mon Sep 17 00:00:00 2001
From: Thomas Wicki <35509028+tmw-wdc@users.noreply.github.com>
Date: Fri, 18 Sep 2020 18:00:45 -0700
Subject: [PATCH] Update release-notes.md

Minor corrections
---
 release-notes.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/release-notes.md b/release-notes.md
index 548d601..efc9f48 100644
--- a/release-notes.md
+++ b/release-notes.md
@@ -1,8 +1,8 @@
 # SweRV RISC-V Core<sup>TM</sup> 1.8 from Western Digital
 ## Release Notes
 
-* Enhanced Debug module to support access to system bus via abstract memory commands (see PRM chapter 9)
-* Enhanced mpmc firmware halt CSR to add atomic MSTATUS.IE enable to mpmc CSR (see PRM section 5.5.1)
+* Enhanced Debug module to support access to system bus via access memory abstract commands (see PRM chapter 9)
+* Enhanced mpmc firmware halt CSR to add atomic MSTATUS.MIE enable to mpmc CSR (see PRM section 5.5.1)
 * Fixed 3 debug module issues reported by Codasip
 * Fixed bug with IO load speculation
 * Fixed issue with PIC ld/st access following a pipe freeze