add jtag demo for GDB which openocd
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@ -1,6 +1,6 @@
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export RV_ROOT = ${PWD}/../..
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LLVMINSTALL = /home/colin/develop/llvm-build/install
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GCC_PREFIX = /opt/riscv/bin/riscv64-unknown-elf
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GCC_PREFIX = /opt/riscv/bin/riscv32-unknown-elf
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GDB_PREFIX = /opt/riscv/bin/riscv32-unknown-elf-gdb
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TEST_CFLAGS = -g -O3 -funroll-all-loops
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@ -8,7 +8,6 @@ ABI = -mabi=ilp32 -march=rv32imc
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DEMODIR = ${PWD}
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BUILD_DIR = ${DEMODIR}/build
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RV_DESIGN = ${RV_ROOT}/design
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RV_SOC = ${RV_ROOT}/soc
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TEST = jtag
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@ -64,10 +63,16 @@ program.hex: $(TEST).o $(LINK)
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@echo Completed building $(TEST)
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%.o : %.s swerv_define
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$(GCC_PREFIX)-cpp -I${BUILD_DIR} $< > $(BUILD_DIR)/$*.cpp.s
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$(GCC_PREFIX)-as $(ABI) $(BUILD_DIR)/$*.cpp.s -o $(BUILD_DIR)/$@
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$(GCC_PREFIX)-cpp -g -I${BUILD_DIR} $< > $(BUILD_DIR)/$*.cpp.s
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$(GCC_PREFIX)-as -g $(ABI) $(BUILD_DIR)/$*.cpp.s -o $(BUILD_DIR)/$@
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##################### llvm hex Build #####################################
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##################### openocd #####################################
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openocd:
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openocd -f swerv.cfg
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gdb:
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$(GDB_PREFIX) -x gdbinit ./build/jtag.bin
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help:
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@echo Possible targets: verilator help clean all verilator-build program.hex
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@ -0,0 +1,2 @@
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target remote :3333
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set remotetimeout 2000
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@ -60,17 +60,18 @@ loop2:
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lb x5, 0(x4)
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sb x5, 0(x3)
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addi x4, x4, 1
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bnez x5, loop2
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# bnez x5, loop2
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beq x0, x0, loop2
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// Write 0xff to STDOUT for TB to terminate test.
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_finish:
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li x3, STDOUT
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addi x5, x0, 0xff
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sb x5, 0(x3)
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beq x0, x0, _finish
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.rept 100
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nop
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.endr
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# _finish:
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# li x3, STDOUT
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# addi x5, x0, 0xff
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# sb x5, 0(x3)
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# beq x0, x0, _finish
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# .rept 100
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# nop
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# .endr
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.global hw_data
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.data
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@ -0,0 +1,27 @@
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# jtag simulation
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## install openocd
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```shell
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git clone https://github.com/riscv/riscv-openocd.git
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cd riscv-openocd
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./bootstrap
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./configure --prefix=$RISCV --enable-remote-bitbang --enable-jtag_vpi --enable-ftdi --enable-jlink
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make
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sudo make install
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```
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## start openocd
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`openocd -d -f swerv.cfg`
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## start gdb
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`/opt/riscv/bin/riscv32-unknown-elf-gdb -ex "target extended-remote :3333"`
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## quick start
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At demo/jtag/
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1. `make all`
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2. `make openocd`
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3. `make gdb`
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@ -0,0 +1,34 @@
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# "JTAG adapter" for simulation, exposed to OpenOCD through a TCP socket
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# speaking the remote_bitbang protocol. The adapter is implemented as
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# SystemVerilog DPI module.
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adapter driver remote_bitbang
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remote_bitbang host localhost
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remote_bitbang port 44853
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# Target configuration for the riscv chip
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set _CHIPNAME riscv
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set _TARGETNAME $_CHIPNAME.cpu
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jtag newtap $_CHIPNAME tap -irlen 5 -expected-id 0x01
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set _TARGETNAME $_CHIPNAME.tap
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target create $_TARGETNAME riscv -chain-position $_TARGETNAME
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# Configure work area in on-chip SRAM
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# $_TARGETNAME configure -work-area-phys 0x1000e000 -work-area-size 1000 -work-area-backup 0
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riscv expose_csrs 1988
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# Be verbose about GDB errors
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gdb_report_data_abort enable
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gdb_report_register_access_error enable
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# Increase timeouts in simulation
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riscv set_command_timeout_sec 1200
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# Conclude OpenOCD configuration
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init
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# Halt the target
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halt
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@ -21,7 +21,7 @@
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/**
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* Simple buffer for passing data between TCP sockets and DPI modules
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*/
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const int BUFSIZE_BYTE = 256;
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const int BUFSIZE_BYTE = 25600;
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struct tcp_buf {
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unsigned int rptr;
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@ -77,11 +77,11 @@ module soc_top;
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logic [1:0] dec_tlu_perfcnt2;
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logic [1:0] dec_tlu_perfcnt3;
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logic jtag_tdo;
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logic jtag_tck;
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logic jtag_tms;
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logic jtag_tdi;
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logic jtag_trst_n;
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wire jtag_tdo;
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wire jtag_tck;
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wire jtag_tms;
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wire jtag_tdi;
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wire jtag_trst_n;
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logic o_cpu_halt_ack;
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logic o_cpu_halt_status;
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@ -324,7 +324,7 @@ module soc_top;
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assign WriteData = lmem.WriteData;
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assign mailbox_data_val = WriteData[7:0] > 8'h5 && WriteData[7:0] < 8'h7f;
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parameter MAX_CYCLES = 10_000_000;
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parameter MAX_CYCLES = 10_000_000_0;
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integer fd, tp, el;
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