add jtag demo for GDB which openocd

demo/jtag/Makefile

@@ -1,6 +1,6 @@
 export RV_ROOT = ${PWD}/../..
-LLVMINSTALL = /home/colin/develop/llvm-build/install
+GCC_PREFIX = /opt/riscv/bin/riscv32-unknown-elf
-GCC_PREFIX = /opt/riscv/bin/riscv64-unknown-elf
+GDB_PREFIX = /opt/riscv/bin/riscv32-unknown-elf-gdb
 
 
 TEST_CFLAGS = -g -O3 -funroll-all-loops
@@ -8,7 +8,6 @@ ABI = -mabi=ilp32 -march=rv32imc
 
 DEMODIR = ${PWD}
 BUILD_DIR = ${DEMODIR}/build
-RV_DESIGN = ${RV_ROOT}/design
 RV_SOC = ${RV_ROOT}/soc
 
 TEST = jtag
@@ -64,10 +63,16 @@ program.hex: $(TEST).o $(LINK)
 	@echo Completed building $(TEST)
 
 %.o : %.s swerv_define
-	$(GCC_PREFIX)-cpp -I${BUILD_DIR}  $<  > $(BUILD_DIR)/$*.cpp.s
+	$(GCC_PREFIX)-cpp -g -I${BUILD_DIR}  $<  > $(BUILD_DIR)/$*.cpp.s
-	$(GCC_PREFIX)-as $(ABI) $(BUILD_DIR)/$*.cpp.s -o $(BUILD_DIR)/$@
+	$(GCC_PREFIX)-as -g $(ABI) $(BUILD_DIR)/$*.cpp.s -o $(BUILD_DIR)/$@
 
-##################### llvm hex Build #####################################
+##################### openocd #####################################
+
+openocd:
+	openocd -f swerv.cfg
+
+gdb:
+	$(GDB_PREFIX) -x gdbinit ./build/jtag.bin
 
 help:
 	@echo Possible targets: verilator help clean all verilator-build program.hex

demo/jtag/gdbinit

@@ -0,0 +1,2 @@
+target remote :3333
+set remotetimeout 2000

demo/jtag/jtag.s

@@ -60,17 +60,18 @@ loop2:
    lb x5, 0(x4)
    sb x5, 0(x3)
    addi x4, x4, 1
-   bnez x5, loop2
+#    bnez x5, loop2
+   beq x0, x0, loop2
 
 // Write 0xff to STDOUT for TB to terminate test.
-_finish:
+# _finish:
-    li x3, STDOUT
+#     li x3, STDOUT
-    addi x5, x0, 0xff
+#     addi x5, x0, 0xff
-    sb x5, 0(x3)
+#     sb x5, 0(x3)
-    beq x0, x0, _finish
+#     beq x0, x0, _finish
-.rept 100
+# .rept 100
-    nop
+#     nop
-.endr
+# .endr
 
 .global hw_data
 .data

demo/jtag/readmd.md

@@ -0,0 +1,27 @@
+# jtag simulation
+
+## install openocd
+
+```shell
+git clone https://github.com/riscv/riscv-openocd.git
+cd riscv-openocd
+./bootstrap
+./configure --prefix=$RISCV --enable-remote-bitbang --enable-jtag_vpi --enable-ftdi --enable-jlink
+make
+sudo make install
+```
+## start openocd
+
+`openocd -d -f swerv.cfg`
+
+## start gdb
+
+`/opt/riscv/bin/riscv32-unknown-elf-gdb -ex "target extended-remote :3333"`
+
+## quick start
+
+At demo/jtag/  
+
+1. `make all`  
+2. `make openocd` 
+3. `make gdb`

demo/jtag/swerv.cfg

@@ -0,0 +1,34 @@
+# "JTAG adapter" for simulation, exposed to OpenOCD through a TCP socket 
+# speaking the remote_bitbang protocol. The adapter is implemented as 
+# SystemVerilog DPI module.
+
+adapter driver remote_bitbang
+remote_bitbang host localhost
+remote_bitbang port 44853
+
+# Target configuration for the riscv chip
+
+set  _CHIPNAME riscv
+set _TARGETNAME $_CHIPNAME.cpu
+
+jtag newtap $_CHIPNAME tap -irlen 5 -expected-id 0x01
+set _TARGETNAME $_CHIPNAME.tap
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME 
+
+# Configure work area in on-chip SRAM
+# $_TARGETNAME configure -work-area-phys 0x1000e000 -work-area-size 1000 -work-area-backup 0
+
+riscv expose_csrs 1988
+
+# Be verbose about GDB errors
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+# Increase timeouts in simulation
+riscv set_command_timeout_sec 1200
+
+# Conclude OpenOCD configuration
+init
+
+# Halt the target
+halt

soc/dpi/common/tcp_server.c

@@ -21,7 +21,7 @@
 /**
  * Simple buffer for passing data between TCP sockets and DPI modules
  */
-const int BUFSIZE_BYTE = 256;
+const int BUFSIZE_BYTE = 25600;
 
 struct tcp_buf {
   unsigned int rptr;

soc/soc_top.sv

@@ -77,11 +77,11 @@ module soc_top;
     logic        [1:0]          dec_tlu_perfcnt2;
     logic        [1:0]          dec_tlu_perfcnt3;
 
-    logic                       jtag_tdo;
+    wire                        jtag_tdo;
-    logic                       jtag_tck;
+    wire                        jtag_tck;
-    logic                       jtag_tms;
+    wire                        jtag_tms;
-    logic                       jtag_tdi;
+    wire                        jtag_tdi;
-    logic                       jtag_trst_n;
+    wire                        jtag_trst_n;
 
     logic                       o_cpu_halt_ack;
     logic                       o_cpu_halt_status;
@@ -324,7 +324,7 @@ module soc_top;
     assign WriteData = lmem.WriteData;
     assign mailbox_data_val = WriteData[7:0] > 8'h5 && WriteData[7:0] < 8'h7f;
 
-    parameter MAX_CYCLES = 10_000_000;
+    parameter MAX_CYCLES = 10_000_000_0;
 
     integer fd, tp, el;