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Switch mem bus from ahb to axi.

This commit is contained in:
colin 2022-02-17 11:35:01 +00:00
parent cffec82632
commit 3edc87e0ea
8 changed files with 821 additions and 417 deletions
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2
Cores-SweRV/demo/helloworld/Makefile
View File

@ -29,7 +29,7 @@ clean:
rm -rf build obj_dir
swerv_define :
BUILD_PATH=${BUILD_DIR} PERLLIB=${RV_SOC} ${RV_SOC}/swerv.config -target=default_ahb -set iccm_enable
BUILD_PATH=${BUILD_DIR} PERLLIB=${RV_SOC} ${RV_SOC}/swerv.config -target=default -set iccm_enable
##################### Verilog Builds #####################################

2
Cores-SweRV/demo/jtag/Makefile
View File

@ -32,7 +32,7 @@ clean:
rm -rf build obj_dir
swerv_define :
BUILD_PATH=${BUILD_DIR} PERLLIB=${RV_SOC} ${RV_SOC}/swerv.config -target=default_ahb -set iccm_enable
BUILD_PATH=${BUILD_DIR} PERLLIB=${RV_SOC} ${RV_SOC}/swerv.config -target=default -set iccm_enable
##################### Verilog Builds #####################################

187
Cores-SweRV/soc/ahb_sif.sv
View File

@ -13,120 +13,97 @@
// See the License for the specific language governing permissions and
// limitations under the License.
//
`ifdef RV_BUILD_AHB_LITE
module ahb_sif (
input logic [63:0] HWDATA,
input logic HCLK,
input logic HSEL,
input logic [3:0] HPROT,
input logic HWRITE,
input logic [1:0] HTRANS,
input logic [2:0] HSIZE,
input logic HREADY,
input logic HRESETn,
input logic [31:0] HADDR,
input logic [2:0] HBURST,
module axi_slv #(
TAGW = 1
) (
input aclk,
input rst_l,
input arvalid,
output reg arready,
input [ 31:0] araddr,
input [TAGW-1:0] arid,
input [ 7:0] arlen,
input [ 1:0] arburst,
input [ 2:0] arsize,
output logic HREADYOUT,
output logic HRESP,
output logic [63:0] HRDATA
output reg rvalid,
input rready,
output reg [ 63:0] rdata,
output reg [ 1:0] rresp,
output reg [TAGW-1:0] rid,
output rlast,
input awvalid,
output awready,
input [ 31:0] awaddr,
input [TAGW-1:0] awid,
input [ 7:0] awlen,
input [ 1:0] awburst,
input [ 2:0] awsize,
input [63:0] wdata,
input [ 7:0] wstrb,
input wvalid,
output wready,
output reg bvalid,
input bready,
output reg [ 1:0] bresp,
output reg [TAGW-1:0] bid
);
// `define RV_ICCM_SADR 32'hee000000
// `define RV_DCCM_SADR 32'hf0040000
parameter OFFSET_ADDR = 32'h00000000;
parameter MEM_DEPTH = 15; // memory size = 0x8000 = 32k
parameter MEM_DEPTH = 15; // memory size = 0x8000 = 32k
logic write;
logic [31:0] laddr, addr;
logic [7:0] strb_lat;
logic [63:0] rdata;
bit [7:0] mem[bit [MEM_DEPTH-1:0]];
bit [63:0] memdata;
bit [7:0] mem [bit[MEM_DEPTH-1:0]];
bit [7:0] wscnt;
int dws = 0;
int iws = 0;
bit dws_rand;
bit iws_rand;
bit ok;
wire [MEM_DEPTH-1:0] saraddr = araddr[MEM_DEPTH-1:0];
wire [MEM_DEPTH-1:0] sawaddr = awaddr[MEM_DEPTH-1:0];
wire [7:0] strb = HSIZE == 3'b000 ? 8'h1 << HADDR[2:0] :
HSIZE == 3'b001 ? 8'h3 << {HADDR[2:1],1'b0} :
HSIZE == 3'b010 ? 8'hf << {HADDR[2],2'b0} : 8'hff;
wire [31:0] RDDR = HADDR - OFFSET_ADDR;
initial begin
if ($value$plusargs("iws=%d", iws));
if ($value$plusargs("dws=%d", dws));
dws_rand = dws < 0;
iws_rand = iws < 0;
end
always @ (negedge HCLK ) begin
if(HREADY)
addr = RDDR;
if (write & HREADY) begin
if(strb_lat[7]) mem[{laddr[MEM_DEPTH-1:3],3'd7}] = HWDATA[63:56];
if(strb_lat[6]) mem[{laddr[MEM_DEPTH-1:3],3'd6}] = HWDATA[55:48];
if(strb_lat[5]) mem[{laddr[MEM_DEPTH-1:3],3'd5}] = HWDATA[47:40];
if(strb_lat[4]) mem[{laddr[MEM_DEPTH-1:3],3'd4}] = HWDATA[39:32];
if(strb_lat[3]) mem[{laddr[MEM_DEPTH-1:3],3'd3}] = HWDATA[31:24];
if(strb_lat[2]) mem[{laddr[MEM_DEPTH-1:3],3'd2}] = HWDATA[23:16];
if(strb_lat[1]) mem[{laddr[MEM_DEPTH-1:3],3'd1}] = HWDATA[15:08];
if(strb_lat[0]) mem[{laddr[MEM_DEPTH-1:3],3'd0}] = HWDATA[07:00];
end
if(HREADY & HSEL & |HTRANS) begin
`ifdef VERILATOR
if(iws_rand & ~HPROT[0])
iws = $random & 15;
if(dws_rand & HPROT[0])
dws = $random & 15;
`else
if(iws_rand & ~HPROT[0])
ok = std::randomize(iws) with {iws dist {0:=10, [1:3]:/2, [4:15]:/1};};
if(dws_rand & HPROT[0])
ok = std::randomize(dws) with {dws dist {0:=10, [1:3]:/2, [4:15]:/1};};
`endif
end
end
assign HRDATA = HREADY ? rdata : ~rdata;
assign HREADYOUT = wscnt == 0;
assign HRESP = 0;
always @(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) begin
laddr <= 32'b0;
write <= 1'b0;
rdata <= '0;
wscnt <= 0;
end
else begin
if(HREADY & HSEL) begin
laddr <= RDDR;
write <= HWRITE & |HTRANS;
if(|HTRANS & ~HWRITE)
rdata <= {mem[{addr[MEM_DEPTH-1:3],3'd7}],
mem[{addr[MEM_DEPTH-1:3],3'd6}],
mem[{addr[MEM_DEPTH-1:3],3'd5}],
mem[{addr[MEM_DEPTH-1:3],3'd4}],
mem[{addr[MEM_DEPTH-1:3],3'd3}],
mem[{addr[MEM_DEPTH-1:3],3'd2}],
mem[{addr[MEM_DEPTH-1:3],3'd1}],
mem[{addr[MEM_DEPTH-1:3],3'd0}]};
strb_lat <= strb;
always @(posedge aclk or negedge rst_l) begin
if (!rst_l) begin
rvalid <= 0;
bvalid <= 0;
end else begin
bid <= awid;
rid <= arid;
rvalid <= arvalid;
bvalid <= awvalid;
rdata <= memdata;
end
end
if(HREADY & HSEL & |HTRANS)
wscnt <= HPROT[0] ? dws[7:0] : iws[7:0];
else if(wscnt != 0)
wscnt <= wscnt-1;
end
always @(negedge aclk) begin
if (arvalid)
memdata <= {
mem[saraddr+7],
mem[saraddr+6],
mem[saraddr+5],
mem[saraddr+4],
mem[saraddr+3],
mem[saraddr+2],
mem[saraddr+1],
mem[saraddr]
};
if (awvalid) begin
if (wstrb[7]) mem[sawaddr+7] = wdata[63:56];
if (wstrb[6]) mem[sawaddr+6] = wdata[55:48];
if (wstrb[5]) mem[sawaddr+5] = wdata[47:40];
if (wstrb[4]) mem[sawaddr+4] = wdata[39:32];
if (wstrb[3]) mem[sawaddr+3] = wdata[31:24];
if (wstrb[2]) mem[sawaddr+2] = wdata[23:16];
if (wstrb[1]) mem[sawaddr+1] = wdata[15:08];
if (wstrb[0]) mem[sawaddr+0] = wdata[07:00];
end
end
assign arready = 1'b1;
assign awready = 1'b1;
assign wready = 1'b1;
assign rresp = 2'b0;
assign bresp = 2'b0;
assign rlast = 1'b1;
endmodule
`endif

259
Cores-SweRV/soc/axi_lsu_dma_bridge.sv
View File

@ -1,199 +1,194 @@
// connects LSI master to external AXI slave and DMA slave
module axi_lsu_dma_bridge
#(
parameter M_ID_WIDTH = 8,
parameter S0_ID_WIDTH = 8
)
(
input clk,
input reset_l,
module axi_lsu_dma_bridge #(
parameter M_ID_WIDTH = 8,
parameter S0_ID_WIDTH = 8
) (
input clk,
input reset_l,
// master read bus
input m_arvalid,
input [M_ID_WIDTH-1:0] m_arid,
input[31:0] m_araddr,
output m_arready,
// master read bus
input m_arvalid,
input [M_ID_WIDTH-1:0] m_arid,
input [ 31:0] m_araddr,
output m_arready,
output m_rvalid,
input m_rready,
output [63:0] m_rdata,
output [M_ID_WIDTH-1:0] m_rid,
output [1:0] m_rresp,
output m_rlast,
output m_rvalid,
input m_rready,
output [ 63:0] m_rdata,
output [M_ID_WIDTH-1:0] m_rid,
output [ 1:0] m_rresp,
output m_rlast,
// master write bus
input m_awvalid,
input [M_ID_WIDTH-1:0] m_awid,
input[31:0] m_awaddr,
output m_awready,
// master write bus
input m_awvalid,
input [M_ID_WIDTH-1:0] m_awid,
input [ 31:0] m_awaddr,
output m_awready,
input m_wvalid,
output m_wready,
input m_wvalid,
output m_wready,
output[1:0] m_bresp,
output m_bvalid,
output[M_ID_WIDTH-1:0] m_bid,
input m_bready,
output [ 1:0] m_bresp,
output m_bvalid,
output [M_ID_WIDTH-1:0] m_bid,
input m_bready,
// slave 0 if general ext memory
output s0_arvalid,
input s0_arready,
// slave 0 if general ext memory
output s0_arvalid,
input s0_arready,
input s0_rvalid,
input[S0_ID_WIDTH-1:0] s0_rid,
input[1:0] s0_rresp,
input[63:0] s0_rdata,
input s0_rlast,
output s0_rready,
input s0_rvalid,
input [S0_ID_WIDTH-1:0] s0_rid,
input [ 1:0] s0_rresp,
input [ 63:0] s0_rdata,
input s0_rlast,
output s0_rready,
output s0_awvalid,
input s0_awready,
output s0_awvalid,
input s0_awready,
output s0_wvalid,
input s0_wready,
output s0_wvalid,
input s0_wready,
input[1:0] s0_bresp,
input s0_bvalid,
input[S0_ID_WIDTH-1:0] s0_bid,
output s0_bready,
input [ 1:0] s0_bresp,
input s0_bvalid,
input [S0_ID_WIDTH-1:0] s0_bid,
output s0_bready,
// slave 1 if DMA port
output s1_arvalid,
input s1_arready,
// slave 1 if DMA port
output s1_arvalid,
input s1_arready,
input s1_rvalid,
input[1:0] s1_rresp,
input[63:0] s1_rdata,
input s1_rlast,
output s1_rready,
input s1_rvalid,
input [ 1:0] s1_rresp,
input [63:0] s1_rdata,
input s1_rlast,
output s1_rready,
output s1_awvalid,
input s1_awready,
output s1_awvalid,
input s1_awready,
output s1_wvalid,
input s1_wready,
output s1_wvalid,
input s1_wready,
input[1:0] s1_bresp,
input s1_bvalid,
output s1_bready
input [1:0] s1_bresp,
input s1_bvalid,
output s1_bready
);
parameter ICCM_BASE = `RV_ICCM_BITS; // in LSBs
localparam IDFIFOSZ = $clog2(`RV_DMA_BUF_DEPTH);
bit[31:0] iccm_real_base_addr = `RV_ICCM_SADR ;
parameter ICCM_BASE = `RV_ICCM_BITS; // in LSBs
localparam IDFIFOSZ = $clog2(`RV_DMA_BUF_DEPTH);
bit [31:0] iccm_real_base_addr = `RV_ICCM_SADR;
wire ar_slave_select;
wire aw_slave_select;
wire w_slave_select;
wire ar_slave_select;
wire aw_slave_select;
wire w_slave_select;
wire rresp_select;
wire bresp_select;
wire ar_iccm_select;
wire aw_iccm_select;
wire rresp_select;
wire bresp_select;
wire ar_iccm_select;
wire aw_iccm_select;
reg [1:0] wsel_iptr, wsel_optr;
reg [2:0] wsel_count;
reg [3:0] wsel;
reg [1:0] wsel_iptr, wsel_optr;
reg [2:0] wsel_count;
reg [3:0] wsel;
reg [M_ID_WIDTH-1:0] arid [1<<IDFIFOSZ];
reg [M_ID_WIDTH-1:0] awid [1<<IDFIFOSZ];
reg [IDFIFOSZ-1:0] arid_cnt;
reg [IDFIFOSZ-1:0] awid_cnt;
reg [IDFIFOSZ-1:0] rid_cnt;
reg [IDFIFOSZ-1:0] bid_cnt;
reg [M_ID_WIDTH-1:0] arid[1<<IDFIFOSZ];
reg [M_ID_WIDTH-1:0] awid[1<<IDFIFOSZ];
reg [IDFIFOSZ-1:0] arid_cnt;
reg [IDFIFOSZ-1:0] awid_cnt;
reg [IDFIFOSZ-1:0] rid_cnt;
reg [IDFIFOSZ-1:0] bid_cnt;
// 1 select slave 1; 0 - slave 0
assign ar_slave_select = ar_iccm_select;
assign aw_slave_select = aw_iccm_select;
// 1 select slave 1; 0 - slave 0
assign ar_slave_select = ar_iccm_select;
assign aw_slave_select = aw_iccm_select;
assign ar_iccm_select = m_araddr[31:ICCM_BASE] == iccm_real_base_addr[31:ICCM_BASE];
assign aw_iccm_select = m_awaddr[31:ICCM_BASE] == iccm_real_base_addr[31:ICCM_BASE];
assign ar_iccm_select = m_araddr[31:ICCM_BASE] == iccm_real_base_addr[31:ICCM_BASE];
assign aw_iccm_select = m_awaddr[31:ICCM_BASE] == iccm_real_base_addr[31:ICCM_BASE];
assign s0_arvalid = m_arvalid & ~ar_slave_select;
assign s1_arvalid = m_arvalid & ar_slave_select;
assign m_arready = ar_slave_select ? s1_arready : s0_arready;
assign s0_arvalid = m_arvalid & ~ar_slave_select;
assign s1_arvalid = m_arvalid & ar_slave_select;
assign m_arready = ar_slave_select ? s1_arready : s0_arready;
assign s0_awvalid = m_awvalid & ~aw_slave_select;
assign s1_awvalid = m_awvalid & aw_slave_select;
assign m_awready = aw_slave_select ? s1_awready : s0_awready;
assign s0_awvalid = m_awvalid & ~aw_slave_select;
assign s1_awvalid = m_awvalid & aw_slave_select;
assign m_awready = aw_slave_select ? s1_awready : s0_awready;
assign s0_wvalid = m_wvalid & ~w_slave_select;
assign s1_wvalid = m_wvalid & w_slave_select;
assign m_wready = w_slave_select ? s1_wready : s0_wready;
assign w_slave_select = (wsel_count == 0 || wsel_count[2]) ? aw_slave_select : wsel[wsel_optr];
assign s0_wvalid = m_wvalid & ~w_slave_select;
assign s1_wvalid = m_wvalid & w_slave_select;
assign m_wready = w_slave_select ? s1_wready : s0_wready;
assign w_slave_select = (wsel_count == 0 || wsel_count[2]) ? aw_slave_select : wsel[wsel_optr];
assign m_rvalid = s0_rvalid | s1_rvalid;
assign s0_rready = m_rready & ~rresp_select;
assign s1_rready = m_rready & rresp_select;
assign m_rdata = rresp_select ? s1_rdata : s0_rdata;
assign m_rresp = rresp_select ? s1_rresp : s0_rresp;
assign m_rid = rresp_select ? arid[rid_cnt] : s0_rid;
assign m_rlast = rresp_select ? s1_rlast : s0_rlast;
assign m_rvalid = s0_rvalid | s1_rvalid;
assign s0_rready = m_rready & ~rresp_select;
assign s1_rready = m_rready & rresp_select;
assign m_rdata = rresp_select ? s1_rdata : s0_rdata;
assign m_rresp = rresp_select ? s1_rresp : s0_rresp;
assign m_rid = rresp_select ? arid[rid_cnt] : s0_rid;
assign m_rlast = rresp_select ? s1_rlast : s0_rlast;
assign rresp_select = s1_rvalid & ~s0_rvalid;
assign rresp_select = s1_rvalid & ~s0_rvalid;
assign m_bvalid = s0_bvalid | s1_bvalid;
assign s0_bready = m_bready & ~bresp_select;
assign s1_bready = m_bready & bresp_select;
assign m_bid = bresp_select ? awid[bid_cnt] : s0_bid;
assign m_bresp = bresp_select ? s1_bresp : s0_bresp;
assign m_bvalid = s0_bvalid | s1_bvalid;
assign s0_bready = m_bready & ~bresp_select;
assign s1_bready = m_bready & bresp_select;
assign m_bid = bresp_select ? awid[bid_cnt] : s0_bid;
assign m_bresp = bresp_select ? s1_bresp : s0_bresp;
assign bresp_select = s1_bvalid & ~s0_bvalid;
assign bresp_select = s1_bvalid & ~s0_bvalid;
// W-channel select fifo
always @ (posedge clk or negedge reset_l)
if(!reset_l) begin
// W-channel select fifo
always @(posedge clk or negedge reset_l)
if (!reset_l) begin
wsel_count <= '0;
wsel_iptr <= '0;
wsel_optr <= '0;
end
else begin
if(m_awvalid & m_awready) begin
end else begin
if (m_awvalid & m_awready) begin
wsel[wsel_iptr] <= aw_slave_select;
if(!(m_wready & m_wvalid )) wsel_count <= wsel_count + 1;
if (!(m_wready & m_wvalid)) wsel_count <= wsel_count + 1;
wsel_iptr <= wsel_iptr + 1;
end
if(m_wvalid & m_wready) begin
if(!(m_awready & m_awvalid ) ) wsel_count <= wsel_count - 1;
if (m_wvalid & m_wready) begin
if (!(m_awready & m_awvalid)) wsel_count <= wsel_count - 1;
wsel_optr <= wsel_optr + 1;
end
end
// id replacement for narrow ID slave
always @ (posedge clk or negedge reset_l)
if(!reset_l) begin
// id replacement for narrow ID slave
always @(posedge clk or negedge reset_l)
if (!reset_l) begin
arid_cnt <= '0;
rid_cnt <= '0;
end
else begin
if(ar_slave_select & m_arready & m_arvalid) begin
end else begin
if (ar_slave_select & m_arready & m_arvalid) begin
arid[arid_cnt] <= m_arid;
arid_cnt <= arid_cnt + 1;
end
if(rresp_select & m_rready & m_rvalid) begin
if (rresp_select & m_rready & m_rvalid) begin
rid_cnt <= rid_cnt + 1;
end
end
always @ (posedge clk or negedge reset_l)
if(!reset_l) begin
always @(posedge clk or negedge reset_l)
if (!reset_l) begin
awid_cnt <= '0;
bid_cnt <= '0;
end
else begin
if(aw_slave_select & m_awready & m_awvalid) begin
end else begin
if (aw_slave_select & m_awready & m_awvalid) begin
awid[awid_cnt] <= m_awid;
awid_cnt <= awid_cnt + 1;
end
if(bresp_select & m_bready & m_bvalid) begin
if (bresp_select & m_bready & m_bvalid) begin
bid_cnt <= bid_cnt + 1;
end
end

4
Cores-SweRV/soc/soc_sim.sv
View File

@ -38,13 +38,13 @@ module soc_sim (
wire [63:0] WriteData;
string abi_reg [ 32]; // ABI register names
assign WriteData = rvsoc.lsu_hwdata;
assign WriteData = rvsoc.lsu_axi_wdata;
assign mailbox_data_val = WriteData[7:0] > 8'h5 && WriteData[7:0] < 8'h7f;
parameter MAILBOX_ADDR = 32'hD0580000;
logic write;
logic [31:0] laddr;
wire mailbox_write = write && laddr == MAILBOX_ADDR;
wire mailbox_write = rvsoc.lmem_axi_awvalid && rvsoc.lsu_axi_awaddr == MAILBOX_ADDR && rst_l;
always @(posedge core_clk or negedge rst_l) begin
if (~rst_l) begin
laddr <= 32'b0;

1
Cores-SweRV/soc/soc_top.mk
View File

@ -44,4 +44,5 @@
../design/lib/axi4_to_ahb.sv
./ahb_sif.sv
./axi_lsu_dma_bridge.sv
./soc_top.sv

643
Cores-SweRV/soc/soc_top.sv
View File

@ -27,34 +27,34 @@ module soc_top (
logic nmi_int;
logic [31:0] reset_vector;
logic [31:0] nmi_vector;
logic [31:1] jtag_id;
logic [ 31:0] reset_vector;
logic [ 31:0] nmi_vector;
logic [ 31:1] jtag_id;
logic [31:0] ic_haddr;
logic [ 31:0] ic_haddr;
logic [ 2:0] ic_hburst;
logic ic_hmastlock;
logic [ 3:0] ic_hprot;
logic [ 2:0] ic_hsize;
logic [ 1:0] ic_htrans;
logic ic_hwrite;
logic [63:0] ic_hrdata;
logic [ 63:0] ic_hrdata;
logic ic_hready;
logic ic_hresp;
logic [31:0] lsu_haddr;
logic [ 31:0] lsu_haddr;
logic [ 2:0] lsu_hburst;
logic lsu_hmastlock;
logic [ 3:0] lsu_hprot;
logic [ 2:0] lsu_hsize;
logic [ 1:0] lsu_htrans;
logic lsu_hwrite;
logic [63:0] lsu_hrdata;
logic [63:0] lsu_hwdata;
logic [ 63:0] lsu_hrdata;
logic [ 63:0] lsu_hwdata;
logic lsu_hready;
logic lsu_hresp;
logic [31:0] sb_haddr;
logic [ 31:0] sb_haddr;
logic [ 2:0] sb_hburst;
logic sb_hmastlock;
logic [ 3:0] sb_hprot;
@ -62,18 +62,18 @@ module soc_top (
logic [ 1:0] sb_htrans;
logic sb_hwrite;
logic [63:0] sb_hrdata;
logic [63:0] sb_hwdata;
logic [ 63:0] sb_hrdata;
logic [ 63:0] sb_hwdata;
logic sb_hready;
logic sb_hresp;
logic [63:0] trace_rv_i_insn_ip;
logic [63:0] trace_rv_i_address_ip;
logic [ 63:0] trace_rv_i_insn_ip;
logic [ 63:0] trace_rv_i_address_ip;
logic [ 2:0] trace_rv_i_valid_ip;
logic [ 2:0] trace_rv_i_exception_ip;
logic [ 4:0] trace_rv_i_ecause_ip;
logic [ 2:0] trace_rv_i_interrupt_ip;
logic [31:0] trace_rv_i_tval_ip;
logic [ 31:0] trace_rv_i_tval_ip;
logic o_debug_mode_status;
logic [ 1:0] dec_tlu_perfcnt0;
@ -86,8 +86,8 @@ module soc_top (
logic o_cpu_run_ack;
logic mailbox_write;
logic [63:0] dma_hrdata;
logic [63:0] dma_hwdata;
logic [ 63:0] dma_hrdata;
logic [ 63:0] dma_hwdata;
logic dma_hready;
logic dma_hresp;
@ -100,6 +100,210 @@ module soc_top (
wire dma_hready_out;
//-------------------------- LSU AXI signals--------------------------
// AXI Write Channels
wire lsu_axi_awvalid;
wire lsu_axi_awready;
wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_awid;
wire [ 31:0] lsu_axi_awaddr;
wire [ 3:0] lsu_axi_awregion;
wire [ 7:0] lsu_axi_awlen;
wire [ 2:0] lsu_axi_awsize;
wire [ 1:0] lsu_axi_awburst;
wire lsu_axi_awlock;
wire [ 3:0] lsu_axi_awcache;
wire [ 2:0] lsu_axi_awprot;
wire [ 3:0] lsu_axi_awqos;
wire lsu_axi_wvalid;
wire lsu_axi_wready;
wire [ 63:0] lsu_axi_wdata;
wire [ 7:0] lsu_axi_wstrb;
wire lsu_axi_wlast;
wire lsu_axi_bvalid;
wire lsu_axi_bready;
wire [ 1:0] lsu_axi_bresp;
wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_bid;
// AXI Read Channels
wire lsu_axi_arvalid;
wire lsu_axi_arready;
wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_arid;
wire [ 31:0] lsu_axi_araddr;
wire [ 3:0] lsu_axi_arregion;
wire [ 7:0] lsu_axi_arlen;
wire [ 2:0] lsu_axi_arsize;
wire [ 1:0] lsu_axi_arburst;
wire lsu_axi_arlock;
wire [ 3:0] lsu_axi_arcache;
wire [ 2:0] lsu_axi_arprot;
wire [ 3:0] lsu_axi_arqos;
wire lsu_axi_rvalid;
wire lsu_axi_rready;
wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_rid;
wire [ 63:0] lsu_axi_rdata;
wire [ 1:0] lsu_axi_rresp;
wire lsu_axi_rlast;
//-------------------------- IFU AXI signals--------------------------
// AXI Write Channels
wire ifu_axi_awvalid;
wire ifu_axi_awready;
wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_awid;
wire [ 31:0] ifu_axi_awaddr;
wire [ 3:0] ifu_axi_awregion;
wire [ 7:0] ifu_axi_awlen;
wire [ 2:0] ifu_axi_awsize;
wire [ 1:0] ifu_axi_awburst;
wire ifu_axi_awlock;
wire [ 3:0] ifu_axi_awcache;
wire [ 2:0] ifu_axi_awprot;
wire [ 3:0] ifu_axi_awqos;
wire ifu_axi_wvalid;
wire ifu_axi_wready;
wire [ 63:0] ifu_axi_wdata;
wire [ 7:0] ifu_axi_wstrb;
wire ifu_axi_wlast;
wire ifu_axi_bvalid;
wire ifu_axi_bready;
wire [ 1:0] ifu_axi_bresp;
wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_bid;
// AXI Read Channels
wire ifu_axi_arvalid;
wire ifu_axi_arready;
wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_arid;
wire [ 31:0] ifu_axi_araddr;
wire [ 3:0] ifu_axi_arregion;
wire [ 7:0] ifu_axi_arlen;
wire [ 2:0] ifu_axi_arsize;
wire [ 1:0] ifu_axi_arburst;
wire ifu_axi_arlock;
wire [ 3:0] ifu_axi_arcache;
wire [ 2:0] ifu_axi_arprot;
wire [ 3:0] ifu_axi_arqos;
wire ifu_axi_rvalid;
wire ifu_axi_rready;
wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_rid;
wire [ 63:0] ifu_axi_rdata;
wire [ 1:0] ifu_axi_rresp;
wire ifu_axi_rlast;
//-------------------------- SB AXI signals--------------------------
// AXI Write Channels
wire sb_axi_awvalid;
wire sb_axi_awready;
wire [ `RV_SB_BUS_TAG-1:0] sb_axi_awid;
wire [ 31:0] sb_axi_awaddr;
wire [ 3:0] sb_axi_awregion;
wire [ 7:0] sb_axi_awlen;
wire [ 2:0] sb_axi_awsize;
wire [ 1:0] sb_axi_awburst;
wire sb_axi_awlock;
wire [ 3:0] sb_axi_awcache;
wire [ 2:0] sb_axi_awprot;
wire [ 3:0] sb_axi_awqos;
wire sb_axi_wvalid;
wire sb_axi_wready;
wire [ 63:0] sb_axi_wdata;
wire [ 7:0] sb_axi_wstrb;
wire sb_axi_wlast;
wire sb_axi_bvalid;
wire sb_axi_bready;
wire [ 1:0] sb_axi_bresp;
wire [ `RV_SB_BUS_TAG-1:0] sb_axi_bid;
// AXI Read Channels
wire sb_axi_arvalid;
wire sb_axi_arready;
wire [ `RV_SB_BUS_TAG-1:0] sb_axi_arid;
wire [ 31:0] sb_axi_araddr;
wire [ 3:0] sb_axi_arregion;
wire [ 7:0] sb_axi_arlen;
wire [ 2:0] sb_axi_arsize;
wire [ 1:0] sb_axi_arburst;
wire sb_axi_arlock;
wire [ 3:0] sb_axi_arcache;
wire [ 2:0] sb_axi_arprot;
wire [ 3:0] sb_axi_arqos;
wire sb_axi_rvalid;
wire sb_axi_rready;
wire [ `RV_SB_BUS_TAG-1:0] sb_axi_rid;
wire [ 63:0] sb_axi_rdata;
wire [ 1:0] sb_axi_rresp;
wire sb_axi_rlast;
//-------------------------- DMA AXI signals--------------------------
// AXI Write Channels
wire dma_axi_awvalid;
wire dma_axi_awready;
wire [`RV_DMA_BUS_TAG-1:0] dma_axi_awid;
wire [ 31:0] dma_axi_awaddr;
wire [ 2:0] dma_axi_awsize;
wire [ 2:0] dma_axi_awprot;
wire [ 7:0] dma_axi_awlen;
wire [ 1:0] dma_axi_awburst;
wire dma_axi_wvalid;
wire dma_axi_wready;
wire [ 63:0] dma_axi_wdata;
wire [ 7:0] dma_axi_wstrb;
wire dma_axi_wlast;
wire dma_axi_bvalid;
wire dma_axi_bready;
wire [ 1:0] dma_axi_bresp;
wire [`RV_DMA_BUS_TAG-1:0] dma_axi_bid;
// AXI Read Channels
wire dma_axi_arvalid;
wire dma_axi_arready;
wire [`RV_DMA_BUS_TAG-1:0] dma_axi_arid;
wire [ 31:0] dma_axi_araddr;
wire [ 2:0] dma_axi_arsize;
wire [ 2:0] dma_axi_arprot;
wire [ 7:0] dma_axi_arlen;
wire [ 1:0] dma_axi_arburst;
wire dma_axi_rvalid;
wire dma_axi_rready;
wire [`RV_DMA_BUS_TAG-1:0] dma_axi_rid;
wire [ 63:0] dma_axi_rdata;
wire [ 1:0] dma_axi_rresp;
wire dma_axi_rlast;
wire lmem_axi_arvalid;
wire lmem_axi_arready;
wire lmem_axi_rvalid;
wire [`RV_LSU_BUS_TAG-1:0] lmem_axi_rid;
wire [ 1:0] lmem_axi_rresp;
wire [ 63:0] lmem_axi_rdata;
wire lmem_axi_rlast;
wire lmem_axi_rready;
wire lmem_axi_awvalid;
wire lmem_axi_awready;
wire lmem_axi_wvalid;
wire lmem_axi_wready;
wire [ 1:0] lmem_axi_bresp;
wire lmem_axi_bvalid;
wire [`RV_LSU_BUS_TAG-1:0] lmem_axi_bid;
wire lmem_axi_bready;
initial begin
jtag_id[31:28] = 4'b1;
jtag_id[27:12] = '0;
@ -122,70 +326,186 @@ module soc_top (
.nmi_vec (nmi_vector[31:1]),
.jtag_id (jtag_id[31:1]),
// RV_BUILD_AHB_LITE START
.haddr (ic_haddr),
.hburst (ic_hburst),
.hmastlock(ic_hmastlock),
.hprot (ic_hprot),
.hsize (ic_hsize),
.htrans (ic_htrans),
.hwrite (ic_hwrite),
//-------------------------- LSU AXI signals--------------------------
// AXI Write Channels
.lsu_axi_awvalid (lsu_axi_awvalid),
.lsu_axi_awready (lsu_axi_awready),
.lsu_axi_awid (lsu_axi_awid),
.lsu_axi_awaddr (lsu_axi_awaddr),
.lsu_axi_awregion(lsu_axi_awregion),
.lsu_axi_awlen (lsu_axi_awlen),
.lsu_axi_awsize (lsu_axi_awsize),
.lsu_axi_awburst (lsu_axi_awburst),
.lsu_axi_awlock (lsu_axi_awlock),
.lsu_axi_awcache (lsu_axi_awcache),
.lsu_axi_awprot (lsu_axi_awprot),
.lsu_axi_awqos (lsu_axi_awqos),
.hrdata(ic_hrdata[63:0]),
.hready(ic_hready),
.hresp (ic_hresp),
.lsu_axi_wvalid(lsu_axi_wvalid),
.lsu_axi_wready(lsu_axi_wready),
.lsu_axi_wdata (lsu_axi_wdata),
.lsu_axi_wstrb (lsu_axi_wstrb),
.lsu_axi_wlast (lsu_axi_wlast),
//---------------------------------------------------------------
// Debug AHB Master
//---------------------------------------------------------------
.sb_haddr (sb_haddr),
.sb_hburst (sb_hburst),
.sb_hmastlock(sb_hmastlock),
.sb_hprot (sb_hprot),
.sb_hsize (sb_hsize),
.sb_htrans (sb_htrans),
.sb_hwrite (sb_hwrite),
.sb_hwdata (sb_hwdata),
.lsu_axi_bvalid(lsu_axi_bvalid),
.lsu_axi_bready(lsu_axi_bready),
.lsu_axi_bresp (lsu_axi_bresp),
.lsu_axi_bid (lsu_axi_bid),
.sb_hrdata(sb_hrdata),
.sb_hready(sb_hready),
.sb_hresp (sb_hresp),
//---------------------------------------------------------------
// LSU AHB Master
//---------------------------------------------------------------
.lsu_haddr (lsu_haddr),
.lsu_hburst (lsu_hburst),
.lsu_hmastlock(lsu_hmastlock),
.lsu_hprot (lsu_hprot),
.lsu_hsize (lsu_hsize),
.lsu_htrans (lsu_htrans),
.lsu_hwrite (lsu_hwrite),
.lsu_hwdata (lsu_hwdata),
.lsu_axi_arvalid (lsu_axi_arvalid),
.lsu_axi_arready (lsu_axi_arready),
.lsu_axi_arid (lsu_axi_arid),
.lsu_axi_araddr (lsu_axi_araddr),
.lsu_axi_arregion(lsu_axi_arregion),
.lsu_axi_arlen (lsu_axi_arlen),
.lsu_axi_arsize (lsu_axi_arsize),
.lsu_axi_arburst (lsu_axi_arburst),
.lsu_axi_arlock (lsu_axi_arlock),
.lsu_axi_arcache (lsu_axi_arcache),
.lsu_axi_arprot (lsu_axi_arprot),
.lsu_axi_arqos (lsu_axi_arqos),
.lsu_hrdata(lsu_hrdata[63:0]),
.lsu_hready(lsu_hready),
.lsu_hresp (lsu_hresp),
.lsu_axi_rvalid(lsu_axi_rvalid),
.lsu_axi_rready(lsu_axi_rready),
.lsu_axi_rid (lsu_axi_rid),
.lsu_axi_rdata (lsu_axi_rdata),
.lsu_axi_rresp (lsu_axi_rresp),
.lsu_axi_rlast (lsu_axi_rlast),
//---------------------------------------------------------------
// DMA Slave
//---------------------------------------------------------------
.dma_haddr ('0),
.dma_hburst ('0),
.dma_hmastlock('0),
.dma_hprot ('0),
.dma_hsize ('0),
.dma_htrans ('0),
.dma_hwrite ('0),
.dma_hwdata ('0),
//-------------------------- IFU AXI signals--------------------------
// AXI Write Channels
.ifu_axi_awvalid (ifu_axi_awvalid),
.ifu_axi_awready (ifu_axi_awready),
.ifu_axi_awid (ifu_axi_awid),
.ifu_axi_awaddr (ifu_axi_awaddr),
.ifu_axi_awregion(ifu_axi_awregion),
.ifu_axi_awlen (ifu_axi_awlen),
.ifu_axi_awsize (ifu_axi_awsize),
.ifu_axi_awburst (ifu_axi_awburst),
.ifu_axi_awlock (ifu_axi_awlock),
.ifu_axi_awcache (ifu_axi_awcache),
.ifu_axi_awprot (ifu_axi_awprot),
.ifu_axi_awqos (ifu_axi_awqos),
.dma_hrdata (dma_hrdata),
.dma_hresp (dma_hresp),
.dma_hsel (1'b1),
.dma_hreadyin (dma_hready_out),
.dma_hreadyout(dma_hready_out),
.ifu_axi_wvalid(ifu_axi_wvalid),
.ifu_axi_wready(ifu_axi_wready),
.ifu_axi_wdata (ifu_axi_wdata),
.ifu_axi_wstrb (ifu_axi_wstrb),
.ifu_axi_wlast (ifu_axi_wlast),
.ifu_axi_bvalid(ifu_axi_bvalid),
.ifu_axi_bready(ifu_axi_bready),
.ifu_axi_bresp (ifu_axi_bresp),
.ifu_axi_bid (ifu_axi_bid),
.ifu_axi_arvalid (ifu_axi_arvalid),
.ifu_axi_arready (ifu_axi_arready),
.ifu_axi_arid (ifu_axi_arid),
.ifu_axi_araddr (ifu_axi_araddr),
.ifu_axi_arregion(ifu_axi_arregion),
.ifu_axi_arlen (ifu_axi_arlen),
.ifu_axi_arsize (ifu_axi_arsize),
.ifu_axi_arburst (ifu_axi_arburst),
.ifu_axi_arlock (ifu_axi_arlock),
.ifu_axi_arcache (ifu_axi_arcache),
.ifu_axi_arprot (ifu_axi_arprot),
.ifu_axi_arqos (ifu_axi_arqos),
.ifu_axi_rvalid(ifu_axi_rvalid),
.ifu_axi_rready(ifu_axi_rready),
.ifu_axi_rid (ifu_axi_rid),
.ifu_axi_rdata (ifu_axi_rdata),
.ifu_axi_rresp (ifu_axi_rresp),
.ifu_axi_rlast (ifu_axi_rlast),
//-------------------------- SB AXI signals--------------------------
// AXI Write Channels
.sb_axi_awvalid (sb_axi_awvalid),
.sb_axi_awready (sb_axi_awready),
.sb_axi_awid (sb_axi_awid),
.sb_axi_awaddr (sb_axi_awaddr),
.sb_axi_awregion(sb_axi_awregion),
.sb_axi_awlen (sb_axi_awlen),
.sb_axi_awsize (sb_axi_awsize),
.sb_axi_awburst (sb_axi_awburst),
.sb_axi_awlock (sb_axi_awlock),
.sb_axi_awcache (sb_axi_awcache),
.sb_axi_awprot (sb_axi_awprot),
.sb_axi_awqos (sb_axi_awqos),
.sb_axi_wvalid(sb_axi_wvalid),
.sb_axi_wready(sb_axi_wready),
.sb_axi_wdata (sb_axi_wdata),
.sb_axi_wstrb (sb_axi_wstrb),
.sb_axi_wlast (sb_axi_wlast),
.sb_axi_bvalid(sb_axi_bvalid),
.sb_axi_bready(sb_axi_bready),
.sb_axi_bresp (sb_axi_bresp),
.sb_axi_bid (sb_axi_bid),
.sb_axi_arvalid (sb_axi_arvalid),
.sb_axi_arready (sb_axi_arready),
.sb_axi_arid (sb_axi_arid),
.sb_axi_araddr (sb_axi_araddr),
.sb_axi_arregion(sb_axi_arregion),
.sb_axi_arlen (sb_axi_arlen),
.sb_axi_arsize (sb_axi_arsize),
.sb_axi_arburst (sb_axi_arburst),
.sb_axi_arlock (sb_axi_arlock),
.sb_axi_arcache (sb_axi_arcache),
.sb_axi_arprot (sb_axi_arprot),
.sb_axi_arqos (sb_axi_arqos),
.sb_axi_rvalid(sb_axi_rvalid),
.sb_axi_rready(sb_axi_rready),
.sb_axi_rid (sb_axi_rid),
.sb_axi_rdata (sb_axi_rdata),
.sb_axi_rresp (sb_axi_rresp),
.sb_axi_rlast (sb_axi_rlast),
//-------------------------- DMA AXI signals--------------------------
// AXI Write Channels
.dma_axi_awvalid(dma_axi_awvalid),
.dma_axi_awready(dma_axi_awready),
.dma_axi_awid ('0), // ids are not used on DMA since it always responses in order
.dma_axi_awaddr(lsu_axi_awaddr),
.dma_axi_awsize(lsu_axi_awsize),
.dma_axi_awprot('0),
.dma_axi_awlen('0),
.dma_axi_awburst('0),
.dma_axi_wvalid(dma_axi_wvalid),
.dma_axi_wready(dma_axi_wready),
.dma_axi_wdata (lsu_axi_wdata),
.dma_axi_wstrb (lsu_axi_wstrb),
.dma_axi_wlast (1'b1),
.dma_axi_bvalid(dma_axi_bvalid),
.dma_axi_bready(dma_axi_bready),
.dma_axi_bresp (dma_axi_bresp),
.dma_axi_bid (),
.dma_axi_arvalid(dma_axi_arvalid),
.dma_axi_arready(dma_axi_arready),
.dma_axi_arid ('0),
.dma_axi_araddr (lsu_axi_araddr),
.dma_axi_arsize (lsu_axi_arsize),
.dma_axi_arprot ('0),
.dma_axi_arlen ('0),
.dma_axi_arburst('0),
.dma_axi_rvalid(dma_axi_rvalid),
.dma_axi_rready(dma_axi_rready),
.dma_axi_rid (),
.dma_axi_rdata (dma_axi_rdata),
.dma_axi_rresp (dma_axi_rresp),
.dma_axi_rlast (dma_axi_rlast),
// RV_BUILD_AHB_LITE END
.timer_int (1'b0),
.extintsrc_req('0),
@ -233,44 +553,155 @@ module soc_top (
);
ahb_sif imem (
// Inputs
.HWDATA(64'h0),
.HCLK(clk),
.HSEL(1'b1),
.HPROT(ic_hprot),
.HWRITE(ic_hwrite),
.HTRANS(ic_htrans),
.HSIZE(ic_hsize),
.HREADY(ic_hready),
.HRESETn(rst),
.HADDR(ic_haddr),
.HBURST(ic_hburst),
axi_slv #(
.TAGW(`RV_IFU_BUS_TAG)
) imem (
.aclk(clk),
.rst_l(rst),
.arvalid(ifu_axi_arvalid),
.arready(ifu_axi_arready),
.araddr(ifu_axi_araddr),
.arid(ifu_axi_arid),
.arlen(ifu_axi_arlen),
.arburst(ifu_axi_arburst),
.arsize(ifu_axi_arsize),
// Outputs
.HREADYOUT(ic_hready),
.HRESP(ic_hresp),
.HRDATA(ic_hrdata[63:0])
.rvalid(ifu_axi_rvalid),
.rready(ifu_axi_rready),
.rdata(ifu_axi_rdata),
.rresp(ifu_axi_rresp),
.rid(ifu_axi_rid),
.rlast(ifu_axi_rlast),
.awvalid(1'b0),
.awready(),
.awaddr('0),
.awid('0),
.awlen('0),
.awburst('0),
.awsize('0),
.wdata ('0),
.wstrb ('0),
.wvalid(1'b0),
.wready(),
.bvalid(),
.bready(1'b0),
.bresp(),
.bid()
);
ahb_sif lmem (
// Inputs
.HWDATA(lsu_hwdata),
.HCLK(clk),
.HSEL(1'b1),
.HPROT(lsu_hprot),
.HWRITE(lsu_hwrite),
.HTRANS(lsu_htrans),
.HSIZE(lsu_hsize),
.HREADY(lsu_hready),
.HRESETn(rst),
.HADDR(lsu_haddr),
.HBURST(lsu_hburst),
defparam lmem.TAGW = `RV_LSU_BUS_TAG;
// Outputs
.HREADYOUT(lsu_hready),
.HRESP(lsu_hresp),
.HRDATA(lsu_hrdata[63:0])
//axi_slv #(.TAGW(`RV_LSU_BUS_TAG)) lmem(
axi_slv lmem (
.aclk(clk),
.rst_l(rst),
.arvalid(lmem_axi_arvalid),
.arready(lmem_axi_arready),
.araddr(lsu_axi_araddr),
.arid(lsu_axi_arid),
.arlen(lsu_axi_arlen),
.arburst(lsu_axi_arburst),
.arsize(lsu_axi_arsize),
.rvalid(lmem_axi_rvalid),
.rready(lmem_axi_rready),
.rdata(lmem_axi_rdata),
.rresp(lmem_axi_rresp),
.rid(lmem_axi_rid),
.rlast(lmem_axi_rlast),
.awvalid(lmem_axi_awvalid),
.awready(lmem_axi_awready),
.awaddr(lsu_axi_awaddr),
.awid(lsu_axi_awid),
.awlen(lsu_axi_awlen),
.awburst(lsu_axi_awburst),
.awsize(lsu_axi_awsize),
.wdata (lsu_axi_wdata),
.wstrb (lsu_axi_wstrb),
.wvalid(lmem_axi_wvalid),
.wready(lmem_axi_wready),
.bvalid(lmem_axi_bvalid),
.bready(lmem_axi_bready),
.bresp(lmem_axi_bresp),
.bid(lmem_axi_bid)
);
axi_lsu_dma_bridge #(`RV_LSU_BUS_TAG, `RV_LSU_BUS_TAG) bridge (
.clk(clk),
.reset_l(rst),
.m_arvalid(lsu_axi_arvalid),
.m_arid(lsu_axi_arid),
.m_araddr(lsu_axi_araddr),
.m_arready(lsu_axi_arready),
.m_rvalid(lsu_axi_rvalid),
.m_rready(lsu_axi_rready),
.m_rdata(lsu_axi_rdata),
.m_rid(lsu_axi_rid),
.m_rresp(lsu_axi_rresp),
.m_rlast(lsu_axi_rlast),
.m_awvalid(lsu_axi_awvalid),
.m_awid(lsu_axi_awid),
.m_awaddr(lsu_axi_awaddr),
.m_awready(lsu_axi_awready),
.m_wvalid(lsu_axi_wvalid),
.m_wready(lsu_axi_wready),
.m_bresp(lsu_axi_bresp),
.m_bvalid(lsu_axi_bvalid),
.m_bid(lsu_axi_bid),
.m_bready(lsu_axi_bready),
.s0_arvalid(lmem_axi_arvalid),
.s0_arready(lmem_axi_arready),
.s0_rvalid(lmem_axi_rvalid),
.s0_rid(lmem_axi_rid),
.s0_rresp(lmem_axi_rresp),
.s0_rdata(lmem_axi_rdata),
.s0_rlast(lmem_axi_rlast),
.s0_rready(lmem_axi_rready),
.s0_awvalid(lmem_axi_awvalid),
.s0_awready(lmem_axi_awready),
.s0_wvalid(lmem_axi_wvalid),
.s0_wready(lmem_axi_wready),
.s0_bresp(lmem_axi_bresp),
.s0_bvalid(lmem_axi_bvalid),
.s0_bid(lmem_axi_bid),
.s0_bready(lmem_axi_bready),
.s1_arvalid(dma_axi_arvalid),
.s1_arready(dma_axi_arready),
.s1_rvalid(dma_axi_rvalid),
.s1_rresp (dma_axi_rresp),
.s1_rdata (dma_axi_rdata),
.s1_rlast (dma_axi_rlast),
.s1_rready(dma_axi_rready),
.s1_awvalid(dma_axi_awvalid),
.s1_awready(dma_axi_awready),
.s1_wvalid(dma_axi_wvalid),
.s1_wready(dma_axi_wready),
.s1_bresp (dma_axi_bresp),
.s1_bvalid(dma_axi_bvalid),
.s1_bready(dma_axi_bready)
);
endmodule

4
Cores-SweRV/soc/swerv.config
View File

@ -258,12 +258,12 @@ if ($target eq "default") {
if (!defined($dccm_enable)) { $dccm_enable=1; }
if (!defined($dccm_region)) { $dccm_region="0xf"; }
if (!defined($dccm_offset)) { $dccm_offset="0x40000"; } #1*256*1024
if (!defined($dccm_size)) { $dccm_size=64; }
if (!defined($dccm_size)) { $dccm_size=32; }
if (!defined($dccm_num_banks)) { $dccm_num_banks=8; }
if (!defined($iccm_enable)) { $iccm_enable=0; }
if (!defined($iccm_region)) { $iccm_region="0xe"; }
if (!defined($iccm_offset)) { $iccm_offset="0xe000000"; } #0x380*256*1024
if (!defined($iccm_size)) { $iccm_size=512; }
if (!defined($iccm_size)) { $iccm_size=32; }
if (!defined($iccm_num_banks)) { $iccm_num_banks=8; }
if (!defined($icache_enable)) { $icache_enable=1; }
if (!defined($icache_ecc)) { $icache_ecc=0; }