From 40db638de645ae0811f6bdcf0ab35307715f42d6 Mon Sep 17 00:00:00 2001 From: Joseph Rahmeh Date: Sat, 10 Aug 2019 13:23:53 -0700 Subject: [PATCH] Mention 1.1.1 release. --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 93ba874..38c5cdc 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,6 @@ # SweRV RISC-V CoreTM 1.1 from Western Digital -This repository contains the SweRV CoreTM 1.1 design RTL. The previous version can be found in [branch 1.0.](https://github.com/chipsalliance/Cores-SweRV/tree/1.0) +This repository contains the SweRV CoreTM 1.1.1 design RTL. The previous version can be found in [branch 1.0](https://github.com/chipsalliance/Cores-SweRV/tree/1.0) and [branch 1.1](https://github.com/chipsalliance/Cores-SweRV/tree/1.1) The SweRV 1 series provides a 32-bit, machine-mode only, implementation of the RISC-V ISA including options I (base integer), M (multiply/divide) and C (compressed instructions from I and M). ## License