diff --git a/Cores-SweRV/demo/Readme.md b/Cores-SweRV/demo/Readme.md
deleted file mode 100644
index 256e79a..0000000
--- a/Cores-SweRV/demo/Readme.md
+++ /dev/null
@@ -1,84 +0,0 @@
-# Demo
-
-## helloworld
-
-This a demo for llvm build and sim with verilator.
-
-## jtag
-
-This is a demo of jtag simulation by openocd running on verilator.
-
-## install verilator
-
-`sudo apt install verilator`
-
-## install openocd
-
-```shell
-git clone https://github.com/riscv/riscv-openocd.git
-cd riscv-openocd
-./bootstrap
-./configure --prefix=$RISCV --enable-remote-bitbang --enable-jtag_vpi --enable-ftdi --enable-jlink
-make
-sudo make install
-```
-
-## may be install sv2v
-
-`https://github.com/zachjs/sv2v`
-
-## install ninja
-
-`sudo apt-get install -y ninja-build`
-
-## Gen quasar core
-
-```bash
-git clone https://github.com/Lampro-Mellon/Quasar.git
-cd tools
-vim configs/quasar.config # to config the core
-make clean
-make conf
-make sbt_
-# Quasar/generated_rtl/quasar_wrapper.sv
-```
-
-## install Bit-Vector
-
-```bash
-wget https://cpan.metacpan.org/authors/id/S/ST/STBEY/Bit-Vector-7.4.tar.gz
-tar -xvf
-cd 
-perl Makefile.PL
-make 
-sudo make install
-```
-
-## build and install riscv tools
-
-* Opetion1 :<https://github.com/riscv-collab/riscv-gnu-toolchain.git>
-
-```bash
-# build 64bit
-sudo make clean
-./configure --prefix=/opt/riscv 
-sudo make -j12
-
-# build 64bit and 32bit
-sudo make clean
-./configure --prefix=/opt/riscv --with-arch=rv32gc --with-abi=ilp32d --enable-multilib
-sudo make -j12
-```
-
-* Opetion2 :  
-
-```bash
-sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev libusb-1.0-0-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev device-tree-compiler pkg-config libexpat-dev libfl-dev
-git clone https://github.com/chipsalliance/rocket-tools.git
-git submodule update --init --recursive
-# riscv-isa-sim and openocd may be checkout to main branch to avoid compile error
-sudo su
-export RISCV=/opt/riscv
-export MAKEFLAGS="-j12"
-./build-rv32ima.sh
-```
diff --git a/Readme.md b/Readme.md
index c2496f0..a69f339 100644
--- a/Readme.md
+++ b/Readme.md
@@ -1,5 +1,88 @@
 # Weekend group
 
+## helloworld
+
+This a demo for llvm build and sim with verilator.
+
+## jtag
+
+This is a demo of jtag simulation by openocd running on verilator.
+
+## install verilator
+
+`sudo apt install verilator`
+
+## install openocd
+
+```shell
+git clone https://github.com/riscv/riscv-openocd.git
+cd riscv-openocd
+./bootstrap
+./configure --prefix=$RISCV --enable-remote-bitbang --enable-jtag_vpi --enable-ftdi --enable-jlink
+make
+sudo make install
+```
+
+## may be install sv2v
+
+`https://github.com/zachjs/sv2v`
+
+## install ninja
+
+`sudo apt-get install -y ninja-build`
+
+## Gen quasar core
+
+```bash
+git clone https://github.com/Lampro-Mellon/Quasar.git
+cd tools
+vim configs/quasar.config # to config the core
+make clean
+make conf
+make sbt_
+# Quasar/generated_rtl/quasar_wrapper.sv
+```
+
+## install Bit-Vector
+
+```bash
+wget https://cpan.metacpan.org/authors/id/S/ST/STBEY/Bit-Vector-7.4.tar.gz
+tar -xvf
+cd 
+perl Makefile.PL
+make 
+sudo make install
+```
+
+## build and install riscv tools
+
+* Opetion1 :<https://github.com/riscv-collab/riscv-gnu-toolchain.git>
+
+```bash
+# build 64bit
+sudo make clean
+./configure --prefix=/opt/riscv 
+sudo make -j12
+
+# build 64bit and 32bit
+sudo make clean
+./configure --prefix=/opt/riscv --with-arch=rv32gc --with-abi=ilp32d --enable-multilib
+sudo make -j12
+```
+
+* Opetion2 :  
+
+```bash
+sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev libusb-1.0-0-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev device-tree-compiler pkg-config libexpat-dev libfl-dev
+git clone https://github.com/chipsalliance/rocket-tools.git
+git submodule update --init --recursive
+# riscv-isa-sim and openocd may be checkout to main branch to avoid compile error
+sudo su
+export RISCV=/opt/riscv
+export MAKEFLAGS="-j12"
+./build-rv32ima.sh
+```
+
 ## tips
 
 * jtag的reset引脚要设置正确 jtag_trst_n 低电平复位