diff --git a/release-notes.md b/release-notes.md
index 4cd34be..fdc0285 100644
--- a/release-notes.md
+++ b/release-notes.md
@@ -15,36 +15,36 @@ is added to the SweRV core.
 * Debug module failed to auto-increment register on system-bus access
   of size 64-bit (reported by Codasip).
 * The core_rst_n signal was incorrectly connected (reported by Codasip).
-* Moudule/instance renamed for tool compatibility.
+* Module/instance renamed for tool compatibility.
 * The program counter was getting corrupted when the load/store unit
   indicated both a single-bit and a double-bit error in the same
   cycle.
-* The MSTATUS control register was not being updated as expected when
-  both a non-maskable-interrupt and an MSTATUS-write happened in the
-  same cycle.
-* Write to SBDATA0 was not starting an system-bus write access when
+* The MSTATUS register was not being updated as expected when both a
+  non-maskable-interrupt and an MSTATUS-write happened in the same
+  cycle.
+* Write to SBDATA0 was not starting a system-bus write access when
   sbreadonaddr/sbreadondata is set.
-* Minstret was incorrectly counting ecall/ebreak instructions
+* Minstret was incorrectly counting ecall/ebreak instructions.
 * The dec_tlu_mpc_halted_only signal was not set for MPC halt after
   reset.
-* The MEPC control register was not being updated when a
-  firmware-halt request was followed by a timer interrupt.
+* The MEPC register was not being updated when a firmware-halt request
+  was followed by a timer interrupt.
 * The MINSTRETH control register was being incremented when
   performance counters were disabled.
 * Bus driver contained combinational logic from multiple clock
   domains that sometimes caused a glitch.
 * System bus reads were always being made with 64-bit size for the
   AXI bus which is incorrect for IO access.
-* DCCM single bit errors were counted for instruction that did not
+* DCCM single-bit errors were counted for instructions that did not
   commit.
-* ICCM Single Bit Errors were double counted.
+* ICCM single bit errors were double-counted.
 * Load/store unit was not detecting access faults when DCCM and PIC
   memories are next to each other.
-* Single bit ECC errors on data load were not always corrected in
+* Single-bit ECC errors on data load were not always corrected in
   the DCCM.
-* ECC single bit error were not always corrected in the DCCM for DMA
-  access.
-* Single bit Errors detected while reading ICCM through DMA were not
+* Single-bit ECC errors were not always corrected in the DCCM for DMA
+  accesses.
+* Single-bit errors detected while reading ICCM through DMA were not
   being corrected in memory.
 
 
@@ -61,7 +61,7 @@ is added to the SweRV core.
 * Updated bus memory to be persistent and handle larger programs.
 * Makefile supports ability to run with source or pre-generated hex
   files.
-* Makefile supports targets for coremarks benchmark (issue #25).
+* Makefile supports targets for CoreMarks benchmark (issue #25).
 * Questa support in Makefile (Issue #19).