From 48dc8668cb0ced4cb854142120388a49674eec0e Mon Sep 17 00:00:00 2001 From: jrahmeh Date: Sun, 9 Jun 2019 19:50:35 -0500 Subject: [PATCH] Update README.md --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index 2d9e1f0..389eacb 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,7 @@ # SweRV RISC-V CoreTM 1.1 from Western Digital This repository contains the SweRV CoreTM 1.1 design RTL. The previous version can be found in [branch 1.0.](https://github.com/chipsalliance/Cores-SweRV/tree/1.0) +The SweRV 1 series provides a 32-bit, machine-mode only, implementation of the RISC-V ISA including options I (base integer), M (multiply/divide) and C (compressed instructions from I and M). ## License