From 4a1d9bd7d5d52a30ff8ec5d1eedcdbb11d8c72a9 Mon Sep 17 00:00:00 2001 From: Colin <> Date: Sun, 20 Apr 2025 20:07:37 +0800 Subject: [PATCH] Add xilinx ip. --- fpga/xc7z010/led.v | 14 ++++ fpga/xc7z010/mult_gen_0.xci | 160 ++++++++++++++++++++++++++++++++++++ fpga/xc7z010/vivado.tcl | 1 + 3 files changed, 175 insertions(+) create mode 100644 fpga/xc7z010/mult_gen_0.xci diff --git a/fpga/xc7z010/led.v b/fpga/xc7z010/led.v index be1c05c..35bace8 100644 --- a/fpga/xc7z010/led.v +++ b/fpga/xc7z010/led.v @@ -60,4 +60,18 @@ always@(posedge clk) else led <= 1'b0; + +reg [17:0] a; +reg [17:0] b; +wire [17:0] p; + +mult_gen_0 mul( + .CLK(clk), + .A(a), + .B(b), + .P(p) +); + + + endmodule diff --git a/fpga/xc7z010/mult_gen_0.xci b/fpga/xc7z010/mult_gen_0.xci new file mode 100644 index 0000000..b4d829b --- /dev/null +++ b/fpga/xc7z010/mult_gen_0.xci @@ -0,0 +1,160 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "mult_gen_0", + "component_reference": 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} ] + } + }, + "b_intf": { + "vlnv": "xilinx.com:signal:data:1.0", + "abstraction_type": "xilinx.com:signal:data_rtl:1.0", + "mode": "slave", + "parameters": { + "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "DATA": [ { "physical_name": "B" } ] + } + }, + "p_intf": { + "vlnv": "xilinx.com:signal:data:1.0", + "abstraction_type": "xilinx.com:signal:data_rtl:1.0", + "mode": "master", + "parameters": { + "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "DATA": [ { "physical_name": "P" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/fpga/xc7z010/vivado.tcl b/fpga/xc7z010/vivado.tcl index 3cb3fbd..c2d23bb 100644 --- a/fpga/xc7z010/vivado.tcl +++ b/fpga/xc7z010/vivado.tcl @@ -14,6 +14,7 @@ add_file /home/colin/develop/abstractaccelerator/fpga/xc7z010/TOP.v add_file /home/colin/develop/abstractaccelerator/fpga/xc7z010/led.v add_file /home/colin/develop/abstractaccelerator/fpga/xc7z010/design_1/design_1.bd +add_file /home/colin/develop/abstractaccelerator/fpga/xc7z010/mult_gen_0.xci # Constraints inclusion