diff --git a/Cores-SweRV/demo/Readme.md b/Cores-SweRV/demo/Readme.md index 6adc437..41ad7f2 100644 --- a/Cores-SweRV/demo/Readme.md +++ b/Cores-SweRV/demo/Readme.md @@ -23,6 +23,10 @@ make sudo make install ``` +## install ninja + +`sudo apt-get install -y ninja-build` + ## build and install riscv tools * Opetion1 :https://github.com/riscv-collab/riscv-gnu-toolchain.git diff --git a/Cores-SweRV/demo/helloworld/Makefile b/Cores-SweRV/demo/helloworld/Makefile index 39622d5..4020287 100644 --- a/Cores-SweRV/demo/helloworld/Makefile +++ b/Cores-SweRV/demo/helloworld/Makefile @@ -29,7 +29,7 @@ clean: rm -rf build obj_dir swerv_define : - BUILD_PATH=${BUILD_DIR} PERLLIB=${RV_SOC} ${RV_SOC}/swerv.config -target=default -set iccm_enable + BUILD_PATH=${BUILD_DIR} PERLLIB=${RV_SOC} ${RV_SOC}/swerv.config -target=default_ahb -set iccm_enable ##################### Verilog Builds ##################################### diff --git a/Cores-SweRV/demo/jtag/Makefile b/Cores-SweRV/demo/jtag/Makefile index eecf4c9..8a3daf5 100644 --- a/Cores-SweRV/demo/jtag/Makefile +++ b/Cores-SweRV/demo/jtag/Makefile @@ -32,7 +32,7 @@ clean: rm -rf build obj_dir swerv_define : - BUILD_PATH=${BUILD_DIR} PERLLIB=${RV_SOC} ${RV_SOC}/swerv.config -target=default -set iccm_enable + BUILD_PATH=${BUILD_DIR} PERLLIB=${RV_SOC} ${RV_SOC}/swerv.config -target=default_ahb -set iccm_enable ##################### Verilog Builds ##################################### diff --git a/Cores-SweRV/soc/soc_top.sv b/Cores-SweRV/soc/soc_top.sv index e2caab2..cc68f47 100644 --- a/Cores-SweRV/soc/soc_top.sv +++ b/Cores-SweRV/soc/soc_top.sv @@ -110,211 +110,6 @@ module soc_top; logic [4:0] wb_dest[1:0]; logic [31:0] wb_data[1:0]; -`ifdef RV_BUILD_AXI4 - //-------------------------- LSU AXI signals-------------------------- - // AXI Write Channels - wire lsu_axi_awvalid; - wire lsu_axi_awready; - wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_awid; - wire [31:0] lsu_axi_awaddr; - wire [3:0] lsu_axi_awregion; - wire [7:0] lsu_axi_awlen; - wire [2:0] lsu_axi_awsize; - wire [1:0] lsu_axi_awburst; - wire lsu_axi_awlock; - wire [3:0] lsu_axi_awcache; - wire [2:0] lsu_axi_awprot; - wire [3:0] lsu_axi_awqos; - - wire lsu_axi_wvalid; - wire lsu_axi_wready; - wire [63:0] lsu_axi_wdata; - wire [7:0] lsu_axi_wstrb; - wire lsu_axi_wlast; - - wire lsu_axi_bvalid; - wire lsu_axi_bready; - wire [1:0] lsu_axi_bresp; - wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_bid; - - // AXI Read Channels - wire lsu_axi_arvalid; - wire lsu_axi_arready; - wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_arid; - wire [31:0] lsu_axi_araddr; - wire [3:0] lsu_axi_arregion; - wire [7:0] lsu_axi_arlen; - wire [2:0] lsu_axi_arsize; - wire [1:0] lsu_axi_arburst; - wire lsu_axi_arlock; - wire [3:0] lsu_axi_arcache; - wire [2:0] lsu_axi_arprot; - wire [3:0] lsu_axi_arqos; - - wire lsu_axi_rvalid; - wire lsu_axi_rready; - wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_rid; - wire [63:0] lsu_axi_rdata; - wire [1:0] lsu_axi_rresp; - wire lsu_axi_rlast; - - //-------------------------- IFU AXI signals-------------------------- - // AXI Write Channels - wire ifu_axi_awvalid; - wire ifu_axi_awready; - wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_awid; - wire [31:0] ifu_axi_awaddr; - wire [3:0] ifu_axi_awregion; - wire [7:0] ifu_axi_awlen; - wire [2:0] ifu_axi_awsize; - wire [1:0] ifu_axi_awburst; - wire ifu_axi_awlock; - wire [3:0] ifu_axi_awcache; - wire [2:0] ifu_axi_awprot; - wire [3:0] ifu_axi_awqos; - - wire ifu_axi_wvalid; - wire ifu_axi_wready; - wire [63:0] ifu_axi_wdata; - wire [7:0] ifu_axi_wstrb; - wire ifu_axi_wlast; - - wire ifu_axi_bvalid; - wire ifu_axi_bready; - wire [1:0] ifu_axi_bresp; - wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_bid; - - // AXI Read Channels - wire ifu_axi_arvalid; - wire ifu_axi_arready; - wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_arid; - wire [31:0] ifu_axi_araddr; - wire [3:0] ifu_axi_arregion; - wire [7:0] ifu_axi_arlen; - wire [2:0] ifu_axi_arsize; - wire [1:0] ifu_axi_arburst; - wire ifu_axi_arlock; - wire [3:0] ifu_axi_arcache; - wire [2:0] ifu_axi_arprot; - wire [3:0] ifu_axi_arqos; - - wire ifu_axi_rvalid; - wire ifu_axi_rready; - wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_rid; - wire [63:0] ifu_axi_rdata; - wire [1:0] ifu_axi_rresp; - wire ifu_axi_rlast; - - //-------------------------- SB AXI signals-------------------------- - // AXI Write Channels - wire sb_axi_awvalid; - wire sb_axi_awready; - wire [`RV_SB_BUS_TAG-1:0] sb_axi_awid; - wire [31:0] sb_axi_awaddr; - wire [3:0] sb_axi_awregion; - wire [7:0] sb_axi_awlen; - wire [2:0] sb_axi_awsize; - wire [1:0] sb_axi_awburst; - wire sb_axi_awlock; - wire [3:0] sb_axi_awcache; - wire [2:0] sb_axi_awprot; - wire [3:0] sb_axi_awqos; - - wire sb_axi_wvalid; - wire sb_axi_wready; - wire [63:0] sb_axi_wdata; - wire [7:0] sb_axi_wstrb; - wire sb_axi_wlast; - - wire sb_axi_bvalid; - wire sb_axi_bready; - wire [1:0] sb_axi_bresp; - wire [`RV_SB_BUS_TAG-1:0] sb_axi_bid; - - // AXI Read Channels - wire sb_axi_arvalid; - wire sb_axi_arready; - wire [`RV_SB_BUS_TAG-1:0] sb_axi_arid; - wire [31:0] sb_axi_araddr; - wire [3:0] sb_axi_arregion; - wire [7:0] sb_axi_arlen; - wire [2:0] sb_axi_arsize; - wire [1:0] sb_axi_arburst; - wire sb_axi_arlock; - wire [3:0] sb_axi_arcache; - wire [2:0] sb_axi_arprot; - wire [3:0] sb_axi_arqos; - - wire sb_axi_rvalid; - wire sb_axi_rready; - wire [`RV_SB_BUS_TAG-1:0] sb_axi_rid; - wire [63:0] sb_axi_rdata; - wire [1:0] sb_axi_rresp; - wire sb_axi_rlast; - - //-------------------------- DMA AXI signals-------------------------- - // AXI Write Channels - wire dma_axi_awvalid; - wire dma_axi_awready; - wire [`RV_DMA_BUS_TAG-1:0] dma_axi_awid; - wire [31:0] dma_axi_awaddr; - wire [2:0] dma_axi_awsize; - wire [2:0] dma_axi_awprot; - wire [7:0] dma_axi_awlen; - wire [1:0] dma_axi_awburst; - - - wire dma_axi_wvalid; - wire dma_axi_wready; - wire [63:0] dma_axi_wdata; - wire [7:0] dma_axi_wstrb; - wire dma_axi_wlast; - - wire dma_axi_bvalid; - wire dma_axi_bready; - wire [1:0] dma_axi_bresp; - wire [`RV_DMA_BUS_TAG-1:0] dma_axi_bid; - - // AXI Read Channels - wire dma_axi_arvalid; - wire dma_axi_arready; - wire [`RV_DMA_BUS_TAG-1:0] dma_axi_arid; - wire [31:0] dma_axi_araddr; - wire [2:0] dma_axi_arsize; - wire [2:0] dma_axi_arprot; - wire [7:0] dma_axi_arlen; - wire [1:0] dma_axi_arburst; - - wire dma_axi_rvalid; - wire dma_axi_rready; - wire [`RV_DMA_BUS_TAG-1:0] dma_axi_rid; - wire [63:0] dma_axi_rdata; - wire [1:0] dma_axi_rresp; - wire dma_axi_rlast; - - wire lmem_axi_arvalid; - wire lmem_axi_arready; - - wire lmem_axi_rvalid; - wire [`RV_LSU_BUS_TAG-1:0] lmem_axi_rid; - wire [1:0] lmem_axi_rresp; - wire [63:0] lmem_axi_rdata; - wire lmem_axi_rlast; - wire lmem_axi_rready; - - wire lmem_axi_awvalid; - wire lmem_axi_awready; - - wire lmem_axi_wvalid; - wire lmem_axi_wready; - - wire [1:0] lmem_axi_bresp; - wire lmem_axi_bvalid; - wire [`RV_LSU_BUS_TAG-1:0] lmem_axi_bid; - wire lmem_axi_bready; - - -`endif wire[63:0] WriteData; string abi_reg[32]; // ABI register names @@ -532,187 +327,7 @@ swerv_wrapper rvtop ( .dma_hreadyin ( dma_hready_out ), .dma_hreadyout ( dma_hready_out ), `endif -`ifdef RV_BUILD_AXI4 - //-------------------------- LSU AXI signals-------------------------- - // AXI Write Channels - .lsu_axi_awvalid (lsu_axi_awvalid), - .lsu_axi_awready (lsu_axi_awready), - .lsu_axi_awid (lsu_axi_awid), - .lsu_axi_awaddr (lsu_axi_awaddr), - .lsu_axi_awregion (lsu_axi_awregion), - .lsu_axi_awlen (lsu_axi_awlen), - .lsu_axi_awsize (lsu_axi_awsize), - .lsu_axi_awburst (lsu_axi_awburst), - .lsu_axi_awlock (lsu_axi_awlock), - .lsu_axi_awcache (lsu_axi_awcache), - .lsu_axi_awprot (lsu_axi_awprot), - .lsu_axi_awqos (lsu_axi_awqos), - .lsu_axi_wvalid (lsu_axi_wvalid), - .lsu_axi_wready (lsu_axi_wready), - .lsu_axi_wdata (lsu_axi_wdata), - .lsu_axi_wstrb (lsu_axi_wstrb), - .lsu_axi_wlast (lsu_axi_wlast), - - .lsu_axi_bvalid (lsu_axi_bvalid), - .lsu_axi_bready (lsu_axi_bready), - .lsu_axi_bresp (lsu_axi_bresp), - .lsu_axi_bid (lsu_axi_bid), - - - .lsu_axi_arvalid (lsu_axi_arvalid), - .lsu_axi_arready (lsu_axi_arready), - .lsu_axi_arid (lsu_axi_arid), - .lsu_axi_araddr (lsu_axi_araddr), - .lsu_axi_arregion (lsu_axi_arregion), - .lsu_axi_arlen (lsu_axi_arlen), - .lsu_axi_arsize (lsu_axi_arsize), - .lsu_axi_arburst (lsu_axi_arburst), - .lsu_axi_arlock (lsu_axi_arlock), - .lsu_axi_arcache (lsu_axi_arcache), - .lsu_axi_arprot (lsu_axi_arprot), - .lsu_axi_arqos (lsu_axi_arqos), - - .lsu_axi_rvalid (lsu_axi_rvalid), - .lsu_axi_rready (lsu_axi_rready), - .lsu_axi_rid (lsu_axi_rid), - .lsu_axi_rdata (lsu_axi_rdata), - .lsu_axi_rresp (lsu_axi_rresp), - .lsu_axi_rlast (lsu_axi_rlast), - - //-------------------------- IFU AXI signals-------------------------- - // AXI Write Channels - .ifu_axi_awvalid (ifu_axi_awvalid), - .ifu_axi_awready (ifu_axi_awready), - .ifu_axi_awid (ifu_axi_awid), - .ifu_axi_awaddr (ifu_axi_awaddr), - .ifu_axi_awregion (ifu_axi_awregion), - .ifu_axi_awlen (ifu_axi_awlen), - .ifu_axi_awsize (ifu_axi_awsize), - .ifu_axi_awburst (ifu_axi_awburst), - .ifu_axi_awlock (ifu_axi_awlock), - .ifu_axi_awcache (ifu_axi_awcache), - .ifu_axi_awprot (ifu_axi_awprot), - .ifu_axi_awqos (ifu_axi_awqos), - - .ifu_axi_wvalid (ifu_axi_wvalid), - .ifu_axi_wready (ifu_axi_wready), - .ifu_axi_wdata (ifu_axi_wdata), - .ifu_axi_wstrb (ifu_axi_wstrb), - .ifu_axi_wlast (ifu_axi_wlast), - - .ifu_axi_bvalid (ifu_axi_bvalid), - .ifu_axi_bready (ifu_axi_bready), - .ifu_axi_bresp (ifu_axi_bresp), - .ifu_axi_bid (ifu_axi_bid), - - .ifu_axi_arvalid (ifu_axi_arvalid), - .ifu_axi_arready (ifu_axi_arready), - .ifu_axi_arid (ifu_axi_arid), - .ifu_axi_araddr (ifu_axi_araddr), - .ifu_axi_arregion (ifu_axi_arregion), - .ifu_axi_arlen (ifu_axi_arlen), - .ifu_axi_arsize (ifu_axi_arsize), - .ifu_axi_arburst (ifu_axi_arburst), - .ifu_axi_arlock (ifu_axi_arlock), - .ifu_axi_arcache (ifu_axi_arcache), - .ifu_axi_arprot (ifu_axi_arprot), - .ifu_axi_arqos (ifu_axi_arqos), - - .ifu_axi_rvalid (ifu_axi_rvalid), - .ifu_axi_rready (ifu_axi_rready), - .ifu_axi_rid (ifu_axi_rid), - .ifu_axi_rdata (ifu_axi_rdata), - .ifu_axi_rresp (ifu_axi_rresp), - .ifu_axi_rlast (ifu_axi_rlast), - - //-------------------------- SB AXI signals-------------------------- - // AXI Write Channels - .sb_axi_awvalid (sb_axi_awvalid), - .sb_axi_awready (sb_axi_awready), - .sb_axi_awid (sb_axi_awid), - .sb_axi_awaddr (sb_axi_awaddr), - .sb_axi_awregion (sb_axi_awregion), - .sb_axi_awlen (sb_axi_awlen), - .sb_axi_awsize (sb_axi_awsize), - .sb_axi_awburst (sb_axi_awburst), - .sb_axi_awlock (sb_axi_awlock), - .sb_axi_awcache (sb_axi_awcache), - .sb_axi_awprot (sb_axi_awprot), - .sb_axi_awqos (sb_axi_awqos), - - .sb_axi_wvalid (sb_axi_wvalid), - .sb_axi_wready (sb_axi_wready), - .sb_axi_wdata (sb_axi_wdata), - .sb_axi_wstrb (sb_axi_wstrb), - .sb_axi_wlast (sb_axi_wlast), - - .sb_axi_bvalid (sb_axi_bvalid), - .sb_axi_bready (sb_axi_bready), - .sb_axi_bresp (sb_axi_bresp), - .sb_axi_bid (sb_axi_bid), - - - .sb_axi_arvalid (sb_axi_arvalid), - .sb_axi_arready (sb_axi_arready), - .sb_axi_arid (sb_axi_arid), - .sb_axi_araddr (sb_axi_araddr), - .sb_axi_arregion (sb_axi_arregion), - .sb_axi_arlen (sb_axi_arlen), - .sb_axi_arsize (sb_axi_arsize), - .sb_axi_arburst (sb_axi_arburst), - .sb_axi_arlock (sb_axi_arlock), - .sb_axi_arcache (sb_axi_arcache), - .sb_axi_arprot (sb_axi_arprot), - .sb_axi_arqos (sb_axi_arqos), - - .sb_axi_rvalid (sb_axi_rvalid), - .sb_axi_rready (sb_axi_rready), - .sb_axi_rid (sb_axi_rid), - .sb_axi_rdata (sb_axi_rdata), - .sb_axi_rresp (sb_axi_rresp), - .sb_axi_rlast (sb_axi_rlast), - - //-------------------------- DMA AXI signals-------------------------- - // AXI Write Channels - .dma_axi_awvalid (dma_axi_awvalid), - .dma_axi_awready (dma_axi_awready), - .dma_axi_awid ('0), // ids are not used on DMA since it always responses in order - .dma_axi_awaddr (lsu_axi_awaddr), - .dma_axi_awsize (lsu_axi_awsize), - .dma_axi_awprot ('0), - .dma_axi_awlen ('0), - .dma_axi_awburst ('0), - - - .dma_axi_wvalid (dma_axi_wvalid), - .dma_axi_wready (dma_axi_wready), - .dma_axi_wdata (lsu_axi_wdata), - .dma_axi_wstrb (lsu_axi_wstrb), - .dma_axi_wlast (1'b1), - - .dma_axi_bvalid (dma_axi_bvalid), - .dma_axi_bready (dma_axi_bready), - .dma_axi_bresp (dma_axi_bresp), - .dma_axi_bid (), - - - .dma_axi_arvalid (dma_axi_arvalid), - .dma_axi_arready (dma_axi_arready), - .dma_axi_arid ('0), - .dma_axi_araddr (lsu_axi_araddr), - .dma_axi_arsize (lsu_axi_arsize), - .dma_axi_arprot ('0), - .dma_axi_arlen ('0), - .dma_axi_arburst ('0), - - .dma_axi_rvalid (dma_axi_rvalid), - .dma_axi_rready (dma_axi_rready), - .dma_axi_rid (), - .dma_axi_rdata (dma_axi_rdata), - .dma_axi_rresp (dma_axi_rresp), - .dma_axi_rlast (dma_axi_rlast), -`endif .timer_int ( 1'b0 ), .extintsrc_req ( '0 ), @@ -806,217 +421,65 @@ ahb_sif lmem ( .HRDATA(lsu_hrdata[63:0]) ); -`endif -`ifdef RV_BUILD_AXI4 -axi_slv #(.TAGW(`RV_IFU_BUS_TAG)) imem( - .aclk(core_clk), - .rst_l(rst_l), - .arvalid(ifu_axi_arvalid), - .arready(ifu_axi_arready), - .araddr(ifu_axi_araddr), - .arid(ifu_axi_arid), - .arlen(ifu_axi_arlen), - .arburst(ifu_axi_arburst), - .arsize(ifu_axi_arsize), - - .rvalid(ifu_axi_rvalid), - .rready(ifu_axi_rready), - .rdata(ifu_axi_rdata), - .rresp(ifu_axi_rresp), - .rid(ifu_axi_rid), - .rlast(ifu_axi_rlast), - - .awvalid(1'b0), - .awready(), - .awaddr('0), - .awid('0), - .awlen('0), - .awburst('0), - .awsize('0), - - .wdata('0), - .wstrb('0), - .wvalid(1'b0), - .wready(), - - .bvalid(), - .bready(1'b0), - .bresp(), - .bid() -); - -defparam lmem.TAGW =`RV_LSU_BUS_TAG; - -//axi_slv #(.TAGW(`RV_LSU_BUS_TAG)) lmem( -axi_slv lmem( - .aclk(core_clk), - .rst_l(rst_l), - .arvalid(lmem_axi_arvalid), - .arready(lmem_axi_arready), - .araddr(lsu_axi_araddr), - .arid(lsu_axi_arid), - .arlen(lsu_axi_arlen), - .arburst(lsu_axi_arburst), - .arsize(lsu_axi_arsize), - - .rvalid(lmem_axi_rvalid), - .rready(lmem_axi_rready), - .rdata(lmem_axi_rdata), - .rresp(lmem_axi_rresp), - .rid(lmem_axi_rid), - .rlast(lmem_axi_rlast), - - .awvalid(lmem_axi_awvalid), - .awready(lmem_axi_awready), - .awaddr(lsu_axi_awaddr), - .awid(lsu_axi_awid), - .awlen(lsu_axi_awlen), - .awburst(lsu_axi_awburst), - .awsize(lsu_axi_awsize), - - .wdata(lsu_axi_wdata), - .wstrb(lsu_axi_wstrb), - .wvalid(lmem_axi_wvalid), - .wready(lmem_axi_wready), - - .bvalid(lmem_axi_bvalid), - .bready(lmem_axi_bready), - .bresp(lmem_axi_bresp), - .bid(lmem_axi_bid) -); - -axi_lsu_dma_bridge # (`RV_LSU_BUS_TAG,`RV_LSU_BUS_TAG ) bridge( - .clk(core_clk), - .reset_l(rst_l), - - .m_arvalid(lsu_axi_arvalid), - .m_arid(lsu_axi_arid), - .m_araddr(lsu_axi_araddr), - .m_arready(lsu_axi_arready), - - .m_rvalid(lsu_axi_rvalid), - .m_rready(lsu_axi_rready), - .m_rdata(lsu_axi_rdata), - .m_rid(lsu_axi_rid), - .m_rresp(lsu_axi_rresp), - .m_rlast(lsu_axi_rlast), - - .m_awvalid(lsu_axi_awvalid), - .m_awid(lsu_axi_awid), - .m_awaddr(lsu_axi_awaddr), - .m_awready(lsu_axi_awready), - - .m_wvalid(lsu_axi_wvalid), - .m_wready(lsu_axi_wready), - - .m_bresp(lsu_axi_bresp), - .m_bvalid(lsu_axi_bvalid), - .m_bid(lsu_axi_bid), - .m_bready(lsu_axi_bready), - - .s0_arvalid(lmem_axi_arvalid), - .s0_arready(lmem_axi_arready), - - .s0_rvalid(lmem_axi_rvalid), - .s0_rid(lmem_axi_rid), - .s0_rresp(lmem_axi_rresp), - .s0_rdata(lmem_axi_rdata), - .s0_rlast(lmem_axi_rlast), - .s0_rready(lmem_axi_rready), - - .s0_awvalid(lmem_axi_awvalid), - .s0_awready(lmem_axi_awready), - - .s0_wvalid(lmem_axi_wvalid), - .s0_wready(lmem_axi_wready), - .s0_bresp(lmem_axi_bresp), - .s0_bvalid(lmem_axi_bvalid), - .s0_bid(lmem_axi_bid), - .s0_bready(lmem_axi_bready), - - - .s1_arvalid(dma_axi_arvalid), - .s1_arready(dma_axi_arready), - - .s1_rvalid(dma_axi_rvalid), - .s1_rresp(dma_axi_rresp), - .s1_rdata(dma_axi_rdata), - .s1_rlast(dma_axi_rlast), - .s1_rready(dma_axi_rready), - - .s1_awvalid(dma_axi_awvalid), - .s1_awready(dma_axi_awready), - - .s1_wvalid(dma_axi_wvalid), - .s1_wready(dma_axi_wready), - - .s1_bresp(dma_axi_bresp), - .s1_bvalid(dma_axi_bvalid), - .s1_bready(dma_axi_bready) - -); - `endif task preload_iccm; -bit[31:0] data; -bit[31:0] addr, eaddr, saddr; + bit[31:0] data; + bit[31:0] addr, eaddr, saddr; -/* -addresses: - 0xfffffff0 - ICCM start address to load - 0xfffffff4 - ICCM end address to load -*/ + /* + addresses: + 0xfffffff0 - ICCM start address to load + 0xfffffff4 - ICCM end address to load + */ -addr = 'hffff_fff0; -saddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]}; -if ( (saddr < `RV_ICCM_SADR) || (saddr > `RV_ICCM_EADR)) return; -`ifndef RV_ICCM_ENABLE - $display("********************************************************"); - $display("ICCM preload: there is no ICCM in SweRV, terminating !!!"); - $display("********************************************************"); - $finish; -`endif -addr += 4; -eaddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]}; -$display("ICCM pre-load from %h to %h", saddr, eaddr); - -for(addr= saddr; addr <= eaddr; addr+=4) begin - data = {imem.mem[addr+3],imem.mem[addr+2],imem.mem[addr+1],imem.mem[addr]}; - slam_iccm_ram(addr, data == 0 ? 0 : {riscv_ecc32(data),data}); -end + addr = 'hffff_fff0; + saddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]}; + if ( (saddr < `RV_ICCM_SADR) || (saddr > `RV_ICCM_EADR)) return; + `ifndef RV_ICCM_ENABLE + $display("********************************************************"); + $display("ICCM preload: there is no ICCM in SweRV, terminating !!!"); + $display("********************************************************"); + $finish; + `endif + addr += 4; + eaddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]}; + $display("ICCM pre-load from %h to %h", saddr, eaddr); + for(addr= saddr; addr <= eaddr; addr+=4) begin + data = {imem.mem[addr+3],imem.mem[addr+2],imem.mem[addr+1],imem.mem[addr]}; + slam_iccm_ram(addr, data == 0 ? 0 : {riscv_ecc32(data),data}); + end endtask task preload_dccm; -bit[31:0] data; -bit[31:0] addr, saddr, eaddr; + bit[31:0] data; + bit[31:0] addr, saddr, eaddr; -/* -addresses: - 0xffff_fff8 - DCCM start address to load - 0xffff_fffc - DCCM end address to load -*/ + /* + addresses: + 0xffff_fff8 - DCCM start address to load + 0xffff_fffc - DCCM end address to load + */ -addr = 'hffff_fff8; -saddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]}; -if (saddr < `RV_DCCM_SADR || saddr > `RV_DCCM_EADR) return; -`ifndef RV_DCCM_ENABLE - $display("********************************************************"); - $display("DCCM preload: there is no DCCM in SweRV, terminating !!!"); - $display("********************************************************"); - $finish; -`endif -addr += 4; -eaddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]}; -$display("DCCM pre-load from %h to %h", saddr, eaddr); - -for(addr=saddr; addr <= eaddr; addr+=4) begin - data = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]}; - slam_dccm_ram(addr, data == 0 ? 0 : {riscv_ecc32(data),data}); -end + addr = 'hffff_fff8; + saddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]}; + if (saddr < `RV_DCCM_SADR || saddr > `RV_DCCM_EADR) return; + `ifndef RV_DCCM_ENABLE + $display("********************************************************"); + $display("DCCM preload: there is no DCCM in SweRV, terminating !!!"); + $display("********************************************************"); + $finish; + `endif + addr += 4; + eaddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]}; + $display("DCCM pre-load from %h to %h", saddr, eaddr); + for(addr=saddr; addr <= eaddr; addr+=4) begin + data = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]}; + slam_dccm_ram(addr, data == 0 ? 0 : {riscv_ecc32(data),data}); + end endtask `define DRAM(bank) \ @@ -1030,93 +493,85 @@ endtask task slam_iccm_ram(input [31:0] addr, input[38:0] data); -int bank, indx; -`ifdef RV_ICCM_ENABLE -bank = get_iccm_bank(addr, indx); -case(bank) -0: `IRAM0(0)[indx] = data; -1: `IRAM1(0)[indx] = data; -2: `IRAM2(0)[indx] = data; -3: `IRAM3(0)[indx] = data; -`ifdef RV_ICCM_NUM_BANKS_8 -4: `IRAM0(1)[indx] = data; -5: `IRAM1(1)[indx] = data; -6: `IRAM2(1)[indx] = data; -7: `IRAM3(1)[indx] = data; -`endif -`ifdef RV_ICCM_NUM_BANKS_16 -8: `IRAM0(2)[indx] = data; -9: `IRAM1(2)[indx] = data; -10: `IRAM2(2)[indx] = data; -11: `IRAM3(2)[indx] = data; -12: `IRAM0(3)[indx] = data; -13: `IRAM1(3)[indx] = data; -14: `IRAM2(3)[indx] = data; -15: `IRAM3(3)[indx] = data; -`endif -endcase -`endif + int bank, indx; + `ifdef RV_ICCM_ENABLE + `ifdef RV_ICCM_NUM_BANKS_4 + indx = int'(addr[`RV_ICCM_BITS-1:4]); + bank = int'( addr[3:2]); + `elsif RV_ICCM_NUM_BANKS_8 + indx = int'(addr[`RV_ICCM_BITS-1:5]); + bank = int'(addr[4:2]); + `else + indx = int'(addr[`RV_ICCM_BITS-1:6]); + bank = int'( addr[5:2]); + `endif + case(bank) + 0: `IRAM0(0)[indx] = data; + 1: `IRAM1(0)[indx] = data; + 2: `IRAM2(0)[indx] = data; + 3: `IRAM3(0)[indx] = data; + `ifdef RV_ICCM_NUM_BANKS_8 + 4: `IRAM0(1)[indx] = data; + 5: `IRAM1(1)[indx] = data; + 6: `IRAM2(1)[indx] = data; + 7: `IRAM3(1)[indx] = data; + `endif + `ifdef RV_ICCM_NUM_BANKS_16 + 8: `IRAM0(2)[indx] = data; + 9: `IRAM1(2)[indx] = data; + 10: `IRAM2(2)[indx] = data; + 11: `IRAM3(2)[indx] = data; + 12: `IRAM0(3)[indx] = data; + 13: `IRAM1(3)[indx] = data; + 14: `IRAM2(3)[indx] = data; + 15: `IRAM3(3)[indx] = data; + `endif + endcase + `endif endtask task slam_dccm_ram(input [31:0] addr, input[38:0] data); -int bank, indx; -`ifdef RV_DCCM_ENABLE -bank = get_dccm_bank(addr, indx); -case(bank) -0: `DRAM(0)[indx] = data; -1: `DRAM(1)[indx] = data; -`ifdef RV_DCCM_NUM_BANKS_4 -2: `DRAM(2)[indx] = data; -3: `DRAM(3)[indx] = data; -`endif -`ifdef RV_DCCM_NUM_BANKS_8 -2: `DRAM(2)[indx] = data; -3: `DRAM(3)[indx] = data; -4: `DRAM(4)[indx] = data; -5: `DRAM(5)[indx] = data; -6: `DRAM(6)[indx] = data; -7: `DRAM(7)[indx] = data; -`endif -endcase -`endif + int bank, indx; + `ifdef RV_DCCM_ENABLE + `ifdef RV_DCCM_NUM_BANKS_2 + indx = int'(addr[`RV_DCCM_BITS-1:3]); + bank = int'( addr[2]); + `elsif RV_DCCM_NUM_BANKS_4 + indx = int'(addr[`RV_DCCM_BITS-1:4]); + bank = int'(addr[3:2]); + `elsif RV_DCCM_NUM_BANKS_8 + indx = int'(addr[`RV_DCCM_BITS-1:5]); + bank = int'( addr[4:2]); + `endif + case(bank) + 0: `DRAM(0)[indx] = data; + 1: `DRAM(1)[indx] = data; + `ifdef RV_DCCM_NUM_BANKS_4 + 2: `DRAM(2)[indx] = data; + 3: `DRAM(3)[indx] = data; + `endif + `ifdef RV_DCCM_NUM_BANKS_8 + 2: `DRAM(2)[indx] = data; + 3: `DRAM(3)[indx] = data; + 4: `DRAM(4)[indx] = data; + 5: `DRAM(5)[indx] = data; + 6: `DRAM(6)[indx] = data; + 7: `DRAM(7)[indx] = data; + `endif + endcase + `endif endtask function[6:0] riscv_ecc32(input[31:0] data); -reg[6:0] synd; -synd[0] = ^(data & 32'h56aa_ad5b); -synd[1] = ^(data & 32'h9b33_366d); -synd[2] = ^(data & 32'he3c3_c78e); -synd[3] = ^(data & 32'h03fc_07f0); -synd[4] = ^(data & 32'h03ff_f800); -synd[5] = ^(data & 32'hfc00_0000); -synd[6] = ^{data, synd[5:0]}; -return synd; -endfunction - -function int get_dccm_bank(input int addr, output int bank_idx); -`ifdef RV_DCCM_NUM_BANKS_2 - bank_idx = int'(addr[`RV_DCCM_BITS-1:3]); - return int'( addr[2]); -`elsif RV_DCCM_NUM_BANKS_4 - bank_idx = int'(addr[`RV_DCCM_BITS-1:4]); - return int'(addr[3:2]); -`elsif RV_DCCM_NUM_BANKS_8 - bank_idx = int'(addr[`RV_DCCM_BITS-1:5]); - return int'( addr[4:2]); -`endif -endfunction - -function int get_iccm_bank(input int addr, output int bank_idx); -`ifdef RV_ICCM_NUM_BANKS_4 - bank_idx = int'(addr[`RV_ICCM_BITS-1:4]); - return int'( addr[3:2]); -`elsif RV_ICCM_NUM_BANKS_8 - bank_idx = int'(addr[`RV_ICCM_BITS-1:5]); - return int'(addr[4:2]); -`else - bank_idx = int'(addr[`RV_ICCM_BITS-1:6]); - return int'( addr[5:2]); -`endif + reg[6:0] synd; + synd[0] = ^(data & 32'h56aa_ad5b); + synd[1] = ^(data & 32'h9b33_366d); + synd[2] = ^(data & 32'he3c3_c78e); + synd[3] = ^(data & 32'h03fc_07f0); + synd[4] = ^(data & 32'h03ff_f800); + synd[5] = ^(data & 32'hfc00_0000); + synd[6] = ^{data, synd[5:0]}; + return synd; endfunction /* verilator lint_off WIDTH */ @@ -1127,6 +582,3 @@ endfunction endmodule -`ifdef RV_BUILD_AXI4 -`include "axi_lsu_dma_bridge.sv" -`endif