New branch: branch1.8
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Joseph Rahmeh
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25
README.md
25
README.md
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@ -1,4 +1,4 @@
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# EH1 SweRV RISC-V Core<sup>TM</sup> 1.7 from Western Digital
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# EH1 SweRV RISC-V Core<sup>TM</sup> 1.8 from Western Digital
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This repository contains the SweRV EH1 Core<sup>TM</sup> design RTL
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@ -95,6 +95,15 @@ Example for csh or its derivatives:
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Snapshots are placed in `$BUILD_PATH` directory
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**Building an FPGA speed optimized model:**
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Use ``-fpga_optimize=1`` option to ``swerv.config`` to build a model that removes clock gating logic from flop model so that the FPGA builds can run at higher speeds. **This is now the default option for
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targets other than ``default_pd``.**
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**Building a Power optimized model (ASIC flows):**
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Use ``-fpga_optimize=0`` option to ``swerv.config`` to build a model that **enables** clock gating logic into the flop model so that the ASIC flows get a better power footprint. **This is now the default option for
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target``default_pd``.**
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### Running RTL simulations
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1. Running a simple Hello World program (verilator)
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@ -170,10 +179,10 @@ User can provide test specific linker file in form `<test_name>.ld` to build the
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in the same directory with the test source.
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User also can create a test specific makefile in form `<test_name>.makefile`, contaning building instructions
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how to create `program.hex`, `data.hex` files used by simulation. The private makefile should be in the same directory
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how to create `program.hex` file, used by simulation. The private makefile should be in the same directory
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as the test source.
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*(`program.hex` file is loaded to instruction bus memory slave and `data.hex` file is loaded to LSU bus memory slave and
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optionally to DCCM at the beginning of simulation)*.
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*(`program.hex` file is loaded to instruction and data bus memory slaves and
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optionally to DCCM/ICCM at the beginning of simulation)*.
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Note: You may need to delete `program.hex` file from work directory, when run a new test.
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@ -191,14 +200,6 @@ cmark_iccm - the same as above, but with code preloaded to iccm - runs on
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The `$RV_ROOT/testbench/hex` directory contains precompiled hex files of the tests, ready for simulation in case RISCV SW tools are not installed.
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**Building an FPGA speed optimized model:**
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Use ``-fpga_optimize=1`` option to ``swerv.config`` to build a model that removes clock gating logic from flop model so that the FPGA builds can run at higher speeds. **This is now the default option for
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targets other than ``default_pd``.**
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**Building a Power optimized model (ASIC flows):**
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Use ``-fpga_optimize=0`` option to ``swerv.config`` to build a model that **enables** clock gating logic into the flop model so that the ASIC flows get a better power footprint. **This is now the default option for
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target``default_pd``.**
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----
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Western Digital, the Western Digital logo, G-Technology, SanDisk, Tegile, Upthere, WD, SweRV Core, SweRV ISS,
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and OmniXtend are registered trademarks or trademarks of Western Digital Corporation or its affiliates in the US
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@ -222,7 +222,7 @@ if (!defined $snapshot ) {
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}
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if (!defined $ENV{BUILD_PATH}) {
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$build_path = "$ENV{RV_ROOT}/configs/snapshots/$snapshot" ;
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$build_path = "$ENV{PWD}/snapshots/$snapshot" ;
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} else {
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$build_path = $ENV{BUILD_PATH};
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}
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@ -417,7 +417,7 @@ our %csr = (#{{{
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"exists" => "true",
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},
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"mimpid" => {
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"reset" => "0x4",
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"reset" => "0x5",
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"mask" => "0x0",
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"exists" => "true",
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},
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@ -446,6 +446,12 @@ our %csr = (#{{{
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"instret" => {
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"exists" => "false",
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},
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"mcountinhibit" => {
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"exists" => "false",
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},
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"mcounteren" => {
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"exists" => "false",
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},
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"mhpmcounter3" => {
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"reset" => "0x0",
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"mask" => "0xffffffff",
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@ -531,6 +537,12 @@ our %csr = (#{{{
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"mask" => "0x0",
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"exists" => "true",
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},
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"mgpmc" => {
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"number" => "0x7d0",
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"reset" => "0x1",
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"mask" => "0x1",
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"exists" => "true",
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},
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"mitcnt0" => {
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"number" => "0x7d2",
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"reset" => "0x0",
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@ -574,10 +586,11 @@ our %csr = (#{{{
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"exists" => "true",
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},
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"mpmc" => {
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"comment" => "Core pause: Implemented as read only.",
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"comment" => "FWHALT",
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"number" => "0x7c6",
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"reset" => "0x0",
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"mask" => "0x0",
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"reset" => "0x2",
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"mask" => "0x2",
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"poke_mask" => "0x2",
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"exists" => "true",
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},
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"micect" => {
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@ -820,8 +833,22 @@ our %config = (#{{{
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"pic_mpiccfg_offset" => '0x3000', # Offset of mpiccfg relative to pic_base_addr
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"pic_meipt_offset" => '0x3004', # Offset of meipt relative to pic_base_addr -- deprecated
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"pic_meigwctrl_offset" => '0x4000', # gateway control regs relative to pic_base_addr
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"pic_meigwclr_offset" => '0x5000' # gateway clear regs relative to pic_base_addr
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"pic_meigwclr_offset" => '0x5000', # gateway clear regs relative to pic_base_addr
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"pic_meipl_mask" => '0xf',
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"pic_meip_mask" => '0x0',
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"pic_meie_mask" => '0x1',
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"pic_mpiccfg_mask" => '0x1',
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"pic_meipt_mask" => '0x0',
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"pic_meigwctrl_mask" => '0x3',
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"pic_meigwclr_mask" => '0x0',
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"pic_meipl_count" => $pic_total_int,
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"pic_meip_count" => 4,
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"pic_meie_count" => $pic_total_int,
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"pic_mpiccfg_count" => 1,
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"pic_meipt_count" => $pic_total_int,
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"pic_meigwctrl_count" => $pic_total_int,
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"pic_meigwclr_count" => $pic_total_int
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},
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"testbench" => {
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"TOP" => "tb_top",
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@ -925,6 +952,7 @@ gen_define("","", \%config,[]);
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print "\nSweRV configuration for target=$target\n\n";
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dump_define("","", \%config,[]);
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# perform final checks
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my $c;
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$c=$config{retstack}{ret_stack_size}; if (!($c >=2 && $c <=8)) { die("$helpusage\n\nFAIL: ret_stack_size == $c; ILLEGAL !!!\n\n"); }
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@ -985,25 +1013,19 @@ $c=$config{protection}{data_access_mask7}; if ((hex($c)&0x3f) != 63)
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if (($config{"testbench"}{"build_ahb_lite"} ne "")) {
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delete $config{"testbench"}{"build_axi4"};
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if (($config{testbench}{build_ahb_lite} ne "")) {
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delete $config{testbench}{build_axi4};
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}
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else { # default is AXI bus
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delete $config{"testbench"}{"build_ahb_lite"};
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delete $config{testbench}{build_ahb_lite};
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}
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# Over-ride MFDC reset value for AXI.
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if (exists($config{"testbench"}{"build_axi_native"}) and
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$config{"testbench"}{"build_axi_native"} ne "") {
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if (exists($config{testbench}{build_axi4}) ) {
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$config{csr}{mfdc}{reset} = "0x00070040" if exists $config{csr}{mfdc};
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}
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# Over-ride MFDC reset value for AXI.
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if (exists($config{"testbench"}{"build_axi_native"}) and
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$config{"testbench"}{"build_axi_native"} ne "") {
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$config{csr}{mfdc}{reset} = "0x00070040" if exists $config{csr}{mfdc};
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}
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# Fill in derived configuration entries.
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@ -1280,6 +1302,8 @@ $config{iccm}{iccm_data_cell} = "ram_$config{iccm}{iccm_rows}x39";
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$config{iccm}{"iccm_num_banks_$config{iccm}{iccm_num_banks}"} = "";
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$config{iccm}{"iccm_size_$config{iccm}{iccm_size}"} = "";
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delete $config{core}{fpga_optimize} if ($config{core}{fpga_optimize} == 0);
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# Track used regions
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$regions_used{hex($config{iccm}{iccm_region})} = 1;
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@ -1884,6 +1908,30 @@ sub collect_mem_protection {
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}
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}
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# Collect the memory mapped registers associated with the pic (platform
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# interrup controller) to include in the whisper.json file.
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sub collect_mem_mapped_regs {
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my ($pic, $results) = @_;
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my $default_mask = 0;
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$results->{default_mask} = $default_mask;
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my $addr = hex($pic->{pic_region})*256*1024*1024 + hex($pic->{pic_offset});
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$results->{address} = sprintf("0x%x", $addr);
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$results->{size} = sprintf("0x%x", $pic->{pic_size}*1024);
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my @names = qw ( mpiccfg meipl meip meie meigwctrl meigwclr meidels );
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$results->{registers} = {};
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foreach my $name (@names) {
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my $tag = "pic_${name}_offset";
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next unless exists $pic->{$tag};
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my %item;
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my $offset = hex($pic->{$tag});
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$offset += 4 if ($name ne 'mpiccfg' and $name ne 'meip');
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$item{address} = sprintf("0x%x", $addr + $offset);
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$item{mask} = $pic->{"pic_${name}_mask"};
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$item{count} = $pic->{"pic_${name}_count"};
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$results->{registers}{$name} = \%item;
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}
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}
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sub dump_whisper_config{#{{{
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my ($config, $path) = @_;
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@ -1911,7 +1959,9 @@ sub dump_whisper_config{#{{{
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collect_mem_protection("data", $config, \@data_mem_prot);
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$jh{memmap}{inst} = [@inst_mem_prot] if @inst_mem_prot;
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$jh{memmap}{data} = [@data_mem_prot] if @data_mem_prot;
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$jh{memmap}{cosnoleio} = $config{memmap}{serialio} if exists $config{memmap}{serialio};
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foreach my $tag (qw ( size page_size serialio )) {
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$jh{memmap}{tag} = $config{memmap}{ta} if exists $config{memmap}{tag};
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}
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# Collect load/store-error rollback parameter.
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if (exists $config{testbench} and exists $config{testbench}{sterr_rollback}) {
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@ -1945,6 +1995,11 @@ sub dump_whisper_config{#{{{
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# Collect pic configs.
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if (exists $config{pic}) {
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my %mem_mapped;
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collect_mem_mapped_regs($config{pic}, \%mem_mapped);
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$jh{'memory_mapped_registers'} = \%mem_mapped;
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# This is now deprecated. To be removed soon.
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while (my ($k, $v) = each %{$config{pic}}) {
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next if $k eq 'pic_base_addr'; # derived from region and offset
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if ($k eq 'pic_size') {
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@ -117,9 +117,21 @@ module dbg (
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`include "global.h"
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typedef enum logic [2:0] {IDLE=3'b000, HALTING=3'b001, HALTED=3'b010, CMD_START=3'b011, CMD_WAIT=3'b100, CMD_DONE=3'b101, RESUMING=3'b110} state_t;
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typedef enum logic [3:0] {IDLE=4'h0, HALTING=4'h1, HALTED=4'h2, CORE_CMD_START=4'h3, CORE_CMD_WAIT=4'h4, SB_CMD_START=4'h5, SB_CMD_SEND=4'h6, SB_CMD_RESP=4'h7, CMD_DONE=4'h8, RESUMING=4'h9} state_t;
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typedef enum logic [3:0] {SBIDLE=4'h0, WAIT_RD=4'h1, WAIT_WR=4'h2, CMD_RD=4'h3, CMD_WR=4'h4, CMD_WR_ADDR=4'h5, CMD_WR_DATA=4'h6, RSP_RD=4'h7, RSP_WR=4'h8, DONE=4'h9} sb_state_t;
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`ifdef RV_ICCM_ENABLE
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localparam ICCM_ENABLE = 1'b1;
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`else
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localparam ICCM_ENABLE = 1'b0;
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`endif
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`ifdef RV_DCCM_ENABLE
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localparam DCCM_ENABLE = 1'b1;
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`else
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localparam DCCM_ENABLE = 1'b0;
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`endif
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state_t dbg_state;
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state_t dbg_nxtstate;
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logic dbg_state_en;
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@ -134,7 +146,7 @@ module dbg (
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// data 0
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logic [31:0] data0_din;
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logic data0_reg_wren, data0_reg_wren0, data0_reg_wren1;
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logic data0_reg_wren, data0_reg_wren0, data0_reg_wren1, data0_reg_wren2;
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// data 1
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logic [31:0] data1_din;
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logic data1_reg_wren, data1_reg_wren0, data1_reg_wren1;
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@ -142,8 +154,12 @@ module dbg (
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logic abstractcs_busy_wren;
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logic abstractcs_busy_din;
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logic [2:0] abstractcs_error_din;
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logic abstractcs_error_sel0, abstractcs_error_sel1, abstractcs_error_sel2, abstractcs_error_sel3, abstractcs_error_sel4, abstractcs_error_sel5;
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logic abstractcs_error_selor;
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logic abstractcs_error_sel0, abstractcs_error_sel1, abstractcs_error_sel2, abstractcs_error_sel3, abstractcs_error_sel4, abstractcs_error_sel5, abstractcs_error_sel6;
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logic dbg_sb_bus_error;
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// abstractauto
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logic abstractauto_reg_wren;
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logic [1:0] abstractauto_reg;
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// dmstatus
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//logic dmstatus_wren;
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logic dmstatus_dmerr_wren;
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@ -158,12 +174,17 @@ module dbg (
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logic dmstatus_havereset;
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// dmcontrol
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logic resumereq;
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logic dmcontrol_wren, dmcontrol_wren_Q;
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// command
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logic command_wren;
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logic execute_command_ns, execute_command;
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logic command_wren, command_regno_wren;
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logic command_transfer_din;
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logic command_postexec_din;
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logic [31:0] command_din;
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logic [3:0] dbg_cmd_addr_incr;
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logic [31:0] dbg_cmd_curr_addr;
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logic [31:0] dbg_cmd_next_addr;
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// needed to send the read data back for dmi reads
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logic [31:0] dmi_reg_rdata_din;
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@ -204,15 +225,40 @@ module dbg (
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logic sbreadondata_access;
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logic sbdata0wr_access;
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logic sb_abmem_cmd_done_in, sb_abmem_data_done_in;
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logic sb_abmem_cmd_done_en, sb_abmem_data_done_en;
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logic sb_abmem_cmd_done, sb_abmem_data_done;
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logic [31:0] abmem_addr;
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logic abmem_addr_in_dccm_region, abmem_addr_in_iccm_region, abmem_addr_in_pic_region;
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logic abmem_addr_core_local;
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logic abmem_addr_external;
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logic sb_cmd_pending, sb_abmem_cmd_pending;
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logic sb_abmem_cmd_arvalid, sb_abmem_cmd_awvalid, sb_abmem_cmd_wvalid;
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logic sb_abmem_read_pend;
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logic sb_abmem_cmd_write;
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logic [2:0] sb_abmem_cmd_size;
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logic [31:0] sb_abmem_cmd_addr;
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logic [31:0] sb_abmem_cmd_wdata;
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logic sb_cmd_awvalid, sb_cmd_wvalid, sb_cmd_arvalid;
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logic sb_read_pend;
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logic [2:0] sb_cmd_size;
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logic [31:0] sb_cmd_addr;
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logic [63:0] sb_cmd_wdata;
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logic [31:0] sb_axi_addr;
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logic [63:0] sb_axi_wrdata;
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logic [2:0] sb_axi_size;
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logic sb_axi_awvalid_q, sb_axi_awready_q;
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logic sb_axi_wvalid_q, sb_axi_wready_q;
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logic sb_axi_arvalid_q, sb_axi_arready_q;
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logic sb_axi_bvalid_q, sb_axi_bready_q;
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logic sb_axi_rvalid_q, sb_axi_rready_q;
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logic [1:0] sb_axi_bresp_q, sb_axi_rresp_q;
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logic [63:0] sb_axi_rdata_q;
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logic [63:0] sb_bus_rdata;
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logic [63:0] sb_bus_rdata;
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//registers
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logic [31:0] sbcs_reg;
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@ -234,10 +280,10 @@ module dbg (
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// clocking
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// used for the abstract commands.
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assign dbg_free_clken = dmi_reg_en | (dbg_state != IDLE) | dbg_state_en | dec_tlu_dbg_halted | clk_override;
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assign dbg_free_clken = dmi_reg_en | execute_command | (dbg_state != IDLE) | dbg_state_en | dec_tlu_dbg_halted | clk_override;
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// used for the system bus
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assign sb_free_clken = dmi_reg_en | sb_state_en | (sb_state != SBIDLE) | clk_override;
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assign sb_free_clken = dmi_reg_en | execute_command | sb_state_en | (sb_state != SBIDLE) | clk_override;
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assign bus_clken = (sb_axi_awvalid | sb_axi_wvalid | sb_axi_arvalid | sb_axi_bvalid | sb_axi_rvalid | clk_override) & dbg_bus_clk_en;
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rvoclkhdr dbg_free_cgc (.en(dbg_free_clken), .l1clk(dbg_free_clk), .*);
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@ -317,8 +363,9 @@ module dbg (
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// rest all the bits are zeroed out
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// dmactive flop is reset based on core rst_l, all other flops use dm_rst_l
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assign dmcontrol_wren = (dmi_reg_addr == 7'h10) & dmi_reg_en & dmi_reg_wr_en;
|
||||
assign dmcontrol_reg[29] = '0;
|
||||
assign dmcontrol_reg[29] = '0;
|
||||
assign dmcontrol_reg[27:2] = '0;
|
||||
assign resumereq = dmcontrol_reg[30] & ~dmcontrol_reg[31] & dmcontrol_wren_Q;
|
||||
rvdffs #(4) dmcontrolff (.din({dmi_reg_wdata[31:30],dmi_reg_wdata[28],dmi_reg_wdata[1]}), .dout({dmcontrol_reg[31:30], dmcontrol_reg[28], dmcontrol_reg[1]}), .en(dmcontrol_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
|
||||
rvdffs #(1) dmcontrol_dmactive_ff (.din(dmi_reg_wdata[0]), .dout(dmcontrol_reg[0]), .en(dmcontrol_wren), .rst_l(dbg_rst_l), .clk(dbg_free_clk));
|
||||
rvdff #(1) dmcontrol_wrenff(.din(dmcontrol_wren), .dout(dmcontrol_wren_Q), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
|
||||
|
|
@ -326,7 +373,6 @@ module dbg (
|
|||
// dmstatus register bits that are implemented
|
||||
// [19:18]-havereset,[17:16]-resume ack, [9:8]-halted, [3:0]-version
|
||||
// rest all the bits are zeroed out
|
||||
//assign dmstatus_wren = (dmi_reg_addr == 32'h11) & dmi_reg_en;
|
||||
assign dmstatus_reg[31:20] = '0;
|
||||
assign dmstatus_reg[19:18] = {2{dmstatus_havereset}};
|
||||
assign dmstatus_reg[15:14] = '0;
|
||||
|
|
@ -338,7 +384,7 @@ module dbg (
|
|||
assign dmstatus_reg[9:8] = {2{dmstatus_halted}};
|
||||
assign dmstatus_reg[3:0] = 4'h2;
|
||||
|
||||
assign dmstatus_resumeack_wren = ((dbg_state == RESUMING) & dec_tlu_resume_ack) | (dmstatus_resumeack & ~dmcontrol_reg[30]);
|
||||
assign dmstatus_resumeack_wren = ((dbg_state == RESUMING) & dec_tlu_resume_ack) | (dmstatus_resumeack & resumereq & dmstatus_halted);
|
||||
assign dmstatus_resumeack_din = (dbg_state == RESUMING) & dec_tlu_resume_ack;
|
||||
|
||||
assign dmstatus_havereset_wren = (dmi_reg_addr == 7'h10) & dmi_reg_wdata[1] & dmi_reg_en & dmi_reg_wr_en;
|
||||
|
|
@ -361,60 +407,77 @@ module dbg (
|
|||
assign abstractcs_reg[11] = '0;
|
||||
assign abstractcs_reg[7:4] = '0;
|
||||
assign abstractcs_reg[3:0] = 4'h2; // One data register
|
||||
assign abstractcs_error_sel0 = abstractcs_reg[12] & dmi_reg_en & ((dmi_reg_wr_en & ( (dmi_reg_addr == 7'h16) | (dmi_reg_addr == 7'h17))) | (dmi_reg_addr == 7'h4));
|
||||
assign abstractcs_error_sel1 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h17) &
|
||||
((~((dmi_reg_wdata[31:24] == 8'b0) | (dmi_reg_wdata[31:24] == 8'h2))) | // Illegal command
|
||||
((dmi_reg_wdata[22:20] != 3'b010) & ((dmi_reg_wdata[31:24] == 8'h2) | ((dmi_reg_wdata[31:24] == 8'h0) & dmi_reg_wdata[17]))) | // Illegal size
|
||||
((dmi_reg_wdata[31:24] == 8'h0) & (dmi_reg_wdata[19] | dmi_reg_wdata[18])) | //aarpostincrement/postexec for abstract register access
|
||||
((dmi_reg_wdata[31:24] == 8'h2) & dmi_reg_wdata[19])); //aampostincrement for abstract memory access
|
||||
assign abstractcs_error_sel2 = core_dbg_cmd_done & core_dbg_cmd_fail;
|
||||
assign abstractcs_error_sel3 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h17) & (dbg_state != HALTED);
|
||||
assign abstractcs_error_sel4 = (dmi_reg_addr == 7'h17) & dmi_reg_en & dmi_reg_wr_en & ((dmi_reg_wdata[31:24] == 8'h2) && (|data1_reg[1:0])); //Unaligned address for abstract memory
|
||||
assign abstractcs_error_sel0 = abstractcs_reg[12] & ~(|abstractcs_reg[10:8]) & dmi_reg_en & ((dmi_reg_wr_en & ((dmi_reg_addr == 7'h16) | (dmi_reg_addr == 7'h17)) | (dmi_reg_addr == 7'h18)) |
|
||||
(dmi_reg_addr == 7'h4) | (dmi_reg_addr == 7'h5));
|
||||
assign abstractcs_error_sel1 = execute_command & ~(|abstractcs_reg[10:8]) &
|
||||
((~((command_reg[31:24] == 8'b0) | (command_reg[31:24] == 8'h2))) | // Illegal command
|
||||
(((command_reg[22:20] == 3'b011) | (command_reg[22])) & (command_reg[31:24] == 8'h2)) | // Illegal abstract memory size (can't be DW or higher)
|
||||
((command_reg[22:20] != 3'b010) & ((command_reg[31:24] == 8'h0) & command_reg[17])) | // Illegal abstract reg size
|
||||
((command_reg[31:24] == 8'h0) & command_reg[18])); //postexec for abstract register access
|
||||
assign abstractcs_error_sel2 = ((core_dbg_cmd_done & core_dbg_cmd_fail) | // exception from core
|
||||
(execute_command & (command_reg[31:24] == 8'h0) & // unimplemented regs
|
||||
(((command_reg[15:12] == 4'h1) & (command_reg[11:5] != 0)) | (command_reg[15:13] != 0)))) & ~(|abstractcs_reg[10:8]);
|
||||
assign abstractcs_error_sel3 = execute_command & (dbg_state != HALTED) & ~(|abstractcs_reg[10:8]);
|
||||
assign abstractcs_error_sel4 = dbg_sb_bus_error & dbg_bus_clk_en & ~(|abstractcs_reg[10:8]);// sb bus error for abstract memory command
|
||||
assign abstractcs_error_sel5 = execute_command & (command_reg[31:24] == 8'h2) & ~(|abstractcs_reg[10:8]) &
|
||||
(((command_reg[22:20] == 3'b001) & data1_reg[0]) | ((command_reg[22:20] == 3'b010) & (|data1_reg[1:0]))); //Unaligned address for abstract memory
|
||||
|
||||
assign abstractcs_error_sel5 = (dmi_reg_addr == 7'h16) & dmi_reg_en & dmi_reg_wr_en;
|
||||
assign abstractcs_error_sel6 = (dmi_reg_addr == 7'h16) & dmi_reg_en & dmi_reg_wr_en;
|
||||
|
||||
assign abstractcs_error_selor = abstractcs_error_sel0 | abstractcs_error_sel1 | abstractcs_error_sel2 | abstractcs_error_sel3 | abstractcs_error_sel4 | abstractcs_error_sel5;
|
||||
|
||||
assign abstractcs_error_din[2:0] = abstractcs_error_sel0 ? 3'b001 : // writing command or abstractcs while a command was executing. Or accessing data0
|
||||
abstractcs_error_sel1 ? 3'b010 : // writing a illegal command type to cmd field of command
|
||||
abstractcs_error_sel2 ? 3'b011 : // exception while running command
|
||||
abstractcs_error_sel3 ? 3'b100 : // writing a comnand when not in the halted state
|
||||
abstractcs_error_sel4 ? 3'b111 : // unaligned or illegal size abstract memory command
|
||||
abstractcs_error_sel5 ? (~dmi_reg_wdata[10:8] & abstractcs_reg[10:8]) : //W1C
|
||||
abstractcs_reg[10:8]; //hold
|
||||
assign abstractcs_error_din[2:0] = abstractcs_error_sel0 ? 3'b001 : // writing command or abstractcs while a command was executing. Or accessing data0
|
||||
abstractcs_error_sel1 ? 3'b010 : // writing a illegal command type to cmd field of command
|
||||
abstractcs_error_sel2 ? 3'b011 : // exception while running command
|
||||
abstractcs_error_sel3 ? 3'b100 : // writing a comnand when not in the halted state
|
||||
abstractcs_error_sel4 ? 3'b101 : // Bus error
|
||||
abstractcs_error_sel5 ? 3'b111 : // unaligned or illegal size abstract memory command
|
||||
abstractcs_error_sel6 ? (~dmi_reg_wdata[10:8] & abstractcs_reg[10:8]) : //W1C
|
||||
abstractcs_reg[10:8]; //hold
|
||||
|
||||
rvdffs #(1) dmabstractcs_busy_reg (.din(abstractcs_busy_din), .dout(abstractcs_reg[12]), .en(abstractcs_busy_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
|
||||
rvdff #(3) dmabstractcs_error_reg (.din(abstractcs_error_din[2:0]), .dout(abstractcs_reg[10:8]), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
|
||||
|
||||
// abstract auto reg
|
||||
assign abstractauto_reg_wren = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h18) & ~abstractcs_reg[12];
|
||||
rvdffs #(2) dbg_abstractauto_reg (.*, .din(dmi_reg_wdata[1:0]), .dout(abstractauto_reg[1:0]), .en(abstractauto_reg_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
|
||||
|
||||
// command register - implemented all the bits in this register
|
||||
// command[16] = 1: write, 0: read
|
||||
assign command_wren = (dmi_reg_addr == 7'h17) & dmi_reg_en & dmi_reg_wr_en & (dbg_state == HALTED);
|
||||
assign command_postexec_din = (dmi_reg_wdata[31:24] == 8'h0) & dmi_reg_wdata[18];
|
||||
assign command_transfer_din = (dmi_reg_wdata[31:24] == 8'h0) & dmi_reg_wdata[17];
|
||||
assign command_din[31:0] = {dmi_reg_wdata[31:24],1'b0,dmi_reg_wdata[22:19],command_postexec_din,command_transfer_din, dmi_reg_wdata[16:0]};
|
||||
rvdffe #(32) dmcommand_reg (.*, .din(command_din[31:0]), .dout(command_reg[31:0]), .en(command_wren), .rst_l(dbg_dm_rst_l));
|
||||
assign execute_command_ns = command_wren |
|
||||
(dmi_reg_en & ~abstractcs_reg[12] & (((dmi_reg_addr == 7'h4) & abstractauto_reg[0]) | ((dmi_reg_addr == 7'h5) & abstractauto_reg[1])));
|
||||
assign command_wren = (dmi_reg_addr == 7'h17) & dmi_reg_en & dmi_reg_wr_en;
|
||||
//assign command_wren = (dmi_reg_addr == 7'h17) & dmi_reg_en & dmi_reg_wr_en & (dbg_state == HALTED) & ~abstractcs_reg[12];
|
||||
assign command_regno_wren = command_wren | ((command_reg[31:24] == 8'h0) & command_reg[19] & (dbg_state == CMD_DONE) & ~(|abstractcs_reg[10:8])); // aarpostincrement
|
||||
assign command_postexec_din = (dmi_reg_wdata[31:24] == 8'h0) & dmi_reg_wdata[18];
|
||||
assign command_transfer_din = (dmi_reg_wdata[31:24] == 8'h0) & dmi_reg_wdata[17];
|
||||
assign command_din[31:16] = {dmi_reg_wdata[31:24],1'b0,dmi_reg_wdata[22:19],command_postexec_din,command_transfer_din, dmi_reg_wdata[16]};
|
||||
assign command_din[15:0] = command_wren ? dmi_reg_wdata[15:0] : dbg_cmd_next_addr[15:0];
|
||||
rvdff #(1) execute_commandff (.*, .din(execute_command_ns), .dout(execute_command), .clk(dbg_free_clk), .rst_l(dbg_dm_rst_l));
|
||||
rvdffe #(16) dmcommand_reg (.*, .din(command_din[31:16]), .dout(command_reg[31:16]), .en(command_wren), .rst_l(dbg_dm_rst_l));
|
||||
rvdffe #(16) dmcommand_regno_reg (.*, .din(command_din[15:0]), .dout(command_reg[15:0]), .en(command_regno_wren), .rst_l(dbg_dm_rst_l));
|
||||
|
||||
// data0 reg
|
||||
assign data0_reg_wren0 = (dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h4) & (dbg_state == HALTED));
|
||||
assign data0_reg_wren1 = core_dbg_cmd_done & (dbg_state == CMD_WAIT) & ~command_reg[16];
|
||||
assign data0_reg_wren = data0_reg_wren0 | data0_reg_wren1;
|
||||
assign data0_reg_wren0 = (dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h4) & (dbg_state == HALTED) & ~abstractcs_reg[12]);
|
||||
assign data0_reg_wren1 = core_dbg_cmd_done & (dbg_state == CORE_CMD_WAIT) & ~command_reg[16];
|
||||
assign data0_reg_wren = data0_reg_wren0 | data0_reg_wren1 | data0_reg_wren2;
|
||||
|
||||
assign data0_din[31:0] = ({32{data0_reg_wren0}} & dmi_reg_wdata[31:0]) |
|
||||
({32{data0_reg_wren1}} & core_dbg_rddata[31:0]);
|
||||
assign data0_din[31:0] = ({32{data0_reg_wren0}} & dmi_reg_wdata[31:0]) |
|
||||
({32{data0_reg_wren1}} & core_dbg_rddata[31:0]) |
|
||||
({32{data0_reg_wren2}} & sb_bus_rdata[31:0]);
|
||||
|
||||
rvdffe #(32) dbg_data0_reg (.*, .din(data0_din[31:0]), .dout(data0_reg[31:0]), .en(data0_reg_wren), .rst_l(dbg_dm_rst_l));
|
||||
|
||||
// data 1
|
||||
assign data1_reg_wren0 = (dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h5) & (dbg_state == HALTED));
|
||||
assign data1_reg_wren1 = 1'b0; // core_dbg_cmd_done & (dbg_state == CMD_WAIT) & ~command_reg[16];
|
||||
assign data1_reg_wren0 = (dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h5) & (dbg_state == HALTED) & ~abstractcs_reg[12]);
|
||||
assign data1_reg_wren1 = (dbg_state == CMD_DONE) & (command_reg[31:24] == 8'h2) & command_reg[19] & ~(|abstractcs_reg[10:8]); // aampostincrement
|
||||
assign data1_reg_wren = data1_reg_wren0 | data1_reg_wren1;
|
||||
|
||||
assign data1_din[31:0] = ({32{data1_reg_wren0}} & dmi_reg_wdata[31:0]);
|
||||
//({32{data0_reg_wren1}} & core_dbg_rddata[31:0]);
|
||||
assign data1_din[31:0] = ({32{data1_reg_wren0}} & dmi_reg_wdata[31:0]) |
|
||||
({32{data1_reg_wren1}} & dbg_cmd_next_addr[31:0]);
|
||||
|
||||
rvdffe #(32) dbg_data1_reg (.*, .din(data1_din[31:0]), .dout(data1_reg[31:0]), .en(data1_reg_wren), .rst_l(dbg_dm_rst_l));
|
||||
|
||||
rvdffs #(1) sb_abmem_cmd_doneff (.din(sb_abmem_cmd_done_in), .dout(sb_abmem_cmd_done), .en(sb_abmem_cmd_done_en), .clk(dbg_free_clk), .rst_l(dbg_dm_rst_l), .*);
|
||||
rvdffs #(1) sb_abmem_data_doneff (.din(sb_abmem_data_done_in), .dout(sb_abmem_data_done), .en(sb_abmem_data_done_en), .clk(dbg_free_clk), .rst_l(dbg_dm_rst_l), .*);
|
||||
|
||||
// FSM to control the debug mode entry, command send/recieve, and Resume flow.
|
||||
always_comb begin
|
||||
|
|
@ -424,13 +487,18 @@ module dbg (
|
|||
abstractcs_busy_din = 1'b0;
|
||||
dbg_halt_req = dmcontrol_wren_Q & dmcontrol_reg[31] & ~dmcontrol_reg[1]; // single pulse output to the core. Need to drive every time this register is written since core might be halted due to MPC
|
||||
dbg_resume_req = 1'b0; // single pulse output to the core
|
||||
dbg_sb_bus_error = 1'b0;
|
||||
data0_reg_wren2 = 1'b0;
|
||||
sb_abmem_cmd_done_in = 1'b0;
|
||||
sb_abmem_data_done_in = 1'b0;
|
||||
sb_abmem_cmd_done_en = 1'b0;
|
||||
sb_abmem_data_done_en = 1'b0;
|
||||
|
||||
case (dbg_state)
|
||||
IDLE: begin
|
||||
dbg_nxtstate = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING; // initiate the halt command to the core
|
||||
dbg_state_en = ((dmcontrol_reg[31] & ~dec_tlu_debug_mode) | dmstatus_reg[9] | dec_tlu_mpc_halted_only) & ~dmcontrol_reg[1]; // when the jtag writes the halt bit in the DM register, OR when the status indicates Halted
|
||||
dbg_halt_req = dmcontrol_reg[31] & ~dmcontrol_reg[1]; // Removed debug mode qualification during MPC changes
|
||||
//dbg_halt_req = dmcontrol_reg[31] & ~dec_tlu_debug_mode; // only when jtag has written the halt_req bit in the control
|
||||
end
|
||||
HALTING : begin
|
||||
dbg_nxtstate = dmcontrol_reg[1] ? IDLE : HALTED; // Goto HALTED once the core sends an ACK
|
||||
|
|
@ -438,28 +506,49 @@ module dbg (
|
|||
end
|
||||
HALTED: begin
|
||||
// wait for halted to go away before send to resume. Else start of new command
|
||||
dbg_nxtstate = (dmstatus_reg[9] & ~dmcontrol_reg[1]) ? ((dmcontrol_reg[30] & ~dmcontrol_reg[31]) ? RESUMING : CMD_START) :
|
||||
dbg_nxtstate = (dmstatus_reg[9] & ~dmcontrol_reg[1]) ? (resumereq ? RESUMING : (((command_reg[31:24] == 8'h2) & abmem_addr_external) ? SB_CMD_START : CORE_CMD_START)) :
|
||||
(dmcontrol_reg[31] ? HALTING : IDLE); // This is MPC halted case
|
||||
//dbg_nxtstate = dmcontrol_reg[1] ? IDLE : (dmcontrol_reg[30] & ~dmcontrol_reg[31]) ? RESUMING : CMD_START; // wait for halted to go away before send to resume. Else start of new command
|
||||
dbg_state_en = (dmstatus_reg[9] & dmcontrol_reg[30] & ~dmcontrol_reg[31] & dmcontrol_wren_Q) | command_wren | dmcontrol_reg[1] | ~(dmstatus_reg[9] | dec_tlu_mpc_halted_only);
|
||||
abstractcs_busy_wren = dbg_state_en & (dbg_nxtstate == CMD_START); // write busy when a new command was written by jtag
|
||||
dbg_state_en = (dmstatus_reg[9] & resumereq) | execute_command | dmcontrol_reg[1] | ~(dmstatus_reg[9] | dec_tlu_mpc_halted_only);
|
||||
abstractcs_busy_wren = dbg_state_en & ((dbg_nxtstate == CORE_CMD_START) | (dbg_nxtstate == SB_CMD_START)); // write busy when a new command was written by jtag
|
||||
abstractcs_busy_din = 1'b1;
|
||||
dbg_resume_req = dbg_state_en & (dbg_nxtstate == RESUMING); // single cycle pulse to core if resuming
|
||||
end
|
||||
CMD_START: begin
|
||||
CORE_CMD_START: begin
|
||||
// Don't execute the command if cmderror or transfer=0 for abstract register access
|
||||
dbg_nxtstate = dmcontrol_reg[1] ? IDLE : ((|abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h0) & ~command_reg[17])) ? CMD_DONE : CMD_WAIT; // new command sent to the core
|
||||
dbg_nxtstate = dmcontrol_reg[1] ? IDLE : ((|abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h0) & ~command_reg[17])) ? CMD_DONE : CORE_CMD_WAIT; // new command sent to the core
|
||||
dbg_state_en = dbg_cmd_valid | (|abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h0) & ~command_reg[17]) | dmcontrol_reg[1];
|
||||
end
|
||||
CMD_WAIT: begin
|
||||
CORE_CMD_WAIT: begin
|
||||
dbg_nxtstate = dmcontrol_reg[1] ? IDLE : CMD_DONE;
|
||||
dbg_state_en = core_dbg_cmd_done | dmcontrol_reg[1]; // go to done state for one cycle after completing current command
|
||||
end
|
||||
SB_CMD_START: begin
|
||||
dbg_nxtstate = dmcontrol_reg[1] ? IDLE : (|abstractcs_reg[10:8]) ? CMD_DONE : SB_CMD_SEND;
|
||||
dbg_state_en = (dbg_bus_clk_en & ~sb_cmd_pending) | (|abstractcs_reg[10:8]) | dmcontrol_reg[1];
|
||||
end
|
||||
SB_CMD_SEND: begin
|
||||
sb_abmem_cmd_done_in = 1'b1;
|
||||
sb_abmem_data_done_in= 1'b1;
|
||||
sb_abmem_cmd_done_en = ((sb_axi_awvalid & sb_axi_awready) | (sb_axi_arvalid & sb_axi_arready)) & dbg_bus_clk_en;
|
||||
sb_abmem_data_done_en= ((sb_axi_wvalid & sb_axi_wready) | (sb_axi_arvalid & sb_axi_arready)) & dbg_bus_clk_en;
|
||||
dbg_nxtstate = dmcontrol_reg[1] ? IDLE : SB_CMD_RESP;
|
||||
dbg_state_en = (sb_abmem_cmd_done | sb_abmem_cmd_done_en) & (sb_abmem_data_done | sb_abmem_data_done_en) & dbg_bus_clk_en;
|
||||
end
|
||||
SB_CMD_RESP: begin
|
||||
dbg_nxtstate = dmcontrol_reg[1] ? IDLE : CMD_DONE;
|
||||
dbg_state_en = ((sb_axi_rvalid & sb_axi_rready) | (sb_axi_bvalid & sb_axi_bready)) & dbg_bus_clk_en;
|
||||
dbg_sb_bus_error = ((sb_axi_rvalid & sb_axi_rready & sb_axi_rresp[1]) | (sb_axi_bvalid & sb_axi_bready & sb_axi_bresp[1])) & dbg_bus_clk_en;
|
||||
data0_reg_wren2 = dbg_state_en & ~sb_abmem_cmd_write & ~dbg_sb_bus_error;
|
||||
end
|
||||
CMD_DONE: begin
|
||||
dbg_nxtstate = dmcontrol_reg[1] ? IDLE : HALTED;
|
||||
dbg_state_en = 1'b1;
|
||||
abstractcs_busy_wren = dbg_state_en; // remove the busy bit from the abstracts ( bit 12 )
|
||||
abstractcs_busy_din = 1'b0;
|
||||
sb_abmem_cmd_done_in = 1'b0;
|
||||
sb_abmem_data_done_in= 1'b0;
|
||||
sb_abmem_cmd_done_en = 1'b1;
|
||||
sb_abmem_data_done_en= 1'b1;
|
||||
end
|
||||
RESUMING : begin
|
||||
dbg_nxtstate = IDLE;
|
||||
|
|
@ -482,6 +571,7 @@ module dbg (
|
|||
({32{dmi_reg_addr == 7'h11}} & dmstatus_reg[31:0]) |
|
||||
({32{dmi_reg_addr == 7'h16}} & abstractcs_reg[31:0]) |
|
||||
({32{dmi_reg_addr == 7'h17}} & command_reg[31:0]) |
|
||||
({32{dmi_reg_addr == 7'h18}} & {30'h0,abstractauto_reg[1:0]}) |
|
||||
({32{dmi_reg_addr == 7'h40}} & haltsum0_reg[31:0]) |
|
||||
({32{dmi_reg_addr == 7'h38}} & sbcs_reg[31:0]) |
|
||||
({32{dmi_reg_addr == 7'h39}} & sbaddress0_reg[31:0]) |
|
||||
|
|
@ -494,16 +584,40 @@ module dbg (
|
|||
// rvdff #(1) dmi_ack_reg (.din(dmi_reg_en), .dout(dmi_reg_ack), .rst_l(rst_l), .clk(free_clk));
|
||||
rvdffs #(32) dmi_rddata_reg(.din(dmi_reg_rdata_din), .dout(dmi_reg_rdata), .en(dmi_reg_en), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
|
||||
|
||||
assign abmem_addr[31:0] = data1_reg[31:0];
|
||||
assign abmem_addr_core_local = (abmem_addr_in_dccm_region | abmem_addr_in_iccm_region | abmem_addr_in_pic_region);
|
||||
assign abmem_addr_external = ~abmem_addr_core_local;
|
||||
|
||||
assign abmem_addr_in_dccm_region = (abmem_addr[31:28] == `RV_DCCM_REGION) & DCCM_ENABLE;
|
||||
assign abmem_addr_in_iccm_region = (abmem_addr[31:28] == `RV_ICCM_REGION) & ICCM_ENABLE;
|
||||
assign abmem_addr_in_pic_region = (abmem_addr[31:28] == `RV_PIC_REGION);
|
||||
|
||||
// interface for the core
|
||||
assign dbg_cmd_addr[31:0] = (command_reg[31:24] == 8'h2) ? {data1_reg[31:2],2'b0} : {20'b0, command_reg[11:0]}; // Only word addresses for abstract memory
|
||||
assign dbg_cmd_wrdata[31:0] = data0_reg[31:0];
|
||||
assign dbg_cmd_valid = (dbg_state == CMD_START) & ~((|abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h0) & ~command_reg[17])) & dma_dbg_ready;
|
||||
assign dbg_cmd_write = command_reg[16];
|
||||
assign dbg_cmd_type[1:0] = (command_reg[31:24] == 8'h2) ? 2'b10 : {1'b0, (command_reg[15:12] == 4'b0)};
|
||||
assign dbg_cmd_size[1:0] = command_reg[21:20];
|
||||
assign dbg_cmd_addr[31:0] = (command_reg[31:24] == 8'h2) ? data1_reg[31:0] : {20'b0, command_reg[11:0]};
|
||||
assign dbg_cmd_wrdata[31:0] = data0_reg[31:0];
|
||||
assign dbg_cmd_valid = (dbg_state == CORE_CMD_START) & ~((|abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h0) & ~command_reg[17]) | ((command_reg[31:24] == 8'h2) & abmem_addr_external)) & dma_dbg_ready;
|
||||
assign dbg_cmd_write = command_reg[16];
|
||||
assign dbg_cmd_type[1:0] = (command_reg[31:24] == 8'h2) ? 2'b10 : {1'b0, (command_reg[15:12] == 4'b0)};
|
||||
assign dbg_cmd_size[1:0] = command_reg[21:20];
|
||||
|
||||
assign dbg_cmd_addr_incr[3:0] = (command_reg[31:24] == 8'h2) ? (4'h1 << sb_abmem_cmd_size[1:0]) : 4'h1;
|
||||
assign dbg_cmd_curr_addr[31:0] = (command_reg[31:24] == 8'h2) ? data1_reg[31:0] : {16'b0, command_reg[15:0]};
|
||||
assign dbg_cmd_next_addr[31:0] = dbg_cmd_curr_addr[31:0] + {28'h0,dbg_cmd_addr_incr[3:0]};
|
||||
|
||||
assign sb_abmem_cmd_awvalid = (dbg_state == SB_CMD_SEND) & sb_abmem_cmd_write & ~sb_abmem_cmd_done;
|
||||
assign sb_abmem_cmd_wvalid = (dbg_state == SB_CMD_SEND) & sb_abmem_cmd_write & ~sb_abmem_data_done;
|
||||
assign sb_abmem_cmd_arvalid = (dbg_state == SB_CMD_SEND) & ~sb_abmem_cmd_write & ~sb_abmem_cmd_done & ~sb_abmem_data_done;
|
||||
assign sb_abmem_read_pend = (dbg_state == SB_CMD_RESP) & ~sb_abmem_cmd_write;
|
||||
assign sb_abmem_cmd_write = command_reg[16];
|
||||
assign sb_abmem_cmd_size[2:0] = {1'b0, command_reg[21:20]};
|
||||
assign sb_abmem_cmd_addr[31:0] = abmem_addr[31:0];
|
||||
assign sb_abmem_cmd_wdata[31:0] = data0_reg[31:0];
|
||||
|
||||
// Ask DMA to stop taking bus trxns since debug request is done
|
||||
assign dbg_dma_bubble = ((dbg_state == CMD_START) & ~(|abstractcs_reg[10:8])) | (dbg_state == CMD_WAIT);
|
||||
assign dbg_dma_bubble = ((dbg_state == CORE_CMD_START) & ~(|abstractcs_reg[10:8])) | (dbg_state == CORE_CMD_WAIT);
|
||||
|
||||
assign sb_cmd_pending = (sb_state == CMD_RD) | (sb_state == CMD_WR) | (sb_state == CMD_WR_ADDR) | (sb_state == CMD_WR_DATA) | (sb_state == RSP_RD) | (sb_state == RSP_WR);
|
||||
assign sb_abmem_cmd_pending = (dbg_state == SB_CMD_START) | (dbg_state == SB_CMD_SEND) | (dbg_state== SB_CMD_RESP);
|
||||
|
||||
// system bus FSM
|
||||
always_comb begin
|
||||
|
|
@ -517,7 +631,7 @@ module dbg (
|
|||
case (sb_state)
|
||||
SBIDLE: begin
|
||||
sb_nxtstate = sbdata0wr_access ? WAIT_WR : WAIT_RD;
|
||||
sb_state_en = sbdata0wr_access | sbreadondata_access | sbreadonaddr_access;
|
||||
sb_state_en = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]);
|
||||
sbcs_sbbusy_wren = sb_state_en; // set the single read bit if it is a singlread command
|
||||
sbcs_sbbusy_din = 1'b1;
|
||||
sbcs_sberror_wren = sbcs_wren & (|dmi_reg_wdata[14:12]); // write to clear the error bits
|
||||
|
|
@ -525,42 +639,42 @@ module dbg (
|
|||
end
|
||||
WAIT_RD: begin
|
||||
sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_RD;
|
||||
sb_state_en = dbg_bus_clk_en | sbcs_unaligned | sbcs_illegal_size;
|
||||
sb_state_en = (dbg_bus_clk_en & ~sb_abmem_cmd_pending) | sbcs_unaligned | sbcs_illegal_size;
|
||||
sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size;
|
||||
sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100;
|
||||
end
|
||||
WAIT_WR: begin
|
||||
sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_WR;
|
||||
sb_state_en = dbg_bus_clk_en | sbcs_unaligned | sbcs_illegal_size;
|
||||
sb_state_en = (dbg_bus_clk_en & ~sb_abmem_cmd_pending) | sbcs_unaligned | sbcs_illegal_size;
|
||||
sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size;
|
||||
sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100;
|
||||
end
|
||||
CMD_RD : begin
|
||||
sb_nxtstate = RSP_RD;
|
||||
sb_state_en = sb_axi_arvalid_q & sb_axi_arready_q & dbg_bus_clk_en;
|
||||
sb_state_en = sb_axi_arvalid & sb_axi_arready & dbg_bus_clk_en;
|
||||
end
|
||||
CMD_WR : begin
|
||||
sb_nxtstate = (sb_axi_awready_q & sb_axi_wready_q) ? RSP_WR : (sb_axi_awready_q ? CMD_WR_DATA : CMD_WR_ADDR);
|
||||
sb_state_en = ((sb_axi_awvalid_q & sb_axi_awready_q) | (sb_axi_wvalid_q & sb_axi_wready_q)) & dbg_bus_clk_en;
|
||||
sb_nxtstate = (sb_axi_awready & sb_axi_wready) ? RSP_WR : (sb_axi_awready ? CMD_WR_DATA : CMD_WR_ADDR);
|
||||
sb_state_en = ((sb_axi_awvalid & sb_axi_awready) | (sb_axi_wvalid & sb_axi_wready)) & dbg_bus_clk_en;
|
||||
end
|
||||
CMD_WR_ADDR : begin
|
||||
sb_nxtstate = RSP_WR;
|
||||
sb_state_en = sb_axi_awvalid_q & sb_axi_awready_q & dbg_bus_clk_en;
|
||||
sb_state_en = sb_axi_awvalid & sb_axi_awready & dbg_bus_clk_en;
|
||||
end
|
||||
CMD_WR_DATA : begin
|
||||
sb_nxtstate = RSP_WR;
|
||||
sb_state_en = sb_axi_wvalid_q & sb_axi_wready_q & dbg_bus_clk_en;
|
||||
sb_state_en = sb_axi_wvalid & sb_axi_wready & dbg_bus_clk_en;
|
||||
end
|
||||
RSP_RD: begin
|
||||
sb_nxtstate = DONE;
|
||||
sb_state_en = sb_axi_rvalid_q & sb_axi_rready_q & dbg_bus_clk_en;
|
||||
sbcs_sberror_wren = sb_state_en & sb_axi_rresp_q[1];
|
||||
sb_state_en = sb_axi_rvalid & sb_axi_rready & dbg_bus_clk_en;
|
||||
sbcs_sberror_wren = sb_state_en & sb_axi_rresp[1];
|
||||
sbcs_sberror_din[2:0] = 3'b010;
|
||||
end
|
||||
RSP_WR: begin
|
||||
sb_nxtstate = DONE;
|
||||
sb_state_en = sb_axi_bvalid_q & sb_axi_bready_q & dbg_bus_clk_en;
|
||||
sbcs_sberror_wren = sb_state_en & sb_axi_bresp_q[1];
|
||||
sb_state_en = sb_axi_bvalid & sb_axi_bready & dbg_bus_clk_en;
|
||||
sbcs_sberror_wren = sb_state_en & sb_axi_bresp[1];
|
||||
sbcs_sberror_din[2:0] = 3'b010;
|
||||
end
|
||||
DONE: begin
|
||||
|
|
@ -584,8 +698,6 @@ module dbg (
|
|||
|
||||
rvdffs #($bits(sb_state_t)) sb_state_reg (.din(sb_nxtstate), .dout({sb_state}), .en(sb_state_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
|
||||
|
||||
//rvdff #(.WIDTH(1)) bus_clken_ff (.din(dbg_bus_clk_en), .dout(dbg_bus_clk_en_q), .rst_l(dbg_dm_rst_l), .clk(dbg_sb_c2_free_clk), .*);
|
||||
|
||||
rvdff_fpga #(2) axi_bresp_ff (.din(sb_axi_bresp[1:0]), .dout(sb_axi_bresp_q[1:0]), .rst_l(dbg_dm_rst_l), .clk(bus_clk), .clken(bus_clken), .rawclk(clk), .*);
|
||||
rvdff_fpga #(2) axi_rresp_ff (.din(sb_axi_rresp[1:0]), .dout(sb_axi_rresp_q[1:0]), .rst_l(dbg_dm_rst_l), .clk(bus_clk), .clken(bus_clken), .rawclk(clk), .*);
|
||||
|
||||
|
|
@ -600,39 +712,50 @@ module dbg (
|
|||
rvdffs #(.WIDTH(1)) axi_bready_ff (.din(sb_axi_bready), .dout(sb_axi_bready_q), .en(dbg_bus_clk_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk), .*);
|
||||
rvdffs #(.WIDTH(1)) axi_rvalid_ff (.din(sb_axi_rvalid), .dout(sb_axi_rvalid_q), .en(dbg_bus_clk_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk), .*);
|
||||
rvdffs #(.WIDTH(1)) axi_rready_ff (.din(sb_axi_rready), .dout(sb_axi_rready_q), .en(dbg_bus_clk_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk), .*);
|
||||
rvdffe #(.WIDTH(64)) axi_rdata_ff (.din(sb_axi_rdata[63:0]), .dout(sb_axi_rdata_q[63:0]), .rst_l(dbg_dm_rst_l), .en(bus_clken), .*);
|
||||
|
||||
assign sb_cmd_awvalid = ((sb_state == CMD_WR) | (sb_state == CMD_WR_ADDR));
|
||||
assign sb_cmd_wvalid = ((sb_state == CMD_WR) | (sb_state == CMD_WR_DATA));
|
||||
assign sb_cmd_arvalid = (sb_state == CMD_RD);
|
||||
assign sb_read_pend = (sb_state == RSP_RD);
|
||||
assign sb_cmd_size[2:0] = sbcs_reg[19:17];
|
||||
assign sb_cmd_wdata[63:0] = {sbdata1_reg[31:0], sbdata0_reg[31:0]};
|
||||
assign sb_cmd_addr[31:0] = sbaddress0_reg[31:0];
|
||||
|
||||
assign sb_axi_size[2:0] = (sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid | sb_abmem_cmd_arvalid | sb_abmem_read_pend) ? sb_abmem_cmd_size[2:0] : sb_cmd_size[2:0];
|
||||
assign sb_axi_addr[31:0] = (sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid | sb_abmem_cmd_arvalid | sb_abmem_read_pend) ? sb_abmem_cmd_addr[31:0] : sb_cmd_addr[31:0];
|
||||
assign sb_axi_wrdata[63:0] = (sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid) ? {2{sb_abmem_cmd_wdata[31:0]}} : sb_cmd_wdata[63:0];
|
||||
|
||||
// AXI Request signals
|
||||
assign sb_axi_awvalid = ((sb_state == CMD_WR) | (sb_state == CMD_WR_ADDR)) & ~(sb_axi_awvalid_q & sb_axi_awready_q);
|
||||
assign sb_axi_awaddr[31:0] = sbaddress0_reg[31:0];
|
||||
assign sb_axi_awvalid = sb_abmem_cmd_awvalid | sb_cmd_awvalid;
|
||||
assign sb_axi_awaddr[31:0] = sb_axi_addr[31:0];
|
||||
assign sb_axi_awid[SB_BUS_TAG-1:0] = '0;
|
||||
assign sb_axi_awsize[2:0] = sbcs_reg[19:17];
|
||||
assign sb_axi_awsize[2:0] = sb_axi_size[2:0];
|
||||
assign sb_axi_awprot[2:0] = '0;
|
||||
assign sb_axi_awcache[3:0] = 4'b1111;
|
||||
assign sb_axi_awregion[3:0] = sbaddress0_reg[31:28];
|
||||
assign sb_axi_awregion[3:0] = sb_axi_addr[31:28];
|
||||
assign sb_axi_awlen[7:0] = '0;
|
||||
assign sb_axi_awburst[1:0] = 2'b01;
|
||||
assign sb_axi_awqos[3:0] = '0;
|
||||
assign sb_axi_awlock = '0;
|
||||
|
||||
assign sb_axi_wvalid = ((sb_state == CMD_WR) | (sb_state == CMD_WR_DATA)) & ~(sb_axi_wvalid_q & sb_axi_wready_q);
|
||||
assign sb_axi_wdata[63:0] = ({64{(sbcs_reg[19:17] == 3'h0)}} & {8{sbdata0_reg[7:0]}}) |
|
||||
({64{(sbcs_reg[19:17] == 3'h1)}} & {4{sbdata0_reg[15:0]}}) |
|
||||
({64{(sbcs_reg[19:17] == 3'h2)}} & {2{sbdata0_reg[31:0]}}) |
|
||||
({64{(sbcs_reg[19:17] == 3'h3)}} & {sbdata1_reg[31:0],sbdata0_reg[31:0]});
|
||||
assign sb_axi_wstrb[7:0] = ({8{(sbcs_reg[19:17] == 3'h0)}} & (8'h1 << sbaddress0_reg[2:0])) |
|
||||
({8{(sbcs_reg[19:17] == 3'h1)}} & (8'h3 << {sbaddress0_reg[2:1],1'b0})) |
|
||||
({8{(sbcs_reg[19:17] == 3'h2)}} & (8'hf << {sbaddress0_reg[2],2'b0})) |
|
||||
({8{(sbcs_reg[19:17] == 3'h3)}} & 8'hff);
|
||||
assign sb_axi_wvalid = sb_abmem_cmd_wvalid | sb_cmd_wvalid;
|
||||
assign sb_axi_wdata[63:0] = ({64{(sb_axi_size[2:0] == 3'h0)}} & {8{sb_axi_wrdata[7:0]}}) |
|
||||
({64{(sb_axi_size[2:0] == 3'h1)}} & {4{sb_axi_wrdata[15:0]}}) |
|
||||
({64{(sb_axi_size[2:0] == 3'h2)}} & {2{sb_axi_wrdata[31:0]}}) |
|
||||
({64{(sb_axi_size[2:0] == 3'h3)}} & {sb_axi_wrdata[63:0]});
|
||||
assign sb_axi_wstrb[7:0] = ({8{(sb_axi_size[2:0] == 3'h0)}} & (8'h1 << sb_axi_addr[2:0])) |
|
||||
({8{(sb_axi_size[2:0] == 3'h1)}} & (8'h3 << {sb_axi_addr[2:1],1'b0})) |
|
||||
({8{(sb_axi_size[2:0] == 3'h2)}} & (8'hf << {sb_axi_addr[2],2'b0})) |
|
||||
({8{(sb_axi_size[2:0] == 3'h3)}} & 8'hff);
|
||||
assign sb_axi_wlast = '1;
|
||||
|
||||
assign sb_axi_arvalid = (sb_state == CMD_RD) & ~(sb_axi_arvalid_q & sb_axi_arready_q);
|
||||
assign sb_axi_araddr[31:0] = sbaddress0_reg[31:0];
|
||||
assign sb_axi_arvalid = sb_abmem_cmd_arvalid | sb_cmd_arvalid;
|
||||
assign sb_axi_araddr[31:0] = sb_axi_addr[31:0];
|
||||
assign sb_axi_arid[SB_BUS_TAG-1:0] = '0;
|
||||
assign sb_axi_arsize[2:0] = sbcs_reg[19:17];
|
||||
assign sb_axi_arsize[2:0] = sb_axi_size[2:0];
|
||||
assign sb_axi_arprot[2:0] = '0;
|
||||
assign sb_axi_arcache[3:0] = 4'b0;
|
||||
assign sb_axi_arregion[3:0] = sbaddress0_reg[31:28];
|
||||
assign sb_axi_arregion[3:0] = sb_axi_addr[31:28];
|
||||
assign sb_axi_arlen[7:0] = '0;
|
||||
assign sb_axi_arburst[1:0] = 2'b01;
|
||||
assign sb_axi_arqos[3:0] = '0;
|
||||
|
|
@ -642,10 +765,10 @@ module dbg (
|
|||
assign sb_axi_bready = 1'b1;
|
||||
|
||||
assign sb_axi_rready = 1'b1;
|
||||
assign sb_bus_rdata[63:0] = ({64{sbcs_reg[19:17] == 3'h0}} & ((sb_axi_rdata_q[63:0] >> 8*sbaddress0_reg[2:0]) & 64'hff)) |
|
||||
({64{sbcs_reg[19:17] == 3'h1}} & ((sb_axi_rdata_q[63:0] >> 16*sbaddress0_reg[2:1]) & 64'hffff)) |
|
||||
({64{sbcs_reg[19:17] == 3'h2}} & ((sb_axi_rdata_q[63:0] >> 32*sbaddress0_reg[2]) & 64'hffff_ffff)) |
|
||||
({64{sbcs_reg[19:17] == 3'h3}} & sb_axi_rdata_q[63:0]);
|
||||
assign sb_bus_rdata[63:0] = ({64{sb_axi_size == 3'h0}} & ((sb_axi_rdata[63:0] >> 8*sb_axi_addr[2:0]) & 64'hff)) |
|
||||
({64{sb_axi_size == 3'h1}} & ((sb_axi_rdata[63:0] >> 16*sb_axi_addr[2:1]) & 64'hffff)) |
|
||||
({64{sb_axi_size == 3'h2}} & ((sb_axi_rdata[63:0] >> 32*sb_axi_addr[2]) & 64'hffff_ffff)) |
|
||||
({64{sb_axi_size == 3'h3}} & sb_axi_rdata[63:0]);
|
||||
|
||||
`ifdef ASSERT_ON
|
||||
// assertion.
|
||||
|
|
|
|||
|
|
@ -198,7 +198,7 @@ csr[ csr_meivt ] = { csr_meivt }
|
|||
csr[ csr_meicurpl ] = { csr_meicurpl }
|
||||
csr[ csr_meicpct ] = { csr_meicpct }
|
||||
csr[ csr_meicidpl ] = { csr_meicidpl }
|
||||
csr[ csr_mpmc ] = { csr_mpmc }
|
||||
csr[ csr_mpmc ] = { csr_mpmc postsync }
|
||||
csr[ csr_mcgc ] = { csr_mcgc }
|
||||
csr[ csr_mgpmc ] = { csr_mgpmc presync postsync }
|
||||
csr[ csr_mcpc ] = { csr_mcpc presync postsync }
|
||||
|
|
|
|||
|
|
@ -106,8 +106,8 @@ module dec
|
|||
|
||||
input logic ifu_i0_icaf, // icache access fault
|
||||
input logic ifu_i1_icaf,
|
||||
input logic ifu_i0_icaf_f1, // i0 has access fault on second fetch group
|
||||
input logic ifu_i1_icaf_f1,
|
||||
input logic ifu_i0_icaf_second, // i0 has access fault on second 2B of 4B inst
|
||||
input logic ifu_i1_icaf_second,
|
||||
input logic ifu_i0_perr, // icache parity error
|
||||
input logic ifu_i1_perr,
|
||||
input logic ifu_i0_sbecc, // icache/iccm single-bit error
|
||||
|
|
@ -482,7 +482,7 @@ module dec
|
|||
logic dec_i0_dbecc_d;
|
||||
logic dec_i1_dbecc_d;
|
||||
|
||||
logic dec_i0_icaf_f1_d;
|
||||
logic dec_i0_icaf_second_d;
|
||||
|
||||
logic dec_i0_decode_d;
|
||||
logic dec_i1_decode_d;
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ module dec_decode_ctl
|
|||
|
||||
input logic dec_i0_icaf_d, // icache access fault
|
||||
input logic dec_i1_icaf_d,
|
||||
input logic dec_i0_icaf_f1_d, // i0 instruction access fault at decode for f1 fetch group
|
||||
input logic dec_i0_icaf_second_d, // i0 instruction access fault on second 2B of 4B inst
|
||||
input logic dec_i0_perr_d, // icache parity error
|
||||
input logic dec_i1_perr_d,
|
||||
input logic dec_i0_sbecc_d, // icache/iccm single-bit error
|
||||
|
|
@ -1342,6 +1342,7 @@ end : cam_array
|
|||
|
||||
assign i1_block_d = leak1_i1_stall |
|
||||
(i0_jal) | // no i1 after a jal, will flush
|
||||
(((|dec_i0_trigger_match_d[3:0]) | ((i0_dp.condbr | i0_dp.jal) & i0_secondary_d)) & i1_dp.load ) | // if branch or branch error then don't allow i1 load
|
||||
i0_presync | i0_postsync |
|
||||
i1_dp.presync | i1_dp.postsync |
|
||||
i1_icaf_d | // instruction access fault is i0 only
|
||||
|
|
@ -1939,7 +1940,7 @@ end : cam_array
|
|||
|
||||
assign dt.legal = i0_legal_decode_d ;
|
||||
assign dt.icaf = i0_icaf_d & i0_legal_decode_d; // dbecc is icaf exception
|
||||
assign dt.icaf_f1 = dec_i0_icaf_f1_d & i0_legal_decode_d; // this includes icaf and dbecc
|
||||
assign dt.icaf_second = dec_i0_icaf_second_d & i0_legal_decode_d; // this includes icaf and dbecc
|
||||
assign dt.perr = dec_i0_perr_d & i0_legal_decode_d;
|
||||
assign dt.sbecc = dec_i0_sbecc_d & i0_legal_decode_d;
|
||||
assign dt.fence_i = (i0_dp.fence_i | debug_fence_i) & i0_legal_decode_d;
|
||||
|
|
|
|||
|
|
@ -42,8 +42,8 @@ module dec_ib_ctl
|
|||
|
||||
input logic ifu_i0_icaf, // i0 instruction access fault
|
||||
input logic ifu_i1_icaf,
|
||||
input logic ifu_i0_icaf_f1, // i0 has access fault on second fetch group
|
||||
input logic ifu_i1_icaf_f1,
|
||||
input logic ifu_i0_icaf_second, // i0 has access fault on second 2B of 4B inst
|
||||
input logic ifu_i1_icaf_second,
|
||||
input logic ifu_i0_perr, // i0 instruction parity error
|
||||
input logic ifu_i1_perr,
|
||||
input logic ifu_i0_sbecc, // i0 single-bit error
|
||||
|
|
@ -85,7 +85,7 @@ module dec_ib_ctl
|
|||
|
||||
output logic dec_i0_icaf_d, // i0 instruction access fault at decode
|
||||
output logic dec_i1_icaf_d,
|
||||
output logic dec_i0_icaf_f1_d, // i0 instruction access fault at decode for f1 fetch group
|
||||
output logic dec_i0_icaf_second_d, // i0 instruction access fault on second 2B of 4B inst
|
||||
output logic dec_i0_perr_d, // i0 instruction parity error at decode
|
||||
output logic dec_i1_perr_d,
|
||||
output logic dec_i0_sbecc_d, // i0 single-bit error at decode
|
||||
|
|
@ -239,9 +239,9 @@ module dec_ib_ctl
|
|||
|
||||
logic [36:0] ifu_i1_pcdata, ifu_i0_pcdata;
|
||||
|
||||
assign ifu_i1_pcdata[36:0] = { ifu_i1_icaf_f1, ifu_i1_dbecc, ifu_i1_sbecc, ifu_i1_perr, ifu_i1_icaf,
|
||||
assign ifu_i1_pcdata[36:0] = { ifu_i1_icaf_second, ifu_i1_dbecc, ifu_i1_sbecc, ifu_i1_perr, ifu_i1_icaf,
|
||||
ifu_i1_pc[31:1], ifu_i1_pc4 };
|
||||
assign ifu_i0_pcdata[36:0] = { ifu_i0_icaf_f1, ifu_i0_dbecc, ifu_i0_sbecc, ifu_i0_perr, ifu_i0_icaf,
|
||||
assign ifu_i0_pcdata[36:0] = { ifu_i0_icaf_second, ifu_i0_dbecc, ifu_i0_sbecc, ifu_i0_perr, ifu_i0_icaf,
|
||||
ifu_i0_pc[31:1], ifu_i0_pc4 };
|
||||
|
||||
if (DEC_INSTBUF_DEPTH==4) begin
|
||||
|
|
@ -275,7 +275,7 @@ module dec_ib_ctl
|
|||
|
||||
rvdffe #(37) pc0ff (.*, .en(ibwrite[0]), .din(pc0_in[36:0]), .dout(pc0[36:0]));
|
||||
|
||||
assign dec_i0_icaf_f1_d = pc0[36]; // icaf's can only decode as i0
|
||||
assign dec_i0_icaf_second_d = pc0[36]; // icaf's can only decode as i0
|
||||
|
||||
assign dec_i1_dbecc_d = pc1[35];
|
||||
assign dec_i0_dbecc_d = pc0[35];
|
||||
|
|
|
|||
|
|
@ -351,7 +351,7 @@ module dec_tlu_ctl
|
|||
logic request_debug_mode_e4, request_debug_mode_wb, request_debug_mode_done, request_debug_mode_done_f;
|
||||
logic take_halt, take_halt_f, halt_taken, halt_taken_f, internal_dbg_halt_mode, dbg_tlu_halted_f, take_reset,
|
||||
dbg_tlu_halted, core_empty, lsu_halt_idle_any_f, ifu_miss_state_idle_f, resume_ack_ns,
|
||||
debug_halt_req_f, debug_resume_req_f, enter_debug_halt_req, dcsr_single_step_done, dcsr_single_step_done_f,
|
||||
debug_halt_req_f, debug_resume_req_f_raw, debug_resume_req_f, enter_debug_halt_req, dcsr_single_step_done, dcsr_single_step_done_f,
|
||||
debug_halt_req_d1, debug_halt_req_ns, dcsr_single_step_running, dcsr_single_step_running_f, internal_dbg_halt_timers;
|
||||
|
||||
logic [3:0] i0_trigger_e4, i1_trigger_e4, trigger_action, trigger_enabled,
|
||||
|
|
@ -382,6 +382,9 @@ module dec_tlu_ctl
|
|||
mpc_debug_halt_ack_f, mpc_debug_run_ack_f, dbg_run_state_f, dbg_halt_state_ff, mpc_debug_halt_req_sync_pulse,
|
||||
mpc_debug_run_req_sync_pulse, debug_brkpt_valid, debug_halt_req, debug_resume_req, dec_tlu_mpc_halted_only_ns;
|
||||
|
||||
logic wr_mpmc_wb, set_mie_pmu_fw_halt;
|
||||
logic [1:1] mpmc_b_ns, mpmc, mpmc_b;
|
||||
|
||||
// internal timer, isolated for size reasons
|
||||
logic [31:0] dec_timer_rddata_d;
|
||||
logic dec_timer_read_d, dec_timer_t0_pulse, dec_timer_t1_pulse;
|
||||
|
|
@ -406,7 +409,7 @@ module dec_tlu_ctl
|
|||
rvoclkhdr lsu_e3_e4_cgc ( .en(lsu_error_pkt_dc3.exc_valid | lsu_error_pkt_dc4.exc_valid | lsu_error_pkt_dc3.single_ecc_error | lsu_error_pkt_dc4.single_ecc_error | clk_override), .l1clk(lsu_e3_e4_clk), .* );
|
||||
rvoclkhdr lsu_e4_e5_cgc ( .en(lsu_error_pkt_dc4.exc_valid | lsu_exc_valid_wb | clk_override), .l1clk(lsu_e4_e5_clk), .* );
|
||||
|
||||
logic e4e5_clk, e4_valid, e5_valid, e4e5_valid, internal_dbg_halt_mode_f;
|
||||
logic e4e5_clk, e4_valid, e5_valid, e4e5_valid, internal_dbg_halt_mode_f, internal_dbg_halt_mode_f2, internal_dbg_halt_mode_f3;
|
||||
assign e4_valid = dec_tlu_i0_valid_e4 | dec_tlu_i1_valid_e4;
|
||||
assign e4e5_valid = e4_valid | e5_valid;
|
||||
rvoclkhdr e4e5_cgc ( .en(e4e5_valid | clk_override), .l1clk(e4e5_clk), .* );
|
||||
|
|
@ -414,8 +417,11 @@ module dec_tlu_ctl
|
|||
|
||||
|
||||
assign lsu_freeze_pulse_e3 = lsu_freeze_dc3 & ~lsu_freeze_e4;
|
||||
rvdff #(8) freeff (.*, .clk(free_clk), .din({lsu_freeze_dc3, lsu_freeze_pulse_e3, e4_valid, lsu_block_interrupts_dc3, internal_dbg_halt_mode, tlu_flush_lower_e4, tlu_i0_kill_writeb_e4, tlu_i1_kill_writeb_e4 }),
|
||||
.dout({lsu_freeze_e4, lsu_freeze_pulse_e4, e5_valid, lsu_block_interrupts_e4, internal_dbg_halt_mode_f, tlu_flush_lower_wb, dec_tlu_i0_kill_writeb_wb, dec_tlu_i1_kill_writeb_wb}));
|
||||
rvdff #(10) freeff (.*, .clk(free_clk),
|
||||
.din({internal_dbg_halt_mode_f2,internal_dbg_halt_mode_f, lsu_freeze_dc3, lsu_freeze_pulse_e3,
|
||||
e4_valid, lsu_block_interrupts_dc3, internal_dbg_halt_mode, tlu_flush_lower_e4, tlu_i0_kill_writeb_e4, tlu_i1_kill_writeb_e4 }),
|
||||
.dout({internal_dbg_halt_mode_f3, internal_dbg_halt_mode_f2, lsu_freeze_e4, lsu_freeze_pulse_e4,
|
||||
e5_valid, lsu_block_interrupts_e4, internal_dbg_halt_mode_f, tlu_flush_lower_wb, dec_tlu_i0_kill_writeb_wb, dec_tlu_i1_kill_writeb_wb}));
|
||||
|
||||
|
||||
rvdff #(2) reset_ff (.*, .clk(free_clk), .din({1'b1, reset_detect}), .dout({reset_detect, reset_detected}));
|
||||
|
|
@ -552,10 +558,13 @@ module dec_tlu_ctl
|
|||
dcsr_single_step_done, debug_halt_req, update_hit_bit_e4[3:0], dec_tlu_wr_pause_wb, dec_pause_state,
|
||||
request_debug_mode_e4, request_debug_mode_done, dcsr_single_step_running, dcsr_single_step_running_f}),
|
||||
.dout({halt_taken_f, take_halt_f, lsu_halt_idle_any_f, ifu_miss_state_idle_f, dbg_tlu_halted_f,
|
||||
dec_tlu_resume_ack, dec_dbg_cmd_done, debug_halt_req_f, debug_resume_req_f, trigger_hit_dmode_wb,
|
||||
dec_tlu_resume_ack, dec_dbg_cmd_done, debug_halt_req_f, debug_resume_req_f_raw, trigger_hit_dmode_wb,
|
||||
dcsr_single_step_done_f, debug_halt_req_d1, update_hit_bit_wb[3:0], dec_tlu_wr_pause_wb_f, dec_pause_state_f,
|
||||
request_debug_mode_wb, request_debug_mode_done_f, dcsr_single_step_running_f, dcsr_single_step_running_ff}));
|
||||
|
||||
// MPC run collides with DBG halt, fix it here
|
||||
assign debug_resume_req_f = debug_resume_req_f_raw & ~dbg_halt_req;
|
||||
|
||||
assign dec_tlu_debug_stall = debug_halt_req_f;
|
||||
assign dec_tlu_dbg_halted = dbg_tlu_halted_f;
|
||||
assign dec_tlu_debug_mode = internal_dbg_halt_mode_f;
|
||||
|
|
@ -884,7 +893,7 @@ module dec_tlu_ctl
|
|||
assign iccm_sbecc_e4 = dec_tlu_packet_e4.sbecc & dec_tlu_i0_valid_e4 & ~i0_trigger_hit_e4;
|
||||
assign inst_acc_e4_raw = dec_tlu_packet_e4.icaf & dec_tlu_i0_valid_e4;
|
||||
assign inst_acc_e4 = inst_acc_e4_raw & ~rfpc_i0_e4 & ~i0_trigger_hit_e4;
|
||||
assign inst_acc_second_e4 = dec_tlu_packet_e4.icaf_f1;
|
||||
assign inst_acc_second_e4 = dec_tlu_packet_e4.icaf_second;
|
||||
|
||||
assign ebreak_to_debug_mode_e4 = (dec_tlu_packet_e4.pmu_i0_itype == EBREAK) & dec_tlu_i0_valid_e4 & ~i0_trigger_hit_e4 & dcsr[`DCSR_EBREAKM];
|
||||
|
||||
|
|
@ -1089,11 +1098,15 @@ module dec_tlu_ctl
|
|||
assign dec_csr_wen_wb_mod = dec_csr_wen_wb & ~trigger_hit_wb;
|
||||
assign wr_mstatus_wb = dec_csr_wen_wb_mod & (dec_csr_wraddr_wb[11:0] == `MSTATUS);
|
||||
|
||||
assign mstatus_ns[1:0] = ( ({2{~wr_mstatus_wb & exc_or_int_valid_wb}} & {mstatus[`MSTATUS_MIE], 1'b0}) |
|
||||
// set this even if we don't go to fwhalt due to debug halt. We committed the inst, so ...
|
||||
assign set_mie_pmu_fw_halt = ~mpmc_b_ns[1] & wr_mpmc_wb & dec_csr_wrdata_wb[0] & ~internal_dbg_halt_mode_f3;
|
||||
|
||||
assign mstatus_ns[1:0] = ( ({2{~wr_mstatus_wb & exc_or_int_valid_wb}} & {(mstatus[`MSTATUS_MIE] | set_mie_pmu_fw_halt), 1'b0}) |
|
||||
({2{ wr_mstatus_wb & exc_or_int_valid_wb}} & {dec_csr_wrdata_wb[3], 1'b0}) |
|
||||
({2{mret_wb & ~exc_or_int_valid_wb}} & {1'b1, mstatus[1]}) |
|
||||
({2{set_mie_pmu_fw_halt & ~exc_or_int_valid_wb}} & {mstatus[1], 1'b1}) |
|
||||
({2{wr_mstatus_wb & ~exc_or_int_valid_wb}} & {dec_csr_wrdata_wb[7], dec_csr_wrdata_wb[3]}) |
|
||||
({2{~wr_mstatus_wb & ~exc_or_int_valid_wb & ~mret_wb}} & mstatus[1:0]) );
|
||||
({2{~wr_mstatus_wb & ~exc_or_int_valid_wb & ~mret_wb & ~set_mie_pmu_fw_halt}} & mstatus[1:0]) );
|
||||
|
||||
// gate MIE if we are single stepping and DCSR[STEPIE] is off
|
||||
assign mstatus_mie_ns = mstatus_ns[`MSTATUS_MIE] & (~dcsr_single_step_running_f | dcsr[`DCSR_STEPIE]);
|
||||
|
|
@ -1444,12 +1457,21 @@ module dec_tlu_ctl
|
|||
|
||||
// ----------------------------------------------------------------------
|
||||
// MPMC (R0W1)
|
||||
// [0:0] : FW halt
|
||||
// [0] : FW halt
|
||||
// [1] : HALTIE
|
||||
//
|
||||
`define MPMC 12'h7c6
|
||||
logic wr_mpmc_wb;
|
||||
assign wr_mpmc_wb = dec_csr_wrdata_wb[0] & dec_csr_wen_wb_mod & (dec_csr_wraddr_wb[11:0] == `MPMC);
|
||||
assign fw_halt_req = wr_mpmc_wb & ~internal_dbg_halt_mode_f & ~interrupt_valid_wb;
|
||||
|
||||
assign wr_mpmc_wb = dec_csr_wen_wb_mod & (dec_csr_wraddr_wb[11:0] == `MPMC);
|
||||
|
||||
// allow the cycle of the dbg halt flush that contains the wr_mpmc_wb to
|
||||
// set the mstatus bit potentially, use delayed version of internal dbg halt.
|
||||
// Kill the req when we commit the fwhalt csr write and take an int
|
||||
assign fw_halt_req = wr_mpmc_wb & dec_csr_wrdata_wb[0] & ~internal_dbg_halt_mode_f3 & ~interrupt_valid_wb;
|
||||
|
||||
assign mpmc_b_ns[1] = wr_mpmc_wb ? ~dec_csr_wrdata_wb[1] : ~mpmc[1];
|
||||
rvdff #(1) mpmc_ff (.*, .clk(csr_wr_clk), .din(mpmc_b_ns[1]), .dout(mpmc_b[1]));
|
||||
assign mpmc[1] = ~mpmc_b[1];
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// MICECT (I-Cache error counter/threshold)
|
||||
|
|
@ -2427,16 +2449,14 @@ assign postsync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
|
|||
&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[5]
|
||||
&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]) | (
|
||||
!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]
|
||||
&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]
|
||||
&dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
|
||||
&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[7]
|
||||
&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7]
|
||||
&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (
|
||||
dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
|
||||
&dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]
|
||||
&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (
|
||||
!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5]
|
||||
&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]);
|
||||
|
||||
&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7]
|
||||
&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
|
||||
&!dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]
|
||||
&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]);
|
||||
|
||||
logic legal_csr;
|
||||
assign legal_csr = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]
|
||||
|
|
@ -2533,7 +2553,7 @@ assign dec_csr_legal_d = ( dec_csr_any_unq_d &
|
|||
assign dec_csr_rddata_d[31:0] = ( ({32{csr_misa}} & 32'h40001104) |
|
||||
({32{csr_mvendorid}} & 32'h00000045) |
|
||||
({32{csr_marchid}} & 32'h0000000b) |
|
||||
({32{csr_mimpid}} & 32'h4) |
|
||||
({32{csr_mimpid}} & 32'h5) |
|
||||
({32{csr_mstatus}} & {19'b0, 2'b11, 3'b0, mstatus[1], 3'b0, mstatus[0], 3'b0}) |
|
||||
({32{csr_mtvec}} & {mtvec[30:1], 1'b0, mtvec[0]}) |
|
||||
({32{csr_mip}} & {1'b0, mip[5:3], 16'b0, mip[2], 3'b0, mip[1], 3'b0, mip[0], 3'b0}) |
|
||||
|
|
@ -2582,6 +2602,7 @@ assign dec_csr_rddata_d[31:0] = ( ({32{csr_misa}} & 32'h40001104) |
|
|||
({32{csr_mhpme4}} & {26'b0,mhpme4[5:0]}) |
|
||||
({32{csr_mhpme5}} & {26'b0,mhpme5[5:0]}) |
|
||||
({32{csr_mhpme6}} & {26'b0,mhpme6[5:0]}) |
|
||||
({32{csr_mpmc}} & {30'b0, mpmc[1], 1'b0}) |
|
||||
({32{csr_mgpmc}} & {31'b0, mgpmc}) |
|
||||
({32{dec_timer_read_d}} & dec_timer_rddata_d[31:0])
|
||||
);
|
||||
|
|
|
|||
|
|
@ -159,6 +159,10 @@ module dma_ctrl (
|
|||
logic [DEPTH_PTR-1:0] RdPtr_Q1, RdPtr_Q2, RdPtr_Q3;
|
||||
logic WrPtrEn, RdPtrEn, RspPtrEn;
|
||||
|
||||
logic [1:0] dma_dbg_sz;
|
||||
logic [1:0] dma_dbg_addr;
|
||||
logic [31:0] dma_dbg_mem_rddata;
|
||||
logic [31:0] dma_dbg_mem_wrdata;
|
||||
logic dma_dbg_cmd_error_in;
|
||||
logic dma_dbg_cmd_done_q;
|
||||
|
||||
|
|
@ -237,9 +241,6 @@ module dma_ctrl (
|
|||
assign fifo_write_in = dbg_cmd_valid ? dbg_cmd_write : axi_mstr_write;
|
||||
assign fifo_posted_write_in = axi_mstr_valid & axi_mstr_posted_write;
|
||||
assign fifo_dbg_in = dbg_cmd_valid;
|
||||
//assign fifo_error_in[1:0] = dccm_dma_rvalid ? {1'b0,dccm_dma_ecc_error} : iccm_dma_rvalid ? {1'b0,iccm_dma_ecc_error} : {(dma_address_error | dma_alignment_error | dma_dbg_cmd_error_in), dma_alignment_error};
|
||||
//assign fifo_data_in[63:0] = dccm_dma_rvalid ? dccm_dma_rdata[63:0] : (iccm_dma_rvalid ? iccm_dma_rdata[63:0] :
|
||||
// (dbg_cmd_valid ? {2{dbg_cmd_wrdata[31:0]}} : axi_mstr_wdata[63:0]));
|
||||
|
||||
for (genvar i=0 ;i<DEPTH; i++) begin: GenFifo
|
||||
assign fifo_valid_en[i] = axi_mstr_valid & (i == WrPtr[DEPTH_PTR-1:0]);
|
||||
|
|
@ -255,14 +256,12 @@ module dma_ctrl (
|
|||
assign fifo_done_en[i] = (((|fifo_error[i]) | ((dma_dccm_req | dma_iccm_req) & dma_mem_write)) & (i == RdPtr[DEPTH_PTR-1:0])) |
|
||||
((dccm_dma_rvalid & (i == RdPtr_Q3[DEPTH_PTR-1:0])) | (iccm_dma_rvalid & (i == RdPtr_Q2[DEPTH_PTR-1:0])));
|
||||
assign fifo_done_bus_en[i] = (fifo_done_en[i] | fifo_done[i]) & dma_bus_clk_en;
|
||||
//assign fifo_rsp_done_en[i] = fifo_valid[i] & ((axi_slv_sent & dma_bus_clk_en) | dma_dbg_cmd_done) & (i == RspPtr[DEPTH_PTR-1:0]);
|
||||
//assign fifo_reset[i] = (fifo_done[i] | fifo_done_en[i]) & (fifo_rsp_done[i] | fifo_rsp_done_en[i]);
|
||||
assign fifo_reset[i] = ((axi_slv_sent & dma_bus_clk_en) | dma_dbg_cmd_done) & (i == RspPtr[DEPTH_PTR-1:0]);
|
||||
assign fifo_error_in[i] = (dccm_dma_rvalid & (i == RdPtr_Q3[DEPTH_PTR-1:0])) ? {1'b0,dccm_dma_ecc_error} : (iccm_dma_rvalid & (i == RdPtr_Q2[DEPTH_PTR-1:0])) ? {1'b0,iccm_dma_ecc_error} :
|
||||
{(dma_address_error | dma_alignment_error | dma_dbg_cmd_error_in), dma_alignment_error};
|
||||
assign fifo_data_in[i] = (fifo_error_en[i] & (|fifo_error_in[i])) ? (fifo_cmd_en[i] ? {32'b0,axi_mstr_addr[31:0]} : {32'b0,fifo_addr[i]}) :
|
||||
((dccm_dma_rvalid & (i == RdPtr_Q3[DEPTH_PTR-1:0])) ? dccm_dma_rdata[63:0] : (iccm_dma_rvalid & (i == RdPtr_Q2[DEPTH_PTR-1:0])) ? iccm_dma_rdata[63:0] :
|
||||
(dbg_cmd_valid ? {2{dbg_cmd_wrdata[31:0]}} : axi_mstr_wdata[63:0]));
|
||||
(dbg_cmd_valid ? {2{dma_dbg_mem_wrdata[31:0]}} : axi_mstr_wdata[63:0]));
|
||||
|
||||
rvdffsc #(1) fifo_valid_dff (.din(1'b1), .dout(fifo_valid[i]), .en(fifo_cmd_en[i]), .clear(fifo_reset[i]), .clk(dma_free_clk), .*);
|
||||
rvdffsc #(2) fifo_error_dff (.din(fifo_error_in[i]), .dout(fifo_error[i]), .en(fifo_error_en[i]), .clear(fifo_reset[i]), .clk(dma_free_clk), .*);
|
||||
|
|
@ -274,7 +273,6 @@ module dma_ctrl (
|
|||
rvdffsc #(1) fifo_rpend_dff (.din(1'b1), .dout(fifo_rpend[i]), .en(fifo_pend_en[i]), .clear(fifo_reset[i]), .clk(dma_free_clk), .*);
|
||||
rvdffsc #(1) fifo_done_dff (.din(1'b1), .dout(fifo_done[i]), .en(fifo_done_en[i]), .clear(fifo_reset[i]), .clk(dma_free_clk), .*);
|
||||
rvdffsc #(1) fifo_done_bus_dff (.din(1'b1), .dout(fifo_done_bus[i]), .en(fifo_done_bus_en[i]), .clear(fifo_reset[i]), .clk(dma_free_clk), .*);
|
||||
//rvdffsc #(1) fifo_rsp_done_dff (.din(1'b1), .dout(fifo_rsp_done[i]), .en(fifo_rsp_done_en[i]), .clear(fifo_reset[i]), .clk(dma_free_clk), .*);
|
||||
rvdffe #(32) fifo_addr_dff (.din(fifo_addr_in[31:0]), .dout(fifo_addr[i]), .en(fifo_cmd_en[i]), .*);
|
||||
rvdffs #(3) fifo_sz_dff (.din(fifo_sz_in[2:0]), .dout(fifo_sz[i]), .en(fifo_cmd_en[i]), .clk(dma_buffer_c1_clk), .*);
|
||||
rvdffs #(1) fifo_write_dff (.din(fifo_write_in), .dout(fifo_write[i]), .en(fifo_cmd_en[i]), .clk(dma_buffer_c1_clk), .*);
|
||||
|
|
@ -289,21 +287,13 @@ module dma_ctrl (
|
|||
assign NxtRdPtr[DEPTH_PTR-1:0] = RdPtr[DEPTH_PTR-1:0] + 1'b1;
|
||||
assign NxtRspPtr[DEPTH_PTR-1:0] = RspPtr[DEPTH_PTR-1:0] + 1'b1;
|
||||
|
||||
// Don't increment the ptr for posted writes if 1)fifo error (it will increment only with response) 2) response done (this is the full case)
|
||||
//assign RspPtr[DEPTH_PTR-1:0] = (dma_dbg_cmd_done_q | axi_slv_sent_q) ? (PrevRspPtr[DEPTH_PTR-1:0] + 1'b1) : PrevRspPtr[DEPTH_PTR-1:0];
|
||||
//assign RspPtr[DEPTH_PTR-1:0] = (dma_dbg_cmd_done_q | axi_slv_sent_q |
|
||||
// (fifo_valid[PrevRspPtr] & fifo_write[PrevRspPtr] & fifo_posted_write[PrevRspPtr] & ~(|fifo_error[PrevRspPtr]) & ~fifo_rsp_done[PrevRspPtr])) ? (PrevRspPtr[DEPTH_PTR-1:0] + 1'b1) : PrevRspPtr[DEPTH_PTR-1:0];
|
||||
|
||||
assign WrPtrEn = |fifo_cmd_en[DEPTH-1:0];
|
||||
assign RdPtrEn = (dma_dccm_req | dma_iccm_req) | ((|fifo_error[RdPtr]) & ~fifo_done[RdPtr]);
|
||||
//assign RdPtrEn = |(fifo_done_en[DEPTH-1:0] & ~fifo_done[DEPTH-1:0]);
|
||||
assign RspPtrEn = (dma_dbg_cmd_done | (axi_slv_sent & dma_bus_clk_en));
|
||||
//assign RspPtrEn = dma_bus_clk_en | dma_dbg_cmd_done_q;
|
||||
|
||||
rvdffs #(DEPTH_PTR) WrPtr_dff(.din(NxtWrPtr[DEPTH_PTR-1:0]), .dout(WrPtr[DEPTH_PTR-1:0]), .en(WrPtrEn), .clk(dma_free_clk), .*);
|
||||
rvdffs #(DEPTH_PTR) RdPtr_dff(.din(NxtRdPtr[DEPTH_PTR-1:0]), .dout(RdPtr[DEPTH_PTR-1:0]), .en(RdPtrEn), .clk(dma_free_clk), .*);
|
||||
rvdffs #(DEPTH_PTR) RspPtr_dff(.din(NxtRspPtr[DEPTH_PTR-1:0]), .dout(RspPtr[DEPTH_PTR-1:0]), .en(RspPtrEn), .clk(dma_free_clk), .*);
|
||||
//rvdffs #(DEPTH_PTR) RspPtr_dff(.din(RspPtr[DEPTH_PTR-1:0]), .dout(PrevRspPtr[DEPTH_PTR-1:0]), .en(RspPtrEn), .clk(dma_free_clk), .*);
|
||||
|
||||
rvdff #(DEPTH_PTR) RdPtrQ1_dff(.din(RdPtr[DEPTH_PTR-1:0]), .dout(RdPtr_Q1[DEPTH_PTR-1:0]), .clk(dma_free_clk), .*);
|
||||
rvdff #(DEPTH_PTR) RdPtrQ2_dff(.din(RdPtr_Q1[DEPTH_PTR-1:0]), .dout(RdPtr_Q2[DEPTH_PTR-1:0]), .clk(dma_free_clk), .*);
|
||||
|
|
@ -334,12 +324,22 @@ module dma_ctrl (
|
|||
//Dbg outputs
|
||||
assign dma_dbg_ready = fifo_empty & dbg_dma_bubble;
|
||||
assign dma_dbg_cmd_done = (fifo_valid[RspPtr] & fifo_dbg[RspPtr] & (fifo_write[RspPtr] | fifo_data_valid[RspPtr] | (|fifo_error[RspPtr])));
|
||||
assign dma_dbg_rddata[31:0] = fifo_addr[RspPtr][2] ? fifo_data[RspPtr][63:32] : fifo_data[RspPtr][31:0];
|
||||
assign dma_dbg_cmd_fail = |fifo_error[RspPtr];
|
||||
|
||||
assign dma_dbg_sz[1:0] = fifo_sz[RspPtr][1:0];
|
||||
assign dma_dbg_addr[1:0] = fifo_addr[RspPtr][1:0];
|
||||
assign dma_dbg_mem_rddata[31:0] = fifo_addr[RspPtr][2] ? fifo_data[RspPtr][63:32] : fifo_data[RspPtr][31:0];
|
||||
assign dma_dbg_rddata[31:0] = ({32{(dma_dbg_sz[1:0] == 2'h0)}} & ((dma_dbg_mem_rddata[31:0] >> 8*dma_dbg_addr[1:0]) & 32'hff)) |
|
||||
({32{(dma_dbg_sz[1:0] == 2'h1)}} & ((dma_dbg_mem_rddata[31:0] >> 16*dma_dbg_addr[1]) & 32'hffff)) |
|
||||
({32{(dma_dbg_sz[1:0] == 2'h2)}} & dma_dbg_mem_rddata[31:0]);
|
||||
|
||||
assign dma_dbg_cmd_error_in = dbg_cmd_valid & (dbg_cmd_type[1:0] == 2'b10) &
|
||||
((~(dma_addr_in_dccm | dma_addr_in_iccm | dma_addr_in_pic)) | (dbg_cmd_size[1:0] != 2'b10)); // Only word accesses allowed
|
||||
//(dma_addr_in_iccm & ~((dbg_cmd_size[1:0] == 2'b10) | (dbg_cmd_size[1:0] == 2'b11))));
|
||||
((~(dma_addr_in_dccm | dma_addr_in_iccm | dma_addr_in_pic)) | // Address outside of ICCM/DCCM/PIC
|
||||
((dma_addr_in_iccm | dma_addr_in_pic) & (dbg_cmd_size[1:0] != 2'b10))); // Only word accesses allowed for ICCM/PIC
|
||||
|
||||
assign dma_dbg_mem_wrdata[31:0] = ({32{dbg_cmd_size[1:0] == 2'h0}} & {4{dbg_cmd_wrdata[7:0]}}) |
|
||||
({32{dbg_cmd_size[1:0] == 2'h1}} & {2{dbg_cmd_wrdata[15:0]}}) |
|
||||
({32{dbg_cmd_size[1:0] == 2'h2}} & dbg_cmd_wrdata[31:0]);
|
||||
|
||||
|
||||
// Block the decode if fifo full
|
||||
|
|
@ -465,11 +465,8 @@ module dma_ctrl (
|
|||
assign axi_mstr_prty_in = ~axi_mstr_priority;
|
||||
assign axi_mstr_prty_en = axi_mstr_valid;
|
||||
|
||||
//assign axi_slv_valid = fifo_valid[RspPtr] & ~fifo_rsp_done[RspPtr] & ~fifo_dbg[RspPtr] &
|
||||
// ((fifo_write[RspPtr] & fifo_done_bus[RspPtr]) | (~fifo_write[RspPtr] & fifo_data_bus_valid[RspPtr]) | fifo_error_bus[RspPtr]);
|
||||
assign axi_slv_valid = fifo_valid[RspPtr] & ~fifo_dbg[RspPtr] & fifo_done_bus[RspPtr];
|
||||
assign axi_slv_tag[DMA_BUS_TAG-1:0] = fifo_tag[RspPtr];
|
||||
//assign axi_slv_rdata[63:0] = (|fifo_error[RspPtr]) ? {32'b0,fifo_addr[RspPtr]} : fifo_data[RspPtr];
|
||||
assign axi_slv_rdata[63:0] = fifo_data[RspPtr];
|
||||
assign axi_slv_write = fifo_write[RspPtr];
|
||||
assign axi_slv_posted_write = axi_slv_write & fifo_posted_write[RspPtr];
|
||||
|
|
@ -489,6 +486,7 @@ module dma_ctrl (
|
|||
|
||||
assign axi_slv_sent = (dma_axi_bvalid & dma_axi_bready) | (dma_axi_rvalid & dma_axi_rready);
|
||||
assign dma_slv_algn_err = fifo_error[RspPtr][1];
|
||||
|
||||
`ifdef ASSERT_ON
|
||||
|
||||
//assert_nack_count: assert #0 (dma_nack_count[2:0] < 3'h4);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
// SPDX-License-Identifier: Apache-2.0
|
||||
// Copyright 2019 Western Digital Corporation or its affiliates.
|
||||
// Copyright 2019 Western Digital Corporation or it's affiliates.
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
|
|
@ -173,6 +173,7 @@ always_comb begin
|
|||
endcase
|
||||
end
|
||||
capture_dr: begin
|
||||
nsr[0] = 1'b0;
|
||||
case(1)
|
||||
dr_en[0]: nsr = {{USER_DR_LENGTH-15{1'b0}}, idle, dmi_stat, abits, version};
|
||||
dr_en[1]: nsr = {{AWIDTH{1'b0}}, rd_data, rd_status};
|
||||
|
|
|
|||
|
|
@ -180,8 +180,8 @@ module ifu
|
|||
output logic ifu_i1_valid, // Instruction 1 valid. From Aligner to Decode
|
||||
output logic ifu_i0_icaf, // Instruction 0 access fault. From Aligner to Decode
|
||||
output logic ifu_i1_icaf, // Instruction 1 access fault. From Aligner to Decode
|
||||
output logic ifu_i0_icaf_f1, // Instruction 0 has access fault on second fetch group
|
||||
output logic ifu_i1_icaf_f1, // Instruction 1 has access fault on second fetch group
|
||||
output logic ifu_i0_icaf_second, // Instruction 0 has access fault on second 2B of 4B inst
|
||||
output logic ifu_i1_icaf_second, // Instruction 1 has access fault on second 2B of 4B inst
|
||||
output logic ifu_i0_perr, // Instruction 0 parity error. From Aligner to Decode
|
||||
output logic ifu_i1_perr, // Instruction 1 parity error. From Aligner to Decode
|
||||
output logic ifu_i0_sbecc, // Instruction 0 has single bit ecc error
|
||||
|
|
@ -252,7 +252,7 @@ module ifu
|
|||
logic ifc_dma_access_ok;
|
||||
logic ifc_iccm_access_f1;
|
||||
logic ifc_region_acc_fault_f1;
|
||||
logic ic_access_fault_f2;
|
||||
logic [7:0] ic_access_fault_f2;
|
||||
logic ifu_ic_mb_empty;
|
||||
|
||||
|
||||
|
|
@ -289,7 +289,7 @@ module ifu
|
|||
logic ifc_fetch_req_f1_raw, ifc_fetch_req_f1, ifc_fetch_req_f2;
|
||||
logic ic_rd_parity_final_err; // This fetch has a data_cache or tag parity error.
|
||||
logic iccm_rd_ecc_single_err; // This fetch has an iccm single error.
|
||||
logic iccm_rd_ecc_double_err; // This fetch has an iccm double error.
|
||||
logic [7:0] iccm_rd_ecc_double_err; // This fetch has an iccm double error.
|
||||
|
||||
icache_err_pkt_t ic_error_f2;
|
||||
|
||||
|
|
@ -303,7 +303,8 @@ module ifu
|
|||
assign ifu_fetch_pc[31:1] = ifc_fetch_addr_f2[31:1];
|
||||
|
||||
// aligner
|
||||
ifu_aln_ctl aln (.*);
|
||||
ifu_aln_ctl aln (.*
|
||||
);
|
||||
|
||||
// icache
|
||||
ifu_mem_ctl mem_ctl
|
||||
|
|
|
|||
|
|
@ -25,12 +25,12 @@ module ifu_aln_ctl
|
|||
input logic active_clk,
|
||||
|
||||
input logic iccm_rd_ecc_single_err, // This fetch has a single ICCM ecc error.
|
||||
input logic iccm_rd_ecc_double_err, // This fetch has a double ICCM ecc error.
|
||||
input logic [7:0] iccm_rd_ecc_double_err, // This fetch has a double ICCM ecc error.
|
||||
input logic ic_rd_parity_final_err, // for tag parity errors
|
||||
|
||||
input logic ifu_icache_fetch_f2,
|
||||
|
||||
input logic ic_access_fault_f2, // Instruction access fault for the current fetch.
|
||||
input logic [7:0] ic_access_fault_f2, // Instruction access fault for the current fetch.
|
||||
input logic [`RV_BHT_GHR_RANGE] ifu_bp_fghr_f2, // fetch GHR
|
||||
input logic [31:1] ifu_bp_btb_target_f2, // predicted RET target
|
||||
input logic [11:0] ifu_bp_poffset_f2, // predicted target offset
|
||||
|
|
@ -72,8 +72,8 @@ module ifu_aln_ctl
|
|||
output logic ifu_i1_valid, // Instruction 1 is valid
|
||||
output logic ifu_i0_icaf, // Instruction 0 has access fault
|
||||
output logic ifu_i1_icaf, // Instruction 1 has access fault
|
||||
output logic ifu_i0_icaf_f1, // Instruction 0 has access fault on second fetch group
|
||||
output logic ifu_i1_icaf_f1, // Instruction 1 has access fault on second fetch group
|
||||
output logic ifu_i0_icaf_second, // Instruction 0 has access fault on second 2B of 4B inst
|
||||
output logic ifu_i1_icaf_second, // Instruction 1 has access fault on second 2B of 4B inst
|
||||
output logic ifu_i0_perr, // Instruction 0 has parity error
|
||||
output logic ifu_i1_perr, // Instruction 1 has parity error
|
||||
output logic ifu_i0_sbecc, // Instruction 0 has single bit ecc error
|
||||
|
|
@ -187,16 +187,16 @@ module ifu_aln_ctl
|
|||
|
||||
logic [31:1] f1prett;
|
||||
logic [31:1] f0prett;
|
||||
logic f1dbecc;
|
||||
logic f0dbecc;
|
||||
logic [7:0] f1dbecc;
|
||||
logic [7:0] f0dbecc;
|
||||
logic f1sbecc;
|
||||
logic f0sbecc;
|
||||
logic f1perr;
|
||||
logic f0perr;
|
||||
logic f1icfetch;
|
||||
logic f0icfetch;
|
||||
logic f1icaf;
|
||||
logic f0icaf;
|
||||
logic [7:0] f1icaf;
|
||||
logic [7:0] f0icaf;
|
||||
|
||||
logic [3:0] alignicfetch;
|
||||
logic [3:0] aligntagperr;
|
||||
|
|
@ -252,7 +252,7 @@ module ifu_aln_ctl
|
|||
logic [2:0] qren;
|
||||
|
||||
logic consume_fb1, consume_fb0;
|
||||
logic [3:1] icaf_eff;
|
||||
logic [3:0] icaf_eff;
|
||||
|
||||
`ifdef RV_ICACHE_ECC
|
||||
logic [39:0] q0ecc, q1ecc, q2ecc;
|
||||
|
|
@ -360,17 +360,17 @@ module ifu_aln_ctl
|
|||
|
||||
// misc data that is associated with each fetch buffer
|
||||
|
||||
localparam MHI = 47+`RV_BHT_GHR_SIZE;
|
||||
localparam MSIZE = 48+`RV_BHT_GHR_SIZE;
|
||||
localparam MHI = 45+`RV_BHT_GHR_SIZE;
|
||||
localparam MSIZE = 46+`RV_BHT_GHR_SIZE;
|
||||
|
||||
logic [MHI:0] misc_data_in, misc2, misc1, misc0;
|
||||
logic [MHI:0] misc1eff, misc0eff;
|
||||
|
||||
assign misc_data_in[MHI:0] = { iccm_rd_ecc_double_err,
|
||||
assign misc_data_in[MHI:0] = {
|
||||
iccm_rd_ecc_single_err,
|
||||
ifu_icache_fetch_f2,
|
||||
ic_rd_parity_final_err,
|
||||
ic_access_fault_f2,
|
||||
|
||||
ifu_bp_btb_target_f2[31:1],
|
||||
ifu_bp_poffset_f2[11:0],
|
||||
ifu_bp_fghr_f2[`RV_BHT_GHR_RANGE]
|
||||
|
|
@ -384,21 +384,21 @@ module ifu_aln_ctl
|
|||
assign {misc1eff[MHI:0],misc0eff[MHI:0]} = (({MSIZE*2{qren[0]}} & {misc1[MHI:0],misc0[MHI:0]}) |
|
||||
({MSIZE*2{qren[1]}} & {misc2[MHI:0],misc1[MHI:0]}) |
|
||||
({MSIZE*2{qren[2]}} & {misc0[MHI:0],misc2[MHI:0]}));
|
||||
assign { f1dbecc,
|
||||
assign {
|
||||
f1sbecc,
|
||||
f1icfetch,
|
||||
f1perr,
|
||||
f1icaf,
|
||||
|
||||
f1prett[31:1],
|
||||
f1poffset[11:0],
|
||||
f1fghr[`RV_BHT_GHR_RANGE]
|
||||
} = misc1eff[MHI:0];
|
||||
|
||||
assign { f0dbecc,
|
||||
assign {
|
||||
f0sbecc,
|
||||
f0icfetch,
|
||||
f0perr,
|
||||
f0icaf,
|
||||
|
||||
f0prett[31:1],
|
||||
f0poffset[11:0],
|
||||
f0fghr[`RV_BHT_GHR_RANGE]
|
||||
|
|
@ -406,24 +406,24 @@ module ifu_aln_ctl
|
|||
|
||||
|
||||
`ifdef RV_BTB_48
|
||||
localparam BRDATA_SIZE=56;
|
||||
localparam BRDATA_WIDTH = 7;
|
||||
localparam BRDATA_SIZE=72;
|
||||
localparam BRDATA_WIDTH = 9;
|
||||
`else
|
||||
localparam BRDATA_SIZE=48;
|
||||
localparam BRDATA_WIDTH = 6;
|
||||
localparam BRDATA_SIZE=64;
|
||||
localparam BRDATA_WIDTH = 8;
|
||||
`endif
|
||||
logic [BRDATA_SIZE-1:0] brdata_in, brdata2, brdata1, brdata0;
|
||||
logic [BRDATA_SIZE-1:0] brdata1eff, brdata0eff;
|
||||
logic [BRDATA_SIZE-1:0] brdata1final, brdata0final;
|
||||
assign brdata_in[BRDATA_SIZE-1:0] = {
|
||||
ifu_bp_hist1_f2[7],ifu_bp_hist0_f2[7],ifu_bp_pc4_f2[7],ifu_bp_way_f2[7],ifu_bp_valid_f2[7],ifu_bp_ret_f2[7],
|
||||
ifu_bp_hist1_f2[6],ifu_bp_hist0_f2[6],ifu_bp_pc4_f2[6],ifu_bp_way_f2[6],ifu_bp_valid_f2[6],ifu_bp_ret_f2[6],
|
||||
ifu_bp_hist1_f2[5],ifu_bp_hist0_f2[5],ifu_bp_pc4_f2[5],ifu_bp_way_f2[5],ifu_bp_valid_f2[5],ifu_bp_ret_f2[5],
|
||||
ifu_bp_hist1_f2[4],ifu_bp_hist0_f2[4],ifu_bp_pc4_f2[4],ifu_bp_way_f2[4],ifu_bp_valid_f2[4],ifu_bp_ret_f2[4],
|
||||
ifu_bp_hist1_f2[3],ifu_bp_hist0_f2[3],ifu_bp_pc4_f2[3],ifu_bp_way_f2[3],ifu_bp_valid_f2[3],ifu_bp_ret_f2[3],
|
||||
ifu_bp_hist1_f2[2],ifu_bp_hist0_f2[2],ifu_bp_pc4_f2[2],ifu_bp_way_f2[2],ifu_bp_valid_f2[2],ifu_bp_ret_f2[2],
|
||||
ifu_bp_hist1_f2[1],ifu_bp_hist0_f2[1],ifu_bp_pc4_f2[1],ifu_bp_way_f2[1],ifu_bp_valid_f2[1],ifu_bp_ret_f2[1],
|
||||
ifu_bp_hist1_f2[0],ifu_bp_hist0_f2[0],ifu_bp_pc4_f2[0],ifu_bp_way_f2[0],ifu_bp_valid_f2[0],ifu_bp_ret_f2[0]
|
||||
iccm_rd_ecc_double_err[7],ic_access_fault_f2[7],ifu_bp_hist1_f2[7],ifu_bp_hist0_f2[7],ifu_bp_pc4_f2[7],ifu_bp_way_f2[7],ifu_bp_valid_f2[7],ifu_bp_ret_f2[7],
|
||||
iccm_rd_ecc_double_err[6],ic_access_fault_f2[6],ifu_bp_hist1_f2[6],ifu_bp_hist0_f2[6],ifu_bp_pc4_f2[6],ifu_bp_way_f2[6],ifu_bp_valid_f2[6],ifu_bp_ret_f2[6],
|
||||
iccm_rd_ecc_double_err[5],ic_access_fault_f2[5],ifu_bp_hist1_f2[5],ifu_bp_hist0_f2[5],ifu_bp_pc4_f2[5],ifu_bp_way_f2[5],ifu_bp_valid_f2[5],ifu_bp_ret_f2[5],
|
||||
iccm_rd_ecc_double_err[4],ic_access_fault_f2[4],ifu_bp_hist1_f2[4],ifu_bp_hist0_f2[4],ifu_bp_pc4_f2[4],ifu_bp_way_f2[4],ifu_bp_valid_f2[4],ifu_bp_ret_f2[4],
|
||||
iccm_rd_ecc_double_err[3],ic_access_fault_f2[3],ifu_bp_hist1_f2[3],ifu_bp_hist0_f2[3],ifu_bp_pc4_f2[3],ifu_bp_way_f2[3],ifu_bp_valid_f2[3],ifu_bp_ret_f2[3],
|
||||
iccm_rd_ecc_double_err[2],ic_access_fault_f2[2],ifu_bp_hist1_f2[2],ifu_bp_hist0_f2[2],ifu_bp_pc4_f2[2],ifu_bp_way_f2[2],ifu_bp_valid_f2[2],ifu_bp_ret_f2[2],
|
||||
iccm_rd_ecc_double_err[1],ic_access_fault_f2[1],ifu_bp_hist1_f2[1],ifu_bp_hist0_f2[1],ifu_bp_pc4_f2[1],ifu_bp_way_f2[1],ifu_bp_valid_f2[1],ifu_bp_ret_f2[1],
|
||||
iccm_rd_ecc_double_err[0],ic_access_fault_f2[0],ifu_bp_hist1_f2[0],ifu_bp_hist0_f2[0],ifu_bp_pc4_f2[0],ifu_bp_way_f2[0],ifu_bp_valid_f2[0],ifu_bp_ret_f2[0]
|
||||
};
|
||||
//
|
||||
rvdffe #(BRDATA_SIZE) brdata2ff (.*, .en(qwen[2]), .din(brdata_in[BRDATA_SIZE-1:0]), .dout(brdata2[BRDATA_SIZE-1:0]));
|
||||
|
|
@ -435,7 +435,7 @@ module ifu_aln_ctl
|
|||
({BRDATA_SIZE*2{qren[1]}} & {brdata2[BRDATA_SIZE-1:0],brdata1[BRDATA_SIZE-1:0]}) |
|
||||
({BRDATA_SIZE*2{qren[2]}} & {brdata0[BRDATA_SIZE-1:0],brdata2[BRDATA_SIZE-1:0]}));
|
||||
|
||||
assign brdata0final[BRDATA_SIZE-1:0] = (({BRDATA_SIZE{q0sel[0]}} & { brdata0eff[8*6-1:0*6]}) |
|
||||
assign brdata0final[BRDATA_SIZE-1:0] = (({BRDATA_SIZE{q0sel[0]}} & { brdata0eff[BRDATA_SIZE-1:0]}) |
|
||||
({BRDATA_SIZE{q0sel[1]}} & {{1*BRDATA_WIDTH{1'b0}},brdata0eff[BRDATA_SIZE-1:1*BRDATA_WIDTH]}) |
|
||||
({BRDATA_SIZE{q0sel[2]}} & {{2*BRDATA_WIDTH{1'b0}},brdata0eff[BRDATA_SIZE-1:2*BRDATA_WIDTH]}) |
|
||||
({BRDATA_SIZE{q0sel[3]}} & {{3*BRDATA_WIDTH{1'b0}},brdata0eff[BRDATA_SIZE-1:3*BRDATA_WIDTH]}) |
|
||||
|
|
@ -444,7 +444,7 @@ module ifu_aln_ctl
|
|||
({BRDATA_SIZE{q0sel[6]}} & {{6*BRDATA_WIDTH{1'b0}},brdata0eff[BRDATA_SIZE-1:6*BRDATA_WIDTH]}) |
|
||||
({BRDATA_SIZE{q0sel[7]}} & {{7*BRDATA_WIDTH{1'b0}},brdata0eff[BRDATA_SIZE-1:7*BRDATA_WIDTH]}));
|
||||
|
||||
assign brdata1final[BRDATA_SIZE-1:0] = (({BRDATA_SIZE{q1sel[0]}} & { brdata1eff[8*6-1:0*6]}) |
|
||||
assign brdata1final[BRDATA_SIZE-1:0] = (({BRDATA_SIZE{q1sel[0]}} & { brdata1eff[BRDATA_SIZE-1:0]}) |
|
||||
({BRDATA_SIZE{q1sel[1]}} & {{1*BRDATA_WIDTH{1'b0}},brdata1eff[BRDATA_SIZE-1:1*BRDATA_WIDTH]}) |
|
||||
({BRDATA_SIZE{q1sel[2]}} & {{2*BRDATA_WIDTH{1'b0}},brdata1eff[BRDATA_SIZE-1:2*BRDATA_WIDTH]}) |
|
||||
({BRDATA_SIZE{q1sel[3]}} & {{3*BRDATA_WIDTH{1'b0}},brdata1eff[BRDATA_SIZE-1:3*BRDATA_WIDTH]}) |
|
||||
|
|
@ -454,25 +454,25 @@ module ifu_aln_ctl
|
|||
({BRDATA_SIZE{q1sel[7]}} & {{7*BRDATA_WIDTH{1'b0}},brdata1eff[BRDATA_SIZE-1:7*BRDATA_WIDTH]}));
|
||||
|
||||
assign {
|
||||
f0hist1[7],f0hist0[7],f0pc4[7],f0way[7],f0brend[7],f0ret[7],
|
||||
f0hist1[6],f0hist0[6],f0pc4[6],f0way[6],f0brend[6],f0ret[6],
|
||||
f0hist1[5],f0hist0[5],f0pc4[5],f0way[5],f0brend[5],f0ret[5],
|
||||
f0hist1[4],f0hist0[4],f0pc4[4],f0way[4],f0brend[4],f0ret[4],
|
||||
f0hist1[3],f0hist0[3],f0pc4[3],f0way[3],f0brend[3],f0ret[3],
|
||||
f0hist1[2],f0hist0[2],f0pc4[2],f0way[2],f0brend[2],f0ret[2],
|
||||
f0hist1[1],f0hist0[1],f0pc4[1],f0way[1],f0brend[1],f0ret[1],
|
||||
f0hist1[0],f0hist0[0],f0pc4[0],f0way[0],f0brend[0],f0ret[0]
|
||||
f0dbecc[7],f0icaf[7],f0hist1[7],f0hist0[7],f0pc4[7],f0way[7],f0brend[7],f0ret[7],
|
||||
f0dbecc[6],f0icaf[6],f0hist1[6],f0hist0[6],f0pc4[6],f0way[6],f0brend[6],f0ret[6],
|
||||
f0dbecc[5],f0icaf[5],f0hist1[5],f0hist0[5],f0pc4[5],f0way[5],f0brend[5],f0ret[5],
|
||||
f0dbecc[4],f0icaf[4],f0hist1[4],f0hist0[4],f0pc4[4],f0way[4],f0brend[4],f0ret[4],
|
||||
f0dbecc[3],f0icaf[3],f0hist1[3],f0hist0[3],f0pc4[3],f0way[3],f0brend[3],f0ret[3],
|
||||
f0dbecc[2],f0icaf[2],f0hist1[2],f0hist0[2],f0pc4[2],f0way[2],f0brend[2],f0ret[2],
|
||||
f0dbecc[1],f0icaf[1],f0hist1[1],f0hist0[1],f0pc4[1],f0way[1],f0brend[1],f0ret[1],
|
||||
f0dbecc[0],f0icaf[0],f0hist1[0],f0hist0[0],f0pc4[0],f0way[0],f0brend[0],f0ret[0]
|
||||
} = brdata0final[BRDATA_SIZE-1:0];
|
||||
|
||||
assign {
|
||||
f1hist1[7],f1hist0[7],f1pc4[7],f1way[7],f1brend[7],f1ret[7],
|
||||
f1hist1[6],f1hist0[6],f1pc4[6],f1way[6],f1brend[6],f1ret[6],
|
||||
f1hist1[5],f1hist0[5],f1pc4[5],f1way[5],f1brend[5],f1ret[5],
|
||||
f1hist1[4],f1hist0[4],f1pc4[4],f1way[4],f1brend[4],f1ret[4],
|
||||
f1hist1[3],f1hist0[3],f1pc4[3],f1way[3],f1brend[3],f1ret[3],
|
||||
f1hist1[2],f1hist0[2],f1pc4[2],f1way[2],f1brend[2],f1ret[2],
|
||||
f1hist1[1],f1hist0[1],f1pc4[1],f1way[1],f1brend[1],f1ret[1],
|
||||
f1hist1[0],f1hist0[0],f1pc4[0],f1way[0],f1brend[0],f1ret[0]
|
||||
f1dbecc[7],f1icaf[7],f1hist1[7],f1hist0[7],f1pc4[7],f1way[7],f1brend[7],f1ret[7],
|
||||
f1dbecc[6],f1icaf[6],f1hist1[6],f1hist0[6],f1pc4[6],f1way[6],f1brend[6],f1ret[6],
|
||||
f1dbecc[5],f1icaf[5],f1hist1[5],f1hist0[5],f1pc4[5],f1way[5],f1brend[5],f1ret[5],
|
||||
f1dbecc[4],f1icaf[4],f1hist1[4],f1hist0[4],f1pc4[4],f1way[4],f1brend[4],f1ret[4],
|
||||
f1dbecc[3],f1icaf[3],f1hist1[3],f1hist0[3],f1pc4[3],f1way[3],f1brend[3],f1ret[3],
|
||||
f1dbecc[2],f1icaf[2],f1hist1[2],f1hist0[2],f1pc4[2],f1way[2],f1brend[2],f1ret[2],
|
||||
f1dbecc[1],f1icaf[1],f1hist1[1],f1hist0[1],f1pc4[1],f1way[1],f1brend[1],f1ret[1],
|
||||
f1dbecc[0],f1icaf[0],f1hist1[0],f1hist0[0],f1pc4[0],f1way[0],f1brend[0],f1ret[0]
|
||||
} = brdata1final[BRDATA_SIZE-1:0];
|
||||
|
||||
|
||||
|
|
@ -711,11 +711,10 @@ module ifu_aln_ctl
|
|||
({4{(f0val[1]&~f0val[2])}} & {f1val[1:0],2'b11}) |
|
||||
({4{(f0val[0]&~f0val[1])}} & {f1val[2:0],1'b1});
|
||||
|
||||
assign alignicaf[3:0] = ({4{(f0val[3])}} & {4{f0icaf}}) |
|
||||
({4{(f0val[2]&~f0val[3])}} & {{1{f1icaf}},{3{f0icaf}}}) |
|
||||
({4{(f0val[1]&~f0val[2])}} & {{2{f1icaf}},{2{f0icaf}}}) |
|
||||
({4{(f0val[0]&~f0val[1])}} & {{3{f1icaf}},{1{f0icaf}}});
|
||||
|
||||
assign alignicaf[3:0] = ({4{(f0val[3])}} & f0icaf[3:0]) |
|
||||
({4{(f0val[2]&~f0val[3])}} & {f1icaf[0],f0icaf[2:0]}) |
|
||||
({4{(f0val[1]&~f0val[2])}} & {f1icaf[1:0],f0icaf[1:0]}) |
|
||||
({4{(f0val[0]&~f0val[1])}} & {f1icaf[2:0],f0icaf[0]});
|
||||
|
||||
assign alignsbecc[3:0] = ({4{(f0val[3])}} & {4{f0sbecc}}) |
|
||||
({4{(f0val[2]&~f0val[3])}} & {{1{f1sbecc}},{3{f0sbecc}}}) |
|
||||
|
|
@ -723,10 +722,10 @@ module ifu_aln_ctl
|
|||
({4{(f0val[0]&~f0val[1])}} & {{3{f1sbecc}},{1{f0sbecc}}});
|
||||
|
||||
|
||||
assign aligndbecc[3:0] = ({4{(f0val[3])}} & {4{f0dbecc}}) |
|
||||
({4{(f0val[2]&~f0val[3])}} & {{1{f1dbecc}},{3{f0dbecc}}}) |
|
||||
({4{(f0val[1]&~f0val[2])}} & {{2{f1dbecc}},{2{f0dbecc}}}) |
|
||||
({4{(f0val[0]&~f0val[1])}} & {{3{f1dbecc}},{1{f0dbecc}}});
|
||||
assign aligndbecc[3:0] = ({4{(f0val[3])}} & f0dbecc[3:0]) |
|
||||
({4{(f0val[2]&~f0val[3])}} & {f1dbecc[0],f0dbecc[2:0]}) |
|
||||
({4{(f0val[1]&~f0val[2])}} & {f1dbecc[1:0],f0dbecc[1:0]}) |
|
||||
({4{(f0val[0]&~f0val[1])}} & {f1dbecc[2:0],f0dbecc[0]});
|
||||
|
||||
// for branch prediction
|
||||
assign alignbrend[3:0] = ({4{(f0val[3])}} & f0brend[3:0]) |
|
||||
|
|
@ -865,7 +864,6 @@ module ifu_aln_ctl
|
|||
|
||||
`endif // !`ifdef RV_ICACHE_ECC
|
||||
|
||||
|
||||
// logic for trace
|
||||
assign ifu_i0_cinst[15:0] = aligndata[15:0];
|
||||
assign ifu_i1_cinst[15:0] = (first4B) ? aligndata[47:32] : aligndata[31:16];
|
||||
|
|
@ -896,19 +894,17 @@ module ifu_aln_ctl
|
|||
|
||||
|
||||
|
||||
assign icaf_eff[3:1] = alignicaf[3:1] | aligndbecc[3:1];
|
||||
assign icaf_eff[3:0] = alignicaf[3:0] | aligndbecc[3:0];
|
||||
|
||||
assign ifu_i0_icaf_f1 = first4B & icaf_eff[1] & alignfromf1[1];
|
||||
assign ifu_i0_icaf_second = first4B & ~icaf_eff[0] & icaf_eff[1];
|
||||
|
||||
assign ifu_i1_icaf = ((first4B & third4B & (|alignicaf[3:2])) |
|
||||
(first4B & third2B & alignicaf[2]) |
|
||||
(first2B & second4B & (|alignicaf[2:1])) |
|
||||
(first2B & second2B & alignicaf[1])) & ~exu_flush_final;
|
||||
|
||||
assign ifu_i1_icaf_f1 = (first4B & third4B & icaf_eff[2] & alignfromf1[2]) |
|
||||
(first4B & third4B & icaf_eff[3] & alignfromf1[3] & ~icaf_eff[2]) |
|
||||
(first2B & second4B & icaf_eff[1] & alignfromf1[1]) |
|
||||
(first2B & second4B & icaf_eff[2] & alignfromf1[2] & ~icaf_eff[1]);
|
||||
assign ifu_i1_icaf_second = (first4B & third4B & ~icaf_eff[2] & icaf_eff[3]) |
|
||||
(first2B & second4B & ~icaf_eff[1] & icaf_eff[2]);
|
||||
|
||||
// inst parity error on any byte of inst results in parity error for the inst
|
||||
|
||||
|
|
|
|||
|
|
@ -167,10 +167,10 @@ module ifu_mem_ctl
|
|||
// IFU control signals
|
||||
output logic ic_hit_f2, // Hit in Icache(if Icache access) or ICCM access( ICCM always has ic_hit_f2)
|
||||
output logic ic_crit_wd_rdy, // Critical fetch is ready to be bypassed.
|
||||
output logic ic_access_fault_f2, // Access fault (bus error or ICCM access in region but out of offset range).
|
||||
output logic [7:0] ic_access_fault_f2, // Access fault (bus error or ICCM access in region but out of offset range).
|
||||
output logic ic_rd_parity_final_err, // This fetch has an tag parity error.
|
||||
output logic iccm_rd_ecc_single_err, // This fetch has a single ICCM ecc error.
|
||||
output logic iccm_rd_ecc_double_err, // This fetch has a double ICCM ecc error.
|
||||
output logic [7:0] iccm_rd_ecc_double_err, // This fetch has a double ICCM ecc error.
|
||||
output logic iccm_dma_sb_error, // Single Bit ECC error from a DMA access
|
||||
output logic [7:0] ic_fetch_val_f2, // valid bytes for fetch. To the Aligner.
|
||||
output logic [127:0] ic_data_f2, // Data read from Icache or ICCM. To the Aligner.
|
||||
|
|
@ -241,7 +241,7 @@ module ifu_mem_ctl
|
|||
|
||||
logic ifu_wr_data_comb_err ;
|
||||
logic ifu_wr_data_error;
|
||||
logic ifu_byp_data_err;
|
||||
logic [7:0] ifu_byp_data_err;
|
||||
logic ifu_wr_cumulative_err_data;
|
||||
logic ifu_wr_cumulative_err;
|
||||
logic ifu_wr_data_comb_err_ff;
|
||||
|
|
@ -251,7 +251,7 @@ module ifu_mem_ctl
|
|||
logic ifc_dma_access_q_ok;
|
||||
logic ifc_iccm_access_f2 ;
|
||||
logic ifc_region_acc_fault_f2;
|
||||
logic ifc_bus_acc_fault_f2;
|
||||
logic [7:0] ifc_bus_acc_fault_f2;
|
||||
logic ic_act_miss_f2;
|
||||
logic ic_miss_under_miss_f2;
|
||||
logic ic_act_hit_f2;
|
||||
|
|
@ -626,7 +626,7 @@ end
|
|||
`endif
|
||||
|
||||
|
||||
assign sel_byp_data = ic_crit_wd_rdy & ~ifu_byp_data_err;
|
||||
assign sel_byp_data = ic_crit_wd_rdy ;//& ~ifu_byp_data_err;
|
||||
assign sel_ic_data = ~ic_crit_wd_rdy & ~fetch_req_iccm_f2 ;
|
||||
`ifdef ICCM_AND_ICACHE
|
||||
assign sel_iccm_data = fetch_req_iccm_f2 ;
|
||||
|
|
@ -664,13 +664,13 @@ end
|
|||
|
||||
assign ifu_icache_fetch_f2 = sel_ic_data ;
|
||||
|
||||
assign ifc_bus_acc_fault_f2 = ic_byp_hit_f2 & ifu_byp_data_err ;
|
||||
assign ifc_bus_acc_fault_f2[7:0] = {8{ic_byp_hit_f2}} & ifu_byp_data_err[7:0] ;
|
||||
assign ic_data_f2[127:0] = ic_final_data[127:0];
|
||||
|
||||
|
||||
rvdff #(1) flush_final_ff (.*, .clk(free_clk), .din({exu_flush_final}), .dout({flush_final_f2}));
|
||||
assign fetch_req_f2_qual = ic_hit_f2 & ~exu_flush_final;
|
||||
assign ic_access_fault_f2 = (ifc_region_acc_fault_f2 | ifc_bus_acc_fault_f2) & ~exu_flush_final;
|
||||
assign ic_access_fault_f2[7:0] = ({8{ifc_region_acc_fault_f2}} | ifc_bus_acc_fault_f2[7:0]) & {8{~exu_flush_final}};
|
||||
|
||||
// right justified
|
||||
assign ic_fetch_val_f2[7] = fetch_req_f2_qual & ifu_bp_inst_mask_f2[7] & ((!vaddr_f2[3]&!vaddr_f2[2]&!vaddr_f2[1]));
|
||||
|
|
@ -772,8 +772,8 @@ assign ic_fetch_val_f2[0] = fetch_req_f2_qual ;
|
|||
.dout(ifu_byp_data_second_half_valid));
|
||||
|
||||
assign ic_byp_data_only[127:0] = { ifu_byp_data_second_half[63:0] , ifu_byp_data_first_half[63:0] } ;
|
||||
assign ifu_byp_data_err = ifu_byp_data_error_second_half | ifu_byp_data_error_first_half ;
|
||||
|
||||
assign ifu_byp_data_err[7:0] = {{4{ ifu_byp_data_error_second_half}} , {4{ifu_byp_data_error_first_half}}} ;
|
||||
|
||||
// Critical word ready.
|
||||
assign ic_crit_wd_complete = (write_byp_first_data & ifu_byp_data_second_half_valid) |
|
||||
|
|
@ -893,7 +893,7 @@ rvecc_decode ecc_decode (
|
|||
end
|
||||
|
||||
assign iccm_rd_ecc_single_err = (|iccm_single_ecc_error ) & ifc_iccm_access_f2;
|
||||
assign iccm_rd_ecc_double_err = (|iccm_double_ecc_error ) & ifc_iccm_access_f2;
|
||||
assign iccm_rd_ecc_double_err[7:0] = ({{2{iccm_double_ecc_error[3]}}, {2{iccm_double_ecc_error[2]}} , {2{iccm_double_ecc_error[1]}} , {2{iccm_double_ecc_error[0]}}} ) & {8{ifc_iccm_access_f2}};
|
||||
|
||||
assign iccm_corrected_data_f2_mux[31:0] = iccm_single_ecc_error[0] ? iccm_corrected_data[0] :
|
||||
iccm_single_ecc_error[1] ? iccm_corrected_data[1] :
|
||||
|
|
@ -926,7 +926,7 @@ assign iccm_corrected_ecc_f2_mux[06:0] = iccm_single_ecc_error[0] ? iccm_correc
|
|||
|
||||
`else
|
||||
assign iccm_rd_ecc_single_err = 1'b0 ;
|
||||
assign iccm_rd_ecc_double_err = 1'b0 ;
|
||||
assign iccm_rd_ecc_double_err = '0 ;
|
||||
assign iccm_rd_ecc_single_err_ff = 1'b0 ;
|
||||
|
||||
assign iccm_ecc_corr_index_ff[ICCM_BITS-1:2] = '0;
|
||||
|
|
@ -1370,7 +1370,7 @@ assign ifu_ic_rw_int_addr_w_debug[ICACHE_TAG_HIGH-1:ICACHE_TAG_LOW] = ((ic_debug
|
|||
|
||||
assign ifu_pmu_ic_miss_in = ic_act_miss_f2 ;
|
||||
assign ifu_pmu_ic_hit_in = ic_act_hit_f2 ;
|
||||
assign ifu_pmu_bus_error_in = ifc_bus_acc_fault_f2;
|
||||
assign ifu_pmu_bus_error_in = |ifc_bus_acc_fault_f2;
|
||||
assign ifu_pmu_bus_trxn_in = axi_cmd_sent ;
|
||||
assign ifu_pmu_bus_busy_in = ifu_axi_arvalid_ff & ~ifu_axi_arready_ff & miss_pending ;
|
||||
|
||||
|
|
|
|||
|
|
@ -130,7 +130,7 @@ typedef struct packed {
|
|||
typedef struct packed {
|
||||
logic legal;
|
||||
logic icaf;
|
||||
logic icaf_f1;
|
||||
logic icaf_second;
|
||||
logic perr;
|
||||
logic sbecc;
|
||||
logic fence_i;
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@ module pic_ctrl
|
|||
input logic active_clk, // active clock
|
||||
input logic rst_l, // Reset for all flops
|
||||
input logic clk_override, // Clock over-ride for gating
|
||||
input logic lsu_freeze_dc3, // LSU pipeline freeze
|
||||
input logic [`RV_PIC_TOTAL_INT_PLUS1-1:0] extintsrc_req, // Interrupt requests
|
||||
input logic [31:0] picm_addr, // Address of the register
|
||||
input logic [31:0] picm_wr_data, // Data to be written to the register
|
||||
|
|
@ -121,6 +122,8 @@ logic [ID_BITS-1:0] claimid_in ;
|
|||
logic [INTPRIORITY_BITS-1:0] pl_in ;
|
||||
logic [INTPRIORITY_BITS-1:0] pl_in_q ;
|
||||
|
||||
logic picm_rden_in, picm_mken_in;
|
||||
|
||||
logic [TOTAL_INT-1:0] extintsrc_req_sync;
|
||||
logic [TOTAL_INT-1:0] extintsrc_req_gw;
|
||||
|
||||
|
|
@ -140,7 +143,7 @@ logic [TOTAL_INT-1:0] extintsrc_req_gw;
|
|||
|
||||
// ---- Clock gating section ------
|
||||
// c1 clock enables
|
||||
assign pic_addr_c1_clken = picm_mken | picm_rden | picm_wren | clk_override;
|
||||
assign pic_addr_c1_clken = (picm_mken | picm_rden | picm_wren | clk_override) & ~lsu_freeze_dc3;
|
||||
assign pic_data_c1_clken = picm_wren | clk_override;
|
||||
assign pic_pri_c1_clken = (addr_intpriority_base_match & (picm_wren_ff | picm_rden_ff)) | clk_override;
|
||||
assign pic_int_c1_clken = (addr_intenable_base_match & (picm_wren_ff | picm_rden_ff)) | clk_override;
|
||||
|
|
@ -162,12 +165,13 @@ assign addr_config_pic_match = (picm_addr_ff[31:0] == EXT_INTR
|
|||
assign addr_config_gw_base_match = (picm_addr_ff[31:NUM_LEVELS+2] == EXT_INTR_GW_CONFIG[31:NUM_LEVELS+2]) ;
|
||||
assign addr_clear_gw_base_match = (picm_addr_ff[31:NUM_LEVELS+2] == EXT_INTR_GW_CLEAR[31:NUM_LEVELS+2]) ;
|
||||
|
||||
|
||||
assign picm_rden_in = lsu_freeze_dc3 ? picm_rden_ff : picm_rden;
|
||||
assign picm_mken_in = lsu_freeze_dc3 ? picm_mken_ff : picm_mken;
|
||||
|
||||
rvdff #(32) picm_add_flop (.*, .din (picm_addr), .dout(picm_addr_ff), .clk(pic_addr_c1_clk));
|
||||
rvdff #(1) picm_wre_flop (.*, .din (picm_wren), .dout(picm_wren_ff), .clk(active_clk));
|
||||
rvdff #(1) picm_rde_flop (.*, .din (picm_rden), .dout(picm_rden_ff), .clk(active_clk));
|
||||
rvdff #(1) picm_mke_flop (.*, .din (picm_mken), .dout(picm_mken_ff), .clk(active_clk));
|
||||
rvdff #(1) picm_rde_flop (.*, .din (picm_rden_in), .dout(picm_rden_ff), .clk(active_clk));
|
||||
rvdff #(1) picm_mke_flop (.*, .din (picm_mken_in), .dout(picm_mken_ff), .clk(active_clk));
|
||||
rvdff #(32) picm_dat_flop (.*, .din (picm_wr_data[31:0]), .dout(picm_wr_data_ff[31:0]), .clk(pic_data_c1_clk));
|
||||
|
||||
rvsyncss #(TOTAL_INT-1) sync_inst
|
||||
|
|
|
|||
|
|
@ -837,8 +837,8 @@ module swerv
|
|||
|
||||
logic ifu_i0_icaf;
|
||||
logic ifu_i1_icaf;
|
||||
logic ifu_i0_icaf_f1;
|
||||
logic ifu_i1_icaf_f1;
|
||||
logic ifu_i0_icaf_second;
|
||||
logic ifu_i1_icaf_second;
|
||||
logic ifu_i0_perr;
|
||||
logic ifu_i1_perr;
|
||||
logic ifu_i0_sbecc;
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
# RISC-V SweRV EH1 V1.7 core from Western Digital
|
||||
# RISC-V SweRV EH1 1.5 core from Western Digital
|
||||
|
||||
## Documentation
|
||||
|
||||
### Contents
|
||||
Name | Description
|
||||
---------------------- | ------------------------------
|
||||
RISC-V_SweRV_EH1_PRM.pdf | Programmer's Reference Manual V1.7 for SweRV EH1 core
|
||||
RISC-V_SweRV_EH1_PRM.pdf | Programmer's Reference Manual V1.5 for SweRV EH1 core
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -1,3 +1,13 @@
|
|||
# SweRV RISC-V Core<sup>TM</sup> 1.8 from Western Digital
|
||||
## Release Notes
|
||||
|
||||
* Enhanced Debug module to support access to system bus via abstract memory commands (see PRM chapter 9)
|
||||
* Enhanced mpmc firmware halt CSR to add atomic MSTATUS.IE enable to mpmc CSR (see PRM section 5.5.1)
|
||||
* Fixed 3 debug module issues reported by Codasip
|
||||
* Fixed bug with IO load speculation
|
||||
* Fixed issue with PIC ld/st access following a pipe freeze
|
||||
* Improvements to demo testbench
|
||||
|
||||
# SweRV RISC-V Core<sup>TM</sup> 1.7 from Western Digital
|
||||
## Release Notes
|
||||
|
||||
|
|
|
|||
|
|
@ -33,17 +33,20 @@ output logic HRESP,
|
|||
output logic [63:0] HRDATA
|
||||
);
|
||||
|
||||
parameter MEM_SIZE_DW = 8192;
|
||||
parameter MAILBOX_ADDR = 32'hD0580000;
|
||||
localparam MEM_SIZE = MEM_SIZE_DW*8;
|
||||
|
||||
logic Write;
|
||||
logic [31:0] Last_HADDR;
|
||||
logic write;
|
||||
logic [31:0] laddr, addr;
|
||||
logic [7:0] strb_lat;
|
||||
logic [63:0] rdata;
|
||||
|
||||
bit [7:0] mem [0:MEM_SIZE-1];
|
||||
//bit [7:0] mem [int];
|
||||
//int kuku[int];
|
||||
bit [7:0] mem [bit[31:0]];
|
||||
bit [7:0] wscnt;
|
||||
int dws = 0;
|
||||
int iws = 0;
|
||||
bit dws_rand;
|
||||
bit iws_rand;
|
||||
bit ok;
|
||||
|
||||
// Wires
|
||||
wire [63:0] WriteData = HWDATA;
|
||||
|
|
@ -51,50 +54,79 @@ wire [7:0] strb = HSIZE == 3'b000 ? 8'h1 << HADDR[2:0] :
|
|||
HSIZE == 3'b001 ? 8'h3 << {HADDR[2:1],1'b0} :
|
||||
HSIZE == 3'b010 ? 8'hf << {HADDR[2],2'b0} : 8'hff;
|
||||
|
||||
wire[31:0] addr = HADDR & (MEM_SIZE-1);
|
||||
wire[31:0] laddr = Last_HADDR & (MEM_SIZE-1);
|
||||
|
||||
wire mailbox_write = Write && Last_HADDR==MAILBOX_ADDR;
|
||||
|
||||
wire [63:0] mem_dout = {mem[{addr[31:3],3'd7}],
|
||||
mem[{addr[31:3],3'd6}],
|
||||
mem[{addr[31:3],3'd5}],
|
||||
mem[{addr[31:3],3'd4}],
|
||||
mem[{addr[31:3],3'd3}],
|
||||
mem[{addr[31:3],3'd2}],
|
||||
mem[{addr[31:3],3'd1}],
|
||||
mem[{addr[31:3],3'd0}]};
|
||||
wire mailbox_write = write && laddr==MAILBOX_ADDR;
|
||||
|
||||
|
||||
always @ (negedge HCLK ) begin
|
||||
if (Write) begin
|
||||
if(strb_lat[7]) mem[{laddr[31:3],3'd7}] = HWDATA[63:56];
|
||||
if(strb_lat[6]) mem[{laddr[31:3],3'd6}] = HWDATA[55:48];
|
||||
if(strb_lat[5]) mem[{laddr[31:3],3'd5}] = HWDATA[47:40];
|
||||
if(strb_lat[4]) mem[{laddr[31:3],3'd4}] = HWDATA[39:32];
|
||||
if(strb_lat[3]) mem[{laddr[31:3],3'd3}] = HWDATA[31:24];
|
||||
if(strb_lat[2]) mem[{laddr[31:3],3'd2}] = HWDATA[23:16];
|
||||
if(strb_lat[1]) mem[{laddr[31:3],3'd1}] = HWDATA[15:08];
|
||||
if(strb_lat[0]) mem[{laddr[31:3],3'd0}] = HWDATA[07:00];
|
||||
end
|
||||
initial begin
|
||||
if ($value$plusargs("iws=%d", iws));
|
||||
if ($value$plusargs("dws=%d", dws));
|
||||
dws_rand = dws < 0;
|
||||
iws_rand = iws < 0;
|
||||
end
|
||||
|
||||
|
||||
assign HREADYOUT = 1;
|
||||
|
||||
always @ (negedge HCLK ) begin
|
||||
if(HREADY)
|
||||
addr = HADDR;
|
||||
if (write & HREADY) begin
|
||||
if(strb_lat[7]) mem[{laddr[31:3],3'd7}] = HWDATA[63:56];
|
||||
if(strb_lat[6]) mem[{laddr[31:3],3'd6}] = HWDATA[55:48];
|
||||
if(strb_lat[5]) mem[{laddr[31:3],3'd5}] = HWDATA[47:40];
|
||||
if(strb_lat[4]) mem[{laddr[31:3],3'd4}] = HWDATA[39:32];
|
||||
if(strb_lat[3]) mem[{laddr[31:3],3'd3}] = HWDATA[31:24];
|
||||
if(strb_lat[2]) mem[{laddr[31:3],3'd2}] = HWDATA[23:16];
|
||||
if(strb_lat[1]) mem[{laddr[31:3],3'd1}] = HWDATA[15:08];
|
||||
if(strb_lat[0]) mem[{laddr[31:3],3'd0}] = HWDATA[07:00];
|
||||
end
|
||||
if(HREADY & HSEL & |HTRANS) begin
|
||||
`ifdef VERILATOR
|
||||
if(iws_rand & ~HPROT[0])
|
||||
iws = $random & 15;
|
||||
if(dws_rand & HPROT[0])
|
||||
dws = $random & 15;
|
||||
`else
|
||||
if(iws_rand & ~HPROT[0])
|
||||
ok = std::randomize(iws) with {iws dist {0:=10, [1:3]:/2, [4:15]:/1};};
|
||||
if(dws_rand & HPROT[0])
|
||||
ok = std::randomize(dws) with {dws dist {0:=10, [1:3]:/2, [4:15]:/1};};
|
||||
`endif
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
assign HRDATA = HREADY ? rdata : ~rdata;
|
||||
assign HREADYOUT = wscnt == 0;
|
||||
assign HRESP = 0;
|
||||
|
||||
always @(posedge HCLK or negedge HRESETn) begin
|
||||
if(~HRESETn) begin
|
||||
Last_HADDR <= 32'b0;
|
||||
Write <= 1'b0;
|
||||
HRDATA <= '0;
|
||||
end else begin
|
||||
Last_HADDR <= HADDR;
|
||||
Write <= HWRITE & |HTRANS;
|
||||
if(|HTRANS & ~HWRITE)
|
||||
HRDATA <= mem_dout;
|
||||
strb_lat <= strb;
|
||||
end
|
||||
if(~HRESETn) begin
|
||||
laddr <= 32'b0;
|
||||
write <= 1'b0;
|
||||
rdata <= '0;
|
||||
wscnt <= 0;
|
||||
end
|
||||
else begin
|
||||
if(HREADY & HSEL) begin
|
||||
laddr <= HADDR;
|
||||
write <= HWRITE & |HTRANS;
|
||||
if(|HTRANS & ~HWRITE)
|
||||
rdata <= {mem[{addr[31:3],3'd7}],
|
||||
mem[{addr[31:3],3'd6}],
|
||||
mem[{addr[31:3],3'd5}],
|
||||
mem[{addr[31:3],3'd4}],
|
||||
mem[{addr[31:3],3'd3}],
|
||||
mem[{addr[31:3],3'd2}],
|
||||
mem[{addr[31:3],3'd1}],
|
||||
mem[{addr[31:3],3'd0}]};
|
||||
strb_lat <= strb;
|
||||
end
|
||||
end
|
||||
if(HREADY & HSEL & |HTRANS)
|
||||
wscnt <= HPROT[0] ? dws[7:0] : iws[7:0];
|
||||
else if(wscnt != 0)
|
||||
wscnt <= wscnt-1;
|
||||
end
|
||||
|
||||
|
||||
|
|
@ -142,14 +174,11 @@ output reg [TAGW-1:0] bid
|
|||
parameter MAILBOX_ADDR = 32'hD0580000;
|
||||
parameter MEM_SIZE_DW = 8192;
|
||||
|
||||
bit [7:0] mem [0:MEM_SIZE_DW*8-1];
|
||||
bit [7:0] mem [bit[31:0]];
|
||||
bit [63:0] memdata;
|
||||
wire [31:0] waddr, raddr;
|
||||
wire [63:0] WriteData;
|
||||
wire mailbox_write;
|
||||
|
||||
assign raddr = araddr & (MEM_SIZE_DW*8-1);
|
||||
assign waddr = awaddr & (MEM_SIZE_DW*8-1);
|
||||
|
||||
assign mailbox_write = awvalid && awaddr==MAILBOX_ADDR && rst_l;
|
||||
assign WriteData = wdata;
|
||||
|
|
@ -169,17 +198,17 @@ always @ ( posedge aclk or negedge rst_l) begin
|
|||
end
|
||||
|
||||
always @ ( negedge aclk) begin
|
||||
if(arvalid) memdata <= {mem[raddr+7], mem[raddr+6], mem[raddr+5], mem[raddr+4],
|
||||
mem[raddr+3], mem[raddr+2], mem[raddr+1], mem[raddr]};
|
||||
if(arvalid) memdata <= {mem[araddr+7], mem[araddr+6], mem[araddr+5], mem[araddr+4],
|
||||
mem[araddr+3], mem[araddr+2], mem[araddr+1], mem[araddr]};
|
||||
if(awvalid) begin
|
||||
if(wstrb[7]) mem[waddr+7] = wdata[63:56];
|
||||
if(wstrb[6]) mem[waddr+6] = wdata[55:48];
|
||||
if(wstrb[5]) mem[waddr+5] = wdata[47:40];
|
||||
if(wstrb[4]) mem[waddr+4] = wdata[39:32];
|
||||
if(wstrb[3]) mem[waddr+3] = wdata[31:24];
|
||||
if(wstrb[2]) mem[waddr+2] = wdata[23:16];
|
||||
if(wstrb[1]) mem[waddr+1] = wdata[15:08];
|
||||
if(wstrb[0]) mem[waddr+0] = wdata[07:00];
|
||||
if(wstrb[7]) mem[awaddr+7] = wdata[63:56];
|
||||
if(wstrb[6]) mem[awaddr+6] = wdata[55:48];
|
||||
if(wstrb[5]) mem[awaddr+5] = wdata[47:40];
|
||||
if(wstrb[4]) mem[awaddr+4] = wdata[39:32];
|
||||
if(wstrb[3]) mem[awaddr+3] = wdata[31:24];
|
||||
if(wstrb[2]) mem[awaddr+2] = wdata[23:16];
|
||||
if(wstrb[1]) mem[awaddr+1] = wdata[15:08];
|
||||
if(wstrb[0]) mem[awaddr+0] = wdata[07:00];
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -193,3 +222,4 @@ assign rlast = 1'b1;
|
|||
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
|
|
|
|||
|
|
@ -2266,7 +2266,7 @@ whisperPrintInt(int value, int base)
|
|||
do
|
||||
{
|
||||
int digit = uu & 0xf;
|
||||
char c = digit < 10 ? '0' + digit : 'a' + digit;
|
||||
char c = digit < 10 ? '0' + digit : 'a' + digit - 10;
|
||||
buffer[charCount++] = c;
|
||||
uu >>= 4;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2267,7 +2267,7 @@ whisperPrintInt(int value, int base)
|
|||
do
|
||||
{
|
||||
int digit = uu & 0xf;
|
||||
char c = digit < 10 ? '0' + digit : 'a' + digit;
|
||||
char c = digit < 10 ? '0' + digit : 'a' + digit - 10;
|
||||
buffer[charCount++] = c;
|
||||
uu >>= 4;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -6,12 +6,14 @@ MEMORY {
|
|||
EXTDATA : ORIGIN = 0x10000, LENGTH = 0x10000
|
||||
ICCM : ORIGIN = 0xee000000, LENGTH = 0x80000
|
||||
DCCM : ORIGIN = 0xf0040000, LENGTH = 0x10000
|
||||
CTL : ORIGIN = 0xfffffff0, LENGTH = 16
|
||||
}
|
||||
SECTIONS {
|
||||
.text_init : {*(.text_init)} > EXTCODE
|
||||
init_end = .;
|
||||
.data.ctl : AT(0xffec) { LONG(ADDR(.text)); LONG(text_end); LONG(LOADADDR(.text)); LONG(0xf0040000); LONG(STACK)}>EXTDATA
|
||||
.text : AT(init_end) { *(.text) *(.text.startup)} > ICCM
|
||||
.text : { *(.text) *(.text.startup)} > ICCM
|
||||
text_end = .;
|
||||
.data : AT(0x10000) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000;} > DCCM
|
||||
.data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;} > DCCM
|
||||
.bss : { *(.bss)} > DCCM
|
||||
.data.ctl : { LONG(ADDR(.text)); LONG(text_end); LONG(0xf0040000); LONG(STACK)}>CTL
|
||||
}
|
||||
|
|
|
|||
|
|
@ -5,8 +5,9 @@ ENTRY(_start)
|
|||
SECTIONS {
|
||||
.text : { *(.text*) }
|
||||
_end = .;
|
||||
. = 0xfff8;
|
||||
.data.ctl : { LONG(0xf0040000); LONG(STACK) }
|
||||
. = 0xf0040000;
|
||||
.data : AT(0x10000) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000;}
|
||||
.data : { *(.*data) *(.rodata*) *(.sbss) STACK = ALIGN(16) + 0x1000;}
|
||||
.bss : { *(.bss) }
|
||||
. = 0xfffffff8;
|
||||
.data.ctl : { LONG(0xf0040000); LONG(STACK) }
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,93 +0,0 @@
|
|||
@00000000
|
||||
A4 05 01 00 AC 05 01 00 B4 05 01 00 96 3F 00 00
|
||||
96 3F 00 00 D0 3F 00 00 D0 3F 00 00 6C 40 00 00
|
||||
2E 7A 00 00 0E 7A 00 00 16 7A 00 00 1E 7A 00 00
|
||||
26 7A 00 00 06 7A 00 00 36 8B 00 00 60 85 00 00
|
||||
60 85 00 00 60 85 00 00 60 85 00 00 60 85 00 00
|
||||
60 85 00 00 60 85 00 00 60 85 00 00 60 85 00 00
|
||||
60 85 00 00 3C 8A 00 00 4A 8A 00 00 60 85 00 00
|
||||
60 85 00 00 60 85 00 00 60 85 00 00 60 85 00 00
|
||||
60 85 00 00 60 85 00 00 60 85 00 00 60 85 00 00
|
||||
60 85 00 00 7C 88 00 00 60 85 00 00 60 85 00 00
|
||||
60 85 00 00 10 88 00 00 60 85 00 00 24 87 00 00
|
||||
60 85 00 00 60 85 00 00 36 8B 00 00 84 05 01 00
|
||||
8C 05 01 00 94 05 01 00 9C 05 01 00 54 05 01 00
|
||||
60 05 01 00 6C 05 01 00 78 05 01 00 24 05 01 00
|
||||
30 05 01 00 3C 05 01 00 48 05 01 00 F4 04 01 00
|
||||
00 05 01 00 0C 05 01 00 18 05 01 00 01 00 00 00
|
||||
01 00 00 00 66 00 00 00 36 6B 20 70 65 72 66 6F
|
||||
72 6D 61 6E 63 65 20 72 75 6E 20 70 61 72 61 6D
|
||||
65 74 65 72 73 20 66 6F 72 20 63 6F 72 65 6D 61
|
||||
72 6B 2E 0A 00 00 00 00 36 6B 20 76 61 6C 69 64
|
||||
61 74 69 6F 6E 20 72 75 6E 20 70 61 72 61 6D 65
|
||||
74 65 72 73 20 66 6F 72 20 63 6F 72 65 6D 61 72
|
||||
6B 2E 0A 00 50 72 6F 66 69 6C 65 20 67 65 6E 65
|
||||
72 61 74 69 6F 6E 20 72 75 6E 20 70 61 72 61 6D
|
||||
65 74 65 72 73 20 66 6F 72 20 63 6F 72 65 6D 61
|
||||
72 6B 2E 0A 00 00 00 00 32 4B 20 70 65 72 66 6F
|
||||
72 6D 61 6E 63 65 20 72 75 6E 20 70 61 72 61 6D
|
||||
65 74 65 72 73 20 66 6F 72 20 63 6F 72 65 6D 61
|
||||
72 6B 2E 0A 00 00 00 00 32 4B 20 76 61 6C 69 64
|
||||
61 74 69 6F 6E 20 72 75 6E 20 70 61 72 61 6D 65
|
||||
74 65 72 73 20 66 6F 72 20 63 6F 72 65 6D 61 72
|
||||
6B 2E 0A 00 5B 25 75 5D 45 52 52 4F 52 21 20 6C
|
||||
69 73 74 20 63 72 63 20 30 78 25 30 34 78 20 2D
|
||||
20 73 68 6F 75 6C 64 20 62 65 20 30 78 25 30 34
|
||||
78 0A 00 00 5B 25 75 5D 45 52 52 4F 52 21 20 6D
|
||||
61 74 72 69 78 20 63 72 63 20 30 78 25 30 34 78
|
||||
20 2D 20 73 68 6F 75 6C 64 20 62 65 20 30 78 25
|
||||
30 34 78 0A 00 00 00 00 5B 25 75 5D 45 52 52 4F
|
||||
52 21 20 73 74 61 74 65 20 63 72 63 20 30 78 25
|
||||
30 34 78 20 2D 20 73 68 6F 75 6C 64 20 62 65 20
|
||||
30 78 25 30 34 78 0A 00 43 6F 72 65 4D 61 72 6B
|
||||
20 53 69 7A 65 20 20 20 20 3A 20 25 75 0A 00 00
|
||||
54 6F 74 61 6C 20 74 69 63 6B 73 20 20 20 20 20
|
||||
20 3A 20 25 75 0A 00 00 54 6F 74 61 6C 20 74 69
|
||||
6D 65 20 28 73 65 63 73 29 3A 20 25 64 0A 00 00
|
||||
45 52 52 4F 52 21 20 4D 75 73 74 20 65 78 65 63
|
||||
75 74 65 20 66 6F 72 20 61 74 20 6C 65 61 73 74
|
||||
20 31 30 20 73 65 63 73 20 66 6F 72 20 61 20 76
|
||||
61 6C 69 64 20 72 65 73 75 6C 74 21 0A 00 00 00
|
||||
49 74 65 72 61 74 2F 53 65 63 2F 4D 48 7A 20 20
|
||||
20 3A 20 25 64 2E 25 64 0A 00 00 00 49 74 65 72
|
||||
61 74 69 6F 6E 73 20 20 20 20 20 20 20 3A 20 25
|
||||
75 0A 00 00 47 43 43 37 2E 32 2E 30 00 00 00 00
|
||||
43 6F 6D 70 69 6C 65 72 20 76 65 72 73 69 6F 6E
|
||||
20 3A 20 25 73 0A 00 00 2D 4F 32 00 43 6F 6D 70
|
||||
69 6C 65 72 20 66 6C 61 67 73 20 20 20 3A 20 25
|
||||
73 0A 00 00 53 54 41 54 49 43 00 00 4D 65 6D 6F
|
||||
72 79 20 6C 6F 63 61 74 69 6F 6E 20 20 3A 20 25
|
||||
73 0A 00 00 73 65 65 64 63 72 63 20 20 20 20 20
|
||||
20 20 20 20 20 3A 20 30 78 25 30 34 78 0A 00 00
|
||||
5B 25 64 5D 63 72 63 6C 69 73 74 20 20 20 20 20
|
||||
20 20 3A 20 30 78 25 30 34 78 0A 00 5B 25 64 5D
|
||||
63 72 63 6D 61 74 72 69 78 20 20 20 20 20 3A 20
|
||||
30 78 25 30 34 78 0A 00 5B 25 64 5D 63 72 63 73
|
||||
74 61 74 65 20 20 20 20 20 20 3A 20 30 78 25 30
|
||||
34 78 0A 00 5B 25 64 5D 63 72 63 66 69 6E 61 6C
|
||||
20 20 20 20 20 20 3A 20 30 78 25 30 34 78 0A 00
|
||||
43 6F 72 72 65 63 74 20 6F 70 65 72 61 74 69 6F
|
||||
6E 20 76 61 6C 69 64 61 74 65 64 2E 20 53 65 65
|
||||
20 72 65 61 64 6D 65 2E 74 78 74 20 66 6F 72 20
|
||||
72 75 6E 20 61 6E 64 20 72 65 70 6F 72 74 69 6E
|
||||
67 20 72 75 6C 65 73 2E 0A 00 00 00 45 72 72 6F
|
||||
72 73 20 64 65 74 65 63 74 65 64 0A 00 00 00 00
|
||||
43 61 6E 6E 6F 74 20 76 61 6C 69 64 61 74 65 20
|
||||
6F 70 65 72 61 74 69 6F 6E 20 66 6F 72 20 74 68
|
||||
65 73 65 20 73 65 65 64 20 76 61 6C 75 65 73 2C
|
||||
20 70 6C 65 61 73 65 20 63 6F 6D 70 61 72 65 20
|
||||
77 69 74 68 20 72 65 73 75 6C 74 73 20 6F 6E 20
|
||||
61 20 6B 6E 6F 77 6E 20 70 6C 61 74 66 6F 72 6D
|
||||
2E 0A 00 00 54 30 2E 33 65 2D 31 46 00 00 00 00
|
||||
2D 54 2E 54 2B 2B 54 71 00 00 00 00 31 54 33 2E
|
||||
34 65 34 7A 00 00 00 00 33 34 2E 30 65 2D 54 5E
|
||||
00 00 00 00 35 2E 35 30 30 65 2B 33 00 00 00 00
|
||||
2D 2E 31 32 33 65 2D 32 00 00 00 00 2D 38 37 65
|
||||
2B 38 33 32 00 00 00 00 2B 30 2E 36 65 2D 31 32
|
||||
00 00 00 00 33 35 2E 35 34 34 30 30 00 00 00 00
|
||||
2E 31 32 33 34 35 30 30 00 00 00 00 2D 31 31 30
|
||||
2E 37 30 30 00 00 00 00 2B 30 2E 36 34 34 30 30
|
||||
00 00 00 00 35 30 31 32 00 00 00 00 31 32 33 34
|
||||
00 00 00 00 2D 38 37 34 00 00 00 00 2B 31 32 32
|
||||
00 00 00 00 53 74 61 74 69 63 00 00 48 65 61 70
|
||||
00 00 00 00 53 74 61 63 6B 00 00 00
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,95 +0,0 @@
|
|||
@00000000
|
||||
A4 05 04 F0 AC 05 04 F0 B4 05 04 F0 9A 3F 00 00
|
||||
9A 3F 00 00 D4 3F 00 00 D4 3F 00 00 70 40 00 00
|
||||
3E 7A 00 00 16 7A 00 00 20 7A 00 00 2A 7A 00 00
|
||||
34 7A 00 00 0C 7A 00 00 50 8B 00 00 7A 85 00 00
|
||||
7A 85 00 00 7A 85 00 00 7A 85 00 00 7A 85 00 00
|
||||
7A 85 00 00 7A 85 00 00 7A 85 00 00 7A 85 00 00
|
||||
7A 85 00 00 56 8A 00 00 64 8A 00 00 7A 85 00 00
|
||||
7A 85 00 00 7A 85 00 00 7A 85 00 00 7A 85 00 00
|
||||
7A 85 00 00 7A 85 00 00 7A 85 00 00 7A 85 00 00
|
||||
7A 85 00 00 96 88 00 00 7A 85 00 00 7A 85 00 00
|
||||
7A 85 00 00 2A 88 00 00 7A 85 00 00 3E 87 00 00
|
||||
7A 85 00 00 7A 85 00 00 50 8B 00 00 84 05 04 F0
|
||||
8C 05 04 F0 94 05 04 F0 9C 05 04 F0 54 05 04 F0
|
||||
60 05 04 F0 6C 05 04 F0 78 05 04 F0 24 05 04 F0
|
||||
30 05 04 F0 3C 05 04 F0 48 05 04 F0 F4 04 04 F0
|
||||
00 05 04 F0 0C 05 04 F0 18 05 04 F0 01 00 00 00
|
||||
01 00 00 00 66 00 00 00 36 6B 20 70 65 72 66 6F
|
||||
72 6D 61 6E 63 65 20 72 75 6E 20 70 61 72 61 6D
|
||||
65 74 65 72 73 20 66 6F 72 20 63 6F 72 65 6D 61
|
||||
72 6B 2E 0A 00 00 00 00 36 6B 20 76 61 6C 69 64
|
||||
61 74 69 6F 6E 20 72 75 6E 20 70 61 72 61 6D 65
|
||||
74 65 72 73 20 66 6F 72 20 63 6F 72 65 6D 61 72
|
||||
6B 2E 0A 00 50 72 6F 66 69 6C 65 20 67 65 6E 65
|
||||
72 61 74 69 6F 6E 20 72 75 6E 20 70 61 72 61 6D
|
||||
65 74 65 72 73 20 66 6F 72 20 63 6F 72 65 6D 61
|
||||
72 6B 2E 0A 00 00 00 00 32 4B 20 70 65 72 66 6F
|
||||
72 6D 61 6E 63 65 20 72 75 6E 20 70 61 72 61 6D
|
||||
65 74 65 72 73 20 66 6F 72 20 63 6F 72 65 6D 61
|
||||
72 6B 2E 0A 00 00 00 00 32 4B 20 76 61 6C 69 64
|
||||
61 74 69 6F 6E 20 72 75 6E 20 70 61 72 61 6D 65
|
||||
74 65 72 73 20 66 6F 72 20 63 6F 72 65 6D 61 72
|
||||
6B 2E 0A 00 5B 25 75 5D 45 52 52 4F 52 21 20 6C
|
||||
69 73 74 20 63 72 63 20 30 78 25 30 34 78 20 2D
|
||||
20 73 68 6F 75 6C 64 20 62 65 20 30 78 25 30 34
|
||||
78 0A 00 00 5B 25 75 5D 45 52 52 4F 52 21 20 6D
|
||||
61 74 72 69 78 20 63 72 63 20 30 78 25 30 34 78
|
||||
20 2D 20 73 68 6F 75 6C 64 20 62 65 20 30 78 25
|
||||
30 34 78 0A 00 00 00 00 5B 25 75 5D 45 52 52 4F
|
||||
52 21 20 73 74 61 74 65 20 63 72 63 20 30 78 25
|
||||
30 34 78 20 2D 20 73 68 6F 75 6C 64 20 62 65 20
|
||||
30 78 25 30 34 78 0A 00 43 6F 72 65 4D 61 72 6B
|
||||
20 53 69 7A 65 20 20 20 20 3A 20 25 75 0A 00 00
|
||||
54 6F 74 61 6C 20 74 69 63 6B 73 20 20 20 20 20
|
||||
20 3A 20 25 75 0A 00 00 54 6F 74 61 6C 20 74 69
|
||||
6D 65 20 28 73 65 63 73 29 3A 20 25 64 0A 00 00
|
||||
45 52 52 4F 52 21 20 4D 75 73 74 20 65 78 65 63
|
||||
75 74 65 20 66 6F 72 20 61 74 20 6C 65 61 73 74
|
||||
20 31 30 20 73 65 63 73 20 66 6F 72 20 61 20 76
|
||||
61 6C 69 64 20 72 65 73 75 6C 74 21 0A 00 00 00
|
||||
49 74 65 72 61 74 2F 53 65 63 2F 4D 48 7A 20 20
|
||||
20 3A 20 25 64 2E 25 64 0A 00 00 00 49 74 65 72
|
||||
61 74 69 6F 6E 73 20 20 20 20 20 20 20 3A 20 25
|
||||
75 0A 00 00 47 43 43 37 2E 32 2E 30 00 00 00 00
|
||||
43 6F 6D 70 69 6C 65 72 20 76 65 72 73 69 6F 6E
|
||||
20 3A 20 25 73 0A 00 00 2D 4F 32 00 43 6F 6D 70
|
||||
69 6C 65 72 20 66 6C 61 67 73 20 20 20 3A 20 25
|
||||
73 0A 00 00 53 54 41 54 49 43 00 00 4D 65 6D 6F
|
||||
72 79 20 6C 6F 63 61 74 69 6F 6E 20 20 3A 20 25
|
||||
73 0A 00 00 73 65 65 64 63 72 63 20 20 20 20 20
|
||||
20 20 20 20 20 3A 20 30 78 25 30 34 78 0A 00 00
|
||||
5B 25 64 5D 63 72 63 6C 69 73 74 20 20 20 20 20
|
||||
20 20 3A 20 30 78 25 30 34 78 0A 00 5B 25 64 5D
|
||||
63 72 63 6D 61 74 72 69 78 20 20 20 20 20 3A 20
|
||||
30 78 25 30 34 78 0A 00 5B 25 64 5D 63 72 63 73
|
||||
74 61 74 65 20 20 20 20 20 20 3A 20 30 78 25 30
|
||||
34 78 0A 00 5B 25 64 5D 63 72 63 66 69 6E 61 6C
|
||||
20 20 20 20 20 20 3A 20 30 78 25 30 34 78 0A 00
|
||||
43 6F 72 72 65 63 74 20 6F 70 65 72 61 74 69 6F
|
||||
6E 20 76 61 6C 69 64 61 74 65 64 2E 20 53 65 65
|
||||
20 72 65 61 64 6D 65 2E 74 78 74 20 66 6F 72 20
|
||||
72 75 6E 20 61 6E 64 20 72 65 70 6F 72 74 69 6E
|
||||
67 20 72 75 6C 65 73 2E 0A 00 00 00 45 72 72 6F
|
||||
72 73 20 64 65 74 65 63 74 65 64 0A 00 00 00 00
|
||||
43 61 6E 6E 6F 74 20 76 61 6C 69 64 61 74 65 20
|
||||
6F 70 65 72 61 74 69 6F 6E 20 66 6F 72 20 74 68
|
||||
65 73 65 20 73 65 65 64 20 76 61 6C 75 65 73 2C
|
||||
20 70 6C 65 61 73 65 20 63 6F 6D 70 61 72 65 20
|
||||
77 69 74 68 20 72 65 73 75 6C 74 73 20 6F 6E 20
|
||||
61 20 6B 6E 6F 77 6E 20 70 6C 61 74 66 6F 72 6D
|
||||
2E 0A 00 00 54 30 2E 33 65 2D 31 46 00 00 00 00
|
||||
2D 54 2E 54 2B 2B 54 71 00 00 00 00 31 54 33 2E
|
||||
34 65 34 7A 00 00 00 00 33 34 2E 30 65 2D 54 5E
|
||||
00 00 00 00 35 2E 35 30 30 65 2B 33 00 00 00 00
|
||||
2D 2E 31 32 33 65 2D 32 00 00 00 00 2D 38 37 65
|
||||
2B 38 33 32 00 00 00 00 2B 30 2E 36 65 2D 31 32
|
||||
00 00 00 00 33 35 2E 35 34 34 30 30 00 00 00 00
|
||||
2E 31 32 33 34 35 30 30 00 00 00 00 2D 31 31 30
|
||||
2E 37 30 30 00 00 00 00 2B 30 2E 36 34 34 30 30
|
||||
00 00 00 00 35 30 31 32 00 00 00 00 31 32 33 34
|
||||
00 00 00 00 2D 38 37 34 00 00 00 00 2B 31 32 32
|
||||
00 00 00 00 53 74 61 74 69 63 00 00 48 65 61 70
|
||||
00 00 00 00 53 74 61 63 6B 00 00 00
|
||||
@0000FFF8
|
||||
00 00 04 F0 C0 85 04 F0
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,96 +0,0 @@
|
|||
@00000000
|
||||
A4 05 04 F0 AC 05 04 F0 B4 05 04 F0 58 3F 00 EE
|
||||
58 3F 00 EE 92 3F 00 EE 92 3F 00 EE 2E 40 00 EE
|
||||
F4 79 00 EE CC 79 00 EE D6 79 00 EE E0 79 00 EE
|
||||
EA 79 00 EE C2 79 00 EE 06 8B 00 EE 30 85 00 EE
|
||||
30 85 00 EE 30 85 00 EE 30 85 00 EE 30 85 00 EE
|
||||
30 85 00 EE 30 85 00 EE 30 85 00 EE 30 85 00 EE
|
||||
30 85 00 EE 0C 8A 00 EE 1A 8A 00 EE 30 85 00 EE
|
||||
30 85 00 EE 30 85 00 EE 30 85 00 EE 30 85 00 EE
|
||||
30 85 00 EE 30 85 00 EE 30 85 00 EE 30 85 00 EE
|
||||
30 85 00 EE 4C 88 00 EE 30 85 00 EE 30 85 00 EE
|
||||
30 85 00 EE E0 87 00 EE 30 85 00 EE F4 86 00 EE
|
||||
30 85 00 EE 30 85 00 EE 06 8B 00 EE 84 05 04 F0
|
||||
8C 05 04 F0 94 05 04 F0 9C 05 04 F0 54 05 04 F0
|
||||
60 05 04 F0 6C 05 04 F0 78 05 04 F0 24 05 04 F0
|
||||
30 05 04 F0 3C 05 04 F0 48 05 04 F0 F4 04 04 F0
|
||||
00 05 04 F0 0C 05 04 F0 18 05 04 F0 01 00 00 00
|
||||
01 00 00 00 66 00 00 00 36 6B 20 70 65 72 66 6F
|
||||
72 6D 61 6E 63 65 20 72 75 6E 20 70 61 72 61 6D
|
||||
65 74 65 72 73 20 66 6F 72 20 63 6F 72 65 6D 61
|
||||
72 6B 2E 0A 00 00 00 00 36 6B 20 76 61 6C 69 64
|
||||
61 74 69 6F 6E 20 72 75 6E 20 70 61 72 61 6D 65
|
||||
74 65 72 73 20 66 6F 72 20 63 6F 72 65 6D 61 72
|
||||
6B 2E 0A 00 50 72 6F 66 69 6C 65 20 67 65 6E 65
|
||||
72 61 74 69 6F 6E 20 72 75 6E 20 70 61 72 61 6D
|
||||
65 74 65 72 73 20 66 6F 72 20 63 6F 72 65 6D 61
|
||||
72 6B 2E 0A 00 00 00 00 32 4B 20 70 65 72 66 6F
|
||||
72 6D 61 6E 63 65 20 72 75 6E 20 70 61 72 61 6D
|
||||
65 74 65 72 73 20 66 6F 72 20 63 6F 72 65 6D 61
|
||||
72 6B 2E 0A 00 00 00 00 32 4B 20 76 61 6C 69 64
|
||||
61 74 69 6F 6E 20 72 75 6E 20 70 61 72 61 6D 65
|
||||
74 65 72 73 20 66 6F 72 20 63 6F 72 65 6D 61 72
|
||||
6B 2E 0A 00 5B 25 75 5D 45 52 52 4F 52 21 20 6C
|
||||
69 73 74 20 63 72 63 20 30 78 25 30 34 78 20 2D
|
||||
20 73 68 6F 75 6C 64 20 62 65 20 30 78 25 30 34
|
||||
78 0A 00 00 5B 25 75 5D 45 52 52 4F 52 21 20 6D
|
||||
61 74 72 69 78 20 63 72 63 20 30 78 25 30 34 78
|
||||
20 2D 20 73 68 6F 75 6C 64 20 62 65 20 30 78 25
|
||||
30 34 78 0A 00 00 00 00 5B 25 75 5D 45 52 52 4F
|
||||
52 21 20 73 74 61 74 65 20 63 72 63 20 30 78 25
|
||||
30 34 78 20 2D 20 73 68 6F 75 6C 64 20 62 65 20
|
||||
30 78 25 30 34 78 0A 00 43 6F 72 65 4D 61 72 6B
|
||||
20 53 69 7A 65 20 20 20 20 3A 20 25 75 0A 00 00
|
||||
54 6F 74 61 6C 20 74 69 63 6B 73 20 20 20 20 20
|
||||
20 3A 20 25 75 0A 00 00 54 6F 74 61 6C 20 74 69
|
||||
6D 65 20 28 73 65 63 73 29 3A 20 25 64 0A 00 00
|
||||
45 52 52 4F 52 21 20 4D 75 73 74 20 65 78 65 63
|
||||
75 74 65 20 66 6F 72 20 61 74 20 6C 65 61 73 74
|
||||
20 31 30 20 73 65 63 73 20 66 6F 72 20 61 20 76
|
||||
61 6C 69 64 20 72 65 73 75 6C 74 21 0A 00 00 00
|
||||
49 74 65 72 61 74 2F 53 65 63 2F 4D 48 7A 20 20
|
||||
20 3A 20 25 64 2E 25 64 0A 00 00 00 49 74 65 72
|
||||
61 74 69 6F 6E 73 20 20 20 20 20 20 20 3A 20 25
|
||||
75 0A 00 00 47 43 43 37 2E 32 2E 30 00 00 00 00
|
||||
43 6F 6D 70 69 6C 65 72 20 76 65 72 73 69 6F 6E
|
||||
20 3A 20 25 73 0A 00 00 2D 4F 32 00 43 6F 6D 70
|
||||
69 6C 65 72 20 66 6C 61 67 73 20 20 20 3A 20 25
|
||||
73 0A 00 00 53 54 41 54 49 43 00 00 4D 65 6D 6F
|
||||
72 79 20 6C 6F 63 61 74 69 6F 6E 20 20 3A 20 25
|
||||
73 0A 00 00 73 65 65 64 63 72 63 20 20 20 20 20
|
||||
20 20 20 20 20 3A 20 30 78 25 30 34 78 0A 00 00
|
||||
5B 25 64 5D 63 72 63 6C 69 73 74 20 20 20 20 20
|
||||
20 20 3A 20 30 78 25 30 34 78 0A 00 5B 25 64 5D
|
||||
63 72 63 6D 61 74 72 69 78 20 20 20 20 20 3A 20
|
||||
30 78 25 30 34 78 0A 00 5B 25 64 5D 63 72 63 73
|
||||
74 61 74 65 20 20 20 20 20 20 3A 20 30 78 25 30
|
||||
34 78 0A 00 5B 25 64 5D 63 72 63 66 69 6E 61 6C
|
||||
20 20 20 20 20 20 3A 20 30 78 25 30 34 78 0A 00
|
||||
43 6F 72 72 65 63 74 20 6F 70 65 72 61 74 69 6F
|
||||
6E 20 76 61 6C 69 64 61 74 65 64 2E 20 53 65 65
|
||||
20 72 65 61 64 6D 65 2E 74 78 74 20 66 6F 72 20
|
||||
72 75 6E 20 61 6E 64 20 72 65 70 6F 72 74 69 6E
|
||||
67 20 72 75 6C 65 73 2E 0A 00 00 00 45 72 72 6F
|
||||
72 73 20 64 65 74 65 63 74 65 64 0A 00 00 00 00
|
||||
43 61 6E 6E 6F 74 20 76 61 6C 69 64 61 74 65 20
|
||||
6F 70 65 72 61 74 69 6F 6E 20 66 6F 72 20 74 68
|
||||
65 73 65 20 73 65 65 64 20 76 61 6C 75 65 73 2C
|
||||
20 70 6C 65 61 73 65 20 63 6F 6D 70 61 72 65 20
|
||||
77 69 74 68 20 72 65 73 75 6C 74 73 20 6F 6E 20
|
||||
61 20 6B 6E 6F 77 6E 20 70 6C 61 74 66 6F 72 6D
|
||||
2E 0A 00 00 54 30 2E 33 65 2D 31 46 00 00 00 00
|
||||
2D 54 2E 54 2B 2B 54 71 00 00 00 00 31 54 33 2E
|
||||
34 65 34 7A 00 00 00 00 33 34 2E 30 65 2D 54 5E
|
||||
00 00 00 00 35 2E 35 30 30 65 2B 33 00 00 00 00
|
||||
2D 2E 31 32 33 65 2D 32 00 00 00 00 2D 38 37 65
|
||||
2B 38 33 32 00 00 00 00 2B 30 2E 36 65 2D 31 32
|
||||
00 00 00 00 33 35 2E 35 34 34 30 30 00 00 00 00
|
||||
2E 31 32 33 34 35 30 30 00 00 00 00 2D 31 31 30
|
||||
2E 37 30 30 00 00 00 00 2B 30 2E 36 34 34 30 30
|
||||
00 00 00 00 35 30 31 32 00 00 00 00 31 32 33 34
|
||||
00 00 00 00 2D 38 37 34 00 00 00 00 2B 31 32 32
|
||||
00 00 00 00 53 74 61 74 69 63 00 00 48 65 61 70
|
||||
00 00 00 00 53 74 61 63 6B 00 00 00
|
||||
@0000FFEC
|
||||
00 00 00 EE 7A 9B 00 EE 40 00 00 00 00 00 04 F0
|
||||
C0 85 04 F0
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,7 +0,0 @@
|
|||
@00001000
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 0A 48
|
||||
65 6C 6C 6F 20 57 6F 72 6C 64 20 66 72 6F 6D 20
|
||||
53 77 65 52 56 20 40 57 44 43 20 21 21 0A 2D 2D
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 00
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
@00000000
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
|
||||
2D 2D 0A 48 65 6C 6C 6F 20 57 6F 72 6C 64 20 66
|
||||
72 6F 6D 20 53 77 65 52 56 20 45 48 31 20 40 57
|
||||
44 43 20 21 21 0A 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 0A 00
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
@00000000
|
||||
73 10 20 B0 73 10 20 B8 B7 00 00 EE 73 90 50 30
|
||||
B7 50 55 5F 93 80 50 55 73 90 00 7C B7 01 58 D0
|
||||
17 02 01 00 13 02 02 FE 83 02 02 00 23 80 51 00
|
||||
05 02 E3 9B 02 FE B7 01 58 D0 93 02 F0 0F 23 80
|
||||
51 00 E3 0A 00 FE 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
@00000000
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
|
||||
2D 2D 0A 48 65 6C 6C 6F 20 57 6F 72 6C 64 20 66
|
||||
72 6F 6D 20 53 77 65 52 56 20 45 48 31 20 40 57
|
||||
44 43 20 21 21 0A 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
|
||||
2D 2D 2D 2D 2D 2D 2D 2D 0A 00
|
||||
@0000FFF8
|
||||
00 00 04 F0 70 80 04 F0
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
@00000000
|
||||
73 10 20 B0 73 10 20 B8 B7 00 00 EE 73 90 50 30
|
||||
B7 50 55 5F 93 80 50 55 73 90 00 7C B7 01 58 D0
|
||||
17 02 04 F0 13 02 02 FE 83 02 02 00 23 80 51 00
|
||||
05 02 E3 9B 02 FE B7 01 58 D0 93 02 F0 0F 23 80
|
||||
51 00 E3 0A 00 FE 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
01 00 01 00 01 00 01 00 01 00 01 00 01 00
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
@00000000
|
||||
73 10 20 B0 73 10 20 B8 B7 00 00 EE 73 90 50 30
|
||||
B7 50 55 55 93 80 50 55 73 90 00 7C B7 01 58 D0
|
||||
17 12 00 00 13 02 02 FE 83 02 02 00 23 80 51 00
|
||||
05 02 E3 9B 02 FE B7 01 58 D0 93 02 F0 0F 23 80
|
||||
51 00 E3 0A 00 FE
|
||||
|
|
@ -357,7 +357,7 @@ module tb_top;
|
|||
nmi_vector = 32'hee000000;
|
||||
nmi_int = 0;
|
||||
|
||||
$readmemh("data.hex", lmem.mem);
|
||||
$readmemh("program.hex", lmem.mem);
|
||||
$readmemh("program.hex", imem.mem);
|
||||
tp = $fopen("trace_port.csv","w");
|
||||
el = $fopen("exec.log","w");
|
||||
|
|
@ -808,16 +808,15 @@ axi_slv lmem(
|
|||
|
||||
task preload_iccm;
|
||||
bit[31:0] data;
|
||||
bit[31:0] addr, eaddr, saddr, faddr;
|
||||
int adr;
|
||||
bit[31:0] addr, eaddr, saddr;
|
||||
|
||||
/*
|
||||
addresses:
|
||||
0xffec - ICCM start address to load
|
||||
0xfff0 - ICCM end address to load
|
||||
0xfff4 - imem start address
|
||||
0xfffffff0 - ICCM start address to load
|
||||
0xfffffff4 - ICCM end address to load
|
||||
*/
|
||||
|
||||
addr = 'hffec;
|
||||
addr = 'hffff_fff0;
|
||||
saddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};
|
||||
if ( (saddr < `RV_ICCM_SADR) || (saddr > `RV_ICCM_EADR)) return;
|
||||
`ifndef RV_ICCM_ENABLE
|
||||
|
|
@ -826,17 +825,13 @@ if ( (saddr < `RV_ICCM_SADR) || (saddr > `RV_ICCM_EADR)) return;
|
|||
$display("********************************************************");
|
||||
$finish;
|
||||
`endif
|
||||
addr = 'hfff0;
|
||||
addr += 4;
|
||||
eaddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};
|
||||
addr = 'hfff4;
|
||||
faddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};
|
||||
$display("ICCM pre-load from %h to %h", saddr, eaddr);
|
||||
|
||||
for(addr= saddr; addr <= eaddr; addr+=4) begin
|
||||
adr = faddr & 'hffff;
|
||||
data = {imem.mem[adr+3],imem.mem[adr+2],imem.mem[adr+1],imem.mem[adr]};
|
||||
data = {imem.mem[addr+3],imem.mem[addr+2],imem.mem[addr+1],imem.mem[addr]};
|
||||
slam_iccm_ram(addr, data == 0 ? 0 : {riscv_ecc32(data),data});
|
||||
faddr+=4;
|
||||
end
|
||||
|
||||
endtask
|
||||
|
|
@ -844,31 +839,29 @@ endtask
|
|||
|
||||
task preload_dccm;
|
||||
bit[31:0] data;
|
||||
bit[31:0] addr, eaddr;
|
||||
int adr;
|
||||
bit[31:0] addr, saddr, eaddr;
|
||||
|
||||
/*
|
||||
addresses:
|
||||
0xfff8 - DCCM start address to load
|
||||
0xfffc - ICCM end address to load
|
||||
0x0 - lmem start addres to load from
|
||||
0xffff_fff8 - DCCM start address to load
|
||||
0xffff_fffc - DCCM end address to load
|
||||
*/
|
||||
|
||||
addr = 'hfff8;
|
||||
eaddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};
|
||||
if (eaddr != `RV_DCCM_SADR) return;
|
||||
addr = 'hffff_fff8;
|
||||
saddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};
|
||||
if (saddr < `RV_DCCM_SADR || saddr > `RV_DCCM_EADR) return;
|
||||
`ifndef RV_DCCM_ENABLE
|
||||
$display("********************************************************");
|
||||
$display("DCCM preload: there is no DCCM in SweRV, terminating !!!");
|
||||
$display("********************************************************");
|
||||
$finish;
|
||||
`endif
|
||||
addr = 'hfffc;
|
||||
addr += 4;
|
||||
eaddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};
|
||||
$display("DCCM pre-load from %h to %h", `RV_DCCM_SADR, eaddr);
|
||||
$display("DCCM pre-load from %h to %h", saddr, eaddr);
|
||||
|
||||
for(addr=`RV_DCCM_SADR; addr <= eaddr; addr+=4) begin
|
||||
adr = addr & 'hffff;
|
||||
data = {lmem.mem[adr+3],lmem.mem[adr+2],lmem.mem[adr+1],lmem.mem[adr]};
|
||||
for(addr=saddr; addr <= eaddr; addr+=4) begin
|
||||
data = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};
|
||||
slam_dccm_ram(addr, data == 0 ? 0 : {riscv_ecc32(data),data});
|
||||
end
|
||||
|
||||
|
|
|
|||
|
|
@ -141,8 +141,7 @@ riviera: program.hex riviera-build
|
|||
ifeq ($(shell which $(GCC_PREFIX)-gcc 2> /dev/null),)
|
||||
program.hex: ${BUILD_DIR}/defines.h
|
||||
@echo " !!! No $(GCC_PREFIX)-gcc in path, using canned hex files !!"
|
||||
cp ${HEX_DIR}/$(TEST).program.hex program.hex
|
||||
cp ${HEX_DIR}/$(TEST).data.hex data.hex
|
||||
cp ${HEX_DIR}/$(TEST).hex program.hex
|
||||
else
|
||||
ifneq (,$(wildcard $(TEST_DIR)/$(TEST).makefile))
|
||||
program.hex:
|
||||
|
|
@ -151,10 +150,8 @@ else
|
|||
program.hex: $(TEST).o $(LINK)
|
||||
@echo Building $(TEST)
|
||||
$(GCC_PREFIX)-ld -m elf32lriscv --discard-none -T$(LINK) -o $(TEST).exe $(TEST).o
|
||||
$(GCC_PREFIX)-objcopy -O verilog --only-section ".data*" --change-section-lma .data=0 $(TEST).exe data.hex
|
||||
$(GCC_PREFIX)-objcopy -O verilog --only-section ".text*" $(TEST).exe program.hex
|
||||
$(GCC_PREFIX)-objcopy -O verilog $(TEST).exe program.hex
|
||||
$(GCC_PREFIX)-objdump -S $(TEST).exe > $(TEST).dis
|
||||
$(GCC_PREFIX)-nm -f posix -C $(TEST).exe > $(TEST).tbl
|
||||
@echo Completed building $(TEST)
|
||||
|
||||
%.o : %.s ${BUILD_DIR}/defines.h
|
||||
|
|
|
|||
Loading…
Reference in New Issue