add jtag demo and refine Makefile
This commit is contained in:
parent
a8fc3642ad
commit
5f80832b1a
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@ -2,10 +2,6 @@ export RV_ROOT = ${PWD}/../..
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LLVMINSTALL = /home/colin/develop/llvm-build/install
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GCC_PREFIX = /opt/riscv/bin/riscv64-unknown-elf
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TEST_CFLAGS = -g -O3 -funroll-all-loops
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ABI = -mabi=ilp32 -march=rv32imc
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DEMODIR = ${PWD}
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BUILD_DIR = ${DEMODIR}/build
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RV_DESIGN = ${RV_ROOT}/design
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@ -20,10 +16,6 @@ endif
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LINK = $(DEMODIR)/link.ld
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OFILES = $(TEST).o
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OUTFILES = $(TEST).out
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# CFLAGS for verilator generated Makefiles. Without -std=c++11 it complains for `auto` variables
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CFLAGS += "-std=c++11"
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# Optimization for better performance; alternative is nothing for slower runtime (faster compiles)
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@ -60,25 +52,12 @@ verilator: program.hex verilator-build
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##################### Test hex Build #####################################
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# program.hex: $(OFILES) $(LINK)
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# @echo Building $(TEST)
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# $(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(BUILD_DIR)/$(TEST).map -lgcc -T$(LINK) -o $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/$(OFILES) -nostartfiles $(TEST_LIBS)
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# $(GCC_PREFIX)-objcopy -O verilog $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/program.hex
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# $(GCC_PREFIX)-objdump -S $(BUILD_DIR)/$(TEST).bin > $(BUILD_DIR)/$(TEST).dis
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# @echo Completed building $(TEST)
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# %.o : %.s swerv_define
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# $(GCC_PREFIX)-cpp -I${BUILD_DIR} $< > $(BUILD_DIR)/$*.cpp.s
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# $(GCC_PREFIX)-as $(ABI) $(BUILD_DIR)/$*.cpp.s -o $(BUILD_DIR)/$@
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program.hex: $(OUTFILES)
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program.hex: $(TEST).out
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@echo Building $(TEST)
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$(GCC_PREFIX)-objcopy -O verilog $(BUILD_DIR)/$(TEST).out $(BUILD_DIR)/program.hex
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$(GCC_PREFIX)-objdump -S $(BUILD_DIR)/$(TEST).out > $(BUILD_DIR)/$(TEST).dis
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##################### llvm hex Build #####################################
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build: $(OUTFILES)
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build: $(TEST).out
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@echo Completed building $(TEST)
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%.out : %.c swerv_define
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@ -0,0 +1,75 @@
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export RV_ROOT = ${PWD}/../..
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LLVMINSTALL = /home/colin/develop/llvm-build/install
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GCC_PREFIX = /opt/riscv/bin/riscv64-unknown-elf
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TEST_CFLAGS = -g -O3 -funroll-all-loops
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ABI = -mabi=ilp32 -march=rv32imc
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DEMODIR = ${PWD}
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BUILD_DIR = ${DEMODIR}/build
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RV_DESIGN = ${RV_ROOT}/design
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RV_SOC = ${RV_ROOT}/soc
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TEST = jtag
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ifdef debug
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DEBUG_PLUS = +dumpon
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VERILATOR_DEBUG = --trace
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endif
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LINK = $(DEMODIR)/link.ld
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# CFLAGS for verilator generated Makefiles. Without -std=c++11 it complains for `auto` variables
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CFLAGS += "-std=c++11"
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# Optimization for better performance; alternative is nothing for slower runtime (faster compiles)
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# -O2 for faster runtime (slower compiles), or -O for balance.
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VERILATOR_MAKE_FLAGS = OPT_FAST="-Os"
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# Targets
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all: clean verilator
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clean:
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rm -rf build obj_dir
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swerv_define :
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BUILD_PATH=${BUILD_DIR} PERLLIB=${RV_SOC} ${RV_SOC}/swerv.config -target=default -set iccm_enable
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##################### Verilog Builds #####################################
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verilator-build: swerv_define
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echo '`undef ASSERT_ON' >> ${BUILD_DIR}/common_defines.vh
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verilator --cc -CFLAGS ${CFLAGS} \
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$(BUILD_DIR)/common_defines.vh \
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-I${BUILD_DIR} \
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-Wno-UNOPTFLAT \
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-F ${RV_SOC}/soc.mk \
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$(RV_SOC)/soc_top.sv \
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--top-module soc_top -exe test_soc_top.cpp --autoflush $(VERILATOR_DEBUG)
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cp ${DEMODIR}/test_soc_top.cpp obj_dir
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$(MAKE) -j -C obj_dir/ -f Vsoc_top.mk $(VERILATOR_MAKE_FLAGS)
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##################### Simulation Runs #####################################
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verilator: program.hex verilator-build
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cd build && ../obj_dir/Vsoc_top ${DEBUG_PLUS}
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##################### Test hex Build #####################################
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program.hex: $(TEST).o $(LINK)
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@echo Building $(TEST)
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$(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(BUILD_DIR)/$(TEST).map -lgcc -T$(LINK) -o $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/$(TEST).o -nostartfiles $(TEST_LIBS)
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$(GCC_PREFIX)-objcopy -O verilog $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/program.hex
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$(GCC_PREFIX)-objdump -S $(BUILD_DIR)/$(TEST).bin > $(BUILD_DIR)/$(TEST).dis
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@echo Completed building $(TEST)
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%.o : %.s swerv_define
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$(GCC_PREFIX)-cpp -I${BUILD_DIR} $< > $(BUILD_DIR)/$*.cpp.s
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$(GCC_PREFIX)-as $(ABI) $(BUILD_DIR)/$*.cpp.s -o $(BUILD_DIR)/$@
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##################### llvm hex Build #####################################
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help:
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@echo Possible targets: verilator help clean all verilator-build program.hex
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.PHONY: help clean verilator
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@ -0,0 +1,81 @@
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// Assembly code for Hello World
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// Not using only ALU ops for creating the string
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#include "defines.h"
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#define STDOUT 0xd0580000
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// Code to execute
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.section .text
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.global _start
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_start:
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// Clear minstret
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csrw minstret, zero
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csrw minstreth, zero
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// Set up MTVEC - not expecting to use it though
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li x1, RV_ICCM_SADR
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csrw mtvec, x1
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// Enable Caches in MRAC
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li x1, 0x5f555555
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csrw 0x7c0, x1
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// Load string from hw_data
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// and write to stdout address
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li x3, STDOUT
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la x4, hw_data
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loop:
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lb x5, 0(x4)
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sb x5, 0(x3)
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addi x4, x4, 1
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bnez x5, loop
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li x3, STDOUT
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la x4, hw_data
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loop2:
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lb x5, 0(x4)
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sb x5, 0(x3)
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addi x4, x4, 1
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bnez x5, loop2
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// Write 0xff to STDOUT for TB to terminate test.
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_finish:
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li x3, STDOUT
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addi x5, x0, 0xff
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sb x5, 0(x3)
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beq x0, x0, _finish
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.rept 100
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nop
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.endr
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.global hw_data
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.data
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hw_data:
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.ascii "----------------------------------\n"
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.ascii "Hello World Colin.liang EH1@WDC !!\n"
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.ascii "----------------------------------\n"
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.byte 0
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@ -0,0 +1,16 @@
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OUTPUT_ARCH( "riscv" )
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ENTRY(_start)
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SECTIONS
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{
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. = 0;
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.text_init : { *(.text_init*) }
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.text : { *(.text*) }
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_end = .;
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. = 0x10000;
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.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000; }
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.bss : { *(.bss) }
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. = 0xd0580000;
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.data.io : { *(.data.io) }
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}
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@ -0,0 +1,65 @@
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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#include <stdlib.h>
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#include <iostream>
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#include <utility>
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#include <string>
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#include "Vsoc_top.h"
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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vluint64_t main_time = 0;
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double sc_time_stamp () {
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return main_time;
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}
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int main(int argc, char** argv) {
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std::cout << "\nVerilatorTB: Start of sim\n" << std::endl;
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Verilated::commandArgs(argc, argv);
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Vsoc_top* soc = new Vsoc_top;
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// init trace dump
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VerilatedVcdC* tfp = NULL;
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#if VM_TRACE
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Verilated::traceEverOn(true);
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tfp = new VerilatedVcdC;
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soc->trace (tfp, 24);
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tfp->open ("sim.vcd");
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#endif
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// Simulate
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while(!Verilated::gotFinish()){
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#if VM_TRACE
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tfp->dump (main_time);
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#endif
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main_time += 5;
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soc->core_clk = !soc->core_clk;
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soc->eval();
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}
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#if VM_TRACE
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tfp->close();
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#endif
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std::cout << "\nVerilatorTB: End of sim" << std::endl;
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exit(EXIT_SUCCESS);
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}
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@ -447,6 +447,19 @@ module soc_top;
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//=========================================================================-
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// RTL instance
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//=========================================================================-
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jtagdpi jtagdpi(
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.clk_i(core_clk),
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.rst_ni(rst_l),
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.jtag_tck(jtag_tck),
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.jtag_tms(jtag_tms),
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.jtag_tdi(jtag_tdi),
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.jtag_tdo(jtag_tdo),
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.jtag_trst_n(jtag_trst_n),
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.jtag_srst_n()
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);
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swerv_wrapper rvtop (
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.rst_l ( rst_l ),
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.dbg_rst_l ( porst_l ),
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