diff --git a/fpga/xc7z010/Makefile b/fpga/xc7z010/Makefile
new file mode 100644
index 0000000..a41738d
--- /dev/null
+++ b/fpga/xc7z010/Makefile
@@ -0,0 +1,36 @@
+export RV_ROOT = ${PWD}/../..
+GCC_PREFIX = /opt/riscv/bin/riscv32-unknown-elf
+GDB_PREFIX = /opt/riscv/bin/riscv32-unknown-elf-gdb
+
+
+TEST_CFLAGS = -g -O3 -funroll-all-loops
+ABI = -mabi=ilp32 -march=rv32imc
+
+DEMODIR = ${PWD}
+BUILD_DIR = ${DEMODIR}/build
+RV_SOC = ${RV_ROOT}/soc
+
+TEST = jtag
+
+
+all: clean verilator
+
+impl:
+ cd build && vivado -mode batch -notrace -quiet -source ../vivado.tcl
+
+prog:
+ cd build && vivado -mode batch -notrace -quiet -source ../vivado-prog.tcl
+
+clean:
+ rm -rf build obj_dir
+
+openocd:
+ openocd -f swerv.cfg
+
+gdb:
+ $(GDB_PREFIX) -x gdbinit ./build/jtag.bin
+
+help:
+ @echo Possible targets: verilator help clean all verilator-build program.hex
+
+.PHONY: help clean verilator
\ No newline at end of file
diff --git a/fpga/xc7z010/design_1/design_1.bda b/fpga/xc7z010/design_1/design_1.bda
index 0700464..b80ed8c 100644
--- a/fpga/xc7z010/design_1/design_1.bda
+++ b/fpga/xc7z010/design_1/design_1.bda
@@ -23,20 +23,20 @@
- design_1
- BC
-
-
- 2
- design_1
- VR
-
-
active
2
PM
-
-
+
+ design_1
+ BC
+
+
+ 2
+ design_1
+ VR
+
+
+
diff --git a/fpga/xc7z010/led.v b/fpga/xc7z010/led.v
index be1c05c..b844b07 100644
--- a/fpga/xc7z010/led.v
+++ b/fpga/xc7z010/led.v
@@ -28,7 +28,7 @@ end
// 100的时候，占空比最大，这个时候直接完全输出低电平，led等熄灭
always@(posedge myclk) begin
if(flag == 0) begin // 占空比递增
- if(current_cycle < (CYCLE_NUMBER/10))
+ if(current_cycle < (CYCLE_NUMBER/2))
current_cycle <= current_cycle + 1'b1;
else
flag <= ~flag;
diff --git a/fpga/xc7z010/vivado-prog.tcl b/fpga/xc7z010/vivado-prog.tcl
new file mode 100644
index 0000000..6f9b7c9
--- /dev/null
+++ b/fpga/xc7z010/vivado-prog.tcl
@@ -0,0 +1,9 @@
+
+
+if { [ catch { open_hw_manager } ] } { open_hw }
+connect_hw_server
+open_hw_target
+puts [get_hw_devices]
+set obj [lindex [get_hw_devices [current_hw_device]] 0]
+set_property PROGRAM.FILE /home/colin/develop/abstractaccelerator/fpga/xc7z010/build/vivado.bit $obj
+program_hw_devices $obj
\ No newline at end of file
diff --git a/fpga/xc7z010/vivado.tcl b/fpga/xc7z010/vivado.tcl
new file mode 100644
index 0000000..3cb3fbd
--- /dev/null
+++ b/fpga/xc7z010/vivado.tcl
@@ -0,0 +1,66 @@
+
+
+# Project configuration -------------------------------------------------------
+
+create_project -force vivado
+set_property SOURCE_MGMT_MODE None [current_project]
+set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1]
+set_property PART xc7z010-2-clg400 [current_project]
+
+# Files inclusion
+
+add_file /home/colin/develop/abstractaccelerator/fpga/xc7z010/TOP.v
+
+add_file /home/colin/develop/abstractaccelerator/fpga/xc7z010/led.v
+
+add_file /home/colin/develop/abstractaccelerator/fpga/xc7z010/design_1/design_1.bd
+
+# Constraints inclusion
+
+add_file -fileset constrs_1 /home/colin/develop/abstractaccelerator/fpga/xc7z010/timing.xdc
+set_property TARGET_CONSTRS_FILE /home/colin/develop/abstractaccelerator/fpga/xc7z010/timing.xdc [current_fileset -constrset]
+
+add_file -fileset constrs_1 /home/colin/develop/abstractaccelerator/fpga/xc7z010/pin.xdc
+
+# Top-level specification
+set_property TOP TOP [current_fileset]
+
+# Verilog Includes
+set_property INCLUDE_DIRS { /home/colin/develop/abstractaccelerator/fpga/xc7z010 } [current_fileset]
+
+# Verilog Parameters / VHDL Generics
+set_property GENERIC { FREQ=125000000 SECS=1 } -objects [get_filesets sources_1]
+
+
+close_project
+
+# Design flow -----------------------------------------------------------------
+
+open_project vivado
+
+# Synthesis
+
+# PRESYNTH
+# set_property DESIGN_MODE GateLvl [current_fileset]
+reset_run synth_1
+launch_runs synth_1
+wait_on_run synth_1
+#report_property [get_runs synth_1]
+if { [get_property STATUS [get_runs synth_1]] ne "synth_design Complete!" } { exit 1 }
+
+# Place and Route
+
+reset_run impl_1
+launch_runs impl_1
+wait_on_run impl_1
+#report_property [get_runs impl_1]
+if { [get_property STATUS [get_runs impl_1]] ne "route_design Complete!" } { exit 1 }
+
+# Bitstream generation
+
+open_run impl_1
+write_bitstream -force vivado
+write_debug_probes -force -quiet vivado.ltx
+
+close_project
+
diff --git a/fpga/xc7z010/zynq7010.py b/fpga/xc7z010/zynq7010.py
index 8c314f0..942f281 100644
--- a/fpga/xc7z010/zynq7010.py
+++ b/fpga/xc7z010/zynq7010.py
@@ -14,5 +14,5 @@ prj.add_vlog('./design_1/design_1.bd')
prj.set_top('TOP')
-# prj.make()
+prj.make()
prj.prog()