diff --git a/fpga/Readme.md b/fpga/Readme.md index bec77c2..49cd078 100644 --- a/fpga/Readme.md +++ b/fpga/Readme.md @@ -9,7 +9,8 @@ sudo apt-get install build-essential clang bison flex libreadline-dev gawk tcl-d ## install ecpdap for configuration to the flash ```bash -curl https://sh.rustup.rs -sSf | sh # install catgo +curl https://sh.rustup.rs -sSf | sh # install cargo +# sudo apt install cargo cargo install ecpdap # install ecpdap # Run ecpdap help for detailed usage. @@ -67,7 +68,7 @@ git clone --recursive https://github.com/YosysHQ/prjtrellis \ ``` git clone https://github.com/YosysHQ/nextpnr.git \ && cd nextpnr \ -&& cmake . -DARCH=ecp5 -DTRELLIS_INSTALL_PREFIX=/usr/local \ +&& cmake . -B build -DARCH=ecp5 -DTRELLIS_INSTALL_PREFIX=/usr/local && cmake --build build \ && make -j \ && sudo make install \ && cd .. diff --git a/fpga/blink/Makefile b/fpga/blink/Makefile index fd53d5e..9119992 100644 --- a/fpga/blink/Makefile +++ b/fpga/blink/Makefile @@ -15,8 +15,8 @@ $(TARGET).bit: $(TARGET).cfg ${TARGET}.svf : ${TARGET}.bit -prog: ${TARGET}.svf - ./dapprog blink.svf +prog: ${TARGET}.bit + ecpdap program blink.bit flash: ${TARGET}.bit ecpdap flash write blink.bit diff --git a/fpga/blink/blink.cfg b/fpga/blink/blink.cfg new file mode 100644 index 0000000..1ed8a78 --- /dev/null +++ b/fpga/blink/blink.cfg @@ -0,0 +1,845 @@ +.device LFE5U-25F + +.comment Part: LFE5U-25F-6CABGA381 + +.tile CIB_R29C1:CIB_LR +arc: JD7 S1_V02N0601 + +.tile CIB_R31C1:CIB_LR +arc: N1_V02N0601 S3_V06N0303 + +.tile CIB_R37C1:CIB_LR_S +arc: N3_V06N0303 S3_V06N0303 + +.tile CIB_R43C1:CIB_LR +arc: N3_V06N0303 S3_V06N0303 + +.tile CIB_R47C71:CIB_LR +arc: S1_V02S0201 W1_H02E0201 + +.tile CIB_R49C1:CIB_LR_S +arc: N3_V06N0303 JF5 + +.tile CIB_R49C3:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R49C42:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C43:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C44:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C45:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C46:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C47:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C48:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C49:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C50:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C51:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C52:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C53:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R49C69:CIB_PLL3 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0701 N1_V01S0100 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R49C6:CIB_EFB0 +enum: CIB.JB3MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R49C71:CIB_LR_S +arc: H00L0000 N1_V02S0201 +arc: JA0 H00L0000 +enum: CIB.JB0MUX 0 + +.tile CIB_R49C7:CIB_EFB1 +enum: CIB.JA3MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD5MUX 0 + +.tile MIB_R13C31:CMUX_UL_0 +arc: G_DCS0CLK0 G_VPFN0000 +arc: G_ULPCLK0 G_HPFE0000 + +.tile MIB_R13C32:CMUX_UR_0 +arc: G_DCS0CLK1 G_VPFN0000 +arc: G_URPCLK0 G_HPFE0000 + +.tile MIB_R13C3:DSP_SPINE_UL1 +unknown: F2B0 +unknown: F3B0 +unknown: F5B0 +unknown: F11B0 +unknown: F13B0 + +.tile MIB_R25C3:LMID_0 +arc: G_LDCC0CLKI G_JLLQPCLKCIB0 + +.tile MIB_R37C31:CMUX_LL_0 +arc: G_DCS1CLK0 G_VPFN0000 +arc: G_LLPCLK0 G_HPFE0000 + +.tile MIB_R37C32:CMUX_LR_0 +arc: G_DCS1CLK1 G_VPFN0000 +arc: G_LRPCLK0 G_HPFE0000 + +.tile MIB_R37C59:EBR_SPINE_LR1 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R48C0:PICL1 +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.HYSTERESIS ON + +.tile MIB_R48C72:PICR1 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R49C0:MIB_CIB_LR +enum: PIOC.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R49C72:MIB_CIB_LR_A +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R50C4:EFB0_PICB0 +unknown: F54B1 +unknown: F56B1 +unknown: F82B1 +unknown: F94B1 + +.tile MIB_R50C71:BANKREF3 +enum: BANK.VCCIO 3V3 + +.tile R47C68:PLC2 +arc: A2 V01N0101 +arc: B2 V01N0001 +arc: C2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 V01S0100 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: MUXCLK0 CLK0 +arc: S1_V02S0201 Q0 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICEB.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R47C69:PLC2 +arc: V00T0000 V02N0401 +arc: A1 F7 +arc: A4 V00T0000 +arc: A5 V02N0101 +arc: A7 V02N0301 +arc: B1 V00B0000 +arc: B4 V02N0701 +arc: B5 S1_V02N0701 +arc: B7 V02N0501 +arc: C1 E1_H01W0000 +arc: C4 V01N0101 +arc: C5 V02N0201 +arc: C7 V02N0001 +arc: CE1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D1 H01E0101 +arc: D2 Q2 +arc: D4 V01N0001 +arc: D5 V02N0601 +arc: D7 S1_V02N0401 +arc: E1_H02E0201 Q2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F0 +arc: M0 V00B0100 +arc: MUXCLK1 CLK0 +arc: V00B0000 F4 +arc: V00B0100 F5 +word: SLICED.K1.INIT 0000000000010000 +word: SLICEC.K0.INIT 0000000100000000 +word: SLICEC.K1.INIT 0001000000000000 +word: SLICEA.K1.INIT 0111111111111111 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICEA.K0.INIT 1111111111111111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX INV +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 + +.tile R47C70:PLC2 +arc: A0 V02N0701 +arc: B0 V01N0001 +arc: C0 V02N0601 +arc: D0 V02N0201 +arc: F0 F0_SLICE +arc: H01W0000 F0 +word: SLICEA.K0.INIT 1000000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R48C67:PLC2 +arc: E1_H01E0001 F3 +arc: F3 F3_SLICE +word: SLICEB.K1.INIT 0000000000000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R48C68:PLC2 +arc: V00B0000 V02S0201 +arc: A0 H01E0001 +arc: A2 V00B0000 +arc: A5 Q5 +arc: A7 Q7 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V01S0000 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 Q7 +arc: E1_H02E0601 Q6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 Q3 +arc: N1_V02N0601 Q4 +arc: V01S0000 Q6 +word: SLICED.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C69:PLC2 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0601 H02E0601 +arc: A5 Q5 +arc: A7 Q7 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: B6 V00B0000 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: N1_V02N0401 Q4 +arc: N1_V02N0501 Q7 +arc: N1_V02N0701 Q5 +arc: V00B0000 Q6 +arc: V00T0000 Q0 +arc: V01S0000 Q6 +arc: V01S0100 Q0 +word: SLICED.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 1100110011000000 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 1 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R48C70:PLC2 +arc: A5 Q5 +arc: B0 V00T0000 +arc: B1 Q1 +arc: B2 H00L0000 +arc: B3 Q3 +arc: B4 H00R0000 +arc: CLK0 G_HPBX0000 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0000 Q2 +arc: H00R0000 Q4 +arc: H01W0100 Q1 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V01N0001 Q3 +arc: N1_V02N0201 Q2 +arc: N1_V02N0601 Q4 +arc: N1_V02N0701 Q5 +arc: V00T0000 Q0 +arc: W1_H02W0001 Q0 +word: SLICED.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 0000000000001110 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C9:PLC2 +word: SLICEC.K1.INIT 1111111111111111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile TAP_R47C60:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + +.tile TAP_R48C60:TAP_DRIVE +arc: R_HPBX0000 G_VPTX0000 + diff --git a/fpga/blink/blink.v b/fpga/blink/blink.v index 9809901..3f71f67 100644 --- a/fpga/blink/blink.v +++ b/fpga/blink/blink.v @@ -55,7 +55,7 @@ module blink ( input clk_i, output reg led_o ); -localparam MAX = 2_500_000_0; +localparam MAX = 100_000_0; localparam WIDTH = $clog2(MAX); wire clk_s;