refine makefile
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9174bfe249
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@ -6,8 +6,6 @@ GCC_PREFIX = /opt/riscv/bin/riscv64-unknown-elf
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TEST_CFLAGS = -g -O3 -funroll-all-loops
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ABI = -mabi=ilp32 -march=rv32imc
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# Allow tool override
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VERILATOR = verilator
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DEMODIR = ${PWD}
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BUILD_DIR = ${DEMODIR}/build
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RV_DESIGN = ${RV_ROOT}/design
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@ -25,10 +23,6 @@ LINK = $(DEMODIR)/link.ld
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OFILES = $(TEST).o
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OUTFILES = $(TEST).out
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SOCFILES = $(RV_SOC)/soc_top.sv $(RV_SOC)/ahb_sif.sv
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defines = $(BUILD_DIR)/common_defines.vh ${RV_DESIGN}/include/swerv_types.sv
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includes = -I${RV_DESIGN}/include -I${RV_DESIGN}/lib -I${BUILD_DIR}
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# CFLAGS for verilator generated Makefiles. Without -std=c++11 it complains for `auto` variables
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CFLAGS += "-std=c++11"
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@ -42,19 +36,22 @@ all: clean verilator
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clean:
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rm -rf build obj_dir
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${BUILD_DIR}/defines.h :
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swerv_define :
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BUILD_PATH=${BUILD_DIR} PERLLIB=${RV_SOC} ${RV_SOC}/swerv.config -target=default -set iccm_enable
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##################### Verilog Builds #####################################
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verilator-build: ${SOCFILES} ${BUILD_DIR}/defines.h test_soc_top.cpp
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defines = $(BUILD_DIR)/common_defines.vh ${RV_DESIGN}/include/swerv_types.sv
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includes = -I${RV_DESIGN}/include -I${BUILD_DIR} -I${RV_SOC}
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verilator-build: swerv_define
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echo '`undef ASSERT_ON' >> ${BUILD_DIR}/common_defines.vh
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$(VERILATOR) --cc -CFLAGS ${CFLAGS} $(defines) $(includes) \
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verilator --cc -CFLAGS ${CFLAGS} \
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$(defines) \
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$(includes) \
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-Wno-UNOPTFLAT \
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-I${DEMODIR} \
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-I${RV_SOC} \
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-f ${RV_SOC}/flist \
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${SOCFILES} \
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-f ${RV_SOC}/flist \
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$(RV_SOC)/soc_top.sv \
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--top-module soc_top -exe test_soc_top.cpp --autoflush $(VERILATOR_DEBUG)
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cp ${DEMODIR}/test_soc_top.cpp obj_dir
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$(MAKE) -j -C obj_dir/ -f Vsoc_top.mk $(VERILATOR_MAKE_FLAGS)
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@ -64,7 +61,7 @@ verilator-build: ${SOCFILES} ${BUILD_DIR}/defines.h test_soc_top.cpp
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verilator: program.hex verilator-build
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cd build && ../obj_dir/Vsoc_top ${DEBUG_PLUS}
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##################### Test Build #####################################
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##################### Test hex Build #####################################
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# program.hex: $(OFILES) $(LINK)
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# @echo Building $(TEST)
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@ -73,7 +70,7 @@ verilator: program.hex verilator-build
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# $(GCC_PREFIX)-objdump -S $(BUILD_DIR)/$(TEST).bin > $(BUILD_DIR)/$(TEST).dis
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# @echo Completed building $(TEST)
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# %.o : %.s ${BUILD_DIR}/defines.h
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# %.o : %.s swerv_define
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# $(GCC_PREFIX)-cpp -I${BUILD_DIR} $< > $(BUILD_DIR)/$*.cpp.s
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# $(GCC_PREFIX)-as $(ABI) $(BUILD_DIR)/$*.cpp.s -o $(BUILD_DIR)/$@
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@ -87,7 +84,7 @@ program.hex: $(OUTFILES)
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build: $(OUTFILES)
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@echo Completed building $(TEST)
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%.out : %.c ${BUILD_DIR}/defines.h
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%.out : %.c swerv_define
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$(LLVMINSTALL)/bin/clang --target=riscv32 -march=rv32gc $*.c -S -o $(BUILD_DIR)/$*.s -mno-relax
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$(LLVMINSTALL)/bin/clang --target=riscv32 -march=rv32gc $*.c -c -o $(BUILD_DIR)/$*.o -mno-relax
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$(LLVMINSTALL)/bin/ld.lld $(BUILD_DIR)/$*.o -Map=$(BUILD_DIR)/$(TEST).map -T$(LINK) -o $(BUILD_DIR)/$*.out
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@ -40,3 +40,5 @@ $RV_ROOT/design/dmi/rvjtag_tap.sv
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-v $RV_ROOT/design/lib/mem_lib.sv
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-v $RV_ROOT/design/lib/ahb_to_axi4.sv
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-v $RV_ROOT/design/lib/axi4_to_ahb.sv
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$RV_ROOT/soc/ahb_sif.sv
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@ -77,8 +77,12 @@ module soc_top;
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logic [1:0] dec_tlu_perfcnt2;
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logic [1:0] dec_tlu_perfcnt3;
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logic jtag_tdo;
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logic jtag_tck;
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logic jtag_tms;
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logic jtag_tdi;
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logic jtag_trst_n;
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logic o_cpu_halt_ack;
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logic o_cpu_halt_status;
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logic o_cpu_run_ack;
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@ -712,10 +716,10 @@ swerv_wrapper rvtop (
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.trace_rv_i_interrupt_ip(trace_rv_i_interrupt_ip),
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.trace_rv_i_tval_ip (trace_rv_i_tval_ip),
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.jtag_tck ( 1'b0 ),
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.jtag_tms ( 1'b0 ),
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.jtag_tdi ( 1'b0 ),
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.jtag_trst_n ( 1'b0 ),
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.jtag_tck ( jtag_tck ),
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.jtag_tms ( jtag_tms ),
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.jtag_tdi ( jtag_tdi ),
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.jtag_trst_n ( jtag_trst_n ),
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.jtag_tdo ( jtag_tdo ),
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.mpc_debug_halt_ack ( mpc_debug_halt_ack),
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