refine makefile

This commit is contained in:
Colin 2022-01-19 09:57:37 +00:00
parent 9174bfe249
commit 65f5085afa
3 changed files with 24 additions and 21 deletions

View File

@ -6,8 +6,6 @@ GCC_PREFIX = /opt/riscv/bin/riscv64-unknown-elf
TEST_CFLAGS = -g -O3 -funroll-all-loops
ABI = -mabi=ilp32 -march=rv32imc
# Allow tool override
VERILATOR = verilator
DEMODIR = ${PWD}
BUILD_DIR = ${DEMODIR}/build
RV_DESIGN = ${RV_ROOT}/design
@ -25,10 +23,6 @@ LINK = $(DEMODIR)/link.ld
OFILES = $(TEST).o
OUTFILES = $(TEST).out
SOCFILES = $(RV_SOC)/soc_top.sv $(RV_SOC)/ahb_sif.sv
defines = $(BUILD_DIR)/common_defines.vh ${RV_DESIGN}/include/swerv_types.sv
includes = -I${RV_DESIGN}/include -I${RV_DESIGN}/lib -I${BUILD_DIR}
# CFLAGS for verilator generated Makefiles. Without -std=c++11 it complains for `auto` variables
CFLAGS += "-std=c++11"
@ -42,19 +36,22 @@ all: clean verilator
clean:
rm -rf build obj_dir
${BUILD_DIR}/defines.h :
swerv_define :
BUILD_PATH=${BUILD_DIR} PERLLIB=${RV_SOC} ${RV_SOC}/swerv.config -target=default -set iccm_enable
##################### Verilog Builds #####################################
verilator-build: ${SOCFILES} ${BUILD_DIR}/defines.h test_soc_top.cpp
defines = $(BUILD_DIR)/common_defines.vh ${RV_DESIGN}/include/swerv_types.sv
includes = -I${RV_DESIGN}/include -I${BUILD_DIR} -I${RV_SOC}
verilator-build: swerv_define
echo '`undef ASSERT_ON' >> ${BUILD_DIR}/common_defines.vh
$(VERILATOR) --cc -CFLAGS ${CFLAGS} $(defines) $(includes) \
verilator --cc -CFLAGS ${CFLAGS} \
$(defines) \
$(includes) \
-Wno-UNOPTFLAT \
-I${DEMODIR} \
-I${RV_SOC} \
-f ${RV_SOC}/flist \
${SOCFILES} \
-f ${RV_SOC}/flist \
$(RV_SOC)/soc_top.sv \
--top-module soc_top -exe test_soc_top.cpp --autoflush $(VERILATOR_DEBUG)
cp ${DEMODIR}/test_soc_top.cpp obj_dir
$(MAKE) -j -C obj_dir/ -f Vsoc_top.mk $(VERILATOR_MAKE_FLAGS)
@ -64,7 +61,7 @@ verilator-build: ${SOCFILES} ${BUILD_DIR}/defines.h test_soc_top.cpp
verilator: program.hex verilator-build
cd build && ../obj_dir/Vsoc_top ${DEBUG_PLUS}
##################### Test Build #####################################
##################### Test hex Build #####################################
# program.hex: $(OFILES) $(LINK)
# @echo Building $(TEST)
@ -73,7 +70,7 @@ verilator: program.hex verilator-build
# $(GCC_PREFIX)-objdump -S $(BUILD_DIR)/$(TEST).bin > $(BUILD_DIR)/$(TEST).dis
# @echo Completed building $(TEST)
# %.o : %.s ${BUILD_DIR}/defines.h
# %.o : %.s swerv_define
# $(GCC_PREFIX)-cpp -I${BUILD_DIR} $< > $(BUILD_DIR)/$*.cpp.s
# $(GCC_PREFIX)-as $(ABI) $(BUILD_DIR)/$*.cpp.s -o $(BUILD_DIR)/$@
@ -87,7 +84,7 @@ program.hex: $(OUTFILES)
build: $(OUTFILES)
@echo Completed building $(TEST)
%.out : %.c ${BUILD_DIR}/defines.h
%.out : %.c swerv_define
$(LLVMINSTALL)/bin/clang --target=riscv32 -march=rv32gc $*.c -S -o $(BUILD_DIR)/$*.s -mno-relax
$(LLVMINSTALL)/bin/clang --target=riscv32 -march=rv32gc $*.c -c -o $(BUILD_DIR)/$*.o -mno-relax
$(LLVMINSTALL)/bin/ld.lld $(BUILD_DIR)/$*.o -Map=$(BUILD_DIR)/$(TEST).map -T$(LINK) -o $(BUILD_DIR)/$*.out

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@ -40,3 +40,5 @@ $RV_ROOT/design/dmi/rvjtag_tap.sv
-v $RV_ROOT/design/lib/mem_lib.sv
-v $RV_ROOT/design/lib/ahb_to_axi4.sv
-v $RV_ROOT/design/lib/axi4_to_ahb.sv
$RV_ROOT/soc/ahb_sif.sv

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@ -77,8 +77,12 @@ module soc_top;
logic [1:0] dec_tlu_perfcnt2;
logic [1:0] dec_tlu_perfcnt3;
logic jtag_tdo;
logic jtag_tck;
logic jtag_tms;
logic jtag_tdi;
logic jtag_trst_n;
logic o_cpu_halt_ack;
logic o_cpu_halt_status;
logic o_cpu_run_ack;
@ -712,10 +716,10 @@ swerv_wrapper rvtop (
.trace_rv_i_interrupt_ip(trace_rv_i_interrupt_ip),
.trace_rv_i_tval_ip (trace_rv_i_tval_ip),
.jtag_tck ( 1'b0 ),
.jtag_tms ( 1'b0 ),
.jtag_tdi ( 1'b0 ),
.jtag_trst_n ( 1'b0 ),
.jtag_tck ( jtag_tck ),
.jtag_tms ( jtag_tms ),
.jtag_tdi ( jtag_tdi ),
.jtag_trst_n ( jtag_trst_n ),
.jtag_tdo ( jtag_tdo ),
.mpc_debug_halt_ack ( mpc_debug_halt_ack),