Removed dead code.
This commit is contained in:
Joseph Rahmeh
parent
0c92ea167b
commit
695883a674
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@ -1,71 +0,0 @@
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// Assembly code for Hello World
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// Not using only ALU ops for creating the string
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#include "defines.h"
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#define STDOUT 0xd0580000
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// Code to execute
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.section .text
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.global _start
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_start:
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// Clear minstret
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csrw minstret, zero
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csrw minstreth, zero
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// Set up MTVEC - not expecting to use it though
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li x1, RV_ICCM_SADR
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csrw mtvec, x1
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// Enable Caches in MRAC
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li x1, 0x55555555
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csrw 0x7c0, x1
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// Load string from hw_data
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// and write to stdout address
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li x3, STDOUT
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la x4, hw_data
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loop:
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lb x5, 0(x4)
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sb x5, 0(x3)
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addi x4, x4, 1
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bnez x5, loop
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// Write 0xff to STDOUT for TB to termiate test.
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_finish:
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li x3, STDOUT
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addi x5, x0, 0xff
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sb x5, 0(x3)
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beq x0, x0, _finish
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.rept 100
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nop
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.endr
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.data
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hw_data:
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.ascii "------------------------------------\n"
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.ascii "Hello World from SweRV EH1.4 @WDC !!\n"
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.ascii "------------------------------------"
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.byte 0
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@ -1,51 +0,0 @@
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$RV_ROOT/workspace/work/snapshots/default/common_defines.vh
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+incdir+$RV_ROOT/workspace/work/snapshots/default
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+incdir+$RV_ROOT/design/lib
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+incdir+$RV_ROOT/design/include
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+incdir+$RV_ROOT/design/dmi
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$RV_ROOT/design/swerv_wrapper.sv
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$RV_ROOT/design/mem.sv
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$RV_ROOT/design/pic_ctrl.sv
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$RV_ROOT/design/swerv.sv
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$RV_ROOT/design/dma_ctrl.sv
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$RV_ROOT/design/ifu/ifu_aln_ctl.sv
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$RV_ROOT/design/ifu/ifu_compress_ctl.sv
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$RV_ROOT/design/ifu/ifu_ifc_ctl.sv
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$RV_ROOT/design/ifu/ifu_bp_ctl.sv
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$RV_ROOT/design/ifu/ifu_ic_mem.sv
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$RV_ROOT/design/ifu/ifu_mem_ctl.sv
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$RV_ROOT/design/ifu/ifu_iccm_mem.sv
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$RV_ROOT/design/ifu/ifu.sv
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$RV_ROOT/design/dec/dec_decode_ctl.sv
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$RV_ROOT/design/dec/dec_gpr_ctl.sv
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$RV_ROOT/design/dec/dec_ib_ctl.sv
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$RV_ROOT/design/dec/dec_tlu_ctl.sv
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$RV_ROOT/design/dec/dec_trigger.sv
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$RV_ROOT/design/dec/dec.sv
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$RV_ROOT/design/exu/exu_alu_ctl.sv
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$RV_ROOT/design/exu/exu_mul_ctl.sv
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$RV_ROOT/design/exu/exu_div_ctl.sv
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$RV_ROOT/design/exu/exu.sv
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$RV_ROOT/design/lsu/lsu.sv
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$RV_ROOT/design/lsu/lsu_clkdomain.sv
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$RV_ROOT/design/lsu/lsu_addrcheck.sv
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$RV_ROOT/design/lsu/lsu_lsc_ctl.sv
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$RV_ROOT/design/lsu/lsu_stbuf.sv
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$RV_ROOT/design/lsu/lsu_bus_buffer.sv
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$RV_ROOT/design/lsu/lsu_bus_intf.sv
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$RV_ROOT/design/lsu/lsu_ecc.sv
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$RV_ROOT/design/lsu/lsu_dccm_mem.sv
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$RV_ROOT/design/lsu/lsu_dccm_ctl.sv
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$RV_ROOT/design/lsu/lsu_trigger.sv
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$RV_ROOT/design/dbg/dbg.sv
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$RV_ROOT/design/dmi/dmi_wrapper.v
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$RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v
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$RV_ROOT/design/dmi/rvjtag_tap.sv
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$RV_ROOT/design/lib/beh_lib.sv
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$RV_ROOT/design/lib/mem_lib.sv
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$RV_ROOT/design/lib/svci_to_ahb.sv
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$RV_ROOT/design/lib/ahb_to_svci.sv
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$RV_ROOT/design/lib/svci_to_axi4.sv
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$RV_ROOT/design/lib/axi4_to_svci.sv
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$RV_ROOT/design/lib/ahb_to_axi4.sv
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$RV_ROOT/design/lib/axi4_to_ahb.sv
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@ -1,42 +0,0 @@
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$RV_ROOT/design/swerv_wrapper.sv
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$RV_ROOT/design/mem.sv
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$RV_ROOT/design/pic_ctrl.sv
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$RV_ROOT/design/swerv.sv
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$RV_ROOT/design/dma_ctrl.sv
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$RV_ROOT/design/ifu/ifu_aln_ctl.sv
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$RV_ROOT/design/ifu/ifu_compress_ctl.sv
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$RV_ROOT/design/ifu/ifu_ifc_ctl.sv
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$RV_ROOT/design/ifu/ifu_bp_ctl.sv
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$RV_ROOT/design/ifu/ifu_ic_mem.sv
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$RV_ROOT/design/ifu/ifu_mem_ctl.sv
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$RV_ROOT/design/ifu/ifu_iccm_mem.sv
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$RV_ROOT/design/ifu/ifu.sv
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$RV_ROOT/design/dec/dec_decode_ctl.sv
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$RV_ROOT/design/dec/dec_gpr_ctl.sv
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$RV_ROOT/design/dec/dec_ib_ctl.sv
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$RV_ROOT/design/dec/dec_tlu_ctl.sv
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$RV_ROOT/design/dec/dec_trigger.sv
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$RV_ROOT/design/dec/dec.sv
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$RV_ROOT/design/exu/exu_alu_ctl.sv
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$RV_ROOT/design/exu/exu_mul_ctl.sv
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$RV_ROOT/design/exu/exu_div_ctl.sv
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$RV_ROOT/design/exu/exu.sv
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$RV_ROOT/design/lsu/lsu.sv
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$RV_ROOT/design/lsu/lsu_clkdomain.sv
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$RV_ROOT/design/lsu/lsu_addrcheck.sv
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$RV_ROOT/design/lsu/lsu_lsc_ctl.sv
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$RV_ROOT/design/lsu/lsu_stbuf.sv
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$RV_ROOT/design/lsu/lsu_bus_buffer.sv
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$RV_ROOT/design/lsu/lsu_bus_intf.sv
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$RV_ROOT/design/lsu/lsu_ecc.sv
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$RV_ROOT/design/lsu/lsu_dccm_mem.sv
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$RV_ROOT/design/lsu/lsu_dccm_ctl.sv
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$RV_ROOT/design/lsu/lsu_trigger.sv
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$RV_ROOT/design/dbg/dbg.sv
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$RV_ROOT/design/dmi/dmi_wrapper.v
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$RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v
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$RV_ROOT/design/dmi/rvjtag_tap.sv
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$RV_ROOT/design/lib/beh_lib.sv
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$RV_ROOT/design/lib/mem_lib.sv
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$RV_ROOT/design/lib/ahb_to_axi4.sv
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$RV_ROOT/design/lib/axi4_to_ahb.sv
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@ -1,42 +0,0 @@
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$RV_ROOT/design/swerv_wrapper.sv
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$RV_ROOT/design/mem.sv
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$RV_ROOT/design/pic_ctrl.sv
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$RV_ROOT/design/swerv.sv
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$RV_ROOT/design/dma_ctrl.sv
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$RV_ROOT/design/ifu/ifu_aln_ctl.sv
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$RV_ROOT/design/ifu/ifu_compress_ctl.sv
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$RV_ROOT/design/ifu/ifu_ifc_ctl.sv
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$RV_ROOT/design/ifu/ifu_bp_ctl.sv
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$RV_ROOT/design/ifu/ifu_ic_mem.sv
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$RV_ROOT/design/ifu/ifu_mem_ctl.sv
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$RV_ROOT/design/ifu/ifu_iccm_mem.sv
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$RV_ROOT/design/ifu/ifu.sv
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$RV_ROOT/design/dec/dec_decode_ctl.sv
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$RV_ROOT/design/dec/dec_gpr_ctl.sv
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$RV_ROOT/design/dec/dec_ib_ctl.sv
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$RV_ROOT/design/dec/dec_tlu_ctl.sv
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$RV_ROOT/design/dec/dec_trigger.sv
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$RV_ROOT/design/dec/dec.sv
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$RV_ROOT/design/exu/exu_alu_ctl.sv
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$RV_ROOT/design/exu/exu_mul_ctl.sv
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$RV_ROOT/design/exu/exu_div_ctl.sv
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$RV_ROOT/design/exu/exu.sv
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$RV_ROOT/design/lsu/lsu.sv
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$RV_ROOT/design/lsu/lsu_clkdomain.sv
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$RV_ROOT/design/lsu/lsu_addrcheck.sv
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$RV_ROOT/design/lsu/lsu_lsc_ctl.sv
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$RV_ROOT/design/lsu/lsu_stbuf.sv
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$RV_ROOT/design/lsu/lsu_bus_buffer.sv
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$RV_ROOT/design/lsu/lsu_bus_intf.sv
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$RV_ROOT/design/lsu/lsu_ecc.sv
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$RV_ROOT/design/lsu/lsu_dccm_mem.sv
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$RV_ROOT/design/lsu/lsu_dccm_ctl.sv
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$RV_ROOT/design/lsu/lsu_trigger.sv
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$RV_ROOT/design/dbg/dbg.sv
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$RV_ROOT/design/dmi/dmi_wrapper.v
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$RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v
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$RV_ROOT/design/dmi/rvjtag_tap.sv
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$RV_ROOT/design/lib/beh_lib.sv
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$RV_ROOT/design/lib/mem_lib.sv
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$RV_ROOT/design/lib/ahb_to_axi4.sv
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$RV_ROOT/design/lib/axi4_to_ahb.sv
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@ -1,42 +0,0 @@
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$RV_ROOT/design/swerv_wrapper.sv
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$RV_ROOT/design/mem.sv
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$RV_ROOT/design/pic_ctrl.sv
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$RV_ROOT/design/swerv.sv
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$RV_ROOT/design/dma_ctrl.sv
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$RV_ROOT/design/ifu/ifu_aln_ctl.sv
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$RV_ROOT/design/ifu/ifu_compress_ctl.sv
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$RV_ROOT/design/ifu/ifu_ifc_ctl.sv
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$RV_ROOT/design/ifu/ifu_bp_ctl.sv
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$RV_ROOT/design/ifu/ifu_ic_mem.sv
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$RV_ROOT/design/ifu/ifu_mem_ctl.sv
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$RV_ROOT/design/ifu/ifu_iccm_mem.sv
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$RV_ROOT/design/ifu/ifu.sv
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$RV_ROOT/design/dec/dec_decode_ctl.sv
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$RV_ROOT/design/dec/dec_gpr_ctl.sv
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$RV_ROOT/design/dec/dec_ib_ctl.sv
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$RV_ROOT/design/dec/dec_tlu_ctl.sv
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$RV_ROOT/design/dec/dec_trigger.sv
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$RV_ROOT/design/dec/dec.sv
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$RV_ROOT/design/exu/exu_alu_ctl.sv
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$RV_ROOT/design/exu/exu_mul_ctl.sv
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$RV_ROOT/design/exu/exu_div_ctl.sv
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$RV_ROOT/design/exu/exu.sv
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$RV_ROOT/design/lsu/lsu.sv
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$RV_ROOT/design/lsu/lsu_clkdomain.sv
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$RV_ROOT/design/lsu/lsu_addrcheck.sv
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$RV_ROOT/design/lsu/lsu_lsc_ctl.sv
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$RV_ROOT/design/lsu/lsu_stbuf.sv
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$RV_ROOT/design/lsu/lsu_bus_buffer.sv
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$RV_ROOT/design/lsu/lsu_bus_intf.sv
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$RV_ROOT/design/lsu/lsu_ecc.sv
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$RV_ROOT/design/lsu/lsu_dccm_mem.sv
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$RV_ROOT/design/lsu/lsu_dccm_ctl.sv
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$RV_ROOT/design/lsu/lsu_trigger.sv
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$RV_ROOT/design/dbg/dbg.sv
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$RV_ROOT/design/dmi/dmi_wrapper.v
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$RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v
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$RV_ROOT/design/dmi/rvjtag_tap.sv
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$RV_ROOT/design/lib/beh_lib.sv
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$RV_ROOT/design/lib/mem_lib.sv
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$RV_ROOT/design/lib/ahb_to_axi4.sv
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$RV_ROOT/design/lib/axi4_to_ahb.sv
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@ -1,42 +0,0 @@
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$RV_ROOT/design/swerv_wrapper.sv
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$RV_ROOT/design/mem.sv
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$RV_ROOT/design/pic_ctrl.sv
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$RV_ROOT/design/swerv.sv
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$RV_ROOT/design/dma_ctrl.sv
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$RV_ROOT/design/ifu/ifu_aln_ctl.sv
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$RV_ROOT/design/ifu/ifu_compress_ctl.sv
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$RV_ROOT/design/ifu/ifu_ifc_ctl.sv
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$RV_ROOT/design/ifu/ifu_bp_ctl.sv
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$RV_ROOT/design/ifu/ifu_ic_mem.sv
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$RV_ROOT/design/ifu/ifu_mem_ctl.sv
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$RV_ROOT/design/ifu/ifu_iccm_mem.sv
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$RV_ROOT/design/ifu/ifu.sv
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$RV_ROOT/design/dec/dec_decode_ctl.sv
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$RV_ROOT/design/dec/dec_gpr_ctl.sv
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$RV_ROOT/design/dec/dec_ib_ctl.sv
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$RV_ROOT/design/dec/dec_tlu_ctl.sv
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$RV_ROOT/design/dec/dec_trigger.sv
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$RV_ROOT/design/dec/dec.sv
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$RV_ROOT/design/exu/exu_alu_ctl.sv
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$RV_ROOT/design/exu/exu_mul_ctl.sv
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$RV_ROOT/design/exu/exu_div_ctl.sv
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$RV_ROOT/design/exu/exu.sv
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$RV_ROOT/design/lsu/lsu.sv
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$RV_ROOT/design/lsu/lsu_clkdomain.sv
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$RV_ROOT/design/lsu/lsu_addrcheck.sv
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$RV_ROOT/design/lsu/lsu_lsc_ctl.sv
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$RV_ROOT/design/lsu/lsu_stbuf.sv
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$RV_ROOT/design/lsu/lsu_bus_buffer.sv
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$RV_ROOT/design/lsu/lsu_bus_intf.sv
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$RV_ROOT/design/lsu/lsu_ecc.sv
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$RV_ROOT/design/lsu/lsu_dccm_mem.sv
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$RV_ROOT/design/lsu/lsu_dccm_ctl.sv
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$RV_ROOT/design/lsu/lsu_trigger.sv
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$RV_ROOT/design/dbg/dbg.sv
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$RV_ROOT/design/dmi/dmi_wrapper.v
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$RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v
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$RV_ROOT/design/dmi/rvjtag_tap.sv
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$RV_ROOT/design/lib/beh_lib.sv
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$RV_ROOT/design/lib/mem_lib.sv
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$RV_ROOT/design/lib/ahb_to_axi4.sv
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$RV_ROOT/design/lib/axi4_to_ahb.sv
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